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HAW-LA_s7-prakt-mikrocontro.../Versuch1_RTOS/Debug/Versuch1_RTOS.list
jonny 4352d8eaa1 Create Versuch4 (copy Versuch3)
2025-12-01 22:55:42 +01:00

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Versuch1_RTOS.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001e0 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0000739c 080001e0 080001e0 000011e0 2**4
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 000000d4 0800757c 0800757c 0000857c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08007650 08007650 0000906c 2**0
CONTENTS, READONLY
4 .ARM 00000008 08007650 08007650 00008650 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08007658 08007658 0000906c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08007658 08007658 00008658 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 0800765c 0800765c 0000865c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000006c 20000000 08007660 00009000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00005194 2000006c 080076cc 0000906c 2**2
ALLOC
10 ._user_heap_stack 00000600 20005200 080076cc 00009200 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0000906c 2**0
CONTENTS, READONLY
12 .debug_info 00019947 00000000 00000000 0000909c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000037c1 00000000 00000000 000229e3 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000015a0 00000000 00000000 000261a8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 000010ce 00000000 00000000 00027748 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00004b21 00000000 00000000 00028816 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 000181aa 00000000 00000000 0002d337 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000ea3eb 00000000 00000000 000454e1 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 0012f8cc 2**0
CONTENTS, READONLY
20 .debug_frame 000061d8 00000000 00000000 0012f910 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000083 00000000 00000000 00135ae8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001e0 <__do_global_dtors_aux>:
80001e0: b510 push {r4, lr}
80001e2: 4c05 ldr r4, [pc, #20] @ (80001f8 <__do_global_dtors_aux+0x18>)
80001e4: 7823 ldrb r3, [r4, #0]
80001e6: b933 cbnz r3, 80001f6 <__do_global_dtors_aux+0x16>
80001e8: 4b04 ldr r3, [pc, #16] @ (80001fc <__do_global_dtors_aux+0x1c>)
80001ea: b113 cbz r3, 80001f2 <__do_global_dtors_aux+0x12>
80001ec: 4804 ldr r0, [pc, #16] @ (8000200 <__do_global_dtors_aux+0x20>)
80001ee: f3af 8000 nop.w
80001f2: 2301 movs r3, #1
80001f4: 7023 strb r3, [r4, #0]
80001f6: bd10 pop {r4, pc}
80001f8: 2000006c .word 0x2000006c
80001fc: 00000000 .word 0x00000000
8000200: 08007564 .word 0x08007564
08000204 <frame_dummy>:
8000204: b508 push {r3, lr}
8000206: 4b03 ldr r3, [pc, #12] @ (8000214 <frame_dummy+0x10>)
8000208: b11b cbz r3, 8000212 <frame_dummy+0xe>
800020a: 4903 ldr r1, [pc, #12] @ (8000218 <frame_dummy+0x14>)
800020c: 4803 ldr r0, [pc, #12] @ (800021c <frame_dummy+0x18>)
800020e: f3af 8000 nop.w
8000212: bd08 pop {r3, pc}
8000214: 00000000 .word 0x00000000
8000218: 20000070 .word 0x20000070
800021c: 08007564 .word 0x08007564
08000220 <memchr>:
8000220: f001 01ff and.w r1, r1, #255 @ 0xff
8000224: 2a10 cmp r2, #16
8000226: db2b blt.n 8000280 <memchr+0x60>
8000228: f010 0f07 tst.w r0, #7
800022c: d008 beq.n 8000240 <memchr+0x20>
800022e: f810 3b01 ldrb.w r3, [r0], #1
8000232: 3a01 subs r2, #1
8000234: 428b cmp r3, r1
8000236: d02d beq.n 8000294 <memchr+0x74>
8000238: f010 0f07 tst.w r0, #7
800023c: b342 cbz r2, 8000290 <memchr+0x70>
800023e: d1f6 bne.n 800022e <memchr+0xe>
8000240: b4f0 push {r4, r5, r6, r7}
8000242: ea41 2101 orr.w r1, r1, r1, lsl #8
8000246: ea41 4101 orr.w r1, r1, r1, lsl #16
800024a: f022 0407 bic.w r4, r2, #7
800024e: f07f 0700 mvns.w r7, #0
8000252: 2300 movs r3, #0
8000254: e8f0 5602 ldrd r5, r6, [r0], #8
8000258: 3c08 subs r4, #8
800025a: ea85 0501 eor.w r5, r5, r1
800025e: ea86 0601 eor.w r6, r6, r1
8000262: fa85 f547 uadd8 r5, r5, r7
8000266: faa3 f587 sel r5, r3, r7
800026a: fa86 f647 uadd8 r6, r6, r7
800026e: faa5 f687 sel r6, r5, r7
8000272: b98e cbnz r6, 8000298 <memchr+0x78>
8000274: d1ee bne.n 8000254 <memchr+0x34>
8000276: bcf0 pop {r4, r5, r6, r7}
8000278: f001 01ff and.w r1, r1, #255 @ 0xff
800027c: f002 0207 and.w r2, r2, #7
8000280: b132 cbz r2, 8000290 <memchr+0x70>
8000282: f810 3b01 ldrb.w r3, [r0], #1
8000286: 3a01 subs r2, #1
8000288: ea83 0301 eor.w r3, r3, r1
800028c: b113 cbz r3, 8000294 <memchr+0x74>
800028e: d1f8 bne.n 8000282 <memchr+0x62>
8000290: 2000 movs r0, #0
8000292: 4770 bx lr
8000294: 3801 subs r0, #1
8000296: 4770 bx lr
8000298: 2d00 cmp r5, #0
800029a: bf06 itte eq
800029c: 4635 moveq r5, r6
800029e: 3803 subeq r0, #3
80002a0: 3807 subne r0, #7
80002a2: f015 0f01 tst.w r5, #1
80002a6: d107 bne.n 80002b8 <memchr+0x98>
80002a8: 3001 adds r0, #1
80002aa: f415 7f80 tst.w r5, #256 @ 0x100
80002ae: bf02 ittt eq
80002b0: 3001 addeq r0, #1
80002b2: f415 3fc0 tsteq.w r5, #98304 @ 0x18000
80002b6: 3001 addeq r0, #1
80002b8: bcf0 pop {r4, r5, r6, r7}
80002ba: 3801 subs r0, #1
80002bc: 4770 bx lr
80002be: bf00 nop
080002c0 <__aeabi_uldivmod>:
80002c0: b953 cbnz r3, 80002d8 <__aeabi_uldivmod+0x18>
80002c2: b94a cbnz r2, 80002d8 <__aeabi_uldivmod+0x18>
80002c4: 2900 cmp r1, #0
80002c6: bf08 it eq
80002c8: 2800 cmpeq r0, #0
80002ca: bf1c itt ne
80002cc: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
80002d0: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
80002d4: f000 b988 b.w 80005e8 <__aeabi_idiv0>
80002d8: f1ad 0c08 sub.w ip, sp, #8
80002dc: e96d ce04 strd ip, lr, [sp, #-16]!
80002e0: f000 f806 bl 80002f0 <__udivmoddi4>
80002e4: f8dd e004 ldr.w lr, [sp, #4]
80002e8: e9dd 2302 ldrd r2, r3, [sp, #8]
80002ec: b004 add sp, #16
80002ee: 4770 bx lr
080002f0 <__udivmoddi4>:
80002f0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80002f4: 9d08 ldr r5, [sp, #32]
80002f6: 468e mov lr, r1
80002f8: 4604 mov r4, r0
80002fa: 4688 mov r8, r1
80002fc: 2b00 cmp r3, #0
80002fe: d14a bne.n 8000396 <__udivmoddi4+0xa6>
8000300: 428a cmp r2, r1
8000302: 4617 mov r7, r2
8000304: d962 bls.n 80003cc <__udivmoddi4+0xdc>
8000306: fab2 f682 clz r6, r2
800030a: b14e cbz r6, 8000320 <__udivmoddi4+0x30>
800030c: f1c6 0320 rsb r3, r6, #32
8000310: fa01 f806 lsl.w r8, r1, r6
8000314: fa20 f303 lsr.w r3, r0, r3
8000318: 40b7 lsls r7, r6
800031a: ea43 0808 orr.w r8, r3, r8
800031e: 40b4 lsls r4, r6
8000320: ea4f 4e17 mov.w lr, r7, lsr #16
8000324: fa1f fc87 uxth.w ip, r7
8000328: fbb8 f1fe udiv r1, r8, lr
800032c: 0c23 lsrs r3, r4, #16
800032e: fb0e 8811 mls r8, lr, r1, r8
8000332: ea43 4308 orr.w r3, r3, r8, lsl #16
8000336: fb01 f20c mul.w r2, r1, ip
800033a: 429a cmp r2, r3
800033c: d909 bls.n 8000352 <__udivmoddi4+0x62>
800033e: 18fb adds r3, r7, r3
8000340: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
8000344: f080 80ea bcs.w 800051c <__udivmoddi4+0x22c>
8000348: 429a cmp r2, r3
800034a: f240 80e7 bls.w 800051c <__udivmoddi4+0x22c>
800034e: 3902 subs r1, #2
8000350: 443b add r3, r7
8000352: 1a9a subs r2, r3, r2
8000354: b2a3 uxth r3, r4
8000356: fbb2 f0fe udiv r0, r2, lr
800035a: fb0e 2210 mls r2, lr, r0, r2
800035e: ea43 4302 orr.w r3, r3, r2, lsl #16
8000362: fb00 fc0c mul.w ip, r0, ip
8000366: 459c cmp ip, r3
8000368: d909 bls.n 800037e <__udivmoddi4+0x8e>
800036a: 18fb adds r3, r7, r3
800036c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
8000370: f080 80d6 bcs.w 8000520 <__udivmoddi4+0x230>
8000374: 459c cmp ip, r3
8000376: f240 80d3 bls.w 8000520 <__udivmoddi4+0x230>
800037a: 443b add r3, r7
800037c: 3802 subs r0, #2
800037e: ea40 4001 orr.w r0, r0, r1, lsl #16
8000382: eba3 030c sub.w r3, r3, ip
8000386: 2100 movs r1, #0
8000388: b11d cbz r5, 8000392 <__udivmoddi4+0xa2>
800038a: 40f3 lsrs r3, r6
800038c: 2200 movs r2, #0
800038e: e9c5 3200 strd r3, r2, [r5]
8000392: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000396: 428b cmp r3, r1
8000398: d905 bls.n 80003a6 <__udivmoddi4+0xb6>
800039a: b10d cbz r5, 80003a0 <__udivmoddi4+0xb0>
800039c: e9c5 0100 strd r0, r1, [r5]
80003a0: 2100 movs r1, #0
80003a2: 4608 mov r0, r1
80003a4: e7f5 b.n 8000392 <__udivmoddi4+0xa2>
80003a6: fab3 f183 clz r1, r3
80003aa: 2900 cmp r1, #0
80003ac: d146 bne.n 800043c <__udivmoddi4+0x14c>
80003ae: 4573 cmp r3, lr
80003b0: d302 bcc.n 80003b8 <__udivmoddi4+0xc8>
80003b2: 4282 cmp r2, r0
80003b4: f200 8105 bhi.w 80005c2 <__udivmoddi4+0x2d2>
80003b8: 1a84 subs r4, r0, r2
80003ba: eb6e 0203 sbc.w r2, lr, r3
80003be: 2001 movs r0, #1
80003c0: 4690 mov r8, r2
80003c2: 2d00 cmp r5, #0
80003c4: d0e5 beq.n 8000392 <__udivmoddi4+0xa2>
80003c6: e9c5 4800 strd r4, r8, [r5]
80003ca: e7e2 b.n 8000392 <__udivmoddi4+0xa2>
80003cc: 2a00 cmp r2, #0
80003ce: f000 8090 beq.w 80004f2 <__udivmoddi4+0x202>
80003d2: fab2 f682 clz r6, r2
80003d6: 2e00 cmp r6, #0
80003d8: f040 80a4 bne.w 8000524 <__udivmoddi4+0x234>
80003dc: 1a8a subs r2, r1, r2
80003de: 0c03 lsrs r3, r0, #16
80003e0: ea4f 4e17 mov.w lr, r7, lsr #16
80003e4: b280 uxth r0, r0
80003e6: b2bc uxth r4, r7
80003e8: 2101 movs r1, #1
80003ea: fbb2 fcfe udiv ip, r2, lr
80003ee: fb0e 221c mls r2, lr, ip, r2
80003f2: ea43 4302 orr.w r3, r3, r2, lsl #16
80003f6: fb04 f20c mul.w r2, r4, ip
80003fa: 429a cmp r2, r3
80003fc: d907 bls.n 800040e <__udivmoddi4+0x11e>
80003fe: 18fb adds r3, r7, r3
8000400: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
8000404: d202 bcs.n 800040c <__udivmoddi4+0x11c>
8000406: 429a cmp r2, r3
8000408: f200 80e0 bhi.w 80005cc <__udivmoddi4+0x2dc>
800040c: 46c4 mov ip, r8
800040e: 1a9b subs r3, r3, r2
8000410: fbb3 f2fe udiv r2, r3, lr
8000414: fb0e 3312 mls r3, lr, r2, r3
8000418: ea40 4303 orr.w r3, r0, r3, lsl #16
800041c: fb02 f404 mul.w r4, r2, r4
8000420: 429c cmp r4, r3
8000422: d907 bls.n 8000434 <__udivmoddi4+0x144>
8000424: 18fb adds r3, r7, r3
8000426: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
800042a: d202 bcs.n 8000432 <__udivmoddi4+0x142>
800042c: 429c cmp r4, r3
800042e: f200 80ca bhi.w 80005c6 <__udivmoddi4+0x2d6>
8000432: 4602 mov r2, r0
8000434: 1b1b subs r3, r3, r4
8000436: ea42 400c orr.w r0, r2, ip, lsl #16
800043a: e7a5 b.n 8000388 <__udivmoddi4+0x98>
800043c: f1c1 0620 rsb r6, r1, #32
8000440: 408b lsls r3, r1
8000442: fa22 f706 lsr.w r7, r2, r6
8000446: 431f orrs r7, r3
8000448: fa0e f401 lsl.w r4, lr, r1
800044c: fa20 f306 lsr.w r3, r0, r6
8000450: fa2e fe06 lsr.w lr, lr, r6
8000454: ea4f 4917 mov.w r9, r7, lsr #16
8000458: 4323 orrs r3, r4
800045a: fa00 f801 lsl.w r8, r0, r1
800045e: fa1f fc87 uxth.w ip, r7
8000462: fbbe f0f9 udiv r0, lr, r9
8000466: 0c1c lsrs r4, r3, #16
8000468: fb09 ee10 mls lr, r9, r0, lr
800046c: ea44 440e orr.w r4, r4, lr, lsl #16
8000470: fb00 fe0c mul.w lr, r0, ip
8000474: 45a6 cmp lr, r4
8000476: fa02 f201 lsl.w r2, r2, r1
800047a: d909 bls.n 8000490 <__udivmoddi4+0x1a0>
800047c: 193c adds r4, r7, r4
800047e: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
8000482: f080 809c bcs.w 80005be <__udivmoddi4+0x2ce>
8000486: 45a6 cmp lr, r4
8000488: f240 8099 bls.w 80005be <__udivmoddi4+0x2ce>
800048c: 3802 subs r0, #2
800048e: 443c add r4, r7
8000490: eba4 040e sub.w r4, r4, lr
8000494: fa1f fe83 uxth.w lr, r3
8000498: fbb4 f3f9 udiv r3, r4, r9
800049c: fb09 4413 mls r4, r9, r3, r4
80004a0: ea4e 4404 orr.w r4, lr, r4, lsl #16
80004a4: fb03 fc0c mul.w ip, r3, ip
80004a8: 45a4 cmp ip, r4
80004aa: d908 bls.n 80004be <__udivmoddi4+0x1ce>
80004ac: 193c adds r4, r7, r4
80004ae: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
80004b2: f080 8082 bcs.w 80005ba <__udivmoddi4+0x2ca>
80004b6: 45a4 cmp ip, r4
80004b8: d97f bls.n 80005ba <__udivmoddi4+0x2ca>
80004ba: 3b02 subs r3, #2
80004bc: 443c add r4, r7
80004be: ea43 4000 orr.w r0, r3, r0, lsl #16
80004c2: eba4 040c sub.w r4, r4, ip
80004c6: fba0 ec02 umull lr, ip, r0, r2
80004ca: 4564 cmp r4, ip
80004cc: 4673 mov r3, lr
80004ce: 46e1 mov r9, ip
80004d0: d362 bcc.n 8000598 <__udivmoddi4+0x2a8>
80004d2: d05f beq.n 8000594 <__udivmoddi4+0x2a4>
80004d4: b15d cbz r5, 80004ee <__udivmoddi4+0x1fe>
80004d6: ebb8 0203 subs.w r2, r8, r3
80004da: eb64 0409 sbc.w r4, r4, r9
80004de: fa04 f606 lsl.w r6, r4, r6
80004e2: fa22 f301 lsr.w r3, r2, r1
80004e6: 431e orrs r6, r3
80004e8: 40cc lsrs r4, r1
80004ea: e9c5 6400 strd r6, r4, [r5]
80004ee: 2100 movs r1, #0
80004f0: e74f b.n 8000392 <__udivmoddi4+0xa2>
80004f2: fbb1 fcf2 udiv ip, r1, r2
80004f6: 0c01 lsrs r1, r0, #16
80004f8: ea41 410e orr.w r1, r1, lr, lsl #16
80004fc: b280 uxth r0, r0
80004fe: ea40 4201 orr.w r2, r0, r1, lsl #16
8000502: 463b mov r3, r7
8000504: 4638 mov r0, r7
8000506: 463c mov r4, r7
8000508: 46b8 mov r8, r7
800050a: 46be mov lr, r7
800050c: 2620 movs r6, #32
800050e: fbb1 f1f7 udiv r1, r1, r7
8000512: eba2 0208 sub.w r2, r2, r8
8000516: ea41 410c orr.w r1, r1, ip, lsl #16
800051a: e766 b.n 80003ea <__udivmoddi4+0xfa>
800051c: 4601 mov r1, r0
800051e: e718 b.n 8000352 <__udivmoddi4+0x62>
8000520: 4610 mov r0, r2
8000522: e72c b.n 800037e <__udivmoddi4+0x8e>
8000524: f1c6 0220 rsb r2, r6, #32
8000528: fa2e f302 lsr.w r3, lr, r2
800052c: 40b7 lsls r7, r6
800052e: 40b1 lsls r1, r6
8000530: fa20 f202 lsr.w r2, r0, r2
8000534: ea4f 4e17 mov.w lr, r7, lsr #16
8000538: 430a orrs r2, r1
800053a: fbb3 f8fe udiv r8, r3, lr
800053e: b2bc uxth r4, r7
8000540: fb0e 3318 mls r3, lr, r8, r3
8000544: 0c11 lsrs r1, r2, #16
8000546: ea41 4103 orr.w r1, r1, r3, lsl #16
800054a: fb08 f904 mul.w r9, r8, r4
800054e: 40b0 lsls r0, r6
8000550: 4589 cmp r9, r1
8000552: ea4f 4310 mov.w r3, r0, lsr #16
8000556: b280 uxth r0, r0
8000558: d93e bls.n 80005d8 <__udivmoddi4+0x2e8>
800055a: 1879 adds r1, r7, r1
800055c: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
8000560: d201 bcs.n 8000566 <__udivmoddi4+0x276>
8000562: 4589 cmp r9, r1
8000564: d81f bhi.n 80005a6 <__udivmoddi4+0x2b6>
8000566: eba1 0109 sub.w r1, r1, r9
800056a: fbb1 f9fe udiv r9, r1, lr
800056e: fb09 f804 mul.w r8, r9, r4
8000572: fb0e 1119 mls r1, lr, r9, r1
8000576: b292 uxth r2, r2
8000578: ea42 4201 orr.w r2, r2, r1, lsl #16
800057c: 4542 cmp r2, r8
800057e: d229 bcs.n 80005d4 <__udivmoddi4+0x2e4>
8000580: 18ba adds r2, r7, r2
8000582: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
8000586: d2c4 bcs.n 8000512 <__udivmoddi4+0x222>
8000588: 4542 cmp r2, r8
800058a: d2c2 bcs.n 8000512 <__udivmoddi4+0x222>
800058c: f1a9 0102 sub.w r1, r9, #2
8000590: 443a add r2, r7
8000592: e7be b.n 8000512 <__udivmoddi4+0x222>
8000594: 45f0 cmp r8, lr
8000596: d29d bcs.n 80004d4 <__udivmoddi4+0x1e4>
8000598: ebbe 0302 subs.w r3, lr, r2
800059c: eb6c 0c07 sbc.w ip, ip, r7
80005a0: 3801 subs r0, #1
80005a2: 46e1 mov r9, ip
80005a4: e796 b.n 80004d4 <__udivmoddi4+0x1e4>
80005a6: eba7 0909 sub.w r9, r7, r9
80005aa: 4449 add r1, r9
80005ac: f1a8 0c02 sub.w ip, r8, #2
80005b0: fbb1 f9fe udiv r9, r1, lr
80005b4: fb09 f804 mul.w r8, r9, r4
80005b8: e7db b.n 8000572 <__udivmoddi4+0x282>
80005ba: 4673 mov r3, lr
80005bc: e77f b.n 80004be <__udivmoddi4+0x1ce>
80005be: 4650 mov r0, sl
80005c0: e766 b.n 8000490 <__udivmoddi4+0x1a0>
80005c2: 4608 mov r0, r1
80005c4: e6fd b.n 80003c2 <__udivmoddi4+0xd2>
80005c6: 443b add r3, r7
80005c8: 3a02 subs r2, #2
80005ca: e733 b.n 8000434 <__udivmoddi4+0x144>
80005cc: f1ac 0c02 sub.w ip, ip, #2
80005d0: 443b add r3, r7
80005d2: e71c b.n 800040e <__udivmoddi4+0x11e>
80005d4: 4649 mov r1, r9
80005d6: e79c b.n 8000512 <__udivmoddi4+0x222>
80005d8: eba1 0109 sub.w r1, r1, r9
80005dc: 46c4 mov ip, r8
80005de: fbb1 f9fe udiv r9, r1, lr
80005e2: fb09 f804 mul.w r8, r9, r4
80005e6: e7c4 b.n 8000572 <__udivmoddi4+0x282>
080005e8 <__aeabi_idiv0>:
80005e8: 4770 bx lr
80005ea: bf00 nop
080005ec <_write>:
int _write( int file, char *ptr, int len );
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
int _write( int file, char *ptr, int len ){
80005ec: b580 push {r7, lr}
80005ee: b084 sub sp, #16
80005f0: af00 add r7, sp, #0
80005f2: 60f8 str r0, [r7, #12]
80005f4: 60b9 str r1, [r7, #8]
80005f6: 607a str r2, [r7, #4]
HAL_UART_Transmit(&huart6, (uint8_t*)ptr, len, 1000);
80005f8: 687b ldr r3, [r7, #4]
80005fa: b29a uxth r2, r3
80005fc: f44f 737a mov.w r3, #1000 @ 0x3e8
8000600: 68b9 ldr r1, [r7, #8]
8000602: 4804 ldr r0, [pc, #16] @ (8000614 <_write+0x28>)
8000604: f002 fdb4 bl 8003170 <HAL_UART_Transmit>
return len;
8000608: 687b ldr r3, [r7, #4]
}
800060a: 4618 mov r0, r3
800060c: 3710 adds r7, #16
800060e: 46bd mov sp, r7
8000610: bd80 pop {r7, pc}
8000612: bf00 nop
8000614: 20000088 .word 0x20000088
08000618 <taskBlinkLed>:
void taskBlinkLed(void *arg)
{
8000618: b580 push {r7, lr}
800061a: b082 sub sp, #8
800061c: af00 add r7, sp, #0
800061e: 6078 str r0, [r7, #4]
while(1){
HAL_GPIO_TogglePin(GPIOA, 5);
8000620: 2105 movs r1, #5
8000622: 4804 ldr r0, [pc, #16] @ (8000634 <taskBlinkLed+0x1c>)
8000624: f001 fa07 bl 8001a36 <HAL_GPIO_TogglePin>
vTaskDelay(pdMS_TO_TICKS(1000));
8000628: f44f 707a mov.w r0, #1000 @ 0x3e8
800062c: f004 fb4e bl 8004ccc <vTaskDelay>
HAL_GPIO_TogglePin(GPIOA, 5);
8000630: bf00 nop
8000632: e7f5 b.n 8000620 <taskBlinkLed+0x8>
8000634: 40020000 .word 0x40020000
08000638 <taskButtonLed>:
}
}
void taskButtonLed(void *arg)
{
8000638: b580 push {r7, lr}
800063a: b084 sub sp, #16
800063c: af00 add r7, sp, #0
800063e: 6078 str r0, [r7, #4]
while(1)
{
GPIO_PinState state = HAL_GPIO_ReadPin(GPIOA, 0);
8000640: 2100 movs r1, #0
8000642: 480a ldr r0, [pc, #40] @ (800066c <taskButtonLed+0x34>)
8000644: f001 f9c6 bl 80019d4 <HAL_GPIO_ReadPin>
8000648: 4603 mov r3, r0
800064a: 73fb strb r3, [r7, #15]
HAL_GPIO_WritePin(GPIOA, 7, (state == GPIO_PIN_SET) ? GPIO_PIN_SET : GPIO_PIN_RESET);
800064c: 7bfb ldrb r3, [r7, #15]
800064e: 2b01 cmp r3, #1
8000650: bf0c ite eq
8000652: 2301 moveq r3, #1
8000654: 2300 movne r3, #0
8000656: b2db uxtb r3, r3
8000658: 461a mov r2, r3
800065a: 2107 movs r1, #7
800065c: 4803 ldr r0, [pc, #12] @ (800066c <taskButtonLed+0x34>)
800065e: f001 f9d1 bl 8001a04 <HAL_GPIO_WritePin>
vTaskDelay(pdMS_TO_TICKS(25)); // poll every 25 ms
8000662: 2019 movs r0, #25
8000664: f004 fb32 bl 8004ccc <vTaskDelay>
{
8000668: bf00 nop
800066a: e7e9 b.n 8000640 <taskButtonLed+0x8>
800066c: 40020000 .word 0x40020000
08000670 <taskPrintHello>:
}
void taskPrintHello(void *arg)
{
8000670: b580 push {r7, lr}
8000672: b082 sub sp, #8
8000674: af00 add r7, sp, #0
8000676: 6078 str r0, [r7, #4]
while(1)
{
printf("hello world %d\n", printCount);
8000678: 4b08 ldr r3, [pc, #32] @ (800069c <taskPrintHello+0x2c>)
800067a: 781b ldrb r3, [r3, #0]
800067c: 4619 mov r1, r3
800067e: 4808 ldr r0, [pc, #32] @ (80006a0 <taskPrintHello+0x30>)
8000680: f006 f8f6 bl 8006870 <iprintf>
printCount++;
8000684: 4b05 ldr r3, [pc, #20] @ (800069c <taskPrintHello+0x2c>)
8000686: 781b ldrb r3, [r3, #0]
8000688: 3301 adds r3, #1
800068a: b2da uxtb r2, r3
800068c: 4b03 ldr r3, [pc, #12] @ (800069c <taskPrintHello+0x2c>)
800068e: 701a strb r2, [r3, #0]
vTaskDelay(pdMS_TO_TICKS(1000));
8000690: f44f 707a mov.w r0, #1000 @ 0x3e8
8000694: f004 fb1a bl 8004ccc <vTaskDelay>
{
8000698: bf00 nop
800069a: e7ed b.n 8000678 <taskPrintHello+0x8>
800069c: 20000114 .word 0x20000114
80006a0: 08007588 .word 0x08007588
080006a4 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80006a4: b580 push {r7, lr}
80006a6: b082 sub sp, #8
80006a8: af02 add r7, sp, #8
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80006aa: f000 fee8 bl 800147e <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80006ae: f000 f849 bl 8000744 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80006b2: f000 f8e7 bl 8000884 <MX_GPIO_Init>
MX_USART6_UART_Init();
80006b6: f000 f8b5 bl 8000824 <MX_USART6_UART_Init>
/* USER CODE END 2 */
/* Init scheduler */
osKernelInitialize();
80006ba: f003 fa19 bl 8003af0 <osKernelInitialize>
/* add queues, ... */
/* USER CODE END RTOS_QUEUES */
/* Create the thread(s) */
/* creation of defaultTask */
defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
80006be: 4a18 ldr r2, [pc, #96] @ (8000720 <main+0x7c>)
80006c0: 2100 movs r1, #0
80006c2: 4818 ldr r0, [pc, #96] @ (8000724 <main+0x80>)
80006c4: f003 fa7e bl 8003bc4 <osThreadNew>
80006c8: 4603 mov r3, r0
80006ca: 4a17 ldr r2, [pc, #92] @ (8000728 <main+0x84>)
80006cc: 6013 str r3, [r2, #0]
/* USER CODE BEGIN RTOS_THREADS */
/* add threads, ... */
// create tasks
xTaskCreate(taskBlinkLed, "taskBlinkLed", 256, NULL, 1, NULL);
80006ce: 2300 movs r3, #0
80006d0: 9301 str r3, [sp, #4]
80006d2: 2301 movs r3, #1
80006d4: 9300 str r3, [sp, #0]
80006d6: 2300 movs r3, #0
80006d8: f44f 7280 mov.w r2, #256 @ 0x100
80006dc: 4913 ldr r1, [pc, #76] @ (800072c <main+0x88>)
80006de: 4814 ldr r0, [pc, #80] @ (8000730 <main+0x8c>)
80006e0: f004 f9ac bl 8004a3c <xTaskCreate>
xTaskCreate(taskButtonLed, "taskButtonLed", 256, NULL, 2, NULL);
80006e4: 2300 movs r3, #0
80006e6: 9301 str r3, [sp, #4]
80006e8: 2302 movs r3, #2
80006ea: 9300 str r3, [sp, #0]
80006ec: 2300 movs r3, #0
80006ee: f44f 7280 mov.w r2, #256 @ 0x100
80006f2: 4910 ldr r1, [pc, #64] @ (8000734 <main+0x90>)
80006f4: 4810 ldr r0, [pc, #64] @ (8000738 <main+0x94>)
80006f6: f004 f9a1 bl 8004a3c <xTaskCreate>
xTaskCreate(taskPrintHello, "taskPrintHello", 256, NULL, 1, NULL);
80006fa: 2300 movs r3, #0
80006fc: 9301 str r3, [sp, #4]
80006fe: 2301 movs r3, #1
8000700: 9300 str r3, [sp, #0]
8000702: 2300 movs r3, #0
8000704: f44f 7280 mov.w r2, #256 @ 0x100
8000708: 490c ldr r1, [pc, #48] @ (800073c <main+0x98>)
800070a: 480d ldr r0, [pc, #52] @ (8000740 <main+0x9c>)
800070c: f004 f996 bl 8004a3c <xTaskCreate>
/* USER CODE BEGIN RTOS_EVENTS */
/* add events, ... */
/* USER CODE END RTOS_EVENTS */
/* Start scheduler */
osKernelStart();
8000710: f003 fa22 bl 8003b58 <osKernelStart>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
vTaskDelay(pdMS_TO_TICKS(10000));
8000714: f242 7010 movw r0, #10000 @ 0x2710
8000718: f004 fad8 bl 8004ccc <vTaskDelay>
800071c: e7fa b.n 8000714 <main+0x70>
800071e: bf00 nop
8000720: 080075e0 .word 0x080075e0
8000724: 0800106d .word 0x0800106d
8000728: 20000110 .word 0x20000110
800072c: 08007598 .word 0x08007598
8000730: 08000619 .word 0x08000619
8000734: 080075a8 .word 0x080075a8
8000738: 08000639 .word 0x08000639
800073c: 080075b8 .word 0x080075b8
8000740: 08000671 .word 0x08000671
08000744 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000744: b580 push {r7, lr}
8000746: b094 sub sp, #80 @ 0x50
8000748: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
800074a: f107 0320 add.w r3, r7, #32
800074e: 2230 movs r2, #48 @ 0x30
8000750: 2100 movs r1, #0
8000752: 4618 mov r0, r3
8000754: f006 f8e1 bl 800691a <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000758: f107 030c add.w r3, r7, #12
800075c: 2200 movs r2, #0
800075e: 601a str r2, [r3, #0]
8000760: 605a str r2, [r3, #4]
8000762: 609a str r2, [r3, #8]
8000764: 60da str r2, [r3, #12]
8000766: 611a str r2, [r3, #16]
/** Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess();
8000768: f001 f980 bl 8001a6c <HAL_PWR_EnableBkUpAccess>
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
800076c: 4b2b ldr r3, [pc, #172] @ (800081c <SystemClock_Config+0xd8>)
800076e: 6c1b ldr r3, [r3, #64] @ 0x40
8000770: 4a2a ldr r2, [pc, #168] @ (800081c <SystemClock_Config+0xd8>)
8000772: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000776: 6413 str r3, [r2, #64] @ 0x40
8000778: 4b28 ldr r3, [pc, #160] @ (800081c <SystemClock_Config+0xd8>)
800077a: 6c1b ldr r3, [r3, #64] @ 0x40
800077c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000780: 60bb str r3, [r7, #8]
8000782: 68bb ldr r3, [r7, #8]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8000784: 4b26 ldr r3, [pc, #152] @ (8000820 <SystemClock_Config+0xdc>)
8000786: 681b ldr r3, [r3, #0]
8000788: 4a25 ldr r2, [pc, #148] @ (8000820 <SystemClock_Config+0xdc>)
800078a: f443 4340 orr.w r3, r3, #49152 @ 0xc000
800078e: 6013 str r3, [r2, #0]
8000790: 4b23 ldr r3, [pc, #140] @ (8000820 <SystemClock_Config+0xdc>)
8000792: 681b ldr r3, [r3, #0]
8000794: f403 4340 and.w r3, r3, #49152 @ 0xc000
8000798: 607b str r3, [r7, #4]
800079a: 687b ldr r3, [r7, #4]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
800079c: 2301 movs r3, #1
800079e: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
80007a0: f44f 3380 mov.w r3, #65536 @ 0x10000
80007a4: 627b str r3, [r7, #36] @ 0x24
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80007a6: 2302 movs r3, #2
80007a8: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
80007aa: f44f 0380 mov.w r3, #4194304 @ 0x400000
80007ae: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.PLL.PLLM = 25;
80007b0: 2319 movs r3, #25
80007b2: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.PLL.PLLN = 432;
80007b4: f44f 73d8 mov.w r3, #432 @ 0x1b0
80007b8: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
80007ba: 2302 movs r3, #2
80007bc: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLQ = 9;
80007be: 2309 movs r3, #9
80007c0: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80007c2: f107 0320 add.w r3, r7, #32
80007c6: 4618 mov r0, r3
80007c8: f001 f9b0 bl 8001b2c <HAL_RCC_OscConfig>
80007cc: 4603 mov r3, r0
80007ce: 2b00 cmp r3, #0
80007d0: d001 beq.n 80007d6 <SystemClock_Config+0x92>
{
Error_Handler();
80007d2: f000 fc65 bl 80010a0 <Error_Handler>
}
/** Activate the Over-Drive mode
*/
if (HAL_PWREx_EnableOverDrive() != HAL_OK)
80007d6: f001 f959 bl 8001a8c <HAL_PWREx_EnableOverDrive>
80007da: 4603 mov r3, r0
80007dc: 2b00 cmp r3, #0
80007de: d001 beq.n 80007e4 <SystemClock_Config+0xa0>
{
Error_Handler();
80007e0: f000 fc5e bl 80010a0 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80007e4: 230f movs r3, #15
80007e6: 60fb str r3, [r7, #12]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
80007e8: 2302 movs r3, #2
80007ea: 613b str r3, [r7, #16]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80007ec: 2300 movs r3, #0
80007ee: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
80007f0: f44f 53a0 mov.w r3, #5120 @ 0x1400
80007f4: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
80007f6: f44f 5380 mov.w r3, #4096 @ 0x1000
80007fa: 61fb str r3, [r7, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
80007fc: f107 030c add.w r3, r7, #12
8000800: 2107 movs r1, #7
8000802: 4618 mov r0, r3
8000804: f001 fc36 bl 8002074 <HAL_RCC_ClockConfig>
8000808: 4603 mov r3, r0
800080a: 2b00 cmp r3, #0
800080c: d001 beq.n 8000812 <SystemClock_Config+0xce>
{
Error_Handler();
800080e: f000 fc47 bl 80010a0 <Error_Handler>
}
}
8000812: bf00 nop
8000814: 3750 adds r7, #80 @ 0x50
8000816: 46bd mov sp, r7
8000818: bd80 pop {r7, pc}
800081a: bf00 nop
800081c: 40023800 .word 0x40023800
8000820: 40007000 .word 0x40007000
08000824 <MX_USART6_UART_Init>:
* @brief USART6 Initialization Function
* @param None
* @retval None
*/
static void MX_USART6_UART_Init(void)
{
8000824: b580 push {r7, lr}
8000826: af00 add r7, sp, #0
/* USER CODE END USART6_Init 0 */
/* USER CODE BEGIN USART6_Init 1 */
/* USER CODE END USART6_Init 1 */
huart6.Instance = USART6;
8000828: 4b14 ldr r3, [pc, #80] @ (800087c <MX_USART6_UART_Init+0x58>)
800082a: 4a15 ldr r2, [pc, #84] @ (8000880 <MX_USART6_UART_Init+0x5c>)
800082c: 601a str r2, [r3, #0]
huart6.Init.BaudRate = 115200;
800082e: 4b13 ldr r3, [pc, #76] @ (800087c <MX_USART6_UART_Init+0x58>)
8000830: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8000834: 605a str r2, [r3, #4]
huart6.Init.WordLength = UART_WORDLENGTH_8B;
8000836: 4b11 ldr r3, [pc, #68] @ (800087c <MX_USART6_UART_Init+0x58>)
8000838: 2200 movs r2, #0
800083a: 609a str r2, [r3, #8]
huart6.Init.StopBits = UART_STOPBITS_1;
800083c: 4b0f ldr r3, [pc, #60] @ (800087c <MX_USART6_UART_Init+0x58>)
800083e: 2200 movs r2, #0
8000840: 60da str r2, [r3, #12]
huart6.Init.Parity = UART_PARITY_NONE;
8000842: 4b0e ldr r3, [pc, #56] @ (800087c <MX_USART6_UART_Init+0x58>)
8000844: 2200 movs r2, #0
8000846: 611a str r2, [r3, #16]
huart6.Init.Mode = UART_MODE_TX_RX;
8000848: 4b0c ldr r3, [pc, #48] @ (800087c <MX_USART6_UART_Init+0x58>)
800084a: 220c movs r2, #12
800084c: 615a str r2, [r3, #20]
huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
800084e: 4b0b ldr r3, [pc, #44] @ (800087c <MX_USART6_UART_Init+0x58>)
8000850: 2200 movs r2, #0
8000852: 619a str r2, [r3, #24]
huart6.Init.OverSampling = UART_OVERSAMPLING_16;
8000854: 4b09 ldr r3, [pc, #36] @ (800087c <MX_USART6_UART_Init+0x58>)
8000856: 2200 movs r2, #0
8000858: 61da str r2, [r3, #28]
huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
800085a: 4b08 ldr r3, [pc, #32] @ (800087c <MX_USART6_UART_Init+0x58>)
800085c: 2200 movs r2, #0
800085e: 621a str r2, [r3, #32]
huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8000860: 4b06 ldr r3, [pc, #24] @ (800087c <MX_USART6_UART_Init+0x58>)
8000862: 2200 movs r2, #0
8000864: 625a str r2, [r3, #36] @ 0x24
if (HAL_UART_Init(&huart6) != HAL_OK)
8000866: 4805 ldr r0, [pc, #20] @ (800087c <MX_USART6_UART_Init+0x58>)
8000868: f002 fc34 bl 80030d4 <HAL_UART_Init>
800086c: 4603 mov r3, r0
800086e: 2b00 cmp r3, #0
8000870: d001 beq.n 8000876 <MX_USART6_UART_Init+0x52>
{
Error_Handler();
8000872: f000 fc15 bl 80010a0 <Error_Handler>
}
/* USER CODE BEGIN USART6_Init 2 */
/* USER CODE END USART6_Init 2 */
}
8000876: bf00 nop
8000878: bd80 pop {r7, pc}
800087a: bf00 nop
800087c: 20000088 .word 0x20000088
8000880: 40011400 .word 0x40011400
08000884 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000884: b580 push {r7, lr}
8000886: b08e sub sp, #56 @ 0x38
8000888: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800088a: f107 0324 add.w r3, r7, #36 @ 0x24
800088e: 2200 movs r2, #0
8000890: 601a str r2, [r3, #0]
8000892: 605a str r2, [r3, #4]
8000894: 609a str r2, [r3, #8]
8000896: 60da str r2, [r3, #12]
8000898: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
800089a: 4bb2 ldr r3, [pc, #712] @ (8000b64 <MX_GPIO_Init+0x2e0>)
800089c: 6b1b ldr r3, [r3, #48] @ 0x30
800089e: 4ab1 ldr r2, [pc, #708] @ (8000b64 <MX_GPIO_Init+0x2e0>)
80008a0: f043 0310 orr.w r3, r3, #16
80008a4: 6313 str r3, [r2, #48] @ 0x30
80008a6: 4baf ldr r3, [pc, #700] @ (8000b64 <MX_GPIO_Init+0x2e0>)
80008a8: 6b1b ldr r3, [r3, #48] @ 0x30
80008aa: f003 0310 and.w r3, r3, #16
80008ae: 623b str r3, [r7, #32]
80008b0: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOB_CLK_ENABLE();
80008b2: 4bac ldr r3, [pc, #688] @ (8000b64 <MX_GPIO_Init+0x2e0>)
80008b4: 6b1b ldr r3, [r3, #48] @ 0x30
80008b6: 4aab ldr r2, [pc, #684] @ (8000b64 <MX_GPIO_Init+0x2e0>)
80008b8: f043 0302 orr.w r3, r3, #2
80008bc: 6313 str r3, [r2, #48] @ 0x30
80008be: 4ba9 ldr r3, [pc, #676] @ (8000b64 <MX_GPIO_Init+0x2e0>)
80008c0: 6b1b ldr r3, [r3, #48] @ 0x30
80008c2: f003 0302 and.w r3, r3, #2
80008c6: 61fb str r3, [r7, #28]
80008c8: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOG_CLK_ENABLE();
80008ca: 4ba6 ldr r3, [pc, #664] @ (8000b64 <MX_GPIO_Init+0x2e0>)
80008cc: 6b1b ldr r3, [r3, #48] @ 0x30
80008ce: 4aa5 ldr r2, [pc, #660] @ (8000b64 <MX_GPIO_Init+0x2e0>)
80008d0: f043 0340 orr.w r3, r3, #64 @ 0x40
80008d4: 6313 str r3, [r2, #48] @ 0x30
80008d6: 4ba3 ldr r3, [pc, #652] @ (8000b64 <MX_GPIO_Init+0x2e0>)
80008d8: 6b1b ldr r3, [r3, #48] @ 0x30
80008da: f003 0340 and.w r3, r3, #64 @ 0x40
80008de: 61bb str r3, [r7, #24]
80008e0: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOD_CLK_ENABLE();
80008e2: 4ba0 ldr r3, [pc, #640] @ (8000b64 <MX_GPIO_Init+0x2e0>)
80008e4: 6b1b ldr r3, [r3, #48] @ 0x30
80008e6: 4a9f ldr r2, [pc, #636] @ (8000b64 <MX_GPIO_Init+0x2e0>)
80008e8: f043 0308 orr.w r3, r3, #8
80008ec: 6313 str r3, [r2, #48] @ 0x30
80008ee: 4b9d ldr r3, [pc, #628] @ (8000b64 <MX_GPIO_Init+0x2e0>)
80008f0: 6b1b ldr r3, [r3, #48] @ 0x30
80008f2: f003 0308 and.w r3, r3, #8
80008f6: 617b str r3, [r7, #20]
80008f8: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOC_CLK_ENABLE();
80008fa: 4b9a ldr r3, [pc, #616] @ (8000b64 <MX_GPIO_Init+0x2e0>)
80008fc: 6b1b ldr r3, [r3, #48] @ 0x30
80008fe: 4a99 ldr r2, [pc, #612] @ (8000b64 <MX_GPIO_Init+0x2e0>)
8000900: f043 0304 orr.w r3, r3, #4
8000904: 6313 str r3, [r2, #48] @ 0x30
8000906: 4b97 ldr r3, [pc, #604] @ (8000b64 <MX_GPIO_Init+0x2e0>)
8000908: 6b1b ldr r3, [r3, #48] @ 0x30
800090a: f003 0304 and.w r3, r3, #4
800090e: 613b str r3, [r7, #16]
8000910: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000912: 4b94 ldr r3, [pc, #592] @ (8000b64 <MX_GPIO_Init+0x2e0>)
8000914: 6b1b ldr r3, [r3, #48] @ 0x30
8000916: 4a93 ldr r2, [pc, #588] @ (8000b64 <MX_GPIO_Init+0x2e0>)
8000918: f043 0301 orr.w r3, r3, #1
800091c: 6313 str r3, [r2, #48] @ 0x30
800091e: 4b91 ldr r3, [pc, #580] @ (8000b64 <MX_GPIO_Init+0x2e0>)
8000920: 6b1b ldr r3, [r3, #48] @ 0x30
8000922: f003 0301 and.w r3, r3, #1
8000926: 60fb str r3, [r7, #12]
8000928: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOI_CLK_ENABLE();
800092a: 4b8e ldr r3, [pc, #568] @ (8000b64 <MX_GPIO_Init+0x2e0>)
800092c: 6b1b ldr r3, [r3, #48] @ 0x30
800092e: 4a8d ldr r2, [pc, #564] @ (8000b64 <MX_GPIO_Init+0x2e0>)
8000930: f443 7380 orr.w r3, r3, #256 @ 0x100
8000934: 6313 str r3, [r2, #48] @ 0x30
8000936: 4b8b ldr r3, [pc, #556] @ (8000b64 <MX_GPIO_Init+0x2e0>)
8000938: 6b1b ldr r3, [r3, #48] @ 0x30
800093a: f403 7380 and.w r3, r3, #256 @ 0x100
800093e: 60bb str r3, [r7, #8]
8000940: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOH_CLK_ENABLE();
8000942: 4b88 ldr r3, [pc, #544] @ (8000b64 <MX_GPIO_Init+0x2e0>)
8000944: 6b1b ldr r3, [r3, #48] @ 0x30
8000946: 4a87 ldr r2, [pc, #540] @ (8000b64 <MX_GPIO_Init+0x2e0>)
8000948: f043 0380 orr.w r3, r3, #128 @ 0x80
800094c: 6313 str r3, [r2, #48] @ 0x30
800094e: 4b85 ldr r3, [pc, #532] @ (8000b64 <MX_GPIO_Init+0x2e0>)
8000950: 6b1b ldr r3, [r3, #48] @ 0x30
8000952: f003 0380 and.w r3, r3, #128 @ 0x80
8000956: 607b str r3, [r7, #4]
8000958: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOF_CLK_ENABLE();
800095a: 4b82 ldr r3, [pc, #520] @ (8000b64 <MX_GPIO_Init+0x2e0>)
800095c: 6b1b ldr r3, [r3, #48] @ 0x30
800095e: 4a81 ldr r2, [pc, #516] @ (8000b64 <MX_GPIO_Init+0x2e0>)
8000960: f043 0320 orr.w r3, r3, #32
8000964: 6313 str r3, [r2, #48] @ 0x30
8000966: 4b7f ldr r3, [pc, #508] @ (8000b64 <MX_GPIO_Init+0x2e0>)
8000968: 6b1b ldr r3, [r3, #48] @ 0x30
800096a: f003 0320 and.w r3, r3, #32
800096e: 603b str r3, [r7, #0]
8000970: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, ARD_D7_GPIO_Pin|ARD_D8_GPIO_Pin, GPIO_PIN_RESET);
8000972: 2200 movs r2, #0
8000974: 2118 movs r1, #24
8000976: 487c ldr r0, [pc, #496] @ (8000b68 <MX_GPIO_Init+0x2e4>)
8000978: f001 f844 bl 8001a04 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOG, WIFI_RST_Pin|WIFI_GPIO_0_Pin|PMOD_GPIO_0_Pin|USB_OTGFS_PPWR_EN_Pin, GPIO_PIN_RESET);
800097c: 2200 movs r2, #0
800097e: f44f 41e2 mov.w r1, #28928 @ 0x7100
8000982: 487a ldr r0, [pc, #488] @ (8000b6c <MX_GPIO_Init+0x2e8>)
8000984: f001 f83e bl 8001a04 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, WIFI_GPIO_2_Pin|WIFI_CH_PD_Pin, GPIO_PIN_RESET);
8000988: 2200 movs r2, #0
800098a: 2148 movs r1, #72 @ 0x48
800098c: 4878 ldr r0, [pc, #480] @ (8000b70 <MX_GPIO_Init+0x2ec>)
800098e: f001 f839 bl 8001a04 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, STMOD_UART4_RXD_s_Pin|ARD_D2_GPIO_Pin, GPIO_PIN_RESET);
8000992: 2200 movs r2, #0
8000994: f44f 6102 mov.w r1, #2080 @ 0x820
8000998: 4876 ldr r0, [pc, #472] @ (8000b74 <MX_GPIO_Init+0x2f0>)
800099a: f001 f833 bl 8001a04 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOI, PMOD_SPI2_MOSI_Pin|PMOD_SPI2_MISO_Pin|GPIO_PIN_10, GPIO_PIN_RESET);
800099e: 2200 movs r2, #0
80009a0: f240 410c movw r1, #1036 @ 0x40c
80009a4: 4874 ldr r0, [pc, #464] @ (8000b78 <MX_GPIO_Init+0x2f4>)
80009a6: f001 f82d bl 8001a04 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOH, PMOD_SEL_0_Pin|CTP_RST_Pin, GPIO_PIN_SET);
80009aa: 2201 movs r2, #1
80009ac: f44f 4102 mov.w r1, #33280 @ 0x8200
80009b0: 4872 ldr r0, [pc, #456] @ (8000b7c <MX_GPIO_Init+0x2f8>)
80009b2: f001 f827 bl 8001a04 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, USB_OTG_FS_ID_Pin|SYS_LD_USER1_Pin, GPIO_PIN_RESET);
80009b6: 2200 movs r2, #0
80009b8: f44f 6190 mov.w r1, #1152 @ 0x480
80009bc: 4870 ldr r0, [pc, #448] @ (8000b80 <MX_GPIO_Init+0x2fc>)
80009be: f001 f821 bl 8001a04 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOH, PMOD_GPIO_1_Pin|ARD_D4_GPIO_Pin|USB_OTGHS_PPWR_EN_Pin|LCD_RST_Pin, GPIO_PIN_RESET);
80009c2: 2200 movs r2, #0
80009c4: f241 018c movw r1, #4236 @ 0x108c
80009c8: 486c ldr r0, [pc, #432] @ (8000b7c <MX_GPIO_Init+0x2f8>)
80009ca: f001 f81b bl 8001a04 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, USB_OTG_HS_ID_Pin|SYS_LD_USER2_Pin, GPIO_PIN_RESET);
80009ce: 2200 movs r2, #0
80009d0: f241 0102 movw r1, #4098 @ 0x1002
80009d4: 486b ldr r0, [pc, #428] @ (8000b84 <MX_GPIO_Init+0x300>)
80009d6: f001 f815 bl 8001a04 <HAL_GPIO_WritePin>
/*Configure GPIO pins : ARD_D7_GPIO_Pin ARD_D8_GPIO_Pin */
GPIO_InitStruct.Pin = ARD_D7_GPIO_Pin|ARD_D8_GPIO_Pin;
80009da: 2318 movs r3, #24
80009dc: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80009de: 2301 movs r3, #1
80009e0: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80009e2: 2300 movs r3, #0
80009e4: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80009e6: 2300 movs r3, #0
80009e8: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
80009ea: f107 0324 add.w r3, r7, #36 @ 0x24
80009ee: 4619 mov r1, r3
80009f0: 485d ldr r0, [pc, #372] @ (8000b68 <MX_GPIO_Init+0x2e4>)
80009f2: f000 fe53 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : QSPI_D2_Pin */
GPIO_InitStruct.Pin = QSPI_D2_Pin;
80009f6: 2304 movs r3, #4
80009f8: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80009fa: 2302 movs r3, #2
80009fc: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80009fe: 2300 movs r3, #0
8000a00: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000a02: 2303 movs r3, #3
8000a04: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
8000a06: 2309 movs r3, #9
8000a08: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(QSPI_D2_GPIO_Port, &GPIO_InitStruct);
8000a0a: f107 0324 add.w r3, r7, #36 @ 0x24
8000a0e: 4619 mov r1, r3
8000a10: 4855 ldr r0, [pc, #340] @ (8000b68 <MX_GPIO_Init+0x2e4>)
8000a12: f000 fe43 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : PSRAM_NBL1_Pin PSRAM_NBL0_Pin LCD_PSRAM_D10_Pin LCD_PSRAM_D5_Pin
LCD_PSRAM_D6_Pin LCD_PSRAM_D8_Pin LCD_PSRAM_D11_Pin LCD_PSRAM_D4_Pin
LCD_PSRAM_D7_Pin LCD_PSRAM_D9_Pin LCD_PSRAM_D12_Pin */
GPIO_InitStruct.Pin = PSRAM_NBL1_Pin|PSRAM_NBL0_Pin|LCD_PSRAM_D10_Pin|LCD_PSRAM_D5_Pin
8000a16: f64f 7383 movw r3, #65411 @ 0xff83
8000a1a: 627b str r3, [r7, #36] @ 0x24
|LCD_PSRAM_D6_Pin|LCD_PSRAM_D8_Pin|LCD_PSRAM_D11_Pin|LCD_PSRAM_D4_Pin
|LCD_PSRAM_D7_Pin|LCD_PSRAM_D9_Pin|LCD_PSRAM_D12_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a1c: 2302 movs r3, #2
8000a1e: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a20: 2300 movs r3, #0
8000a22: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000a24: 2303 movs r3, #3
8000a26: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8000a28: 230c movs r3, #12
8000a2a: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8000a2c: f107 0324 add.w r3, r7, #36 @ 0x24
8000a30: 4619 mov r1, r3
8000a32: 484d ldr r0, [pc, #308] @ (8000b68 <MX_GPIO_Init+0x2e4>)
8000a34: f000 fe32 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : SAI2_I2C1_SCL_Pin SAI2_I2C1_SDA_Pin */
GPIO_InitStruct.Pin = SAI2_I2C1_SCL_Pin|SAI2_I2C1_SDA_Pin;
8000a38: f44f 7340 mov.w r3, #768 @ 0x300
8000a3c: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000a3e: 2312 movs r3, #18
8000a40: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a42: 2300 movs r3, #0
8000a44: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000a46: 2303 movs r3, #3
8000a48: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
8000a4a: 2304 movs r3, #4
8000a4c: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000a4e: f107 0324 add.w r3, r7, #36 @ 0x24
8000a52: 4619 mov r1, r3
8000a54: 484b ldr r0, [pc, #300] @ (8000b84 <MX_GPIO_Init+0x300>)
8000a56: f000 fe21 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D11_TIM3_CH2_SPI1_MOSI_Pin ARD_D12_SPI1_MISO_Pin */
GPIO_InitStruct.Pin = ARD_D11_TIM3_CH2_SPI1_MOSI_Pin|ARD_D12_SPI1_MISO_Pin;
8000a5a: 2330 movs r3, #48 @ 0x30
8000a5c: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a5e: 2302 movs r3, #2
8000a60: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a62: 2300 movs r3, #0
8000a64: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000a66: 2303 movs r3, #3
8000a68: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
8000a6a: 2305 movs r3, #5
8000a6c: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000a6e: f107 0324 add.w r3, r7, #36 @ 0x24
8000a72: 4619 mov r1, r3
8000a74: 4843 ldr r0, [pc, #268] @ (8000b84 <MX_GPIO_Init+0x300>)
8000a76: f000 fe11 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : WIFI_RST_Pin WIFI_GPIO_0_Pin PMOD_GPIO_0_Pin USB_OTGFS_PPWR_EN_Pin */
GPIO_InitStruct.Pin = WIFI_RST_Pin|WIFI_GPIO_0_Pin|PMOD_GPIO_0_Pin|USB_OTGFS_PPWR_EN_Pin;
8000a7a: f44f 43e2 mov.w r3, #28928 @ 0x7100
8000a7e: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000a80: 2301 movs r3, #1
8000a82: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a84: 2300 movs r3, #0
8000a86: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000a88: 2300 movs r3, #0
8000a8a: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8000a8c: f107 0324 add.w r3, r7, #36 @ 0x24
8000a90: 4619 mov r1, r3
8000a92: 4836 ldr r0, [pc, #216] @ (8000b6c <MX_GPIO_Init+0x2e8>)
8000a94: f000 fe02 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : PSRAM_NE1_Pin LCD_PSRAM_D2_Pin LCD_PSRAM_NWE_Pin LCD_PSRAM_D3_Pin
LCD_PSRAM_NWED4_Pin LCD_PSRAM_D1_Pin LCD_PSRAM_D0_Pin PSRAM_A17_Pin
PSRAM_A16_Pin LCD_PSRAM_D15_Pin LCD_PSRAM_D14_Pin LCD_PSRAM_D13_Pin */
GPIO_InitStruct.Pin = PSRAM_NE1_Pin|LCD_PSRAM_D2_Pin|LCD_PSRAM_NWE_Pin|LCD_PSRAM_D3_Pin
8000a98: f64d 73b3 movw r3, #57267 @ 0xdfb3
8000a9c: 627b str r3, [r7, #36] @ 0x24
|LCD_PSRAM_NWED4_Pin|LCD_PSRAM_D1_Pin|LCD_PSRAM_D0_Pin|PSRAM_A17_Pin
|PSRAM_A16_Pin|LCD_PSRAM_D15_Pin|LCD_PSRAM_D14_Pin|LCD_PSRAM_D13_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a9e: 2302 movs r3, #2
8000aa0: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000aa2: 2300 movs r3, #0
8000aa4: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000aa6: 2303 movs r3, #3
8000aa8: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8000aaa: 230c movs r3, #12
8000aac: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000aae: f107 0324 add.w r3, r7, #36 @ 0x24
8000ab2: 4619 mov r1, r3
8000ab4: 482e ldr r0, [pc, #184] @ (8000b70 <MX_GPIO_Init+0x2ec>)
8000ab6: f000 fdf1 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : UART_TXD_WIFI_RX_Pin */
GPIO_InitStruct.Pin = UART_TXD_WIFI_RX_Pin;
8000aba: f44f 5380 mov.w r3, #4096 @ 0x1000
8000abe: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000ac0: 2302 movs r3, #2
8000ac2: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ac4: 2300 movs r3, #0
8000ac6: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000ac8: 2303 movs r3, #3
8000aca: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
8000acc: 2308 movs r3, #8
8000ace: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(UART_TXD_WIFI_RX_GPIO_Port, &GPIO_InitStruct);
8000ad0: f107 0324 add.w r3, r7, #36 @ 0x24
8000ad4: 4619 mov r1, r3
8000ad6: 4827 ldr r0, [pc, #156] @ (8000b74 <MX_GPIO_Init+0x2f0>)
8000ad8: f000 fde0 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : STMOD_TIM2_CH1_2_ETR_Pin ARD_D10_TIM2_CH2_SPI1_NSS_Pin */
GPIO_InitStruct.Pin = STMOD_TIM2_CH1_2_ETR_Pin|ARD_D10_TIM2_CH2_SPI1_NSS_Pin;
8000adc: f248 0302 movw r3, #32770 @ 0x8002
8000ae0: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000ae2: 2302 movs r3, #2
8000ae4: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ae6: 2300 movs r3, #0
8000ae8: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000aea: 2300 movs r3, #0
8000aec: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
8000aee: 2301 movs r3, #1
8000af0: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000af2: f107 0324 add.w r3, r7, #36 @ 0x24
8000af6: 4619 mov r1, r3
8000af8: 4821 ldr r0, [pc, #132] @ (8000b80 <MX_GPIO_Init+0x2fc>)
8000afa: f000 fdcf bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D3_TIM9_CH1_Pin ARD_D6_TIM9_CH2_Pin */
GPIO_InitStruct.Pin = ARD_D3_TIM9_CH1_Pin|ARD_D6_TIM9_CH2_Pin;
8000afe: 2360 movs r3, #96 @ 0x60
8000b00: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000b02: 2302 movs r3, #2
8000b04: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b06: 2300 movs r3, #0
8000b08: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000b0a: 2300 movs r3, #0
8000b0c: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF3_TIM9;
8000b0e: 2303 movs r3, #3
8000b10: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8000b12: f107 0324 add.w r3, r7, #36 @ 0x24
8000b16: 4619 mov r1, r3
8000b18: 4813 ldr r0, [pc, #76] @ (8000b68 <MX_GPIO_Init+0x2e4>)
8000b1a: f000 fdbf bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : NC1_Pin */
GPIO_InitStruct.Pin = NC1_Pin;
8000b1e: 2380 movs r3, #128 @ 0x80
8000b20: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000b22: 2302 movs r3, #2
8000b24: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b26: 2300 movs r3, #0
8000b28: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000b2a: 2303 movs r3, #3
8000b2c: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8000b2e: 230c movs r3, #12
8000b30: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(NC1_GPIO_Port, &GPIO_InitStruct);
8000b32: f107 0324 add.w r3, r7, #36 @ 0x24
8000b36: 4619 mov r1, r3
8000b38: 4812 ldr r0, [pc, #72] @ (8000b84 <MX_GPIO_Init+0x300>)
8000b3a: f000 fdaf bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : QSPI_NCS_Pin */
GPIO_InitStruct.Pin = QSPI_NCS_Pin;
8000b3e: 2340 movs r3, #64 @ 0x40
8000b40: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000b42: 2302 movs r3, #2
8000b44: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b46: 2300 movs r3, #0
8000b48: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000b4a: 2303 movs r3, #3
8000b4c: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
8000b4e: 230a movs r3, #10
8000b50: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(QSPI_NCS_GPIO_Port, &GPIO_InitStruct);
8000b52: f107 0324 add.w r3, r7, #36 @ 0x24
8000b56: 4619 mov r1, r3
8000b58: 480a ldr r0, [pc, #40] @ (8000b84 <MX_GPIO_Init+0x300>)
8000b5a: f000 fd9f bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : SAI2_INT_Pin */
GPIO_InitStruct.Pin = SAI2_INT_Pin;
8000b5e: f44f 4300 mov.w r3, #32768 @ 0x8000
8000b62: e011 b.n 8000b88 <MX_GPIO_Init+0x304>
8000b64: 40023800 .word 0x40023800
8000b68: 40021000 .word 0x40021000
8000b6c: 40021800 .word 0x40021800
8000b70: 40020c00 .word 0x40020c00
8000b74: 40020800 .word 0x40020800
8000b78: 40022000 .word 0x40022000
8000b7c: 40021c00 .word 0x40021c00
8000b80: 40020000 .word 0x40020000
8000b84: 40020400 .word 0x40020400
8000b88: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000b8a: f44f 1388 mov.w r3, #1114112 @ 0x110000
8000b8e: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b90: 2300 movs r3, #0
8000b92: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(SAI2_INT_GPIO_Port, &GPIO_InitStruct);
8000b94: f107 0324 add.w r3, r7, #36 @ 0x24
8000b98: 4619 mov r1, r3
8000b9a: 48bd ldr r0, [pc, #756] @ (8000e90 <MX_GPIO_Init+0x60c>)
8000b9c: f000 fd7e bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : SAI2_SD_B_Pin */
GPIO_InitStruct.Pin = SAI2_SD_B_Pin;
8000ba0: f44f 6380 mov.w r3, #1024 @ 0x400
8000ba4: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000ba6: 2302 movs r3, #2
8000ba8: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000baa: 2300 movs r3, #0
8000bac: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000bae: 2300 movs r3, #0
8000bb0: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF10_SAI2;
8000bb2: 230a movs r3, #10
8000bb4: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(SAI2_SD_B_GPIO_Port, &GPIO_InitStruct);
8000bb6: f107 0324 add.w r3, r7, #36 @ 0x24
8000bba: 4619 mov r1, r3
8000bbc: 48b4 ldr r0, [pc, #720] @ (8000e90 <MX_GPIO_Init+0x60c>)
8000bbe: f000 fd6d bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : WIFI_GPIO_2_Pin WIFI_CH_PD_Pin */
GPIO_InitStruct.Pin = WIFI_GPIO_2_Pin|WIFI_CH_PD_Pin;
8000bc2: 2348 movs r3, #72 @ 0x48
8000bc4: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000bc6: 2301 movs r3, #1
8000bc8: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000bca: 2300 movs r3, #0
8000bcc: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000bce: 2300 movs r3, #0
8000bd0: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000bd2: f107 0324 add.w r3, r7, #36 @ 0x24
8000bd6: 4619 mov r1, r3
8000bd8: 48ae ldr r0, [pc, #696] @ (8000e94 <MX_GPIO_Init+0x610>)
8000bda: f000 fd5f bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : STMOD_UART4_RXD_s_Pin ARD_D2_GPIO_Pin */
GPIO_InitStruct.Pin = STMOD_UART4_RXD_s_Pin|ARD_D2_GPIO_Pin;
8000bde: f44f 6302 mov.w r3, #2080 @ 0x820
8000be2: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000be4: 2301 movs r3, #1
8000be6: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000be8: 2300 movs r3, #0
8000bea: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000bec: 2300 movs r3, #0
8000bee: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000bf0: f107 0324 add.w r3, r7, #36 @ 0x24
8000bf4: 4619 mov r1, r3
8000bf6: 48a8 ldr r0, [pc, #672] @ (8000e98 <MX_GPIO_Init+0x614>)
8000bf8: f000 fd50 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : QSPI_D1_Pin QSPI_D0_Pin */
GPIO_InitStruct.Pin = QSPI_D1_Pin|QSPI_D0_Pin;
8000bfc: f44f 63c0 mov.w r3, #1536 @ 0x600
8000c00: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c02: 2302 movs r3, #2
8000c04: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c06: 2300 movs r3, #0
8000c08: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000c0a: 2303 movs r3, #3
8000c0c: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
8000c0e: 2309 movs r3, #9
8000c10: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000c12: f107 0324 add.w r3, r7, #36 @ 0x24
8000c16: 4619 mov r1, r3
8000c18: 489f ldr r0, [pc, #636] @ (8000e98 <MX_GPIO_Init+0x614>)
8000c1a: f000 fd3f bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : PA12 PA11 */
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11;
8000c1e: f44f 53c0 mov.w r3, #6144 @ 0x1800
8000c22: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c24: 2302 movs r3, #2
8000c26: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c28: 2300 movs r3, #0
8000c2a: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000c2c: 2303 movs r3, #3
8000c2e: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
8000c30: 230a movs r3, #10
8000c32: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000c34: f107 0324 add.w r3, r7, #36 @ 0x24
8000c38: 4619 mov r1, r3
8000c3a: 4898 ldr r0, [pc, #608] @ (8000e9c <MX_GPIO_Init+0x618>)
8000c3c: f000 fd2e bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : SAI2_FS_A_Pin SAI2_SD_A_Pin SAI2_SCK_A_Pin SAI2_MCLK_A_Pin */
GPIO_InitStruct.Pin = SAI2_FS_A_Pin|SAI2_SD_A_Pin|SAI2_SCK_A_Pin|SAI2_MCLK_A_Pin;
8000c40: 23f0 movs r3, #240 @ 0xf0
8000c42: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c44: 2302 movs r3, #2
8000c46: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c48: 2300 movs r3, #0
8000c4a: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c4c: 2300 movs r3, #0
8000c4e: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF10_SAI2;
8000c50: 230a movs r3, #10
8000c52: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8000c54: f107 0324 add.w r3, r7, #36 @ 0x24
8000c58: 4619 mov r1, r3
8000c5a: 4891 ldr r0, [pc, #580] @ (8000ea0 <MX_GPIO_Init+0x61c>)
8000c5c: f000 fd1e bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : LCD_NE_Pin PSRAM_A15_Pin PSRAM_A14_Pin PSRAM_A13_Pin
PSRAM_A12_Pin PSRAM_A11_Pin PSRAM_A10_Pin */
GPIO_InitStruct.Pin = LCD_NE_Pin|PSRAM_A15_Pin|PSRAM_A14_Pin|PSRAM_A13_Pin
8000c60: f240 233f movw r3, #575 @ 0x23f
8000c64: 627b str r3, [r7, #36] @ 0x24
|PSRAM_A12_Pin|PSRAM_A11_Pin|PSRAM_A10_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c66: 2302 movs r3, #2
8000c68: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c6a: 2300 movs r3, #0
8000c6c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000c6e: 2303 movs r3, #3
8000c70: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8000c72: 230c movs r3, #12
8000c74: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8000c76: f107 0324 add.w r3, r7, #36 @ 0x24
8000c7a: 4619 mov r1, r3
8000c7c: 4884 ldr r0, [pc, #528] @ (8000e90 <MX_GPIO_Init+0x60c>)
8000c7e: f000 fd0d bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_SPI2_MOSI_Pin PMOD_SPI2_MISO_Pin PI10 */
GPIO_InitStruct.Pin = PMOD_SPI2_MOSI_Pin|PMOD_SPI2_MISO_Pin|GPIO_PIN_10;
8000c82: f240 430c movw r3, #1036 @ 0x40c
8000c86: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000c88: 2301 movs r3, #1
8000c8a: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c8c: 2300 movs r3, #0
8000c8e: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c90: 2300 movs r3, #0
8000c92: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8000c94: f107 0324 add.w r3, r7, #36 @ 0x24
8000c98: 4619 mov r1, r3
8000c9a: 4881 ldr r0, [pc, #516] @ (8000ea0 <MX_GPIO_Init+0x61c>)
8000c9c: f000 fcfe bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : CTP_INT_Pin */
GPIO_InitStruct.Pin = CTP_INT_Pin;
8000ca0: f44f 7300 mov.w r3, #512 @ 0x200
8000ca4: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000ca6: f44f 1388 mov.w r3, #1114112 @ 0x110000
8000caa: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000cac: 2300 movs r3, #0
8000cae: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(CTP_INT_GPIO_Port, &GPIO_InitStruct);
8000cb0: f107 0324 add.w r3, r7, #36 @ 0x24
8000cb4: 4619 mov r1, r3
8000cb6: 487a ldr r0, [pc, #488] @ (8000ea0 <MX_GPIO_Init+0x61c>)
8000cb8: f000 fcf0 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : UART_RXD_WIFI_TX_Pin */
GPIO_InitStruct.Pin = UART_RXD_WIFI_TX_Pin;
8000cbc: 2304 movs r3, #4
8000cbe: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000cc0: 2302 movs r3, #2
8000cc2: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000cc4: 2300 movs r3, #0
8000cc6: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000cc8: 2303 movs r3, #3
8000cca: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
8000ccc: 2308 movs r3, #8
8000cce: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(UART_RXD_WIFI_TX_GPIO_Port, &GPIO_InitStruct);
8000cd0: f107 0324 add.w r3, r7, #36 @ 0x24
8000cd4: 4619 mov r1, r3
8000cd6: 486f ldr r0, [pc, #444] @ (8000e94 <MX_GPIO_Init+0x610>)
8000cd8: f000 fce0 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_SEL_0_Pin PMOD_GPIO_1_Pin ARD_D4_GPIO_Pin USB_OTGHS_PPWR_EN_Pin
CTP_RST_Pin LCD_RST_Pin */
GPIO_InitStruct.Pin = PMOD_SEL_0_Pin|PMOD_GPIO_1_Pin|ARD_D4_GPIO_Pin|USB_OTGHS_PPWR_EN_Pin
8000cdc: f249 238c movw r3, #37516 @ 0x928c
8000ce0: 627b str r3, [r7, #36] @ 0x24
|CTP_RST_Pin|LCD_RST_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000ce2: 2301 movs r3, #1
8000ce4: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ce6: 2300 movs r3, #0
8000ce8: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000cea: 2300 movs r3, #0
8000cec: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8000cee: f107 0324 add.w r3, r7, #36 @ 0x24
8000cf2: 4619 mov r1, r3
8000cf4: 486b ldr r0, [pc, #428] @ (8000ea4 <MX_GPIO_Init+0x620>)
8000cf6: f000 fcd1 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_SPI2_SCK_Pin PMOD_SPI2_NSS_Pin */
GPIO_InitStruct.Pin = PMOD_SPI2_SCK_Pin|PMOD_SPI2_NSS_Pin;
8000cfa: 2303 movs r3, #3
8000cfc: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000cfe: 2302 movs r3, #2
8000d00: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d02: 2300 movs r3, #0
8000d04: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000d06: 2303 movs r3, #3
8000d08: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8000d0a: 2305 movs r3, #5
8000d0c: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8000d0e: f107 0324 add.w r3, r7, #36 @ 0x24
8000d12: 4619 mov r1, r3
8000d14: 4862 ldr r0, [pc, #392] @ (8000ea0 <MX_GPIO_Init+0x61c>)
8000d16: f000 fcc1 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : USB_OTG_FS_ID_Pin SYS_LD_USER1_Pin */
GPIO_InitStruct.Pin = USB_OTG_FS_ID_Pin|SYS_LD_USER1_Pin;
8000d1a: f44f 6390 mov.w r3, #1152 @ 0x480
8000d1e: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000d20: 2301 movs r3, #1
8000d22: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d24: 2300 movs r3, #0
8000d26: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000d28: 2300 movs r3, #0
8000d2a: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000d2c: f107 0324 add.w r3, r7, #36 @ 0x24
8000d30: 4619 mov r1, r3
8000d32: 485a ldr r0, [pc, #360] @ (8000e9c <MX_GPIO_Init+0x618>)
8000d34: f000 fcb2 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : PSRAM_A0_Pin PSRAM_A2_Pin PSRAM_A1_Pin PSRAM_A3_Pin
PSRAM_A4_Pin PSRAM_A5_Pin PSRAM_A7_Pin PSRAM_A6_Pin
PSRAM_A9_Pin PSRAM_A8_Pin */
GPIO_InitStruct.Pin = PSRAM_A0_Pin|PSRAM_A2_Pin|PSRAM_A1_Pin|PSRAM_A3_Pin
8000d38: f24f 033f movw r3, #61503 @ 0xf03f
8000d3c: 627b str r3, [r7, #36] @ 0x24
|PSRAM_A4_Pin|PSRAM_A5_Pin|PSRAM_A7_Pin|PSRAM_A6_Pin
|PSRAM_A9_Pin|PSRAM_A8_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000d3e: 2302 movs r3, #2
8000d40: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d42: 2300 movs r3, #0
8000d44: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000d46: 2303 movs r3, #3
8000d48: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8000d4a: 230c movs r3, #12
8000d4c: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8000d4e: f107 0324 add.w r3, r7, #36 @ 0x24
8000d52: 4619 mov r1, r3
8000d54: 4854 ldr r0, [pc, #336] @ (8000ea8 <MX_GPIO_Init+0x624>)
8000d56: f000 fca1 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : STMOD_UART4_TXD_Pin STMOD_UART4_RXD_Pin */
GPIO_InitStruct.Pin = STMOD_UART4_TXD_Pin|STMOD_UART4_RXD_Pin;
8000d5a: f44f 43c0 mov.w r3, #24576 @ 0x6000
8000d5e: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000d60: 2302 movs r3, #2
8000d62: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d64: 2300 movs r3, #0
8000d66: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000d68: 2303 movs r3, #3
8000d6a: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
8000d6c: 2308 movs r3, #8
8000d6e: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8000d70: f107 0324 add.w r3, r7, #36 @ 0x24
8000d74: 4619 mov r1, r3
8000d76: 484b ldr r0, [pc, #300] @ (8000ea4 <MX_GPIO_Init+0x620>)
8000d78: f000 fc90 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : PA9 */
GPIO_InitStruct.Pin = GPIO_PIN_9;
8000d7c: f44f 7300 mov.w r3, #512 @ 0x200
8000d80: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000d82: 2300 movs r3, #0
8000d84: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d86: 2300 movs r3, #0
8000d88: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000d8a: f107 0324 add.w r3, r7, #36 @ 0x24
8000d8e: 4619 mov r1, r3
8000d90: 4842 ldr r0, [pc, #264] @ (8000e9c <MX_GPIO_Init+0x618>)
8000d92: f000 fc83 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : CTP_SCL_Pin */
GPIO_InitStruct.Pin = CTP_SCL_Pin;
8000d96: f44f 7380 mov.w r3, #256 @ 0x100
8000d9a: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000d9c: 2312 movs r3, #18
8000d9e: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000da0: 2300 movs r3, #0
8000da2: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000da4: 2303 movs r3, #3
8000da6: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
8000da8: 2304 movs r3, #4
8000daa: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(CTP_SCL_GPIO_Port, &GPIO_InitStruct);
8000dac: f107 0324 add.w r3, r7, #36 @ 0x24
8000db0: 4619 mov r1, r3
8000db2: 483a ldr r0, [pc, #232] @ (8000e9c <MX_GPIO_Init+0x618>)
8000db4: f000 fc72 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : LCD_TE_INT_Pin */
GPIO_InitStruct.Pin = LCD_TE_INT_Pin;
8000db8: f44f 7380 mov.w r3, #256 @ 0x100
8000dbc: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000dbe: f44f 1388 mov.w r3, #1114112 @ 0x110000
8000dc2: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000dc4: 2300 movs r3, #0
8000dc6: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(LCD_TE_INT_GPIO_Port, &GPIO_InitStruct);
8000dc8: f107 0324 add.w r3, r7, #36 @ 0x24
8000dcc: 4619 mov r1, r3
8000dce: 4832 ldr r0, [pc, #200] @ (8000e98 <MX_GPIO_Init+0x614>)
8000dd0: f000 fc64 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D15_STMOD_I2C2_SCL_Pin ARD_D14_STMOD_I2C2_SDA_Pin */
GPIO_InitStruct.Pin = ARD_D15_STMOD_I2C2_SCL_Pin|ARD_D14_STMOD_I2C2_SDA_Pin;
8000dd4: 2330 movs r3, #48 @ 0x30
8000dd6: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000dd8: 2312 movs r3, #18
8000dda: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ddc: 2300 movs r3, #0
8000dde: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000de0: 2303 movs r3, #3
8000de2: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
8000de4: 2304 movs r3, #4
8000de6: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8000de8: f107 0324 add.w r3, r7, #36 @ 0x24
8000dec: 4619 mov r1, r3
8000dee: 482d ldr r0, [pc, #180] @ (8000ea4 <MX_GPIO_Init+0x620>)
8000df0: f000 fc54 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_UART7_TXD_Pin PMOD_UART7_RXD_Pin PMOD_UART7_CTS_Pin PMOD_UART7_RTS_Pin */
GPIO_InitStruct.Pin = PMOD_UART7_TXD_Pin|PMOD_UART7_RXD_Pin|PMOD_UART7_CTS_Pin|PMOD_UART7_RTS_Pin;
8000df4: f44f 7370 mov.w r3, #960 @ 0x3c0
8000df8: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000dfa: 2302 movs r3, #2
8000dfc: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000dfe: 2300 movs r3, #0
8000e00: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000e02: 2303 movs r3, #3
8000e04: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART7;
8000e06: 2308 movs r3, #8
8000e08: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8000e0a: f107 0324 add.w r3, r7, #36 @ 0x24
8000e0e: 4619 mov r1, r3
8000e10: 4825 ldr r0, [pc, #148] @ (8000ea8 <MX_GPIO_Init+0x624>)
8000e12: f000 fc43 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_A3_ADC3_IN8_Pin */
GPIO_InitStruct.Pin = ARD_A3_ADC3_IN8_Pin;
8000e16: f44f 6380 mov.w r3, #1024 @ 0x400
8000e1a: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000e1c: 2303 movs r3, #3
8000e1e: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e20: 2300 movs r3, #0
8000e22: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(ARD_A3_ADC3_IN8_GPIO_Port, &GPIO_InitStruct);
8000e24: f107 0324 add.w r3, r7, #36 @ 0x24
8000e28: 4619 mov r1, r3
8000e2a: 481f ldr r0, [pc, #124] @ (8000ea8 <MX_GPIO_Init+0x624>)
8000e2c: f000 fc36 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : LCD_BL_Pin */
GPIO_InitStruct.Pin = LCD_BL_Pin;
8000e30: f44f 6300 mov.w r3, #2048 @ 0x800
8000e34: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000e36: 2302 movs r3, #2
8000e38: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e3a: 2300 movs r3, #0
8000e3c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000e3e: 2300 movs r3, #0
8000e40: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF2_TIM5;
8000e42: 2302 movs r3, #2
8000e44: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(LCD_BL_GPIO_Port, &GPIO_InitStruct);
8000e46: f107 0324 add.w r3, r7, #36 @ 0x24
8000e4a: 4619 mov r1, r3
8000e4c: 4815 ldr r0, [pc, #84] @ (8000ea4 <MX_GPIO_Init+0x620>)
8000e4e: f000 fc25 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : USB_OTGHS_OVCR_INT_Pin */
GPIO_InitStruct.Pin = USB_OTGHS_OVCR_INT_Pin;
8000e52: f44f 6380 mov.w r3, #1024 @ 0x400
8000e56: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000e58: 2300 movs r3, #0
8000e5a: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e5c: 2300 movs r3, #0
8000e5e: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(USB_OTGHS_OVCR_INT_GPIO_Port, &GPIO_InitStruct);
8000e60: f107 0324 add.w r3, r7, #36 @ 0x24
8000e64: 4619 mov r1, r3
8000e66: 480f ldr r0, [pc, #60] @ (8000ea4 <MX_GPIO_Init+0x620>)
8000e68: f000 fc18 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_A4_Pin ARD_A5_Pin ARD_A2_Pin */
GPIO_InitStruct.Pin = ARD_A4_Pin|ARD_A5_Pin|ARD_A2_Pin;
8000e6c: 2313 movs r3, #19
8000e6e: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000e70: 2303 movs r3, #3
8000e72: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e74: 2300 movs r3, #0
8000e76: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000e78: f107 0324 add.w r3, r7, #36 @ 0x24
8000e7c: 4619 mov r1, r3
8000e7e: 4806 ldr r0, [pc, #24] @ (8000e98 <MX_GPIO_Init+0x614>)
8000e80: f000 fc0c bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : STMOD_SPI2_MISOs_Pin STMOD_SPI2_MOSIs_Pin */
GPIO_InitStruct.Pin = STMOD_SPI2_MISOs_Pin|STMOD_SPI2_MOSIs_Pin;
8000e84: 230c movs r3, #12
8000e86: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000e88: 2302 movs r3, #2
8000e8a: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e8c: 2300 movs r3, #0
8000e8e: e00d b.n 8000eac <MX_GPIO_Init+0x628>
8000e90: 40021800 .word 0x40021800
8000e94: 40020c00 .word 0x40020c00
8000e98: 40020800 .word 0x40020800
8000e9c: 40020000 .word 0x40020000
8000ea0: 40022000 .word 0x40022000
8000ea4: 40021c00 .word 0x40021c00
8000ea8: 40021400 .word 0x40021400
8000eac: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000eae: 2303 movs r3, #3
8000eb0: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8000eb2: 2305 movs r3, #5
8000eb4: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000eb6: f107 0324 add.w r3, r7, #36 @ 0x24
8000eba: 4619 mov r1, r3
8000ebc: 4865 ldr r0, [pc, #404] @ (8001054 <MX_GPIO_Init+0x7d0>)
8000ebe: f000 fbed bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : QSPI_CLK_Pin */
GPIO_InitStruct.Pin = QSPI_CLK_Pin;
8000ec2: 2304 movs r3, #4
8000ec4: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000ec6: 2302 movs r3, #2
8000ec8: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000eca: 2300 movs r3, #0
8000ecc: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000ece: 2303 movs r3, #3
8000ed0: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
8000ed2: 2309 movs r3, #9
8000ed4: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(QSPI_CLK_GPIO_Port, &GPIO_InitStruct);
8000ed6: f107 0324 add.w r3, r7, #36 @ 0x24
8000eda: 4619 mov r1, r3
8000edc: 485e ldr r0, [pc, #376] @ (8001058 <MX_GPIO_Init+0x7d4>)
8000ede: f000 fbdd bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_D9_TIM12_CH1_Pin */
GPIO_InitStruct.Pin = ARD_D9_TIM12_CH1_Pin;
8000ee2: 2340 movs r3, #64 @ 0x40
8000ee4: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000ee6: 2302 movs r3, #2
8000ee8: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000eea: 2300 movs r3, #0
8000eec: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000eee: 2300 movs r3, #0
8000ef0: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_TIM12;
8000ef2: 2309 movs r3, #9
8000ef4: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(ARD_D9_TIM12_CH1_GPIO_Port, &GPIO_InitStruct);
8000ef6: f107 0324 add.w r3, r7, #36 @ 0x24
8000efa: 4619 mov r1, r3
8000efc: 4857 ldr r0, [pc, #348] @ (800105c <MX_GPIO_Init+0x7d8>)
8000efe: f000 fbcd bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : CTP_SDA_Pin */
GPIO_InitStruct.Pin = CTP_SDA_Pin;
8000f02: f44f 7380 mov.w r3, #256 @ 0x100
8000f06: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000f08: 2312 movs r3, #18
8000f0a: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f0c: 2300 movs r3, #0
8000f0e: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000f10: 2303 movs r3, #3
8000f12: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
8000f14: 2304 movs r3, #4
8000f16: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(CTP_SDA_GPIO_Port, &GPIO_InitStruct);
8000f18: f107 0324 add.w r3, r7, #36 @ 0x24
8000f1c: 4619 mov r1, r3
8000f1e: 484f ldr r0, [pc, #316] @ (800105c <MX_GPIO_Init+0x7d8>)
8000f20: f000 fbbc bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : QSPI_D3_Pin */
GPIO_InitStruct.Pin = QSPI_D3_Pin;
8000f24: f44f 5300 mov.w r3, #8192 @ 0x2000
8000f28: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000f2a: 2302 movs r3, #2
8000f2c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f2e: 2300 movs r3, #0
8000f30: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000f32: 2303 movs r3, #3
8000f34: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
8000f36: 2309 movs r3, #9
8000f38: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(QSPI_D3_GPIO_Port, &GPIO_InitStruct);
8000f3a: f107 0324 add.w r3, r7, #36 @ 0x24
8000f3e: 4619 mov r1, r3
8000f40: 4847 ldr r0, [pc, #284] @ (8001060 <MX_GPIO_Init+0x7dc>)
8000f42: f000 fbab bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : PA0 */
GPIO_InitStruct.Pin = GPIO_PIN_0;
8000f46: 2301 movs r3, #1
8000f48: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000f4a: 2300 movs r3, #0
8000f4c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f4e: 2300 movs r3, #0
8000f50: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000f52: f107 0324 add.w r3, r7, #36 @ 0x24
8000f56: 4619 mov r1, r3
8000f58: 4842 ldr r0, [pc, #264] @ (8001064 <MX_GPIO_Init+0x7e0>)
8000f5a: f000 fb9f bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_A1_Pin ARD_A0_Pin */
GPIO_InitStruct.Pin = ARD_A1_Pin|ARD_A0_Pin;
8000f5e: 2350 movs r3, #80 @ 0x50
8000f60: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000f62: 2303 movs r3, #3
8000f64: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f66: 2300 movs r3, #0
8000f68: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000f6a: f107 0324 add.w r3, r7, #36 @ 0x24
8000f6e: 4619 mov r1, r3
8000f70: 483c ldr r0, [pc, #240] @ (8001064 <MX_GPIO_Init+0x7e0>)
8000f72: f000 fb93 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D1_USART2_TX_Pin ARD_D0_USART2_RX_Pin */
GPIO_InitStruct.Pin = ARD_D1_USART2_TX_Pin|ARD_D0_USART2_RX_Pin;
8000f76: 230c movs r3, #12
8000f78: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000f7a: 2302 movs r3, #2
8000f7c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f7e: 2300 movs r3, #0
8000f80: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000f82: 2303 movs r3, #3
8000f84: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
8000f86: 2307 movs r3, #7
8000f88: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000f8a: f107 0324 add.w r3, r7, #36 @ 0x24
8000f8e: 4619 mov r1, r3
8000f90: 4834 ldr r0, [pc, #208] @ (8001064 <MX_GPIO_Init+0x7e0>)
8000f92: f000 fb83 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_D13_SPI1_SCK_Pin */
GPIO_InitStruct.Pin = ARD_D13_SPI1_SCK_Pin;
8000f96: 2320 movs r3, #32
8000f98: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000f9a: 2302 movs r3, #2
8000f9c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f9e: 2300 movs r3, #0
8000fa0: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000fa2: 2303 movs r3, #3
8000fa4: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
8000fa6: 2305 movs r3, #5
8000fa8: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(ARD_D13_SPI1_SCK_GPIO_Port, &GPIO_InitStruct);
8000faa: f107 0324 add.w r3, r7, #36 @ 0x24
8000fae: 4619 mov r1, r3
8000fb0: 482c ldr r0, [pc, #176] @ (8001064 <MX_GPIO_Init+0x7e0>)
8000fb2: f000 fb73 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : USB_OTG_HS_ID_Pin SYS_LD_USER2_Pin */
GPIO_InitStruct.Pin = USB_OTG_HS_ID_Pin|SYS_LD_USER2_Pin;
8000fb6: f241 0302 movw r3, #4098 @ 0x1002
8000fba: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000fbc: 2301 movs r3, #1
8000fbe: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000fc0: 2300 movs r3, #0
8000fc2: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000fc4: 2300 movs r3, #0
8000fc6: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000fc8: f107 0324 add.w r3, r7, #36 @ 0x24
8000fcc: 4619 mov r1, r3
8000fce: 4822 ldr r0, [pc, #136] @ (8001058 <MX_GPIO_Init+0x7d4>)
8000fd0: f000 fb64 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : USB_OTG_HS_VBUS_Pin USB_OTGFS_OVCR_INT_Pin PMOD_INT_Pin */
GPIO_InitStruct.Pin = USB_OTG_HS_VBUS_Pin|USB_OTGFS_OVCR_INT_Pin|PMOD_INT_Pin;
8000fd4: f44f 5330 mov.w r3, #11264 @ 0x2c00
8000fd8: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000fda: f44f 1388 mov.w r3, #1114112 @ 0x110000
8000fde: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000fe0: 2300 movs r3, #0
8000fe2: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000fe4: f107 0324 add.w r3, r7, #36 @ 0x24
8000fe8: 4619 mov r1, r3
8000fea: 481b ldr r0, [pc, #108] @ (8001058 <MX_GPIO_Init+0x7d4>)
8000fec: f000 fb56 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_D5_STMOD_TIM3_CH3_Pin */
GPIO_InitStruct.Pin = ARD_D5_STMOD_TIM3_CH3_Pin;
8000ff0: 2301 movs r3, #1
8000ff2: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000ff4: 2302 movs r3, #2
8000ff6: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ff8: 2300 movs r3, #0
8000ffa: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000ffc: 2300 movs r3, #0
8000ffe: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
8001000: 2302 movs r3, #2
8001002: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(ARD_D5_STMOD_TIM3_CH3_GPIO_Port, &GPIO_InitStruct);
8001004: f107 0324 add.w r3, r7, #36 @ 0x24
8001008: 4619 mov r1, r3
800100a: 4813 ldr r0, [pc, #76] @ (8001058 <MX_GPIO_Init+0x7d4>)
800100c: f000 fb46 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pin : PMOD_RESET_Pin */
GPIO_InitStruct.Pin = PMOD_RESET_Pin;
8001010: f44f 6300 mov.w r3, #2048 @ 0x800
8001014: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001016: 2300 movs r3, #0
8001018: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800101a: 2300 movs r3, #0
800101c: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(PMOD_RESET_GPIO_Port, &GPIO_InitStruct);
800101e: f107 0324 add.w r3, r7, #36 @ 0x24
8001022: 4619 mov r1, r3
8001024: 4810 ldr r0, [pc, #64] @ (8001068 <MX_GPIO_Init+0x7e4>)
8001026: f000 fb39 bl 800169c <HAL_GPIO_Init>
/*Configure GPIO pins : PB14 PB15 */
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
800102a: f44f 4340 mov.w r3, #49152 @ 0xc000
800102e: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001030: 2302 movs r3, #2
8001032: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001034: 2300 movs r3, #0
8001036: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001038: 2303 movs r3, #3
800103a: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;
800103c: 230c movs r3, #12
800103e: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001040: f107 0324 add.w r3, r7, #36 @ 0x24
8001044: 4619 mov r1, r3
8001046: 4804 ldr r0, [pc, #16] @ (8001058 <MX_GPIO_Init+0x7d4>)
8001048: f000 fb28 bl 800169c <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
800104c: bf00 nop
800104e: 3738 adds r7, #56 @ 0x38
8001050: 46bd mov sp, r7
8001052: bd80 pop {r7, pc}
8001054: 40020800 .word 0x40020800
8001058: 40020400 .word 0x40020400
800105c: 40021c00 .word 0x40021c00
8001060: 40020c00 .word 0x40020c00
8001064: 40020000 .word 0x40020000
8001068: 40021400 .word 0x40021400
0800106c <StartDefaultTask>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_StartDefaultTask */
void StartDefaultTask(void *argument)
{
800106c: b580 push {r7, lr}
800106e: b082 sub sp, #8
8001070: af00 add r7, sp, #0
8001072: 6078 str r0, [r7, #4]
/* USER CODE BEGIN 5 */
/* Infinite loop */
for(;;)
{
osDelay(1);
8001074: 2001 movs r0, #1
8001076: f002 fe4b bl 8003d10 <osDelay>
800107a: e7fb b.n 8001074 <StartDefaultTask+0x8>
0800107c <HAL_TIM_PeriodElapsedCallback>:
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
800107c: b580 push {r7, lr}
800107e: b082 sub sp, #8
8001080: af00 add r7, sp, #0
8001082: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM14)
8001084: 687b ldr r3, [r7, #4]
8001086: 681b ldr r3, [r3, #0]
8001088: 4a04 ldr r2, [pc, #16] @ (800109c <HAL_TIM_PeriodElapsedCallback+0x20>)
800108a: 4293 cmp r3, r2
800108c: d101 bne.n 8001092 <HAL_TIM_PeriodElapsedCallback+0x16>
{
HAL_IncTick();
800108e: f000 fa03 bl 8001498 <HAL_IncTick>
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
8001092: bf00 nop
8001094: 3708 adds r7, #8
8001096: 46bd mov sp, r7
8001098: bd80 pop {r7, pc}
800109a: bf00 nop
800109c: 40002000 .word 0x40002000
080010a0 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80010a0: b480 push {r7}
80010a2: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80010a4: b672 cpsid i
}
80010a6: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80010a8: bf00 nop
80010aa: e7fd b.n 80010a8 <Error_Handler+0x8>
080010ac <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80010ac: b580 push {r7, lr}
80010ae: b082 sub sp, #8
80010b0: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_PWR_CLK_ENABLE();
80010b2: 4b11 ldr r3, [pc, #68] @ (80010f8 <HAL_MspInit+0x4c>)
80010b4: 6c1b ldr r3, [r3, #64] @ 0x40
80010b6: 4a10 ldr r2, [pc, #64] @ (80010f8 <HAL_MspInit+0x4c>)
80010b8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80010bc: 6413 str r3, [r2, #64] @ 0x40
80010be: 4b0e ldr r3, [pc, #56] @ (80010f8 <HAL_MspInit+0x4c>)
80010c0: 6c1b ldr r3, [r3, #64] @ 0x40
80010c2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80010c6: 607b str r3, [r7, #4]
80010c8: 687b ldr r3, [r7, #4]
__HAL_RCC_SYSCFG_CLK_ENABLE();
80010ca: 4b0b ldr r3, [pc, #44] @ (80010f8 <HAL_MspInit+0x4c>)
80010cc: 6c5b ldr r3, [r3, #68] @ 0x44
80010ce: 4a0a ldr r2, [pc, #40] @ (80010f8 <HAL_MspInit+0x4c>)
80010d0: f443 4380 orr.w r3, r3, #16384 @ 0x4000
80010d4: 6453 str r3, [r2, #68] @ 0x44
80010d6: 4b08 ldr r3, [pc, #32] @ (80010f8 <HAL_MspInit+0x4c>)
80010d8: 6c5b ldr r3, [r3, #68] @ 0x44
80010da: f403 4380 and.w r3, r3, #16384 @ 0x4000
80010de: 603b str r3, [r7, #0]
80010e0: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
80010e2: 2200 movs r2, #0
80010e4: 210f movs r1, #15
80010e6: f06f 0001 mvn.w r0, #1
80010ea: f000 faad bl 8001648 <HAL_NVIC_SetPriority>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
80010ee: bf00 nop
80010f0: 3708 adds r7, #8
80010f2: 46bd mov sp, r7
80010f4: bd80 pop {r7, pc}
80010f6: bf00 nop
80010f8: 40023800 .word 0x40023800
080010fc <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
80010fc: b580 push {r7, lr}
80010fe: b0aa sub sp, #168 @ 0xa8
8001100: af00 add r7, sp, #0
8001102: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001104: f107 0394 add.w r3, r7, #148 @ 0x94
8001108: 2200 movs r2, #0
800110a: 601a str r2, [r3, #0]
800110c: 605a str r2, [r3, #4]
800110e: 609a str r2, [r3, #8]
8001110: 60da str r2, [r3, #12]
8001112: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
8001114: f107 0314 add.w r3, r7, #20
8001118: 2280 movs r2, #128 @ 0x80
800111a: 2100 movs r1, #0
800111c: 4618 mov r0, r3
800111e: f005 fbfc bl 800691a <memset>
if(huart->Instance==USART6)
8001122: 687b ldr r3, [r7, #4]
8001124: 681b ldr r3, [r3, #0]
8001126: 4a21 ldr r2, [pc, #132] @ (80011ac <HAL_UART_MspInit+0xb0>)
8001128: 4293 cmp r3, r2
800112a: d13b bne.n 80011a4 <HAL_UART_MspInit+0xa8>
/* USER CODE END USART6_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6;
800112c: f44f 6300 mov.w r3, #2048 @ 0x800
8001130: 617b str r3, [r7, #20]
PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
8001132: 2300 movs r3, #0
8001134: 667b str r3, [r7, #100] @ 0x64
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
8001136: f107 0314 add.w r3, r7, #20
800113a: 4618 mov r0, r3
800113c: f001 f9b2 bl 80024a4 <HAL_RCCEx_PeriphCLKConfig>
8001140: 4603 mov r3, r0
8001142: 2b00 cmp r3, #0
8001144: d001 beq.n 800114a <HAL_UART_MspInit+0x4e>
{
Error_Handler();
8001146: f7ff ffab bl 80010a0 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_USART6_CLK_ENABLE();
800114a: 4b19 ldr r3, [pc, #100] @ (80011b0 <HAL_UART_MspInit+0xb4>)
800114c: 6c5b ldr r3, [r3, #68] @ 0x44
800114e: 4a18 ldr r2, [pc, #96] @ (80011b0 <HAL_UART_MspInit+0xb4>)
8001150: f043 0320 orr.w r3, r3, #32
8001154: 6453 str r3, [r2, #68] @ 0x44
8001156: 4b16 ldr r3, [pc, #88] @ (80011b0 <HAL_UART_MspInit+0xb4>)
8001158: 6c5b ldr r3, [r3, #68] @ 0x44
800115a: f003 0320 and.w r3, r3, #32
800115e: 613b str r3, [r7, #16]
8001160: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
8001162: 4b13 ldr r3, [pc, #76] @ (80011b0 <HAL_UART_MspInit+0xb4>)
8001164: 6b1b ldr r3, [r3, #48] @ 0x30
8001166: 4a12 ldr r2, [pc, #72] @ (80011b0 <HAL_UART_MspInit+0xb4>)
8001168: f043 0304 orr.w r3, r3, #4
800116c: 6313 str r3, [r2, #48] @ 0x30
800116e: 4b10 ldr r3, [pc, #64] @ (80011b0 <HAL_UART_MspInit+0xb4>)
8001170: 6b1b ldr r3, [r3, #48] @ 0x30
8001172: f003 0304 and.w r3, r3, #4
8001176: 60fb str r3, [r7, #12]
8001178: 68fb ldr r3, [r7, #12]
/**USART6 GPIO Configuration
PC7 ------> USART6_RX
PC6 ------> USART6_TX
*/
GPIO_InitStruct.Pin = VCP_RX_Pin|VCP_TX_Pin;
800117a: 23c0 movs r3, #192 @ 0xc0
800117c: f8c7 3094 str.w r3, [r7, #148] @ 0x94
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001180: 2302 movs r3, #2
8001182: f8c7 3098 str.w r3, [r7, #152] @ 0x98
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001186: 2300 movs r3, #0
8001188: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800118c: 2303 movs r3, #3
800118e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
8001192: 2308 movs r3, #8
8001194: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001198: f107 0394 add.w r3, r7, #148 @ 0x94
800119c: 4619 mov r1, r3
800119e: 4805 ldr r0, [pc, #20] @ (80011b4 <HAL_UART_MspInit+0xb8>)
80011a0: f000 fa7c bl 800169c <HAL_GPIO_Init>
/* USER CODE END USART6_MspInit 1 */
}
}
80011a4: bf00 nop
80011a6: 37a8 adds r7, #168 @ 0xa8
80011a8: 46bd mov sp, r7
80011aa: bd80 pop {r7, pc}
80011ac: 40011400 .word 0x40011400
80011b0: 40023800 .word 0x40023800
80011b4: 40020800 .word 0x40020800
080011b8 <HAL_InitTick>:
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80011b8: b580 push {r7, lr}
80011ba: b08e sub sp, #56 @ 0x38
80011bc: af00 add r7, sp, #0
80011be: 6078 str r0, [r7, #4]
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock, uwAPB1Prescaler = 0U;
80011c0: 2300 movs r3, #0
80011c2: 62fb str r3, [r7, #44] @ 0x2c
uint32_t uwPrescalerValue = 0U;
80011c4: 2300 movs r3, #0
80011c6: 62bb str r3, [r7, #40] @ 0x28
uint32_t pFLatency;
HAL_StatusTypeDef status;
/* Enable TIM14 clock */
__HAL_RCC_TIM14_CLK_ENABLE();
80011c8: 4b33 ldr r3, [pc, #204] @ (8001298 <HAL_InitTick+0xe0>)
80011ca: 6c1b ldr r3, [r3, #64] @ 0x40
80011cc: 4a32 ldr r2, [pc, #200] @ (8001298 <HAL_InitTick+0xe0>)
80011ce: f443 7380 orr.w r3, r3, #256 @ 0x100
80011d2: 6413 str r3, [r2, #64] @ 0x40
80011d4: 4b30 ldr r3, [pc, #192] @ (8001298 <HAL_InitTick+0xe0>)
80011d6: 6c1b ldr r3, [r3, #64] @ 0x40
80011d8: f403 7380 and.w r3, r3, #256 @ 0x100
80011dc: 60fb str r3, [r7, #12]
80011de: 68fb ldr r3, [r7, #12]
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
80011e0: f107 0210 add.w r2, r7, #16
80011e4: f107 0314 add.w r3, r7, #20
80011e8: 4611 mov r1, r2
80011ea: 4618 mov r0, r3
80011ec: f001 f928 bl 8002440 <HAL_RCC_GetClockConfig>
/* Get APB1 prescaler */
uwAPB1Prescaler = clkconfig.APB1CLKDivider;
80011f0: 6a3b ldr r3, [r7, #32]
80011f2: 62fb str r3, [r7, #44] @ 0x2c
/* Compute TIM14 clock */
if (uwAPB1Prescaler == RCC_HCLK_DIV1)
80011f4: 6afb ldr r3, [r7, #44] @ 0x2c
80011f6: 2b00 cmp r3, #0
80011f8: d103 bne.n 8001202 <HAL_InitTick+0x4a>
{
uwTimclock = HAL_RCC_GetPCLK1Freq();
80011fa: f001 f8f9 bl 80023f0 <HAL_RCC_GetPCLK1Freq>
80011fe: 6378 str r0, [r7, #52] @ 0x34
8001200: e004 b.n 800120c <HAL_InitTick+0x54>
}
else
{
uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
8001202: f001 f8f5 bl 80023f0 <HAL_RCC_GetPCLK1Freq>
8001206: 4603 mov r3, r0
8001208: 005b lsls r3, r3, #1
800120a: 637b str r3, [r7, #52] @ 0x34
}
/* Compute the prescaler value to have TIM14 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
800120c: 6b7b ldr r3, [r7, #52] @ 0x34
800120e: 4a23 ldr r2, [pc, #140] @ (800129c <HAL_InitTick+0xe4>)
8001210: fba2 2303 umull r2, r3, r2, r3
8001214: 0c9b lsrs r3, r3, #18
8001216: 3b01 subs r3, #1
8001218: 62bb str r3, [r7, #40] @ 0x28
/* Initialize TIM14 */
htim14.Instance = TIM14;
800121a: 4b21 ldr r3, [pc, #132] @ (80012a0 <HAL_InitTick+0xe8>)
800121c: 4a21 ldr r2, [pc, #132] @ (80012a4 <HAL_InitTick+0xec>)
800121e: 601a str r2, [r3, #0]
* Period = [(TIM14CLK/1000) - 1]. to have a (1/1000) s time base.
* Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
* ClockDivision = 0
* Counter direction = Up
*/
htim14.Init.Period = (1000000U / 1000U) - 1U;
8001220: 4b1f ldr r3, [pc, #124] @ (80012a0 <HAL_InitTick+0xe8>)
8001222: f240 32e7 movw r2, #999 @ 0x3e7
8001226: 60da str r2, [r3, #12]
htim14.Init.Prescaler = uwPrescalerValue;
8001228: 4a1d ldr r2, [pc, #116] @ (80012a0 <HAL_InitTick+0xe8>)
800122a: 6abb ldr r3, [r7, #40] @ 0x28
800122c: 6053 str r3, [r2, #4]
htim14.Init.ClockDivision = 0;
800122e: 4b1c ldr r3, [pc, #112] @ (80012a0 <HAL_InitTick+0xe8>)
8001230: 2200 movs r2, #0
8001232: 611a str r2, [r3, #16]
htim14.Init.CounterMode = TIM_COUNTERMODE_UP;
8001234: 4b1a ldr r3, [pc, #104] @ (80012a0 <HAL_InitTick+0xe8>)
8001236: 2200 movs r2, #0
8001238: 609a str r2, [r3, #8]
htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800123a: 4b19 ldr r3, [pc, #100] @ (80012a0 <HAL_InitTick+0xe8>)
800123c: 2200 movs r2, #0
800123e: 619a str r2, [r3, #24]
status = HAL_TIM_Base_Init(&htim14);
8001240: 4817 ldr r0, [pc, #92] @ (80012a0 <HAL_InitTick+0xe8>)
8001242: f001 fc79 bl 8002b38 <HAL_TIM_Base_Init>
8001246: 4603 mov r3, r0
8001248: f887 3033 strb.w r3, [r7, #51] @ 0x33
if (status == HAL_OK)
800124c: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
8001250: 2b00 cmp r3, #0
8001252: d11b bne.n 800128c <HAL_InitTick+0xd4>
{
/* Start the TIM time Base generation in interrupt mode */
status = HAL_TIM_Base_Start_IT(&htim14);
8001254: 4812 ldr r0, [pc, #72] @ (80012a0 <HAL_InitTick+0xe8>)
8001256: f001 fcd1 bl 8002bfc <HAL_TIM_Base_Start_IT>
800125a: 4603 mov r3, r0
800125c: f887 3033 strb.w r3, [r7, #51] @ 0x33
if (status == HAL_OK)
8001260: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
8001264: 2b00 cmp r3, #0
8001266: d111 bne.n 800128c <HAL_InitTick+0xd4>
{
/* Enable the TIM14 global Interrupt */
HAL_NVIC_EnableIRQ(TIM8_TRG_COM_TIM14_IRQn);
8001268: 202d movs r0, #45 @ 0x2d
800126a: f000 fa09 bl 8001680 <HAL_NVIC_EnableIRQ>
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
800126e: 687b ldr r3, [r7, #4]
8001270: 2b0f cmp r3, #15
8001272: d808 bhi.n 8001286 <HAL_InitTick+0xce>
{
/* Configure the TIM IRQ priority */
HAL_NVIC_SetPriority(TIM8_TRG_COM_TIM14_IRQn, TickPriority, 0U);
8001274: 2200 movs r2, #0
8001276: 6879 ldr r1, [r7, #4]
8001278: 202d movs r0, #45 @ 0x2d
800127a: f000 f9e5 bl 8001648 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
800127e: 4a0a ldr r2, [pc, #40] @ (80012a8 <HAL_InitTick+0xf0>)
8001280: 687b ldr r3, [r7, #4]
8001282: 6013 str r3, [r2, #0]
8001284: e002 b.n 800128c <HAL_InitTick+0xd4>
}
else
{
status = HAL_ERROR;
8001286: 2301 movs r3, #1
8001288: f887 3033 strb.w r3, [r7, #51] @ 0x33
}
}
}
/* Return function status */
return status;
800128c: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
}
8001290: 4618 mov r0, r3
8001292: 3738 adds r7, #56 @ 0x38
8001294: 46bd mov sp, r7
8001296: bd80 pop {r7, pc}
8001298: 40023800 .word 0x40023800
800129c: 431bde83 .word 0x431bde83
80012a0: 20000118 .word 0x20000118
80012a4: 40002000 .word 0x40002000
80012a8: 20000004 .word 0x20000004
080012ac <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
80012ac: b480 push {r7}
80012ae: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
80012b0: bf00 nop
80012b2: e7fd b.n 80012b0 <NMI_Handler+0x4>
080012b4 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
80012b4: b480 push {r7}
80012b6: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80012b8: bf00 nop
80012ba: e7fd b.n 80012b8 <HardFault_Handler+0x4>
080012bc <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
80012bc: b480 push {r7}
80012be: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
80012c0: bf00 nop
80012c2: e7fd b.n 80012c0 <MemManage_Handler+0x4>
080012c4 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
80012c4: b480 push {r7}
80012c6: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
80012c8: bf00 nop
80012ca: e7fd b.n 80012c8 <BusFault_Handler+0x4>
080012cc <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
80012cc: b480 push {r7}
80012ce: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80012d0: bf00 nop
80012d2: e7fd b.n 80012d0 <UsageFault_Handler+0x4>
080012d4 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80012d4: b480 push {r7}
80012d6: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
80012d8: bf00 nop
80012da: 46bd mov sp, r7
80012dc: f85d 7b04 ldr.w r7, [sp], #4
80012e0: 4770 bx lr
...
080012e4 <TIM8_TRG_COM_TIM14_IRQHandler>:
/**
* @brief This function handles TIM8 trigger and commutation interrupts and TIM14 global interrupt.
*/
void TIM8_TRG_COM_TIM14_IRQHandler(void)
{
80012e4: b580 push {r7, lr}
80012e6: af00 add r7, sp, #0
/* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 0 */
/* USER CODE END TIM8_TRG_COM_TIM14_IRQn 0 */
HAL_TIM_IRQHandler(&htim14);
80012e8: 4802 ldr r0, [pc, #8] @ (80012f4 <TIM8_TRG_COM_TIM14_IRQHandler+0x10>)
80012ea: f001 fcff bl 8002cec <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 1 */
/* USER CODE END TIM8_TRG_COM_TIM14_IRQn 1 */
}
80012ee: bf00 nop
80012f0: bd80 pop {r7, pc}
80012f2: bf00 nop
80012f4: 20000118 .word 0x20000118
080012f8 <_read>:
_kill(status, -1);
while (1) {} /* Make sure we hang here */
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
80012f8: b580 push {r7, lr}
80012fa: b086 sub sp, #24
80012fc: af00 add r7, sp, #0
80012fe: 60f8 str r0, [r7, #12]
8001300: 60b9 str r1, [r7, #8]
8001302: 607a str r2, [r7, #4]
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
8001304: 2300 movs r3, #0
8001306: 617b str r3, [r7, #20]
8001308: e00a b.n 8001320 <_read+0x28>
{
*ptr++ = __io_getchar();
800130a: f3af 8000 nop.w
800130e: 4601 mov r1, r0
8001310: 68bb ldr r3, [r7, #8]
8001312: 1c5a adds r2, r3, #1
8001314: 60ba str r2, [r7, #8]
8001316: b2ca uxtb r2, r1
8001318: 701a strb r2, [r3, #0]
for (DataIdx = 0; DataIdx < len; DataIdx++)
800131a: 697b ldr r3, [r7, #20]
800131c: 3301 adds r3, #1
800131e: 617b str r3, [r7, #20]
8001320: 697a ldr r2, [r7, #20]
8001322: 687b ldr r3, [r7, #4]
8001324: 429a cmp r2, r3
8001326: dbf0 blt.n 800130a <_read+0x12>
}
return len;
8001328: 687b ldr r3, [r7, #4]
}
800132a: 4618 mov r0, r3
800132c: 3718 adds r7, #24
800132e: 46bd mov sp, r7
8001330: bd80 pop {r7, pc}
08001332 <_close>:
}
return len;
}
int _close(int file)
{
8001332: b480 push {r7}
8001334: b083 sub sp, #12
8001336: af00 add r7, sp, #0
8001338: 6078 str r0, [r7, #4]
(void)file;
return -1;
800133a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
}
800133e: 4618 mov r0, r3
8001340: 370c adds r7, #12
8001342: 46bd mov sp, r7
8001344: f85d 7b04 ldr.w r7, [sp], #4
8001348: 4770 bx lr
0800134a <_fstat>:
int _fstat(int file, struct stat *st)
{
800134a: b480 push {r7}
800134c: b083 sub sp, #12
800134e: af00 add r7, sp, #0
8001350: 6078 str r0, [r7, #4]
8001352: 6039 str r1, [r7, #0]
(void)file;
st->st_mode = S_IFCHR;
8001354: 683b ldr r3, [r7, #0]
8001356: f44f 5200 mov.w r2, #8192 @ 0x2000
800135a: 605a str r2, [r3, #4]
return 0;
800135c: 2300 movs r3, #0
}
800135e: 4618 mov r0, r3
8001360: 370c adds r7, #12
8001362: 46bd mov sp, r7
8001364: f85d 7b04 ldr.w r7, [sp], #4
8001368: 4770 bx lr
0800136a <_isatty>:
int _isatty(int file)
{
800136a: b480 push {r7}
800136c: b083 sub sp, #12
800136e: af00 add r7, sp, #0
8001370: 6078 str r0, [r7, #4]
(void)file;
return 1;
8001372: 2301 movs r3, #1
}
8001374: 4618 mov r0, r3
8001376: 370c adds r7, #12
8001378: 46bd mov sp, r7
800137a: f85d 7b04 ldr.w r7, [sp], #4
800137e: 4770 bx lr
08001380 <_lseek>:
int _lseek(int file, int ptr, int dir)
{
8001380: b480 push {r7}
8001382: b085 sub sp, #20
8001384: af00 add r7, sp, #0
8001386: 60f8 str r0, [r7, #12]
8001388: 60b9 str r1, [r7, #8]
800138a: 607a str r2, [r7, #4]
(void)file;
(void)ptr;
(void)dir;
return 0;
800138c: 2300 movs r3, #0
}
800138e: 4618 mov r0, r3
8001390: 3714 adds r7, #20
8001392: 46bd mov sp, r7
8001394: f85d 7b04 ldr.w r7, [sp], #4
8001398: 4770 bx lr
...
0800139c <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
800139c: b580 push {r7, lr}
800139e: b086 sub sp, #24
80013a0: af00 add r7, sp, #0
80013a2: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
80013a4: 4a14 ldr r2, [pc, #80] @ (80013f8 <_sbrk+0x5c>)
80013a6: 4b15 ldr r3, [pc, #84] @ (80013fc <_sbrk+0x60>)
80013a8: 1ad3 subs r3, r2, r3
80013aa: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
80013ac: 697b ldr r3, [r7, #20]
80013ae: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
80013b0: 4b13 ldr r3, [pc, #76] @ (8001400 <_sbrk+0x64>)
80013b2: 681b ldr r3, [r3, #0]
80013b4: 2b00 cmp r3, #0
80013b6: d102 bne.n 80013be <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
80013b8: 4b11 ldr r3, [pc, #68] @ (8001400 <_sbrk+0x64>)
80013ba: 4a12 ldr r2, [pc, #72] @ (8001404 <_sbrk+0x68>)
80013bc: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
80013be: 4b10 ldr r3, [pc, #64] @ (8001400 <_sbrk+0x64>)
80013c0: 681a ldr r2, [r3, #0]
80013c2: 687b ldr r3, [r7, #4]
80013c4: 4413 add r3, r2
80013c6: 693a ldr r2, [r7, #16]
80013c8: 429a cmp r2, r3
80013ca: d207 bcs.n 80013dc <_sbrk+0x40>
{
errno = ENOMEM;
80013cc: f005 faf4 bl 80069b8 <__errno>
80013d0: 4603 mov r3, r0
80013d2: 220c movs r2, #12
80013d4: 601a str r2, [r3, #0]
return (void *)-1;
80013d6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
80013da: e009 b.n 80013f0 <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
80013dc: 4b08 ldr r3, [pc, #32] @ (8001400 <_sbrk+0x64>)
80013de: 681b ldr r3, [r3, #0]
80013e0: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
80013e2: 4b07 ldr r3, [pc, #28] @ (8001400 <_sbrk+0x64>)
80013e4: 681a ldr r2, [r3, #0]
80013e6: 687b ldr r3, [r7, #4]
80013e8: 4413 add r3, r2
80013ea: 4a05 ldr r2, [pc, #20] @ (8001400 <_sbrk+0x64>)
80013ec: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
80013ee: 68fb ldr r3, [r7, #12]
}
80013f0: 4618 mov r0, r3
80013f2: 3718 adds r7, #24
80013f4: 46bd mov sp, r7
80013f6: bd80 pop {r7, pc}
80013f8: 20040000 .word 0x20040000
80013fc: 00000400 .word 0x00000400
8001400: 20000164 .word 0x20000164
8001404: 20005200 .word 0x20005200
08001408 <SystemInit>:
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
8001408: b480 push {r7}
800140a: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
800140c: 4b06 ldr r3, [pc, #24] @ (8001428 <SystemInit+0x20>)
800140e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8001412: 4a05 ldr r2, [pc, #20] @ (8001428 <SystemInit+0x20>)
8001414: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
8001418: f8c2 3088 str.w r3, [r2, #136] @ 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
800141c: bf00 nop
800141e: 46bd mov sp, r7
8001420: f85d 7b04 ldr.w r7, [sp], #4
8001424: 4770 bx lr
8001426: bf00 nop
8001428: e000ed00 .word 0xe000ed00
0800142c <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
800142c: f8df d034 ldr.w sp, [pc, #52] @ 8001464 <LoopFillZerobss+0xe>
/* Call the clock system initialization function.*/
bl SystemInit
8001430: f7ff ffea bl 8001408 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8001434: 480c ldr r0, [pc, #48] @ (8001468 <LoopFillZerobss+0x12>)
ldr r1, =_edata
8001436: 490d ldr r1, [pc, #52] @ (800146c <LoopFillZerobss+0x16>)
ldr r2, =_sidata
8001438: 4a0d ldr r2, [pc, #52] @ (8001470 <LoopFillZerobss+0x1a>)
movs r3, #0
800143a: 2300 movs r3, #0
b LoopCopyDataInit
800143c: e002 b.n 8001444 <LoopCopyDataInit>
0800143e <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
800143e: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8001440: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8001442: 3304 adds r3, #4
08001444 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8001444: 18c4 adds r4, r0, r3
cmp r4, r1
8001446: 428c cmp r4, r1
bcc CopyDataInit
8001448: d3f9 bcc.n 800143e <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
800144a: 4a0a ldr r2, [pc, #40] @ (8001474 <LoopFillZerobss+0x1e>)
ldr r4, =_ebss
800144c: 4c0a ldr r4, [pc, #40] @ (8001478 <LoopFillZerobss+0x22>)
movs r3, #0
800144e: 2300 movs r3, #0
b LoopFillZerobss
8001450: e001 b.n 8001456 <LoopFillZerobss>
08001452 <FillZerobss>:
FillZerobss:
str r3, [r2]
8001452: 6013 str r3, [r2, #0]
adds r2, r2, #4
8001454: 3204 adds r2, #4
08001456 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8001456: 42a2 cmp r2, r4
bcc FillZerobss
8001458: d3fb bcc.n 8001452 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
800145a: f005 fab3 bl 80069c4 <__libc_init_array>
/* Call the application's entry point.*/
bl main
800145e: f7ff f921 bl 80006a4 <main>
bx lr
8001462: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8001464: 20040000 .word 0x20040000
ldr r0, =_sdata
8001468: 20000000 .word 0x20000000
ldr r1, =_edata
800146c: 2000006c .word 0x2000006c
ldr r2, =_sidata
8001470: 08007660 .word 0x08007660
ldr r2, =_sbss
8001474: 2000006c .word 0x2000006c
ldr r4, =_ebss
8001478: 20005200 .word 0x20005200
0800147c <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
800147c: e7fe b.n 800147c <ADC_IRQHandler>
0800147e <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
800147e: b580 push {r7, lr}
8001480: af00 add r7, sp, #0
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8001482: 2003 movs r0, #3
8001484: f000 f8d5 bl 8001632 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8001488: 200f movs r0, #15
800148a: f7ff fe95 bl 80011b8 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
800148e: f7ff fe0d bl 80010ac <HAL_MspInit>
/* Return function status */
return HAL_OK;
8001492: 2300 movs r3, #0
}
8001494: 4618 mov r0, r3
8001496: bd80 pop {r7, pc}
08001498 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001498: b480 push {r7}
800149a: af00 add r7, sp, #0
uwTick += uwTickFreq;
800149c: 4b06 ldr r3, [pc, #24] @ (80014b8 <HAL_IncTick+0x20>)
800149e: 781b ldrb r3, [r3, #0]
80014a0: 461a mov r2, r3
80014a2: 4b06 ldr r3, [pc, #24] @ (80014bc <HAL_IncTick+0x24>)
80014a4: 681b ldr r3, [r3, #0]
80014a6: 4413 add r3, r2
80014a8: 4a04 ldr r2, [pc, #16] @ (80014bc <HAL_IncTick+0x24>)
80014aa: 6013 str r3, [r2, #0]
}
80014ac: bf00 nop
80014ae: 46bd mov sp, r7
80014b0: f85d 7b04 ldr.w r7, [sp], #4
80014b4: 4770 bx lr
80014b6: bf00 nop
80014b8: 20000008 .word 0x20000008
80014bc: 20000168 .word 0x20000168
080014c0 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80014c0: b480 push {r7}
80014c2: af00 add r7, sp, #0
return uwTick;
80014c4: 4b03 ldr r3, [pc, #12] @ (80014d4 <HAL_GetTick+0x14>)
80014c6: 681b ldr r3, [r3, #0]
}
80014c8: 4618 mov r0, r3
80014ca: 46bd mov sp, r7
80014cc: f85d 7b04 ldr.w r7, [sp], #4
80014d0: 4770 bx lr
80014d2: bf00 nop
80014d4: 20000168 .word 0x20000168
080014d8 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80014d8: b480 push {r7}
80014da: b085 sub sp, #20
80014dc: af00 add r7, sp, #0
80014de: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80014e0: 687b ldr r3, [r7, #4]
80014e2: f003 0307 and.w r3, r3, #7
80014e6: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80014e8: 4b0b ldr r3, [pc, #44] @ (8001518 <__NVIC_SetPriorityGrouping+0x40>)
80014ea: 68db ldr r3, [r3, #12]
80014ec: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80014ee: 68ba ldr r2, [r7, #8]
80014f0: f64f 03ff movw r3, #63743 @ 0xf8ff
80014f4: 4013 ands r3, r2
80014f6: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80014f8: 68fb ldr r3, [r7, #12]
80014fa: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80014fc: 68bb ldr r3, [r7, #8]
80014fe: 431a orrs r2, r3
reg_value = (reg_value |
8001500: 4b06 ldr r3, [pc, #24] @ (800151c <__NVIC_SetPriorityGrouping+0x44>)
8001502: 4313 orrs r3, r2
8001504: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8001506: 4a04 ldr r2, [pc, #16] @ (8001518 <__NVIC_SetPriorityGrouping+0x40>)
8001508: 68bb ldr r3, [r7, #8]
800150a: 60d3 str r3, [r2, #12]
}
800150c: bf00 nop
800150e: 3714 adds r7, #20
8001510: 46bd mov sp, r7
8001512: f85d 7b04 ldr.w r7, [sp], #4
8001516: 4770 bx lr
8001518: e000ed00 .word 0xe000ed00
800151c: 05fa0000 .word 0x05fa0000
08001520 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8001520: b480 push {r7}
8001522: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8001524: 4b04 ldr r3, [pc, #16] @ (8001538 <__NVIC_GetPriorityGrouping+0x18>)
8001526: 68db ldr r3, [r3, #12]
8001528: 0a1b lsrs r3, r3, #8
800152a: f003 0307 and.w r3, r3, #7
}
800152e: 4618 mov r0, r3
8001530: 46bd mov sp, r7
8001532: f85d 7b04 ldr.w r7, [sp], #4
8001536: 4770 bx lr
8001538: e000ed00 .word 0xe000ed00
0800153c <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
800153c: b480 push {r7}
800153e: b083 sub sp, #12
8001540: af00 add r7, sp, #0
8001542: 4603 mov r3, r0
8001544: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001546: f997 3007 ldrsb.w r3, [r7, #7]
800154a: 2b00 cmp r3, #0
800154c: db0b blt.n 8001566 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800154e: 79fb ldrb r3, [r7, #7]
8001550: f003 021f and.w r2, r3, #31
8001554: 4907 ldr r1, [pc, #28] @ (8001574 <__NVIC_EnableIRQ+0x38>)
8001556: f997 3007 ldrsb.w r3, [r7, #7]
800155a: 095b lsrs r3, r3, #5
800155c: 2001 movs r0, #1
800155e: fa00 f202 lsl.w r2, r0, r2
8001562: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8001566: bf00 nop
8001568: 370c adds r7, #12
800156a: 46bd mov sp, r7
800156c: f85d 7b04 ldr.w r7, [sp], #4
8001570: 4770 bx lr
8001572: bf00 nop
8001574: e000e100 .word 0xe000e100
08001578 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001578: b480 push {r7}
800157a: b083 sub sp, #12
800157c: af00 add r7, sp, #0
800157e: 4603 mov r3, r0
8001580: 6039 str r1, [r7, #0]
8001582: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001584: f997 3007 ldrsb.w r3, [r7, #7]
8001588: 2b00 cmp r3, #0
800158a: db0a blt.n 80015a2 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800158c: 683b ldr r3, [r7, #0]
800158e: b2da uxtb r2, r3
8001590: 490c ldr r1, [pc, #48] @ (80015c4 <__NVIC_SetPriority+0x4c>)
8001592: f997 3007 ldrsb.w r3, [r7, #7]
8001596: 0112 lsls r2, r2, #4
8001598: b2d2 uxtb r2, r2
800159a: 440b add r3, r1
800159c: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80015a0: e00a b.n 80015b8 <__NVIC_SetPriority+0x40>
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80015a2: 683b ldr r3, [r7, #0]
80015a4: b2da uxtb r2, r3
80015a6: 4908 ldr r1, [pc, #32] @ (80015c8 <__NVIC_SetPriority+0x50>)
80015a8: 79fb ldrb r3, [r7, #7]
80015aa: f003 030f and.w r3, r3, #15
80015ae: 3b04 subs r3, #4
80015b0: 0112 lsls r2, r2, #4
80015b2: b2d2 uxtb r2, r2
80015b4: 440b add r3, r1
80015b6: 761a strb r2, [r3, #24]
}
80015b8: bf00 nop
80015ba: 370c adds r7, #12
80015bc: 46bd mov sp, r7
80015be: f85d 7b04 ldr.w r7, [sp], #4
80015c2: 4770 bx lr
80015c4: e000e100 .word 0xe000e100
80015c8: e000ed00 .word 0xe000ed00
080015cc <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80015cc: b480 push {r7}
80015ce: b089 sub sp, #36 @ 0x24
80015d0: af00 add r7, sp, #0
80015d2: 60f8 str r0, [r7, #12]
80015d4: 60b9 str r1, [r7, #8]
80015d6: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80015d8: 68fb ldr r3, [r7, #12]
80015da: f003 0307 and.w r3, r3, #7
80015de: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80015e0: 69fb ldr r3, [r7, #28]
80015e2: f1c3 0307 rsb r3, r3, #7
80015e6: 2b04 cmp r3, #4
80015e8: bf28 it cs
80015ea: 2304 movcs r3, #4
80015ec: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80015ee: 69fb ldr r3, [r7, #28]
80015f0: 3304 adds r3, #4
80015f2: 2b06 cmp r3, #6
80015f4: d902 bls.n 80015fc <NVIC_EncodePriority+0x30>
80015f6: 69fb ldr r3, [r7, #28]
80015f8: 3b03 subs r3, #3
80015fa: e000 b.n 80015fe <NVIC_EncodePriority+0x32>
80015fc: 2300 movs r3, #0
80015fe: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001600: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8001604: 69bb ldr r3, [r7, #24]
8001606: fa02 f303 lsl.w r3, r2, r3
800160a: 43da mvns r2, r3
800160c: 68bb ldr r3, [r7, #8]
800160e: 401a ands r2, r3
8001610: 697b ldr r3, [r7, #20]
8001612: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8001614: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
8001618: 697b ldr r3, [r7, #20]
800161a: fa01 f303 lsl.w r3, r1, r3
800161e: 43d9 mvns r1, r3
8001620: 687b ldr r3, [r7, #4]
8001622: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001624: 4313 orrs r3, r2
);
}
8001626: 4618 mov r0, r3
8001628: 3724 adds r7, #36 @ 0x24
800162a: 46bd mov sp, r7
800162c: f85d 7b04 ldr.w r7, [sp], #4
8001630: 4770 bx lr
08001632 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001632: b580 push {r7, lr}
8001634: b082 sub sp, #8
8001636: af00 add r7, sp, #0
8001638: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
800163a: 6878 ldr r0, [r7, #4]
800163c: f7ff ff4c bl 80014d8 <__NVIC_SetPriorityGrouping>
}
8001640: bf00 nop
8001642: 3708 adds r7, #8
8001644: 46bd mov sp, r7
8001646: bd80 pop {r7, pc}
08001648 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001648: b580 push {r7, lr}
800164a: b086 sub sp, #24
800164c: af00 add r7, sp, #0
800164e: 4603 mov r3, r0
8001650: 60b9 str r1, [r7, #8]
8001652: 607a str r2, [r7, #4]
8001654: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
8001656: 2300 movs r3, #0
8001658: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
800165a: f7ff ff61 bl 8001520 <__NVIC_GetPriorityGrouping>
800165e: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8001660: 687a ldr r2, [r7, #4]
8001662: 68b9 ldr r1, [r7, #8]
8001664: 6978 ldr r0, [r7, #20]
8001666: f7ff ffb1 bl 80015cc <NVIC_EncodePriority>
800166a: 4602 mov r2, r0
800166c: f997 300f ldrsb.w r3, [r7, #15]
8001670: 4611 mov r1, r2
8001672: 4618 mov r0, r3
8001674: f7ff ff80 bl 8001578 <__NVIC_SetPriority>
}
8001678: bf00 nop
800167a: 3718 adds r7, #24
800167c: 46bd mov sp, r7
800167e: bd80 pop {r7, pc}
08001680 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8001680: b580 push {r7, lr}
8001682: b082 sub sp, #8
8001684: af00 add r7, sp, #0
8001686: 4603 mov r3, r0
8001688: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
800168a: f997 3007 ldrsb.w r3, [r7, #7]
800168e: 4618 mov r0, r3
8001690: f7ff ff54 bl 800153c <__NVIC_EnableIRQ>
}
8001694: bf00 nop
8001696: 3708 adds r7, #8
8001698: 46bd mov sp, r7
800169a: bd80 pop {r7, pc}
0800169c <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
800169c: b480 push {r7}
800169e: b089 sub sp, #36 @ 0x24
80016a0: af00 add r7, sp, #0
80016a2: 6078 str r0, [r7, #4]
80016a4: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
80016a6: 2300 movs r3, #0
80016a8: 61fb str r3, [r7, #28]
uint32_t ioposition = 0x00;
80016aa: 2300 movs r3, #0
80016ac: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
80016ae: 2300 movs r3, #0
80016b0: 613b str r3, [r7, #16]
uint32_t temp = 0x00;
80016b2: 2300 movs r3, #0
80016b4: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for (position = 0; position < GPIO_NUMBER; position++)
80016b6: 2300 movs r3, #0
80016b8: 61fb str r3, [r7, #28]
80016ba: e169 b.n 8001990 <HAL_GPIO_Init+0x2f4>
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
80016bc: 2201 movs r2, #1
80016be: 69fb ldr r3, [r7, #28]
80016c0: fa02 f303 lsl.w r3, r2, r3
80016c4: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
80016c6: 683b ldr r3, [r7, #0]
80016c8: 681b ldr r3, [r3, #0]
80016ca: 697a ldr r2, [r7, #20]
80016cc: 4013 ands r3, r2
80016ce: 613b str r3, [r7, #16]
if (iocurrent == ioposition)
80016d0: 693a ldr r2, [r7, #16]
80016d2: 697b ldr r3, [r7, #20]
80016d4: 429a cmp r2, r3
80016d6: f040 8158 bne.w 800198a <HAL_GPIO_Init+0x2ee>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
80016da: 683b ldr r3, [r7, #0]
80016dc: 685b ldr r3, [r3, #4]
80016de: f003 0303 and.w r3, r3, #3
80016e2: 2b01 cmp r3, #1
80016e4: d005 beq.n 80016f2 <HAL_GPIO_Init+0x56>
80016e6: 683b ldr r3, [r7, #0]
80016e8: 685b ldr r3, [r3, #4]
80016ea: f003 0303 and.w r3, r3, #3
80016ee: 2b02 cmp r3, #2
80016f0: d130 bne.n 8001754 <HAL_GPIO_Init+0xb8>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
80016f2: 687b ldr r3, [r7, #4]
80016f4: 689b ldr r3, [r3, #8]
80016f6: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
80016f8: 69fb ldr r3, [r7, #28]
80016fa: 005b lsls r3, r3, #1
80016fc: 2203 movs r2, #3
80016fe: fa02 f303 lsl.w r3, r2, r3
8001702: 43db mvns r3, r3
8001704: 69ba ldr r2, [r7, #24]
8001706: 4013 ands r3, r2
8001708: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2));
800170a: 683b ldr r3, [r7, #0]
800170c: 68da ldr r2, [r3, #12]
800170e: 69fb ldr r3, [r7, #28]
8001710: 005b lsls r3, r3, #1
8001712: fa02 f303 lsl.w r3, r2, r3
8001716: 69ba ldr r2, [r7, #24]
8001718: 4313 orrs r3, r2
800171a: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
800171c: 687b ldr r3, [r7, #4]
800171e: 69ba ldr r2, [r7, #24]
8001720: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001722: 687b ldr r3, [r7, #4]
8001724: 685b ldr r3, [r3, #4]
8001726: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8001728: 2201 movs r2, #1
800172a: 69fb ldr r3, [r7, #28]
800172c: fa02 f303 lsl.w r3, r2, r3
8001730: 43db mvns r3, r3
8001732: 69ba ldr r2, [r7, #24]
8001734: 4013 ands r3, r2
8001736: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8001738: 683b ldr r3, [r7, #0]
800173a: 685b ldr r3, [r3, #4]
800173c: 091b lsrs r3, r3, #4
800173e: f003 0201 and.w r2, r3, #1
8001742: 69fb ldr r3, [r7, #28]
8001744: fa02 f303 lsl.w r3, r2, r3
8001748: 69ba ldr r2, [r7, #24]
800174a: 4313 orrs r3, r2
800174c: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
800174e: 687b ldr r3, [r7, #4]
8001750: 69ba ldr r2, [r7, #24]
8001752: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8001754: 683b ldr r3, [r7, #0]
8001756: 685b ldr r3, [r3, #4]
8001758: f003 0303 and.w r3, r3, #3
800175c: 2b03 cmp r3, #3
800175e: d017 beq.n 8001790 <HAL_GPIO_Init+0xf4>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8001760: 687b ldr r3, [r7, #4]
8001762: 68db ldr r3, [r3, #12]
8001764: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
8001766: 69fb ldr r3, [r7, #28]
8001768: 005b lsls r3, r3, #1
800176a: 2203 movs r2, #3
800176c: fa02 f303 lsl.w r3, r2, r3
8001770: 43db mvns r3, r3
8001772: 69ba ldr r2, [r7, #24]
8001774: 4013 ands r3, r2
8001776: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2));
8001778: 683b ldr r3, [r7, #0]
800177a: 689a ldr r2, [r3, #8]
800177c: 69fb ldr r3, [r7, #28]
800177e: 005b lsls r3, r3, #1
8001780: fa02 f303 lsl.w r3, r2, r3
8001784: 69ba ldr r2, [r7, #24]
8001786: 4313 orrs r3, r2
8001788: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
800178a: 687b ldr r3, [r7, #4]
800178c: 69ba ldr r2, [r7, #24]
800178e: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001790: 683b ldr r3, [r7, #0]
8001792: 685b ldr r3, [r3, #4]
8001794: f003 0303 and.w r3, r3, #3
8001798: 2b02 cmp r3, #2
800179a: d123 bne.n 80017e4 <HAL_GPIO_Init+0x148>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
800179c: 69fb ldr r3, [r7, #28]
800179e: 08da lsrs r2, r3, #3
80017a0: 687b ldr r3, [r7, #4]
80017a2: 3208 adds r2, #8
80017a4: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80017a8: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
80017aa: 69fb ldr r3, [r7, #28]
80017ac: f003 0307 and.w r3, r3, #7
80017b0: 009b lsls r3, r3, #2
80017b2: 220f movs r2, #15
80017b4: fa02 f303 lsl.w r3, r2, r3
80017b8: 43db mvns r3, r3
80017ba: 69ba ldr r2, [r7, #24]
80017bc: 4013 ands r3, r2
80017be: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
80017c0: 683b ldr r3, [r7, #0]
80017c2: 691a ldr r2, [r3, #16]
80017c4: 69fb ldr r3, [r7, #28]
80017c6: f003 0307 and.w r3, r3, #7
80017ca: 009b lsls r3, r3, #2
80017cc: fa02 f303 lsl.w r3, r2, r3
80017d0: 69ba ldr r2, [r7, #24]
80017d2: 4313 orrs r3, r2
80017d4: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3] = temp;
80017d6: 69fb ldr r3, [r7, #28]
80017d8: 08da lsrs r2, r3, #3
80017da: 687b ldr r3, [r7, #4]
80017dc: 3208 adds r2, #8
80017de: 69b9 ldr r1, [r7, #24]
80017e0: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
80017e4: 687b ldr r3, [r7, #4]
80017e6: 681b ldr r3, [r3, #0]
80017e8: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
80017ea: 69fb ldr r3, [r7, #28]
80017ec: 005b lsls r3, r3, #1
80017ee: 2203 movs r2, #3
80017f0: fa02 f303 lsl.w r3, r2, r3
80017f4: 43db mvns r3, r3
80017f6: 69ba ldr r2, [r7, #24]
80017f8: 4013 ands r3, r2
80017fa: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
80017fc: 683b ldr r3, [r7, #0]
80017fe: 685b ldr r3, [r3, #4]
8001800: f003 0203 and.w r2, r3, #3
8001804: 69fb ldr r3, [r7, #28]
8001806: 005b lsls r3, r3, #1
8001808: fa02 f303 lsl.w r3, r2, r3
800180c: 69ba ldr r2, [r7, #24]
800180e: 4313 orrs r3, r2
8001810: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8001812: 687b ldr r3, [r7, #4]
8001814: 69ba ldr r2, [r7, #24]
8001816: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8001818: 683b ldr r3, [r7, #0]
800181a: 685b ldr r3, [r3, #4]
800181c: f403 3340 and.w r3, r3, #196608 @ 0x30000
8001820: 2b00 cmp r3, #0
8001822: f000 80b2 beq.w 800198a <HAL_GPIO_Init+0x2ee>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001826: 4b60 ldr r3, [pc, #384] @ (80019a8 <HAL_GPIO_Init+0x30c>)
8001828: 6c5b ldr r3, [r3, #68] @ 0x44
800182a: 4a5f ldr r2, [pc, #380] @ (80019a8 <HAL_GPIO_Init+0x30c>)
800182c: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8001830: 6453 str r3, [r2, #68] @ 0x44
8001832: 4b5d ldr r3, [pc, #372] @ (80019a8 <HAL_GPIO_Init+0x30c>)
8001834: 6c5b ldr r3, [r3, #68] @ 0x44
8001836: f403 4380 and.w r3, r3, #16384 @ 0x4000
800183a: 60fb str r3, [r7, #12]
800183c: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2];
800183e: 4a5b ldr r2, [pc, #364] @ (80019ac <HAL_GPIO_Init+0x310>)
8001840: 69fb ldr r3, [r7, #28]
8001842: 089b lsrs r3, r3, #2
8001844: 3302 adds r3, #2
8001846: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800184a: 61bb str r3, [r7, #24]
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
800184c: 69fb ldr r3, [r7, #28]
800184e: f003 0303 and.w r3, r3, #3
8001852: 009b lsls r3, r3, #2
8001854: 220f movs r2, #15
8001856: fa02 f303 lsl.w r3, r2, r3
800185a: 43db mvns r3, r3
800185c: 69ba ldr r2, [r7, #24]
800185e: 4013 ands r3, r2
8001860: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
8001862: 687b ldr r3, [r7, #4]
8001864: 4a52 ldr r2, [pc, #328] @ (80019b0 <HAL_GPIO_Init+0x314>)
8001866: 4293 cmp r3, r2
8001868: d02b beq.n 80018c2 <HAL_GPIO_Init+0x226>
800186a: 687b ldr r3, [r7, #4]
800186c: 4a51 ldr r2, [pc, #324] @ (80019b4 <HAL_GPIO_Init+0x318>)
800186e: 4293 cmp r3, r2
8001870: d025 beq.n 80018be <HAL_GPIO_Init+0x222>
8001872: 687b ldr r3, [r7, #4]
8001874: 4a50 ldr r2, [pc, #320] @ (80019b8 <HAL_GPIO_Init+0x31c>)
8001876: 4293 cmp r3, r2
8001878: d01f beq.n 80018ba <HAL_GPIO_Init+0x21e>
800187a: 687b ldr r3, [r7, #4]
800187c: 4a4f ldr r2, [pc, #316] @ (80019bc <HAL_GPIO_Init+0x320>)
800187e: 4293 cmp r3, r2
8001880: d019 beq.n 80018b6 <HAL_GPIO_Init+0x21a>
8001882: 687b ldr r3, [r7, #4]
8001884: 4a4e ldr r2, [pc, #312] @ (80019c0 <HAL_GPIO_Init+0x324>)
8001886: 4293 cmp r3, r2
8001888: d013 beq.n 80018b2 <HAL_GPIO_Init+0x216>
800188a: 687b ldr r3, [r7, #4]
800188c: 4a4d ldr r2, [pc, #308] @ (80019c4 <HAL_GPIO_Init+0x328>)
800188e: 4293 cmp r3, r2
8001890: d00d beq.n 80018ae <HAL_GPIO_Init+0x212>
8001892: 687b ldr r3, [r7, #4]
8001894: 4a4c ldr r2, [pc, #304] @ (80019c8 <HAL_GPIO_Init+0x32c>)
8001896: 4293 cmp r3, r2
8001898: d007 beq.n 80018aa <HAL_GPIO_Init+0x20e>
800189a: 687b ldr r3, [r7, #4]
800189c: 4a4b ldr r2, [pc, #300] @ (80019cc <HAL_GPIO_Init+0x330>)
800189e: 4293 cmp r3, r2
80018a0: d101 bne.n 80018a6 <HAL_GPIO_Init+0x20a>
80018a2: 2307 movs r3, #7
80018a4: e00e b.n 80018c4 <HAL_GPIO_Init+0x228>
80018a6: 2308 movs r3, #8
80018a8: e00c b.n 80018c4 <HAL_GPIO_Init+0x228>
80018aa: 2306 movs r3, #6
80018ac: e00a b.n 80018c4 <HAL_GPIO_Init+0x228>
80018ae: 2305 movs r3, #5
80018b0: e008 b.n 80018c4 <HAL_GPIO_Init+0x228>
80018b2: 2304 movs r3, #4
80018b4: e006 b.n 80018c4 <HAL_GPIO_Init+0x228>
80018b6: 2303 movs r3, #3
80018b8: e004 b.n 80018c4 <HAL_GPIO_Init+0x228>
80018ba: 2302 movs r3, #2
80018bc: e002 b.n 80018c4 <HAL_GPIO_Init+0x228>
80018be: 2301 movs r3, #1
80018c0: e000 b.n 80018c4 <HAL_GPIO_Init+0x228>
80018c2: 2300 movs r3, #0
80018c4: 69fa ldr r2, [r7, #28]
80018c6: f002 0203 and.w r2, r2, #3
80018ca: 0092 lsls r2, r2, #2
80018cc: 4093 lsls r3, r2
80018ce: 69ba ldr r2, [r7, #24]
80018d0: 4313 orrs r3, r2
80018d2: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2] = temp;
80018d4: 4935 ldr r1, [pc, #212] @ (80019ac <HAL_GPIO_Init+0x310>)
80018d6: 69fb ldr r3, [r7, #28]
80018d8: 089b lsrs r3, r3, #2
80018da: 3302 adds r3, #2
80018dc: 69ba ldr r2, [r7, #24]
80018de: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
80018e2: 4b3b ldr r3, [pc, #236] @ (80019d0 <HAL_GPIO_Init+0x334>)
80018e4: 689b ldr r3, [r3, #8]
80018e6: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80018e8: 693b ldr r3, [r7, #16]
80018ea: 43db mvns r3, r3
80018ec: 69ba ldr r2, [r7, #24]
80018ee: 4013 ands r3, r2
80018f0: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
80018f2: 683b ldr r3, [r7, #0]
80018f4: 685b ldr r3, [r3, #4]
80018f6: f403 1380 and.w r3, r3, #1048576 @ 0x100000
80018fa: 2b00 cmp r3, #0
80018fc: d003 beq.n 8001906 <HAL_GPIO_Init+0x26a>
{
temp |= iocurrent;
80018fe: 69ba ldr r2, [r7, #24]
8001900: 693b ldr r3, [r7, #16]
8001902: 4313 orrs r3, r2
8001904: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
8001906: 4a32 ldr r2, [pc, #200] @ (80019d0 <HAL_GPIO_Init+0x334>)
8001908: 69bb ldr r3, [r7, #24]
800190a: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
800190c: 4b30 ldr r3, [pc, #192] @ (80019d0 <HAL_GPIO_Init+0x334>)
800190e: 68db ldr r3, [r3, #12]
8001910: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001912: 693b ldr r3, [r7, #16]
8001914: 43db mvns r3, r3
8001916: 69ba ldr r2, [r7, #24]
8001918: 4013 ands r3, r2
800191a: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
800191c: 683b ldr r3, [r7, #0]
800191e: 685b ldr r3, [r3, #4]
8001920: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8001924: 2b00 cmp r3, #0
8001926: d003 beq.n 8001930 <HAL_GPIO_Init+0x294>
{
temp |= iocurrent;
8001928: 69ba ldr r2, [r7, #24]
800192a: 693b ldr r3, [r7, #16]
800192c: 4313 orrs r3, r2
800192e: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8001930: 4a27 ldr r2, [pc, #156] @ (80019d0 <HAL_GPIO_Init+0x334>)
8001932: 69bb ldr r3, [r7, #24]
8001934: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8001936: 4b26 ldr r3, [pc, #152] @ (80019d0 <HAL_GPIO_Init+0x334>)
8001938: 685b ldr r3, [r3, #4]
800193a: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
800193c: 693b ldr r3, [r7, #16]
800193e: 43db mvns r3, r3
8001940: 69ba ldr r2, [r7, #24]
8001942: 4013 ands r3, r2
8001944: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8001946: 683b ldr r3, [r7, #0]
8001948: 685b ldr r3, [r3, #4]
800194a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800194e: 2b00 cmp r3, #0
8001950: d003 beq.n 800195a <HAL_GPIO_Init+0x2be>
{
temp |= iocurrent;
8001952: 69ba ldr r2, [r7, #24]
8001954: 693b ldr r3, [r7, #16]
8001956: 4313 orrs r3, r2
8001958: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
800195a: 4a1d ldr r2, [pc, #116] @ (80019d0 <HAL_GPIO_Init+0x334>)
800195c: 69bb ldr r3, [r7, #24]
800195e: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8001960: 4b1b ldr r3, [pc, #108] @ (80019d0 <HAL_GPIO_Init+0x334>)
8001962: 681b ldr r3, [r3, #0]
8001964: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001966: 693b ldr r3, [r7, #16]
8001968: 43db mvns r3, r3
800196a: 69ba ldr r2, [r7, #24]
800196c: 4013 ands r3, r2
800196e: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8001970: 683b ldr r3, [r7, #0]
8001972: 685b ldr r3, [r3, #4]
8001974: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001978: 2b00 cmp r3, #0
800197a: d003 beq.n 8001984 <HAL_GPIO_Init+0x2e8>
{
temp |= iocurrent;
800197c: 69ba ldr r2, [r7, #24]
800197e: 693b ldr r3, [r7, #16]
8001980: 4313 orrs r3, r2
8001982: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
8001984: 4a12 ldr r2, [pc, #72] @ (80019d0 <HAL_GPIO_Init+0x334>)
8001986: 69bb ldr r3, [r7, #24]
8001988: 6013 str r3, [r2, #0]
for (position = 0; position < GPIO_NUMBER; position++)
800198a: 69fb ldr r3, [r7, #28]
800198c: 3301 adds r3, #1
800198e: 61fb str r3, [r7, #28]
8001990: 69fb ldr r3, [r7, #28]
8001992: 2b0f cmp r3, #15
8001994: f67f ae92 bls.w 80016bc <HAL_GPIO_Init+0x20>
}
}
}
}
8001998: bf00 nop
800199a: bf00 nop
800199c: 3724 adds r7, #36 @ 0x24
800199e: 46bd mov sp, r7
80019a0: f85d 7b04 ldr.w r7, [sp], #4
80019a4: 4770 bx lr
80019a6: bf00 nop
80019a8: 40023800 .word 0x40023800
80019ac: 40013800 .word 0x40013800
80019b0: 40020000 .word 0x40020000
80019b4: 40020400 .word 0x40020400
80019b8: 40020800 .word 0x40020800
80019bc: 40020c00 .word 0x40020c00
80019c0: 40021000 .word 0x40021000
80019c4: 40021400 .word 0x40021400
80019c8: 40021800 .word 0x40021800
80019cc: 40021c00 .word 0x40021c00
80019d0: 40013c00 .word 0x40013c00
080019d4 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
80019d4: b480 push {r7}
80019d6: b085 sub sp, #20
80019d8: af00 add r7, sp, #0
80019da: 6078 str r0, [r7, #4]
80019dc: 460b mov r3, r1
80019de: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
80019e0: 687b ldr r3, [r7, #4]
80019e2: 691a ldr r2, [r3, #16]
80019e4: 887b ldrh r3, [r7, #2]
80019e6: 4013 ands r3, r2
80019e8: 2b00 cmp r3, #0
80019ea: d002 beq.n 80019f2 <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
80019ec: 2301 movs r3, #1
80019ee: 73fb strb r3, [r7, #15]
80019f0: e001 b.n 80019f6 <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
80019f2: 2300 movs r3, #0
80019f4: 73fb strb r3, [r7, #15]
}
return bitstatus;
80019f6: 7bfb ldrb r3, [r7, #15]
}
80019f8: 4618 mov r0, r3
80019fa: 3714 adds r7, #20
80019fc: 46bd mov sp, r7
80019fe: f85d 7b04 ldr.w r7, [sp], #4
8001a02: 4770 bx lr
08001a04 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001a04: b480 push {r7}
8001a06: b083 sub sp, #12
8001a08: af00 add r7, sp, #0
8001a0a: 6078 str r0, [r7, #4]
8001a0c: 460b mov r3, r1
8001a0e: 807b strh r3, [r7, #2]
8001a10: 4613 mov r3, r2
8001a12: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8001a14: 787b ldrb r3, [r7, #1]
8001a16: 2b00 cmp r3, #0
8001a18: d003 beq.n 8001a22 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8001a1a: 887a ldrh r2, [r7, #2]
8001a1c: 687b ldr r3, [r7, #4]
8001a1e: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
}
}
8001a20: e003 b.n 8001a2a <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
8001a22: 887b ldrh r3, [r7, #2]
8001a24: 041a lsls r2, r3, #16
8001a26: 687b ldr r3, [r7, #4]
8001a28: 619a str r2, [r3, #24]
}
8001a2a: bf00 nop
8001a2c: 370c adds r7, #12
8001a2e: 46bd mov sp, r7
8001a30: f85d 7b04 ldr.w r7, [sp], #4
8001a34: 4770 bx lr
08001a36 <HAL_GPIO_TogglePin>:
* @param GPIO_Pin Specifies the pins to be toggled.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
8001a36: b480 push {r7}
8001a38: b085 sub sp, #20
8001a3a: af00 add r7, sp, #0
8001a3c: 6078 str r0, [r7, #4]
8001a3e: 460b mov r3, r1
8001a40: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
8001a42: 687b ldr r3, [r7, #4]
8001a44: 695b ldr r3, [r3, #20]
8001a46: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
8001a48: 887a ldrh r2, [r7, #2]
8001a4a: 68fb ldr r3, [r7, #12]
8001a4c: 4013 ands r3, r2
8001a4e: 041a lsls r2, r3, #16
8001a50: 68fb ldr r3, [r7, #12]
8001a52: 43d9 mvns r1, r3
8001a54: 887b ldrh r3, [r7, #2]
8001a56: 400b ands r3, r1
8001a58: 431a orrs r2, r3
8001a5a: 687b ldr r3, [r7, #4]
8001a5c: 619a str r2, [r3, #24]
}
8001a5e: bf00 nop
8001a60: 3714 adds r7, #20
8001a62: 46bd mov sp, r7
8001a64: f85d 7b04 ldr.w r7, [sp], #4
8001a68: 4770 bx lr
...
08001a6c <HAL_PWR_EnableBkUpAccess>:
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
8001a6c: b480 push {r7}
8001a6e: af00 add r7, sp, #0
/* Enable access to RTC and backup registers */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8001a70: 4b05 ldr r3, [pc, #20] @ (8001a88 <HAL_PWR_EnableBkUpAccess+0x1c>)
8001a72: 681b ldr r3, [r3, #0]
8001a74: 4a04 ldr r2, [pc, #16] @ (8001a88 <HAL_PWR_EnableBkUpAccess+0x1c>)
8001a76: f443 7380 orr.w r3, r3, #256 @ 0x100
8001a7a: 6013 str r3, [r2, #0]
}
8001a7c: bf00 nop
8001a7e: 46bd mov sp, r7
8001a80: f85d 7b04 ldr.w r7, [sp], #4
8001a84: 4770 bx lr
8001a86: bf00 nop
8001a88: 40007000 .word 0x40007000
08001a8c <HAL_PWREx_EnableOverDrive>:
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
{
8001a8c: b580 push {r7, lr}
8001a8e: b082 sub sp, #8
8001a90: af00 add r7, sp, #0
uint32_t tickstart = 0;
8001a92: 2300 movs r3, #0
8001a94: 607b str r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8001a96: 4b23 ldr r3, [pc, #140] @ (8001b24 <HAL_PWREx_EnableOverDrive+0x98>)
8001a98: 6c1b ldr r3, [r3, #64] @ 0x40
8001a9a: 4a22 ldr r2, [pc, #136] @ (8001b24 <HAL_PWREx_EnableOverDrive+0x98>)
8001a9c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001aa0: 6413 str r3, [r2, #64] @ 0x40
8001aa2: 4b20 ldr r3, [pc, #128] @ (8001b24 <HAL_PWREx_EnableOverDrive+0x98>)
8001aa4: 6c1b ldr r3, [r3, #64] @ 0x40
8001aa6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001aaa: 603b str r3, [r7, #0]
8001aac: 683b ldr r3, [r7, #0]
/* Enable the Over-drive to extend the clock frequency to 216 MHz */
__HAL_PWR_OVERDRIVE_ENABLE();
8001aae: 4b1e ldr r3, [pc, #120] @ (8001b28 <HAL_PWREx_EnableOverDrive+0x9c>)
8001ab0: 681b ldr r3, [r3, #0]
8001ab2: 4a1d ldr r2, [pc, #116] @ (8001b28 <HAL_PWREx_EnableOverDrive+0x9c>)
8001ab4: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001ab8: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8001aba: f7ff fd01 bl 80014c0 <HAL_GetTick>
8001abe: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
8001ac0: e009 b.n 8001ad6 <HAL_PWREx_EnableOverDrive+0x4a>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8001ac2: f7ff fcfd bl 80014c0 <HAL_GetTick>
8001ac6: 4602 mov r2, r0
8001ac8: 687b ldr r3, [r7, #4]
8001aca: 1ad3 subs r3, r2, r3
8001acc: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
8001ad0: d901 bls.n 8001ad6 <HAL_PWREx_EnableOverDrive+0x4a>
{
return HAL_TIMEOUT;
8001ad2: 2303 movs r3, #3
8001ad4: e022 b.n 8001b1c <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
8001ad6: 4b14 ldr r3, [pc, #80] @ (8001b28 <HAL_PWREx_EnableOverDrive+0x9c>)
8001ad8: 685b ldr r3, [r3, #4]
8001ada: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001ade: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8001ae2: d1ee bne.n 8001ac2 <HAL_PWREx_EnableOverDrive+0x36>
}
}
/* Enable the Over-drive switch */
__HAL_PWR_OVERDRIVESWITCHING_ENABLE();
8001ae4: 4b10 ldr r3, [pc, #64] @ (8001b28 <HAL_PWREx_EnableOverDrive+0x9c>)
8001ae6: 681b ldr r3, [r3, #0]
8001ae8: 4a0f ldr r2, [pc, #60] @ (8001b28 <HAL_PWREx_EnableOverDrive+0x9c>)
8001aea: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8001aee: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8001af0: f7ff fce6 bl 80014c0 <HAL_GetTick>
8001af4: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
8001af6: e009 b.n 8001b0c <HAL_PWREx_EnableOverDrive+0x80>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8001af8: f7ff fce2 bl 80014c0 <HAL_GetTick>
8001afc: 4602 mov r2, r0
8001afe: 687b ldr r3, [r7, #4]
8001b00: 1ad3 subs r3, r2, r3
8001b02: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
8001b06: d901 bls.n 8001b0c <HAL_PWREx_EnableOverDrive+0x80>
{
return HAL_TIMEOUT;
8001b08: 2303 movs r3, #3
8001b0a: e007 b.n 8001b1c <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
8001b0c: 4b06 ldr r3, [pc, #24] @ (8001b28 <HAL_PWREx_EnableOverDrive+0x9c>)
8001b0e: 685b ldr r3, [r3, #4]
8001b10: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001b14: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
8001b18: d1ee bne.n 8001af8 <HAL_PWREx_EnableOverDrive+0x6c>
}
}
return HAL_OK;
8001b1a: 2300 movs r3, #0
}
8001b1c: 4618 mov r0, r3
8001b1e: 3708 adds r7, #8
8001b20: 46bd mov sp, r7
8001b22: bd80 pop {r7, pc}
8001b24: 40023800 .word 0x40023800
8001b28: 40007000 .word 0x40007000
08001b2c <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8001b2c: b580 push {r7, lr}
8001b2e: b086 sub sp, #24
8001b30: af00 add r7, sp, #0
8001b32: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
FlagStatus pwrclkchanged = RESET;
8001b34: 2300 movs r3, #0
8001b36: 75fb strb r3, [r7, #23]
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8001b38: 687b ldr r3, [r7, #4]
8001b3a: 2b00 cmp r3, #0
8001b3c: d101 bne.n 8001b42 <HAL_RCC_OscConfig+0x16>
{
return HAL_ERROR;
8001b3e: 2301 movs r3, #1
8001b40: e291 b.n 8002066 <HAL_RCC_OscConfig+0x53a>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8001b42: 687b ldr r3, [r7, #4]
8001b44: 681b ldr r3, [r3, #0]
8001b46: f003 0301 and.w r3, r3, #1
8001b4a: 2b00 cmp r3, #0
8001b4c: f000 8087 beq.w 8001c5e <HAL_RCC_OscConfig+0x132>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8001b50: 4b96 ldr r3, [pc, #600] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001b52: 689b ldr r3, [r3, #8]
8001b54: f003 030c and.w r3, r3, #12
8001b58: 2b04 cmp r3, #4
8001b5a: d00c beq.n 8001b76 <HAL_RCC_OscConfig+0x4a>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8001b5c: 4b93 ldr r3, [pc, #588] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001b5e: 689b ldr r3, [r3, #8]
8001b60: f003 030c and.w r3, r3, #12
8001b64: 2b08 cmp r3, #8
8001b66: d112 bne.n 8001b8e <HAL_RCC_OscConfig+0x62>
8001b68: 4b90 ldr r3, [pc, #576] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001b6a: 685b ldr r3, [r3, #4]
8001b6c: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8001b70: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8001b74: d10b bne.n 8001b8e <HAL_RCC_OscConfig+0x62>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001b76: 4b8d ldr r3, [pc, #564] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001b78: 681b ldr r3, [r3, #0]
8001b7a: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001b7e: 2b00 cmp r3, #0
8001b80: d06c beq.n 8001c5c <HAL_RCC_OscConfig+0x130>
8001b82: 687b ldr r3, [r7, #4]
8001b84: 685b ldr r3, [r3, #4]
8001b86: 2b00 cmp r3, #0
8001b88: d168 bne.n 8001c5c <HAL_RCC_OscConfig+0x130>
{
return HAL_ERROR;
8001b8a: 2301 movs r3, #1
8001b8c: e26b b.n 8002066 <HAL_RCC_OscConfig+0x53a>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8001b8e: 687b ldr r3, [r7, #4]
8001b90: 685b ldr r3, [r3, #4]
8001b92: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8001b96: d106 bne.n 8001ba6 <HAL_RCC_OscConfig+0x7a>
8001b98: 4b84 ldr r3, [pc, #528] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001b9a: 681b ldr r3, [r3, #0]
8001b9c: 4a83 ldr r2, [pc, #524] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001b9e: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001ba2: 6013 str r3, [r2, #0]
8001ba4: e02e b.n 8001c04 <HAL_RCC_OscConfig+0xd8>
8001ba6: 687b ldr r3, [r7, #4]
8001ba8: 685b ldr r3, [r3, #4]
8001baa: 2b00 cmp r3, #0
8001bac: d10c bne.n 8001bc8 <HAL_RCC_OscConfig+0x9c>
8001bae: 4b7f ldr r3, [pc, #508] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001bb0: 681b ldr r3, [r3, #0]
8001bb2: 4a7e ldr r2, [pc, #504] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001bb4: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8001bb8: 6013 str r3, [r2, #0]
8001bba: 4b7c ldr r3, [pc, #496] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001bbc: 681b ldr r3, [r3, #0]
8001bbe: 4a7b ldr r2, [pc, #492] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001bc0: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8001bc4: 6013 str r3, [r2, #0]
8001bc6: e01d b.n 8001c04 <HAL_RCC_OscConfig+0xd8>
8001bc8: 687b ldr r3, [r7, #4]
8001bca: 685b ldr r3, [r3, #4]
8001bcc: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8001bd0: d10c bne.n 8001bec <HAL_RCC_OscConfig+0xc0>
8001bd2: 4b76 ldr r3, [pc, #472] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001bd4: 681b ldr r3, [r3, #0]
8001bd6: 4a75 ldr r2, [pc, #468] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001bd8: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8001bdc: 6013 str r3, [r2, #0]
8001bde: 4b73 ldr r3, [pc, #460] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001be0: 681b ldr r3, [r3, #0]
8001be2: 4a72 ldr r2, [pc, #456] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001be4: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001be8: 6013 str r3, [r2, #0]
8001bea: e00b b.n 8001c04 <HAL_RCC_OscConfig+0xd8>
8001bec: 4b6f ldr r3, [pc, #444] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001bee: 681b ldr r3, [r3, #0]
8001bf0: 4a6e ldr r2, [pc, #440] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001bf2: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8001bf6: 6013 str r3, [r2, #0]
8001bf8: 4b6c ldr r3, [pc, #432] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001bfa: 681b ldr r3, [r3, #0]
8001bfc: 4a6b ldr r2, [pc, #428] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001bfe: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8001c02: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8001c04: 687b ldr r3, [r7, #4]
8001c06: 685b ldr r3, [r3, #4]
8001c08: 2b00 cmp r3, #0
8001c0a: d013 beq.n 8001c34 <HAL_RCC_OscConfig+0x108>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001c0c: f7ff fc58 bl 80014c0 <HAL_GetTick>
8001c10: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001c12: e008 b.n 8001c26 <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8001c14: f7ff fc54 bl 80014c0 <HAL_GetTick>
8001c18: 4602 mov r2, r0
8001c1a: 693b ldr r3, [r7, #16]
8001c1c: 1ad3 subs r3, r2, r3
8001c1e: 2b64 cmp r3, #100 @ 0x64
8001c20: d901 bls.n 8001c26 <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
8001c22: 2303 movs r3, #3
8001c24: e21f b.n 8002066 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001c26: 4b61 ldr r3, [pc, #388] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001c28: 681b ldr r3, [r3, #0]
8001c2a: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001c2e: 2b00 cmp r3, #0
8001c30: d0f0 beq.n 8001c14 <HAL_RCC_OscConfig+0xe8>
8001c32: e014 b.n 8001c5e <HAL_RCC_OscConfig+0x132>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001c34: f7ff fc44 bl 80014c0 <HAL_GetTick>
8001c38: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8001c3a: e008 b.n 8001c4e <HAL_RCC_OscConfig+0x122>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8001c3c: f7ff fc40 bl 80014c0 <HAL_GetTick>
8001c40: 4602 mov r2, r0
8001c42: 693b ldr r3, [r7, #16]
8001c44: 1ad3 subs r3, r2, r3
8001c46: 2b64 cmp r3, #100 @ 0x64
8001c48: d901 bls.n 8001c4e <HAL_RCC_OscConfig+0x122>
{
return HAL_TIMEOUT;
8001c4a: 2303 movs r3, #3
8001c4c: e20b b.n 8002066 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8001c4e: 4b57 ldr r3, [pc, #348] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001c50: 681b ldr r3, [r3, #0]
8001c52: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001c56: 2b00 cmp r3, #0
8001c58: d1f0 bne.n 8001c3c <HAL_RCC_OscConfig+0x110>
8001c5a: e000 b.n 8001c5e <HAL_RCC_OscConfig+0x132>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001c5c: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8001c5e: 687b ldr r3, [r7, #4]
8001c60: 681b ldr r3, [r3, #0]
8001c62: f003 0302 and.w r3, r3, #2
8001c66: 2b00 cmp r3, #0
8001c68: d069 beq.n 8001d3e <HAL_RCC_OscConfig+0x212>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8001c6a: 4b50 ldr r3, [pc, #320] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001c6c: 689b ldr r3, [r3, #8]
8001c6e: f003 030c and.w r3, r3, #12
8001c72: 2b00 cmp r3, #0
8001c74: d00b beq.n 8001c8e <HAL_RCC_OscConfig+0x162>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
8001c76: 4b4d ldr r3, [pc, #308] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001c78: 689b ldr r3, [r3, #8]
8001c7a: f003 030c and.w r3, r3, #12
8001c7e: 2b08 cmp r3, #8
8001c80: d11c bne.n 8001cbc <HAL_RCC_OscConfig+0x190>
8001c82: 4b4a ldr r3, [pc, #296] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001c84: 685b ldr r3, [r3, #4]
8001c86: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8001c8a: 2b00 cmp r3, #0
8001c8c: d116 bne.n 8001cbc <HAL_RCC_OscConfig+0x190>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001c8e: 4b47 ldr r3, [pc, #284] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001c90: 681b ldr r3, [r3, #0]
8001c92: f003 0302 and.w r3, r3, #2
8001c96: 2b00 cmp r3, #0
8001c98: d005 beq.n 8001ca6 <HAL_RCC_OscConfig+0x17a>
8001c9a: 687b ldr r3, [r7, #4]
8001c9c: 68db ldr r3, [r3, #12]
8001c9e: 2b01 cmp r3, #1
8001ca0: d001 beq.n 8001ca6 <HAL_RCC_OscConfig+0x17a>
{
return HAL_ERROR;
8001ca2: 2301 movs r3, #1
8001ca4: e1df b.n 8002066 <HAL_RCC_OscConfig+0x53a>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001ca6: 4b41 ldr r3, [pc, #260] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001ca8: 681b ldr r3, [r3, #0]
8001caa: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8001cae: 687b ldr r3, [r7, #4]
8001cb0: 691b ldr r3, [r3, #16]
8001cb2: 00db lsls r3, r3, #3
8001cb4: 493d ldr r1, [pc, #244] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001cb6: 4313 orrs r3, r2
8001cb8: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001cba: e040 b.n 8001d3e <HAL_RCC_OscConfig+0x212>
}
}
else
{
/* Check the HSI State */
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
8001cbc: 687b ldr r3, [r7, #4]
8001cbe: 68db ldr r3, [r3, #12]
8001cc0: 2b00 cmp r3, #0
8001cc2: d023 beq.n 8001d0c <HAL_RCC_OscConfig+0x1e0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8001cc4: 4b39 ldr r3, [pc, #228] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001cc6: 681b ldr r3, [r3, #0]
8001cc8: 4a38 ldr r2, [pc, #224] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001cca: f043 0301 orr.w r3, r3, #1
8001cce: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001cd0: f7ff fbf6 bl 80014c0 <HAL_GetTick>
8001cd4: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001cd6: e008 b.n 8001cea <HAL_RCC_OscConfig+0x1be>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8001cd8: f7ff fbf2 bl 80014c0 <HAL_GetTick>
8001cdc: 4602 mov r2, r0
8001cde: 693b ldr r3, [r7, #16]
8001ce0: 1ad3 subs r3, r2, r3
8001ce2: 2b02 cmp r3, #2
8001ce4: d901 bls.n 8001cea <HAL_RCC_OscConfig+0x1be>
{
return HAL_TIMEOUT;
8001ce6: 2303 movs r3, #3
8001ce8: e1bd b.n 8002066 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001cea: 4b30 ldr r3, [pc, #192] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001cec: 681b ldr r3, [r3, #0]
8001cee: f003 0302 and.w r3, r3, #2
8001cf2: 2b00 cmp r3, #0
8001cf4: d0f0 beq.n 8001cd8 <HAL_RCC_OscConfig+0x1ac>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001cf6: 4b2d ldr r3, [pc, #180] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001cf8: 681b ldr r3, [r3, #0]
8001cfa: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8001cfe: 687b ldr r3, [r7, #4]
8001d00: 691b ldr r3, [r3, #16]
8001d02: 00db lsls r3, r3, #3
8001d04: 4929 ldr r1, [pc, #164] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001d06: 4313 orrs r3, r2
8001d08: 600b str r3, [r1, #0]
8001d0a: e018 b.n 8001d3e <HAL_RCC_OscConfig+0x212>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001d0c: 4b27 ldr r3, [pc, #156] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001d0e: 681b ldr r3, [r3, #0]
8001d10: 4a26 ldr r2, [pc, #152] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001d12: f023 0301 bic.w r3, r3, #1
8001d16: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001d18: f7ff fbd2 bl 80014c0 <HAL_GetTick>
8001d1c: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001d1e: e008 b.n 8001d32 <HAL_RCC_OscConfig+0x206>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8001d20: f7ff fbce bl 80014c0 <HAL_GetTick>
8001d24: 4602 mov r2, r0
8001d26: 693b ldr r3, [r7, #16]
8001d28: 1ad3 subs r3, r2, r3
8001d2a: 2b02 cmp r3, #2
8001d2c: d901 bls.n 8001d32 <HAL_RCC_OscConfig+0x206>
{
return HAL_TIMEOUT;
8001d2e: 2303 movs r3, #3
8001d30: e199 b.n 8002066 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001d32: 4b1e ldr r3, [pc, #120] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001d34: 681b ldr r3, [r3, #0]
8001d36: f003 0302 and.w r3, r3, #2
8001d3a: 2b00 cmp r3, #0
8001d3c: d1f0 bne.n 8001d20 <HAL_RCC_OscConfig+0x1f4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8001d3e: 687b ldr r3, [r7, #4]
8001d40: 681b ldr r3, [r3, #0]
8001d42: f003 0308 and.w r3, r3, #8
8001d46: 2b00 cmp r3, #0
8001d48: d038 beq.n 8001dbc <HAL_RCC_OscConfig+0x290>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
8001d4a: 687b ldr r3, [r7, #4]
8001d4c: 695b ldr r3, [r3, #20]
8001d4e: 2b00 cmp r3, #0
8001d50: d019 beq.n 8001d86 <HAL_RCC_OscConfig+0x25a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001d52: 4b16 ldr r3, [pc, #88] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001d54: 6f5b ldr r3, [r3, #116] @ 0x74
8001d56: 4a15 ldr r2, [pc, #84] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001d58: f043 0301 orr.w r3, r3, #1
8001d5c: 6753 str r3, [r2, #116] @ 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001d5e: f7ff fbaf bl 80014c0 <HAL_GetTick>
8001d62: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001d64: e008 b.n 8001d78 <HAL_RCC_OscConfig+0x24c>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8001d66: f7ff fbab bl 80014c0 <HAL_GetTick>
8001d6a: 4602 mov r2, r0
8001d6c: 693b ldr r3, [r7, #16]
8001d6e: 1ad3 subs r3, r2, r3
8001d70: 2b02 cmp r3, #2
8001d72: d901 bls.n 8001d78 <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
8001d74: 2303 movs r3, #3
8001d76: e176 b.n 8002066 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001d78: 4b0c ldr r3, [pc, #48] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001d7a: 6f5b ldr r3, [r3, #116] @ 0x74
8001d7c: f003 0302 and.w r3, r3, #2
8001d80: 2b00 cmp r3, #0
8001d82: d0f0 beq.n 8001d66 <HAL_RCC_OscConfig+0x23a>
8001d84: e01a b.n 8001dbc <HAL_RCC_OscConfig+0x290>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001d86: 4b09 ldr r3, [pc, #36] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001d88: 6f5b ldr r3, [r3, #116] @ 0x74
8001d8a: 4a08 ldr r2, [pc, #32] @ (8001dac <HAL_RCC_OscConfig+0x280>)
8001d8c: f023 0301 bic.w r3, r3, #1
8001d90: 6753 str r3, [r2, #116] @ 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001d92: f7ff fb95 bl 80014c0 <HAL_GetTick>
8001d96: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001d98: e00a b.n 8001db0 <HAL_RCC_OscConfig+0x284>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8001d9a: f7ff fb91 bl 80014c0 <HAL_GetTick>
8001d9e: 4602 mov r2, r0
8001da0: 693b ldr r3, [r7, #16]
8001da2: 1ad3 subs r3, r2, r3
8001da4: 2b02 cmp r3, #2
8001da6: d903 bls.n 8001db0 <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
8001da8: 2303 movs r3, #3
8001daa: e15c b.n 8002066 <HAL_RCC_OscConfig+0x53a>
8001dac: 40023800 .word 0x40023800
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001db0: 4b91 ldr r3, [pc, #580] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001db2: 6f5b ldr r3, [r3, #116] @ 0x74
8001db4: f003 0302 and.w r3, r3, #2
8001db8: 2b00 cmp r3, #0
8001dba: d1ee bne.n 8001d9a <HAL_RCC_OscConfig+0x26e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8001dbc: 687b ldr r3, [r7, #4]
8001dbe: 681b ldr r3, [r3, #0]
8001dc0: f003 0304 and.w r3, r3, #4
8001dc4: 2b00 cmp r3, #0
8001dc6: f000 80a4 beq.w 8001f12 <HAL_RCC_OscConfig+0x3e6>
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8001dca: 4b8b ldr r3, [pc, #556] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001dcc: 6c1b ldr r3, [r3, #64] @ 0x40
8001dce: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001dd2: 2b00 cmp r3, #0
8001dd4: d10d bne.n 8001df2 <HAL_RCC_OscConfig+0x2c6>
{
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
8001dd6: 4b88 ldr r3, [pc, #544] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001dd8: 6c1b ldr r3, [r3, #64] @ 0x40
8001dda: 4a87 ldr r2, [pc, #540] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001ddc: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001de0: 6413 str r3, [r2, #64] @ 0x40
8001de2: 4b85 ldr r3, [pc, #532] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001de4: 6c1b ldr r3, [r3, #64] @ 0x40
8001de6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001dea: 60bb str r3, [r7, #8]
8001dec: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8001dee: 2301 movs r3, #1
8001df0: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001df2: 4b82 ldr r3, [pc, #520] @ (8001ffc <HAL_RCC_OscConfig+0x4d0>)
8001df4: 681b ldr r3, [r3, #0]
8001df6: f403 7380 and.w r3, r3, #256 @ 0x100
8001dfa: 2b00 cmp r3, #0
8001dfc: d118 bne.n 8001e30 <HAL_RCC_OscConfig+0x304>
{
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
8001dfe: 4b7f ldr r3, [pc, #508] @ (8001ffc <HAL_RCC_OscConfig+0x4d0>)
8001e00: 681b ldr r3, [r3, #0]
8001e02: 4a7e ldr r2, [pc, #504] @ (8001ffc <HAL_RCC_OscConfig+0x4d0>)
8001e04: f443 7380 orr.w r3, r3, #256 @ 0x100
8001e08: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8001e0a: f7ff fb59 bl 80014c0 <HAL_GetTick>
8001e0e: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001e10: e008 b.n 8001e24 <HAL_RCC_OscConfig+0x2f8>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001e12: f7ff fb55 bl 80014c0 <HAL_GetTick>
8001e16: 4602 mov r2, r0
8001e18: 693b ldr r3, [r7, #16]
8001e1a: 1ad3 subs r3, r2, r3
8001e1c: 2b64 cmp r3, #100 @ 0x64
8001e1e: d901 bls.n 8001e24 <HAL_RCC_OscConfig+0x2f8>
{
return HAL_TIMEOUT;
8001e20: 2303 movs r3, #3
8001e22: e120 b.n 8002066 <HAL_RCC_OscConfig+0x53a>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001e24: 4b75 ldr r3, [pc, #468] @ (8001ffc <HAL_RCC_OscConfig+0x4d0>)
8001e26: 681b ldr r3, [r3, #0]
8001e28: f403 7380 and.w r3, r3, #256 @ 0x100
8001e2c: 2b00 cmp r3, #0
8001e2e: d0f0 beq.n 8001e12 <HAL_RCC_OscConfig+0x2e6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001e30: 687b ldr r3, [r7, #4]
8001e32: 689b ldr r3, [r3, #8]
8001e34: 2b01 cmp r3, #1
8001e36: d106 bne.n 8001e46 <HAL_RCC_OscConfig+0x31a>
8001e38: 4b6f ldr r3, [pc, #444] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001e3a: 6f1b ldr r3, [r3, #112] @ 0x70
8001e3c: 4a6e ldr r2, [pc, #440] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001e3e: f043 0301 orr.w r3, r3, #1
8001e42: 6713 str r3, [r2, #112] @ 0x70
8001e44: e02d b.n 8001ea2 <HAL_RCC_OscConfig+0x376>
8001e46: 687b ldr r3, [r7, #4]
8001e48: 689b ldr r3, [r3, #8]
8001e4a: 2b00 cmp r3, #0
8001e4c: d10c bne.n 8001e68 <HAL_RCC_OscConfig+0x33c>
8001e4e: 4b6a ldr r3, [pc, #424] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001e50: 6f1b ldr r3, [r3, #112] @ 0x70
8001e52: 4a69 ldr r2, [pc, #420] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001e54: f023 0301 bic.w r3, r3, #1
8001e58: 6713 str r3, [r2, #112] @ 0x70
8001e5a: 4b67 ldr r3, [pc, #412] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001e5c: 6f1b ldr r3, [r3, #112] @ 0x70
8001e5e: 4a66 ldr r2, [pc, #408] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001e60: f023 0304 bic.w r3, r3, #4
8001e64: 6713 str r3, [r2, #112] @ 0x70
8001e66: e01c b.n 8001ea2 <HAL_RCC_OscConfig+0x376>
8001e68: 687b ldr r3, [r7, #4]
8001e6a: 689b ldr r3, [r3, #8]
8001e6c: 2b05 cmp r3, #5
8001e6e: d10c bne.n 8001e8a <HAL_RCC_OscConfig+0x35e>
8001e70: 4b61 ldr r3, [pc, #388] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001e72: 6f1b ldr r3, [r3, #112] @ 0x70
8001e74: 4a60 ldr r2, [pc, #384] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001e76: f043 0304 orr.w r3, r3, #4
8001e7a: 6713 str r3, [r2, #112] @ 0x70
8001e7c: 4b5e ldr r3, [pc, #376] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001e7e: 6f1b ldr r3, [r3, #112] @ 0x70
8001e80: 4a5d ldr r2, [pc, #372] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001e82: f043 0301 orr.w r3, r3, #1
8001e86: 6713 str r3, [r2, #112] @ 0x70
8001e88: e00b b.n 8001ea2 <HAL_RCC_OscConfig+0x376>
8001e8a: 4b5b ldr r3, [pc, #364] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001e8c: 6f1b ldr r3, [r3, #112] @ 0x70
8001e8e: 4a5a ldr r2, [pc, #360] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001e90: f023 0301 bic.w r3, r3, #1
8001e94: 6713 str r3, [r2, #112] @ 0x70
8001e96: 4b58 ldr r3, [pc, #352] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001e98: 6f1b ldr r3, [r3, #112] @ 0x70
8001e9a: 4a57 ldr r2, [pc, #348] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001e9c: f023 0304 bic.w r3, r3, #4
8001ea0: 6713 str r3, [r2, #112] @ 0x70
/* Check the LSE State */
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8001ea2: 687b ldr r3, [r7, #4]
8001ea4: 689b ldr r3, [r3, #8]
8001ea6: 2b00 cmp r3, #0
8001ea8: d015 beq.n 8001ed6 <HAL_RCC_OscConfig+0x3aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001eaa: f7ff fb09 bl 80014c0 <HAL_GetTick>
8001eae: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001eb0: e00a b.n 8001ec8 <HAL_RCC_OscConfig+0x39c>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8001eb2: f7ff fb05 bl 80014c0 <HAL_GetTick>
8001eb6: 4602 mov r2, r0
8001eb8: 693b ldr r3, [r7, #16]
8001eba: 1ad3 subs r3, r2, r3
8001ebc: f241 3288 movw r2, #5000 @ 0x1388
8001ec0: 4293 cmp r3, r2
8001ec2: d901 bls.n 8001ec8 <HAL_RCC_OscConfig+0x39c>
{
return HAL_TIMEOUT;
8001ec4: 2303 movs r3, #3
8001ec6: e0ce b.n 8002066 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001ec8: 4b4b ldr r3, [pc, #300] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001eca: 6f1b ldr r3, [r3, #112] @ 0x70
8001ecc: f003 0302 and.w r3, r3, #2
8001ed0: 2b00 cmp r3, #0
8001ed2: d0ee beq.n 8001eb2 <HAL_RCC_OscConfig+0x386>
8001ed4: e014 b.n 8001f00 <HAL_RCC_OscConfig+0x3d4>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001ed6: f7ff faf3 bl 80014c0 <HAL_GetTick>
8001eda: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001edc: e00a b.n 8001ef4 <HAL_RCC_OscConfig+0x3c8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8001ede: f7ff faef bl 80014c0 <HAL_GetTick>
8001ee2: 4602 mov r2, r0
8001ee4: 693b ldr r3, [r7, #16]
8001ee6: 1ad3 subs r3, r2, r3
8001ee8: f241 3288 movw r2, #5000 @ 0x1388
8001eec: 4293 cmp r3, r2
8001eee: d901 bls.n 8001ef4 <HAL_RCC_OscConfig+0x3c8>
{
return HAL_TIMEOUT;
8001ef0: 2303 movs r3, #3
8001ef2: e0b8 b.n 8002066 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001ef4: 4b40 ldr r3, [pc, #256] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001ef6: 6f1b ldr r3, [r3, #112] @ 0x70
8001ef8: f003 0302 and.w r3, r3, #2
8001efc: 2b00 cmp r3, #0
8001efe: d1ee bne.n 8001ede <HAL_RCC_OscConfig+0x3b2>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
8001f00: 7dfb ldrb r3, [r7, #23]
8001f02: 2b01 cmp r3, #1
8001f04: d105 bne.n 8001f12 <HAL_RCC_OscConfig+0x3e6>
{
__HAL_RCC_PWR_CLK_DISABLE();
8001f06: 4b3c ldr r3, [pc, #240] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001f08: 6c1b ldr r3, [r3, #64] @ 0x40
8001f0a: 4a3b ldr r2, [pc, #236] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001f0c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8001f10: 6413 str r3, [r2, #64] @ 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8001f12: 687b ldr r3, [r7, #4]
8001f14: 699b ldr r3, [r3, #24]
8001f16: 2b00 cmp r3, #0
8001f18: f000 80a4 beq.w 8002064 <HAL_RCC_OscConfig+0x538>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8001f1c: 4b36 ldr r3, [pc, #216] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001f1e: 689b ldr r3, [r3, #8]
8001f20: f003 030c and.w r3, r3, #12
8001f24: 2b08 cmp r3, #8
8001f26: d06b beq.n 8002000 <HAL_RCC_OscConfig+0x4d4>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8001f28: 687b ldr r3, [r7, #4]
8001f2a: 699b ldr r3, [r3, #24]
8001f2c: 2b02 cmp r3, #2
8001f2e: d149 bne.n 8001fc4 <HAL_RCC_OscConfig+0x498>
#if defined (RCC_PLLCFGR_PLLR)
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001f30: 4b31 ldr r3, [pc, #196] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001f32: 681b ldr r3, [r3, #0]
8001f34: 4a30 ldr r2, [pc, #192] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001f36: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8001f3a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001f3c: f7ff fac0 bl 80014c0 <HAL_GetTick>
8001f40: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001f42: e008 b.n 8001f56 <HAL_RCC_OscConfig+0x42a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001f44: f7ff fabc bl 80014c0 <HAL_GetTick>
8001f48: 4602 mov r2, r0
8001f4a: 693b ldr r3, [r7, #16]
8001f4c: 1ad3 subs r3, r2, r3
8001f4e: 2b02 cmp r3, #2
8001f50: d901 bls.n 8001f56 <HAL_RCC_OscConfig+0x42a>
{
return HAL_TIMEOUT;
8001f52: 2303 movs r3, #3
8001f54: e087 b.n 8002066 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001f56: 4b28 ldr r3, [pc, #160] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001f58: 681b ldr r3, [r3, #0]
8001f5a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8001f5e: 2b00 cmp r3, #0
8001f60: d1f0 bne.n 8001f44 <HAL_RCC_OscConfig+0x418>
RCC_OscInitStruct->PLL.PLLN,
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#else
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001f62: 687b ldr r3, [r7, #4]
8001f64: 69da ldr r2, [r3, #28]
8001f66: 687b ldr r3, [r7, #4]
8001f68: 6a1b ldr r3, [r3, #32]
8001f6a: 431a orrs r2, r3
8001f6c: 687b ldr r3, [r7, #4]
8001f6e: 6a5b ldr r3, [r3, #36] @ 0x24
8001f70: 019b lsls r3, r3, #6
8001f72: 431a orrs r2, r3
8001f74: 687b ldr r3, [r7, #4]
8001f76: 6a9b ldr r3, [r3, #40] @ 0x28
8001f78: 085b lsrs r3, r3, #1
8001f7a: 3b01 subs r3, #1
8001f7c: 041b lsls r3, r3, #16
8001f7e: 431a orrs r2, r3
8001f80: 687b ldr r3, [r7, #4]
8001f82: 6adb ldr r3, [r3, #44] @ 0x2c
8001f84: 061b lsls r3, r3, #24
8001f86: 4313 orrs r3, r2
8001f88: 4a1b ldr r2, [pc, #108] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001f8a: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
8001f8e: 6053 str r3, [r2, #4]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001f90: 4b19 ldr r3, [pc, #100] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001f92: 681b ldr r3, [r3, #0]
8001f94: 4a18 ldr r2, [pc, #96] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001f96: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8001f9a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001f9c: f7ff fa90 bl 80014c0 <HAL_GetTick>
8001fa0: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001fa2: e008 b.n 8001fb6 <HAL_RCC_OscConfig+0x48a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001fa4: f7ff fa8c bl 80014c0 <HAL_GetTick>
8001fa8: 4602 mov r2, r0
8001faa: 693b ldr r3, [r7, #16]
8001fac: 1ad3 subs r3, r2, r3
8001fae: 2b02 cmp r3, #2
8001fb0: d901 bls.n 8001fb6 <HAL_RCC_OscConfig+0x48a>
{
return HAL_TIMEOUT;
8001fb2: 2303 movs r3, #3
8001fb4: e057 b.n 8002066 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001fb6: 4b10 ldr r3, [pc, #64] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001fb8: 681b ldr r3, [r3, #0]
8001fba: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8001fbe: 2b00 cmp r3, #0
8001fc0: d0f0 beq.n 8001fa4 <HAL_RCC_OscConfig+0x478>
8001fc2: e04f b.n 8002064 <HAL_RCC_OscConfig+0x538>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001fc4: 4b0c ldr r3, [pc, #48] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001fc6: 681b ldr r3, [r3, #0]
8001fc8: 4a0b ldr r2, [pc, #44] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001fca: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8001fce: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001fd0: f7ff fa76 bl 80014c0 <HAL_GetTick>
8001fd4: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001fd6: e008 b.n 8001fea <HAL_RCC_OscConfig+0x4be>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001fd8: f7ff fa72 bl 80014c0 <HAL_GetTick>
8001fdc: 4602 mov r2, r0
8001fde: 693b ldr r3, [r7, #16]
8001fe0: 1ad3 subs r3, r2, r3
8001fe2: 2b02 cmp r3, #2
8001fe4: d901 bls.n 8001fea <HAL_RCC_OscConfig+0x4be>
{
return HAL_TIMEOUT;
8001fe6: 2303 movs r3, #3
8001fe8: e03d b.n 8002066 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001fea: 4b03 ldr r3, [pc, #12] @ (8001ff8 <HAL_RCC_OscConfig+0x4cc>)
8001fec: 681b ldr r3, [r3, #0]
8001fee: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8001ff2: 2b00 cmp r3, #0
8001ff4: d1f0 bne.n 8001fd8 <HAL_RCC_OscConfig+0x4ac>
8001ff6: e035 b.n 8002064 <HAL_RCC_OscConfig+0x538>
8001ff8: 40023800 .word 0x40023800
8001ffc: 40007000 .word 0x40007000
}
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
8002000: 4b1b ldr r3, [pc, #108] @ (8002070 <HAL_RCC_OscConfig+0x544>)
8002002: 685b ldr r3, [r3, #4]
8002004: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8002006: 687b ldr r3, [r7, #4]
8002008: 699b ldr r3, [r3, #24]
800200a: 2b01 cmp r3, #1
800200c: d028 beq.n 8002060 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800200e: 68fb ldr r3, [r7, #12]
8002010: f403 0280 and.w r2, r3, #4194304 @ 0x400000
8002014: 687b ldr r3, [r7, #4]
8002016: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8002018: 429a cmp r2, r3
800201a: d121 bne.n 8002060 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
800201c: 68fb ldr r3, [r7, #12]
800201e: f003 023f and.w r2, r3, #63 @ 0x3f
8002022: 687b ldr r3, [r7, #4]
8002024: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002026: 429a cmp r2, r3
8002028: d11a bne.n 8002060 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
800202a: 68fa ldr r2, [r7, #12]
800202c: f647 73c0 movw r3, #32704 @ 0x7fc0
8002030: 4013 ands r3, r2
8002032: 687a ldr r2, [r7, #4]
8002034: 6a52 ldr r2, [r2, #36] @ 0x24
8002036: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8002038: 4293 cmp r3, r2
800203a: d111 bne.n 8002060 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
800203c: 68fb ldr r3, [r7, #12]
800203e: f403 3240 and.w r2, r3, #196608 @ 0x30000
8002042: 687b ldr r3, [r7, #4]
8002044: 6a9b ldr r3, [r3, #40] @ 0x28
8002046: 085b lsrs r3, r3, #1
8002048: 3b01 subs r3, #1
800204a: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
800204c: 429a cmp r2, r3
800204e: d107 bne.n 8002060 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
8002050: 68fb ldr r3, [r7, #12]
8002052: f003 6270 and.w r2, r3, #251658240 @ 0xf000000
8002056: 687b ldr r3, [r7, #4]
8002058: 6adb ldr r3, [r3, #44] @ 0x2c
800205a: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
800205c: 429a cmp r2, r3
800205e: d001 beq.n 8002064 <HAL_RCC_OscConfig+0x538>
#endif
{
return HAL_ERROR;
8002060: 2301 movs r3, #1
8002062: e000 b.n 8002066 <HAL_RCC_OscConfig+0x53a>
}
}
}
return HAL_OK;
8002064: 2300 movs r3, #0
}
8002066: 4618 mov r0, r3
8002068: 3718 adds r7, #24
800206a: 46bd mov sp, r7
800206c: bd80 pop {r7, pc}
800206e: bf00 nop
8002070: 40023800 .word 0x40023800
08002074 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8002074: b580 push {r7, lr}
8002076: b084 sub sp, #16
8002078: af00 add r7, sp, #0
800207a: 6078 str r0, [r7, #4]
800207c: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
800207e: 2300 movs r3, #0
8002080: 60fb str r3, [r7, #12]
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8002082: 687b ldr r3, [r7, #4]
8002084: 2b00 cmp r3, #0
8002086: d101 bne.n 800208c <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8002088: 2301 movs r3, #1
800208a: e0d0 b.n 800222e <HAL_RCC_ClockConfig+0x1ba>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
800208c: 4b6a ldr r3, [pc, #424] @ (8002238 <HAL_RCC_ClockConfig+0x1c4>)
800208e: 681b ldr r3, [r3, #0]
8002090: f003 030f and.w r3, r3, #15
8002094: 683a ldr r2, [r7, #0]
8002096: 429a cmp r2, r3
8002098: d910 bls.n 80020bc <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800209a: 4b67 ldr r3, [pc, #412] @ (8002238 <HAL_RCC_ClockConfig+0x1c4>)
800209c: 681b ldr r3, [r3, #0]
800209e: f023 020f bic.w r2, r3, #15
80020a2: 4965 ldr r1, [pc, #404] @ (8002238 <HAL_RCC_ClockConfig+0x1c4>)
80020a4: 683b ldr r3, [r7, #0]
80020a6: 4313 orrs r3, r2
80020a8: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80020aa: 4b63 ldr r3, [pc, #396] @ (8002238 <HAL_RCC_ClockConfig+0x1c4>)
80020ac: 681b ldr r3, [r3, #0]
80020ae: f003 030f and.w r3, r3, #15
80020b2: 683a ldr r2, [r7, #0]
80020b4: 429a cmp r2, r3
80020b6: d001 beq.n 80020bc <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
80020b8: 2301 movs r3, #1
80020ba: e0b8 b.n 800222e <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80020bc: 687b ldr r3, [r7, #4]
80020be: 681b ldr r3, [r3, #0]
80020c0: f003 0302 and.w r3, r3, #2
80020c4: 2b00 cmp r3, #0
80020c6: d020 beq.n 800210a <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80020c8: 687b ldr r3, [r7, #4]
80020ca: 681b ldr r3, [r3, #0]
80020cc: f003 0304 and.w r3, r3, #4
80020d0: 2b00 cmp r3, #0
80020d2: d005 beq.n 80020e0 <HAL_RCC_ClockConfig+0x6c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
80020d4: 4b59 ldr r3, [pc, #356] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
80020d6: 689b ldr r3, [r3, #8]
80020d8: 4a58 ldr r2, [pc, #352] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
80020da: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00
80020de: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80020e0: 687b ldr r3, [r7, #4]
80020e2: 681b ldr r3, [r3, #0]
80020e4: f003 0308 and.w r3, r3, #8
80020e8: 2b00 cmp r3, #0
80020ea: d005 beq.n 80020f8 <HAL_RCC_ClockConfig+0x84>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
80020ec: 4b53 ldr r3, [pc, #332] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
80020ee: 689b ldr r3, [r3, #8]
80020f0: 4a52 ldr r2, [pc, #328] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
80020f2: f443 4360 orr.w r3, r3, #57344 @ 0xe000
80020f6: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80020f8: 4b50 ldr r3, [pc, #320] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
80020fa: 689b ldr r3, [r3, #8]
80020fc: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8002100: 687b ldr r3, [r7, #4]
8002102: 689b ldr r3, [r3, #8]
8002104: 494d ldr r1, [pc, #308] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
8002106: 4313 orrs r3, r2
8002108: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800210a: 687b ldr r3, [r7, #4]
800210c: 681b ldr r3, [r3, #0]
800210e: f003 0301 and.w r3, r3, #1
8002112: 2b00 cmp r3, #0
8002114: d040 beq.n 8002198 <HAL_RCC_ClockConfig+0x124>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8002116: 687b ldr r3, [r7, #4]
8002118: 685b ldr r3, [r3, #4]
800211a: 2b01 cmp r3, #1
800211c: d107 bne.n 800212e <HAL_RCC_ClockConfig+0xba>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800211e: 4b47 ldr r3, [pc, #284] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
8002120: 681b ldr r3, [r3, #0]
8002122: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002126: 2b00 cmp r3, #0
8002128: d115 bne.n 8002156 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
800212a: 2301 movs r3, #1
800212c: e07f b.n 800222e <HAL_RCC_ClockConfig+0x1ba>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800212e: 687b ldr r3, [r7, #4]
8002130: 685b ldr r3, [r3, #4]
8002132: 2b02 cmp r3, #2
8002134: d107 bne.n 8002146 <HAL_RCC_ClockConfig+0xd2>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002136: 4b41 ldr r3, [pc, #260] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
8002138: 681b ldr r3, [r3, #0]
800213a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800213e: 2b00 cmp r3, #0
8002140: d109 bne.n 8002156 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
8002142: 2301 movs r3, #1
8002144: e073 b.n 800222e <HAL_RCC_ClockConfig+0x1ba>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002146: 4b3d ldr r3, [pc, #244] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
8002148: 681b ldr r3, [r3, #0]
800214a: f003 0302 and.w r3, r3, #2
800214e: 2b00 cmp r3, #0
8002150: d101 bne.n 8002156 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
8002152: 2301 movs r3, #1
8002154: e06b b.n 800222e <HAL_RCC_ClockConfig+0x1ba>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8002156: 4b39 ldr r3, [pc, #228] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
8002158: 689b ldr r3, [r3, #8]
800215a: f023 0203 bic.w r2, r3, #3
800215e: 687b ldr r3, [r7, #4]
8002160: 685b ldr r3, [r3, #4]
8002162: 4936 ldr r1, [pc, #216] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
8002164: 4313 orrs r3, r2
8002166: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002168: f7ff f9aa bl 80014c0 <HAL_GetTick>
800216c: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800216e: e00a b.n 8002186 <HAL_RCC_ClockConfig+0x112>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8002170: f7ff f9a6 bl 80014c0 <HAL_GetTick>
8002174: 4602 mov r2, r0
8002176: 68fb ldr r3, [r7, #12]
8002178: 1ad3 subs r3, r2, r3
800217a: f241 3288 movw r2, #5000 @ 0x1388
800217e: 4293 cmp r3, r2
8002180: d901 bls.n 8002186 <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
8002182: 2303 movs r3, #3
8002184: e053 b.n 800222e <HAL_RCC_ClockConfig+0x1ba>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002186: 4b2d ldr r3, [pc, #180] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
8002188: 689b ldr r3, [r3, #8]
800218a: f003 020c and.w r2, r3, #12
800218e: 687b ldr r3, [r7, #4]
8002190: 685b ldr r3, [r3, #4]
8002192: 009b lsls r3, r3, #2
8002194: 429a cmp r2, r3
8002196: d1eb bne.n 8002170 <HAL_RCC_ClockConfig+0xfc>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8002198: 4b27 ldr r3, [pc, #156] @ (8002238 <HAL_RCC_ClockConfig+0x1c4>)
800219a: 681b ldr r3, [r3, #0]
800219c: f003 030f and.w r3, r3, #15
80021a0: 683a ldr r2, [r7, #0]
80021a2: 429a cmp r2, r3
80021a4: d210 bcs.n 80021c8 <HAL_RCC_ClockConfig+0x154>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80021a6: 4b24 ldr r3, [pc, #144] @ (8002238 <HAL_RCC_ClockConfig+0x1c4>)
80021a8: 681b ldr r3, [r3, #0]
80021aa: f023 020f bic.w r2, r3, #15
80021ae: 4922 ldr r1, [pc, #136] @ (8002238 <HAL_RCC_ClockConfig+0x1c4>)
80021b0: 683b ldr r3, [r7, #0]
80021b2: 4313 orrs r3, r2
80021b4: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80021b6: 4b20 ldr r3, [pc, #128] @ (8002238 <HAL_RCC_ClockConfig+0x1c4>)
80021b8: 681b ldr r3, [r3, #0]
80021ba: f003 030f and.w r3, r3, #15
80021be: 683a ldr r2, [r7, #0]
80021c0: 429a cmp r2, r3
80021c2: d001 beq.n 80021c8 <HAL_RCC_ClockConfig+0x154>
{
return HAL_ERROR;
80021c4: 2301 movs r3, #1
80021c6: e032 b.n 800222e <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80021c8: 687b ldr r3, [r7, #4]
80021ca: 681b ldr r3, [r3, #0]
80021cc: f003 0304 and.w r3, r3, #4
80021d0: 2b00 cmp r3, #0
80021d2: d008 beq.n 80021e6 <HAL_RCC_ClockConfig+0x172>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80021d4: 4b19 ldr r3, [pc, #100] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
80021d6: 689b ldr r3, [r3, #8]
80021d8: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00
80021dc: 687b ldr r3, [r7, #4]
80021de: 68db ldr r3, [r3, #12]
80021e0: 4916 ldr r1, [pc, #88] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
80021e2: 4313 orrs r3, r2
80021e4: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80021e6: 687b ldr r3, [r7, #4]
80021e8: 681b ldr r3, [r3, #0]
80021ea: f003 0308 and.w r3, r3, #8
80021ee: 2b00 cmp r3, #0
80021f0: d009 beq.n 8002206 <HAL_RCC_ClockConfig+0x192>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
80021f2: 4b12 ldr r3, [pc, #72] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
80021f4: 689b ldr r3, [r3, #8]
80021f6: f423 4260 bic.w r2, r3, #57344 @ 0xe000
80021fa: 687b ldr r3, [r7, #4]
80021fc: 691b ldr r3, [r3, #16]
80021fe: 00db lsls r3, r3, #3
8002200: 490e ldr r1, [pc, #56] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
8002202: 4313 orrs r3, r2
8002204: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8002206: f000 f821 bl 800224c <HAL_RCC_GetSysClockFreq>
800220a: 4602 mov r2, r0
800220c: 4b0b ldr r3, [pc, #44] @ (800223c <HAL_RCC_ClockConfig+0x1c8>)
800220e: 689b ldr r3, [r3, #8]
8002210: 091b lsrs r3, r3, #4
8002212: f003 030f and.w r3, r3, #15
8002216: 490a ldr r1, [pc, #40] @ (8002240 <HAL_RCC_ClockConfig+0x1cc>)
8002218: 5ccb ldrb r3, [r1, r3]
800221a: fa22 f303 lsr.w r3, r2, r3
800221e: 4a09 ldr r2, [pc, #36] @ (8002244 <HAL_RCC_ClockConfig+0x1d0>)
8002220: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
8002222: 4b09 ldr r3, [pc, #36] @ (8002248 <HAL_RCC_ClockConfig+0x1d4>)
8002224: 681b ldr r3, [r3, #0]
8002226: 4618 mov r0, r3
8002228: f7fe ffc6 bl 80011b8 <HAL_InitTick>
return HAL_OK;
800222c: 2300 movs r3, #0
}
800222e: 4618 mov r0, r3
8002230: 3710 adds r7, #16
8002232: 46bd mov sp, r7
8002234: bd80 pop {r7, pc}
8002236: bf00 nop
8002238: 40023c00 .word 0x40023c00
800223c: 40023800 .word 0x40023800
8002240: 08007604 .word 0x08007604
8002244: 20000000 .word 0x20000000
8002248: 20000004 .word 0x20000004
0800224c <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
800224c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8002250: b090 sub sp, #64 @ 0x40
8002252: af00 add r7, sp, #0
uint32_t pllm = 0, pllvco = 0, pllp = 0;
8002254: 2300 movs r3, #0
8002256: 637b str r3, [r7, #52] @ 0x34
8002258: 2300 movs r3, #0
800225a: 63fb str r3, [r7, #60] @ 0x3c
800225c: 2300 movs r3, #0
800225e: 633b str r3, [r7, #48] @ 0x30
uint32_t sysclockfreq = 0;
8002260: 2300 movs r3, #0
8002262: 63bb str r3, [r7, #56] @ 0x38
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8002264: 4b59 ldr r3, [pc, #356] @ (80023cc <HAL_RCC_GetSysClockFreq+0x180>)
8002266: 689b ldr r3, [r3, #8]
8002268: f003 030c and.w r3, r3, #12
800226c: 2b08 cmp r3, #8
800226e: d00d beq.n 800228c <HAL_RCC_GetSysClockFreq+0x40>
8002270: 2b08 cmp r3, #8
8002272: f200 80a1 bhi.w 80023b8 <HAL_RCC_GetSysClockFreq+0x16c>
8002276: 2b00 cmp r3, #0
8002278: d002 beq.n 8002280 <HAL_RCC_GetSysClockFreq+0x34>
800227a: 2b04 cmp r3, #4
800227c: d003 beq.n 8002286 <HAL_RCC_GetSysClockFreq+0x3a>
800227e: e09b b.n 80023b8 <HAL_RCC_GetSysClockFreq+0x16c>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8002280: 4b53 ldr r3, [pc, #332] @ (80023d0 <HAL_RCC_GetSysClockFreq+0x184>)
8002282: 63bb str r3, [r7, #56] @ 0x38
break;
8002284: e09b b.n 80023be <HAL_RCC_GetSysClockFreq+0x172>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8002286: 4b53 ldr r3, [pc, #332] @ (80023d4 <HAL_RCC_GetSysClockFreq+0x188>)
8002288: 63bb str r3, [r7, #56] @ 0x38
break;
800228a: e098 b.n 80023be <HAL_RCC_GetSysClockFreq+0x172>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
800228c: 4b4f ldr r3, [pc, #316] @ (80023cc <HAL_RCC_GetSysClockFreq+0x180>)
800228e: 685b ldr r3, [r3, #4]
8002290: f003 033f and.w r3, r3, #63 @ 0x3f
8002294: 637b str r3, [r7, #52] @ 0x34
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
8002296: 4b4d ldr r3, [pc, #308] @ (80023cc <HAL_RCC_GetSysClockFreq+0x180>)
8002298: 685b ldr r3, [r3, #4]
800229a: f403 0380 and.w r3, r3, #4194304 @ 0x400000
800229e: 2b00 cmp r3, #0
80022a0: d028 beq.n 80022f4 <HAL_RCC_GetSysClockFreq+0xa8>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
80022a2: 4b4a ldr r3, [pc, #296] @ (80023cc <HAL_RCC_GetSysClockFreq+0x180>)
80022a4: 685b ldr r3, [r3, #4]
80022a6: 099b lsrs r3, r3, #6
80022a8: 2200 movs r2, #0
80022aa: 623b str r3, [r7, #32]
80022ac: 627a str r2, [r7, #36] @ 0x24
80022ae: 6a3b ldr r3, [r7, #32]
80022b0: f3c3 0008 ubfx r0, r3, #0, #9
80022b4: 2100 movs r1, #0
80022b6: 4b47 ldr r3, [pc, #284] @ (80023d4 <HAL_RCC_GetSysClockFreq+0x188>)
80022b8: fb03 f201 mul.w r2, r3, r1
80022bc: 2300 movs r3, #0
80022be: fb00 f303 mul.w r3, r0, r3
80022c2: 4413 add r3, r2
80022c4: 4a43 ldr r2, [pc, #268] @ (80023d4 <HAL_RCC_GetSysClockFreq+0x188>)
80022c6: fba0 1202 umull r1, r2, r0, r2
80022ca: 62fa str r2, [r7, #44] @ 0x2c
80022cc: 460a mov r2, r1
80022ce: 62ba str r2, [r7, #40] @ 0x28
80022d0: 6afa ldr r2, [r7, #44] @ 0x2c
80022d2: 4413 add r3, r2
80022d4: 62fb str r3, [r7, #44] @ 0x2c
80022d6: 6b7b ldr r3, [r7, #52] @ 0x34
80022d8: 2200 movs r2, #0
80022da: 61bb str r3, [r7, #24]
80022dc: 61fa str r2, [r7, #28]
80022de: e9d7 2306 ldrd r2, r3, [r7, #24]
80022e2: e9d7 010a ldrd r0, r1, [r7, #40] @ 0x28
80022e6: f7fd ffeb bl 80002c0 <__aeabi_uldivmod>
80022ea: 4602 mov r2, r0
80022ec: 460b mov r3, r1
80022ee: 4613 mov r3, r2
80022f0: 63fb str r3, [r7, #60] @ 0x3c
80022f2: e053 b.n 800239c <HAL_RCC_GetSysClockFreq+0x150>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
80022f4: 4b35 ldr r3, [pc, #212] @ (80023cc <HAL_RCC_GetSysClockFreq+0x180>)
80022f6: 685b ldr r3, [r3, #4]
80022f8: 099b lsrs r3, r3, #6
80022fa: 2200 movs r2, #0
80022fc: 613b str r3, [r7, #16]
80022fe: 617a str r2, [r7, #20]
8002300: 693b ldr r3, [r7, #16]
8002302: f3c3 0a08 ubfx sl, r3, #0, #9
8002306: f04f 0b00 mov.w fp, #0
800230a: 4652 mov r2, sl
800230c: 465b mov r3, fp
800230e: f04f 0000 mov.w r0, #0
8002312: f04f 0100 mov.w r1, #0
8002316: 0159 lsls r1, r3, #5
8002318: ea41 61d2 orr.w r1, r1, r2, lsr #27
800231c: 0150 lsls r0, r2, #5
800231e: 4602 mov r2, r0
8002320: 460b mov r3, r1
8002322: ebb2 080a subs.w r8, r2, sl
8002326: eb63 090b sbc.w r9, r3, fp
800232a: f04f 0200 mov.w r2, #0
800232e: f04f 0300 mov.w r3, #0
8002332: ea4f 1389 mov.w r3, r9, lsl #6
8002336: ea43 6398 orr.w r3, r3, r8, lsr #26
800233a: ea4f 1288 mov.w r2, r8, lsl #6
800233e: ebb2 0408 subs.w r4, r2, r8
8002342: eb63 0509 sbc.w r5, r3, r9
8002346: f04f 0200 mov.w r2, #0
800234a: f04f 0300 mov.w r3, #0
800234e: 00eb lsls r3, r5, #3
8002350: ea43 7354 orr.w r3, r3, r4, lsr #29
8002354: 00e2 lsls r2, r4, #3
8002356: 4614 mov r4, r2
8002358: 461d mov r5, r3
800235a: eb14 030a adds.w r3, r4, sl
800235e: 603b str r3, [r7, #0]
8002360: eb45 030b adc.w r3, r5, fp
8002364: 607b str r3, [r7, #4]
8002366: f04f 0200 mov.w r2, #0
800236a: f04f 0300 mov.w r3, #0
800236e: e9d7 4500 ldrd r4, r5, [r7]
8002372: 4629 mov r1, r5
8002374: 028b lsls r3, r1, #10
8002376: 4621 mov r1, r4
8002378: ea43 5391 orr.w r3, r3, r1, lsr #22
800237c: 4621 mov r1, r4
800237e: 028a lsls r2, r1, #10
8002380: 4610 mov r0, r2
8002382: 4619 mov r1, r3
8002384: 6b7b ldr r3, [r7, #52] @ 0x34
8002386: 2200 movs r2, #0
8002388: 60bb str r3, [r7, #8]
800238a: 60fa str r2, [r7, #12]
800238c: e9d7 2302 ldrd r2, r3, [r7, #8]
8002390: f7fd ff96 bl 80002c0 <__aeabi_uldivmod>
8002394: 4602 mov r2, r0
8002396: 460b mov r3, r1
8002398: 4613 mov r3, r2
800239a: 63fb str r3, [r7, #60] @ 0x3c
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
800239c: 4b0b ldr r3, [pc, #44] @ (80023cc <HAL_RCC_GetSysClockFreq+0x180>)
800239e: 685b ldr r3, [r3, #4]
80023a0: 0c1b lsrs r3, r3, #16
80023a2: f003 0303 and.w r3, r3, #3
80023a6: 3301 adds r3, #1
80023a8: 005b lsls r3, r3, #1
80023aa: 633b str r3, [r7, #48] @ 0x30
sysclockfreq = pllvco / pllp;
80023ac: 6bfa ldr r2, [r7, #60] @ 0x3c
80023ae: 6b3b ldr r3, [r7, #48] @ 0x30
80023b0: fbb2 f3f3 udiv r3, r2, r3
80023b4: 63bb str r3, [r7, #56] @ 0x38
break;
80023b6: e002 b.n 80023be <HAL_RCC_GetSysClockFreq+0x172>
}
default:
{
sysclockfreq = HSI_VALUE;
80023b8: 4b05 ldr r3, [pc, #20] @ (80023d0 <HAL_RCC_GetSysClockFreq+0x184>)
80023ba: 63bb str r3, [r7, #56] @ 0x38
break;
80023bc: bf00 nop
}
}
return sysclockfreq;
80023be: 6bbb ldr r3, [r7, #56] @ 0x38
}
80023c0: 4618 mov r0, r3
80023c2: 3740 adds r7, #64 @ 0x40
80023c4: 46bd mov sp, r7
80023c6: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
80023ca: bf00 nop
80023cc: 40023800 .word 0x40023800
80023d0: 00f42400 .word 0x00f42400
80023d4: 017d7840 .word 0x017d7840
080023d8 <HAL_RCC_GetHCLKFreq>:
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
80023d8: b480 push {r7}
80023da: af00 add r7, sp, #0
return SystemCoreClock;
80023dc: 4b03 ldr r3, [pc, #12] @ (80023ec <HAL_RCC_GetHCLKFreq+0x14>)
80023de: 681b ldr r3, [r3, #0]
}
80023e0: 4618 mov r0, r3
80023e2: 46bd mov sp, r7
80023e4: f85d 7b04 ldr.w r7, [sp], #4
80023e8: 4770 bx lr
80023ea: bf00 nop
80023ec: 20000000 .word 0x20000000
080023f0 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
80023f0: b580 push {r7, lr}
80023f2: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
80023f4: f7ff fff0 bl 80023d8 <HAL_RCC_GetHCLKFreq>
80023f8: 4602 mov r2, r0
80023fa: 4b05 ldr r3, [pc, #20] @ (8002410 <HAL_RCC_GetPCLK1Freq+0x20>)
80023fc: 689b ldr r3, [r3, #8]
80023fe: 0a9b lsrs r3, r3, #10
8002400: f003 0307 and.w r3, r3, #7
8002404: 4903 ldr r1, [pc, #12] @ (8002414 <HAL_RCC_GetPCLK1Freq+0x24>)
8002406: 5ccb ldrb r3, [r1, r3]
8002408: fa22 f303 lsr.w r3, r2, r3
}
800240c: 4618 mov r0, r3
800240e: bd80 pop {r7, pc}
8002410: 40023800 .word 0x40023800
8002414: 08007614 .word 0x08007614
08002418 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8002418: b580 push {r7, lr}
800241a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
800241c: f7ff ffdc bl 80023d8 <HAL_RCC_GetHCLKFreq>
8002420: 4602 mov r2, r0
8002422: 4b05 ldr r3, [pc, #20] @ (8002438 <HAL_RCC_GetPCLK2Freq+0x20>)
8002424: 689b ldr r3, [r3, #8]
8002426: 0b5b lsrs r3, r3, #13
8002428: f003 0307 and.w r3, r3, #7
800242c: 4903 ldr r1, [pc, #12] @ (800243c <HAL_RCC_GetPCLK2Freq+0x24>)
800242e: 5ccb ldrb r3, [r1, r3]
8002430: fa22 f303 lsr.w r3, r2, r3
}
8002434: 4618 mov r0, r3
8002436: bd80 pop {r7, pc}
8002438: 40023800 .word 0x40023800
800243c: 08007614 .word 0x08007614
08002440 <HAL_RCC_GetClockConfig>:
* will be configured.
* @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
8002440: b480 push {r7}
8002442: b083 sub sp, #12
8002444: af00 add r7, sp, #0
8002446: 6078 str r0, [r7, #4]
8002448: 6039 str r1, [r7, #0]
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
800244a: 687b ldr r3, [r7, #4]
800244c: 220f movs r2, #15
800244e: 601a str r2, [r3, #0]
/* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
8002450: 4b12 ldr r3, [pc, #72] @ (800249c <HAL_RCC_GetClockConfig+0x5c>)
8002452: 689b ldr r3, [r3, #8]
8002454: f003 0203 and.w r2, r3, #3
8002458: 687b ldr r3, [r7, #4]
800245a: 605a str r2, [r3, #4]
/* Get the HCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
800245c: 4b0f ldr r3, [pc, #60] @ (800249c <HAL_RCC_GetClockConfig+0x5c>)
800245e: 689b ldr r3, [r3, #8]
8002460: f003 02f0 and.w r2, r3, #240 @ 0xf0
8002464: 687b ldr r3, [r7, #4]
8002466: 609a str r2, [r3, #8]
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
8002468: 4b0c ldr r3, [pc, #48] @ (800249c <HAL_RCC_GetClockConfig+0x5c>)
800246a: 689b ldr r3, [r3, #8]
800246c: f403 52e0 and.w r2, r3, #7168 @ 0x1c00
8002470: 687b ldr r3, [r7, #4]
8002472: 60da str r2, [r3, #12]
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
8002474: 4b09 ldr r3, [pc, #36] @ (800249c <HAL_RCC_GetClockConfig+0x5c>)
8002476: 689b ldr r3, [r3, #8]
8002478: 08db lsrs r3, r3, #3
800247a: f403 52e0 and.w r2, r3, #7168 @ 0x1c00
800247e: 687b ldr r3, [r7, #4]
8002480: 611a str r2, [r3, #16]
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
8002482: 4b07 ldr r3, [pc, #28] @ (80024a0 <HAL_RCC_GetClockConfig+0x60>)
8002484: 681b ldr r3, [r3, #0]
8002486: f003 020f and.w r2, r3, #15
800248a: 683b ldr r3, [r7, #0]
800248c: 601a str r2, [r3, #0]
}
800248e: bf00 nop
8002490: 370c adds r7, #12
8002492: 46bd mov sp, r7
8002494: f85d 7b04 ldr.w r7, [sp], #4
8002498: 4770 bx lr
800249a: bf00 nop
800249c: 40023800 .word 0x40023800
80024a0: 40023c00 .word 0x40023c00
080024a4 <HAL_RCCEx_PeriphCLKConfig>:
* the backup registers) are set to their reset values.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
80024a4: b580 push {r7, lr}
80024a6: b088 sub sp, #32
80024a8: af00 add r7, sp, #0
80024aa: 6078 str r0, [r7, #4]
uint32_t tickstart = 0;
80024ac: 2300 movs r3, #0
80024ae: 617b str r3, [r7, #20]
uint32_t tmpreg0 = 0;
80024b0: 2300 movs r3, #0
80024b2: 613b str r3, [r7, #16]
uint32_t plli2sused = 0;
80024b4: 2300 movs r3, #0
80024b6: 61fb str r3, [r7, #28]
uint32_t pllsaiused = 0;
80024b8: 2300 movs r3, #0
80024ba: 61bb str r3, [r7, #24]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*----------------------------------- I2S configuration ----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
80024bc: 687b ldr r3, [r7, #4]
80024be: 681b ldr r3, [r3, #0]
80024c0: f003 0301 and.w r3, r3, #1
80024c4: 2b00 cmp r3, #0
80024c6: d012 beq.n 80024ee <HAL_RCCEx_PeriphCLKConfig+0x4a>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure I2S Clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
80024c8: 4b65 ldr r3, [pc, #404] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80024ca: 689b ldr r3, [r3, #8]
80024cc: 4a64 ldr r2, [pc, #400] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80024ce: f423 0300 bic.w r3, r3, #8388608 @ 0x800000
80024d2: 6093 str r3, [r2, #8]
80024d4: 4b62 ldr r3, [pc, #392] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80024d6: 689a ldr r2, [r3, #8]
80024d8: 687b ldr r3, [r7, #4]
80024da: 6adb ldr r3, [r3, #44] @ 0x2c
80024dc: 4960 ldr r1, [pc, #384] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80024de: 4313 orrs r3, r2
80024e0: 608b str r3, [r1, #8]
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
80024e2: 687b ldr r3, [r7, #4]
80024e4: 6adb ldr r3, [r3, #44] @ 0x2c
80024e6: 2b00 cmp r3, #0
80024e8: d101 bne.n 80024ee <HAL_RCCEx_PeriphCLKConfig+0x4a>
{
plli2sused = 1;
80024ea: 2301 movs r3, #1
80024ec: 61fb str r3, [r7, #28]
}
}
/*------------------------------------ SAI1 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
80024ee: 687b ldr r3, [r7, #4]
80024f0: 681b ldr r3, [r3, #0]
80024f2: f403 2300 and.w r3, r3, #524288 @ 0x80000
80024f6: 2b00 cmp r3, #0
80024f8: d017 beq.n 800252a <HAL_RCCEx_PeriphCLKConfig+0x86>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure SAI1 Clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
80024fa: 4b59 ldr r3, [pc, #356] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80024fc: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8002500: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
8002504: 687b ldr r3, [r7, #4]
8002506: 6b5b ldr r3, [r3, #52] @ 0x34
8002508: 4955 ldr r1, [pc, #340] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
800250a: 4313 orrs r3, r2
800250c: f8c1 308c str.w r3, [r1, #140] @ 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
8002510: 687b ldr r3, [r7, #4]
8002512: 6b5b ldr r3, [r3, #52] @ 0x34
8002514: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8002518: d101 bne.n 800251e <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
plli2sused = 1;
800251a: 2301 movs r3, #1
800251c: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
800251e: 687b ldr r3, [r7, #4]
8002520: 6b5b ldr r3, [r3, #52] @ 0x34
8002522: 2b00 cmp r3, #0
8002524: d101 bne.n 800252a <HAL_RCCEx_PeriphCLKConfig+0x86>
{
pllsaiused = 1;
8002526: 2301 movs r3, #1
8002528: 61bb str r3, [r7, #24]
}
}
/*------------------------------------ SAI2 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
800252a: 687b ldr r3, [r7, #4]
800252c: 681b ldr r3, [r3, #0]
800252e: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8002532: 2b00 cmp r3, #0
8002534: d017 beq.n 8002566 <HAL_RCCEx_PeriphCLKConfig+0xc2>
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
/* Configure SAI2 Clock source */
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
8002536: 4b4a ldr r3, [pc, #296] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002538: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
800253c: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
8002540: 687b ldr r3, [r7, #4]
8002542: 6b9b ldr r3, [r3, #56] @ 0x38
8002544: 4946 ldr r1, [pc, #280] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002546: 4313 orrs r3, r2
8002548: f8c1 308c str.w r3, [r1, #140] @ 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
800254c: 687b ldr r3, [r7, #4]
800254e: 6b9b ldr r3, [r3, #56] @ 0x38
8002550: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8002554: d101 bne.n 800255a <HAL_RCCEx_PeriphCLKConfig+0xb6>
{
plli2sused = 1;
8002556: 2301 movs r3, #1
8002558: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
800255a: 687b ldr r3, [r7, #4]
800255c: 6b9b ldr r3, [r3, #56] @ 0x38
800255e: 2b00 cmp r3, #0
8002560: d101 bne.n 8002566 <HAL_RCCEx_PeriphCLKConfig+0xc2>
{
pllsaiused = 1;
8002562: 2301 movs r3, #1
8002564: 61bb str r3, [r7, #24]
}
}
/*------------------------------------ RTC configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
8002566: 687b ldr r3, [r7, #4]
8002568: 681b ldr r3, [r3, #0]
800256a: f003 0320 and.w r3, r3, #32
800256e: 2b00 cmp r3, #0
8002570: f000 808b beq.w 800268a <HAL_RCCEx_PeriphCLKConfig+0x1e6>
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
8002574: 4b3a ldr r3, [pc, #232] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002576: 6c1b ldr r3, [r3, #64] @ 0x40
8002578: 4a39 ldr r2, [pc, #228] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
800257a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800257e: 6413 str r3, [r2, #64] @ 0x40
8002580: 4b37 ldr r3, [pc, #220] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002582: 6c1b ldr r3, [r3, #64] @ 0x40
8002584: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002588: 60fb str r3, [r7, #12]
800258a: 68fb ldr r3, [r7, #12]
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
800258c: 4b35 ldr r3, [pc, #212] @ (8002664 <HAL_RCCEx_PeriphCLKConfig+0x1c0>)
800258e: 681b ldr r3, [r3, #0]
8002590: 4a34 ldr r2, [pc, #208] @ (8002664 <HAL_RCCEx_PeriphCLKConfig+0x1c0>)
8002592: f443 7380 orr.w r3, r3, #256 @ 0x100
8002596: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002598: f7fe ff92 bl 80014c0 <HAL_GetTick>
800259c: 6178 str r0, [r7, #20]
/* Wait for Backup domain Write protection disable */
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
800259e: e008 b.n 80025b2 <HAL_RCCEx_PeriphCLKConfig+0x10e>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80025a0: f7fe ff8e bl 80014c0 <HAL_GetTick>
80025a4: 4602 mov r2, r0
80025a6: 697b ldr r3, [r7, #20]
80025a8: 1ad3 subs r3, r2, r3
80025aa: 2b64 cmp r3, #100 @ 0x64
80025ac: d901 bls.n 80025b2 <HAL_RCCEx_PeriphCLKConfig+0x10e>
{
return HAL_TIMEOUT;
80025ae: 2303 movs r3, #3
80025b0: e2bc b.n 8002b2c <HAL_RCCEx_PeriphCLKConfig+0x688>
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
80025b2: 4b2c ldr r3, [pc, #176] @ (8002664 <HAL_RCCEx_PeriphCLKConfig+0x1c0>)
80025b4: 681b ldr r3, [r3, #0]
80025b6: f403 7380 and.w r3, r3, #256 @ 0x100
80025ba: 2b00 cmp r3, #0
80025bc: d0f0 beq.n 80025a0 <HAL_RCCEx_PeriphCLKConfig+0xfc>
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified */
tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
80025be: 4b28 ldr r3, [pc, #160] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80025c0: 6f1b ldr r3, [r3, #112] @ 0x70
80025c2: f403 7340 and.w r3, r3, #768 @ 0x300
80025c6: 613b str r3, [r7, #16]
if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
80025c8: 693b ldr r3, [r7, #16]
80025ca: 2b00 cmp r3, #0
80025cc: d035 beq.n 800263a <HAL_RCCEx_PeriphCLKConfig+0x196>
80025ce: 687b ldr r3, [r7, #4]
80025d0: 6a9b ldr r3, [r3, #40] @ 0x28
80025d2: f403 7340 and.w r3, r3, #768 @ 0x300
80025d6: 693a ldr r2, [r7, #16]
80025d8: 429a cmp r2, r3
80025da: d02e beq.n 800263a <HAL_RCCEx_PeriphCLKConfig+0x196>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
80025dc: 4b20 ldr r3, [pc, #128] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80025de: 6f1b ldr r3, [r3, #112] @ 0x70
80025e0: f423 7340 bic.w r3, r3, #768 @ 0x300
80025e4: 613b str r3, [r7, #16]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
80025e6: 4b1e ldr r3, [pc, #120] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80025e8: 6f1b ldr r3, [r3, #112] @ 0x70
80025ea: 4a1d ldr r2, [pc, #116] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80025ec: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80025f0: 6713 str r3, [r2, #112] @ 0x70
__HAL_RCC_BACKUPRESET_RELEASE();
80025f2: 4b1b ldr r3, [pc, #108] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80025f4: 6f1b ldr r3, [r3, #112] @ 0x70
80025f6: 4a1a ldr r2, [pc, #104] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80025f8: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80025fc: 6713 str r3, [r2, #112] @ 0x70
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg0;
80025fe: 4a18 ldr r2, [pc, #96] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002600: 693b ldr r3, [r7, #16]
8002602: 6713 str r3, [r2, #112] @ 0x70
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
8002604: 4b16 ldr r3, [pc, #88] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002606: 6f1b ldr r3, [r3, #112] @ 0x70
8002608: f003 0301 and.w r3, r3, #1
800260c: 2b01 cmp r3, #1
800260e: d114 bne.n 800263a <HAL_RCCEx_PeriphCLKConfig+0x196>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002610: f7fe ff56 bl 80014c0 <HAL_GetTick>
8002614: 6178 str r0, [r7, #20]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002616: e00a b.n 800262e <HAL_RCCEx_PeriphCLKConfig+0x18a>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8002618: f7fe ff52 bl 80014c0 <HAL_GetTick>
800261c: 4602 mov r2, r0
800261e: 697b ldr r3, [r7, #20]
8002620: 1ad3 subs r3, r2, r3
8002622: f241 3288 movw r2, #5000 @ 0x1388
8002626: 4293 cmp r3, r2
8002628: d901 bls.n 800262e <HAL_RCCEx_PeriphCLKConfig+0x18a>
{
return HAL_TIMEOUT;
800262a: 2303 movs r3, #3
800262c: e27e b.n 8002b2c <HAL_RCCEx_PeriphCLKConfig+0x688>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800262e: 4b0c ldr r3, [pc, #48] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002630: 6f1b ldr r3, [r3, #112] @ 0x70
8002632: f003 0302 and.w r3, r3, #2
8002636: 2b00 cmp r3, #0
8002638: d0ee beq.n 8002618 <HAL_RCCEx_PeriphCLKConfig+0x174>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
800263a: 687b ldr r3, [r7, #4]
800263c: 6a9b ldr r3, [r3, #40] @ 0x28
800263e: f403 7340 and.w r3, r3, #768 @ 0x300
8002642: f5b3 7f40 cmp.w r3, #768 @ 0x300
8002646: d111 bne.n 800266c <HAL_RCCEx_PeriphCLKConfig+0x1c8>
8002648: 4b05 ldr r3, [pc, #20] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
800264a: 689b ldr r3, [r3, #8]
800264c: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000
8002650: 687b ldr r3, [r7, #4]
8002652: 6a99 ldr r1, [r3, #40] @ 0x28
8002654: 4b04 ldr r3, [pc, #16] @ (8002668 <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
8002656: 400b ands r3, r1
8002658: 4901 ldr r1, [pc, #4] @ (8002660 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
800265a: 4313 orrs r3, r2
800265c: 608b str r3, [r1, #8]
800265e: e00b b.n 8002678 <HAL_RCCEx_PeriphCLKConfig+0x1d4>
8002660: 40023800 .word 0x40023800
8002664: 40007000 .word 0x40007000
8002668: 0ffffcff .word 0x0ffffcff
800266c: 4ba4 ldr r3, [pc, #656] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800266e: 689b ldr r3, [r3, #8]
8002670: 4aa3 ldr r2, [pc, #652] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002672: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000
8002676: 6093 str r3, [r2, #8]
8002678: 4ba1 ldr r3, [pc, #644] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800267a: 6f1a ldr r2, [r3, #112] @ 0x70
800267c: 687b ldr r3, [r7, #4]
800267e: 6a9b ldr r3, [r3, #40] @ 0x28
8002680: f3c3 030b ubfx r3, r3, #0, #12
8002684: 499e ldr r1, [pc, #632] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002686: 4313 orrs r3, r2
8002688: 670b str r3, [r1, #112] @ 0x70
}
/*------------------------------------ TIM configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
800268a: 687b ldr r3, [r7, #4]
800268c: 681b ldr r3, [r3, #0]
800268e: f003 0310 and.w r3, r3, #16
8002692: 2b00 cmp r3, #0
8002694: d010 beq.n 80026b8 <HAL_RCCEx_PeriphCLKConfig+0x214>
{
/* Check the parameters */
assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
/* Configure Timer Prescaler */
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
8002696: 4b9a ldr r3, [pc, #616] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002698: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
800269c: 4a98 ldr r2, [pc, #608] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800269e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
80026a2: f8c2 308c str.w r3, [r2, #140] @ 0x8c
80026a6: 4b96 ldr r3, [pc, #600] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80026a8: f8d3 208c ldr.w r2, [r3, #140] @ 0x8c
80026ac: 687b ldr r3, [r7, #4]
80026ae: 6b1b ldr r3, [r3, #48] @ 0x30
80026b0: 4993 ldr r1, [pc, #588] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80026b2: 4313 orrs r3, r2
80026b4: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*-------------------------------------- I2C1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
80026b8: 687b ldr r3, [r7, #4]
80026ba: 681b ldr r3, [r3, #0]
80026bc: f403 4380 and.w r3, r3, #16384 @ 0x4000
80026c0: 2b00 cmp r3, #0
80026c2: d00a beq.n 80026da <HAL_RCCEx_PeriphCLKConfig+0x236>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
80026c4: 4b8e ldr r3, [pc, #568] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80026c6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80026ca: f423 3240 bic.w r2, r3, #196608 @ 0x30000
80026ce: 687b ldr r3, [r7, #4]
80026d0: 6ddb ldr r3, [r3, #92] @ 0x5c
80026d2: 498b ldr r1, [pc, #556] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80026d4: 4313 orrs r3, r2
80026d6: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- I2C2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
80026da: 687b ldr r3, [r7, #4]
80026dc: 681b ldr r3, [r3, #0]
80026de: f403 4300 and.w r3, r3, #32768 @ 0x8000
80026e2: 2b00 cmp r3, #0
80026e4: d00a beq.n 80026fc <HAL_RCCEx_PeriphCLKConfig+0x258>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
80026e6: 4b86 ldr r3, [pc, #536] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80026e8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80026ec: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
80026f0: 687b ldr r3, [r7, #4]
80026f2: 6e1b ldr r3, [r3, #96] @ 0x60
80026f4: 4982 ldr r1, [pc, #520] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80026f6: 4313 orrs r3, r2
80026f8: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- I2C3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
80026fc: 687b ldr r3, [r7, #4]
80026fe: 681b ldr r3, [r3, #0]
8002700: f403 3380 and.w r3, r3, #65536 @ 0x10000
8002704: 2b00 cmp r3, #0
8002706: d00a beq.n 800271e <HAL_RCCEx_PeriphCLKConfig+0x27a>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
8002708: 4b7d ldr r3, [pc, #500] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800270a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800270e: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
8002712: 687b ldr r3, [r7, #4]
8002714: 6e5b ldr r3, [r3, #100] @ 0x64
8002716: 497a ldr r1, [pc, #488] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002718: 4313 orrs r3, r2
800271a: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
800271e: 687b ldr r3, [r7, #4]
8002720: 681b ldr r3, [r3, #0]
8002722: f003 0340 and.w r3, r3, #64 @ 0x40
8002726: 2b00 cmp r3, #0
8002728: d00a beq.n 8002740 <HAL_RCCEx_PeriphCLKConfig+0x29c>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
800272a: 4b75 ldr r3, [pc, #468] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800272c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002730: f023 0203 bic.w r2, r3, #3
8002734: 687b ldr r3, [r7, #4]
8002736: 6bdb ldr r3, [r3, #60] @ 0x3c
8002738: 4971 ldr r1, [pc, #452] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800273a: 4313 orrs r3, r2
800273c: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
8002740: 687b ldr r3, [r7, #4]
8002742: 681b ldr r3, [r3, #0]
8002744: f003 0380 and.w r3, r3, #128 @ 0x80
8002748: 2b00 cmp r3, #0
800274a: d00a beq.n 8002762 <HAL_RCCEx_PeriphCLKConfig+0x2be>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
800274c: 4b6c ldr r3, [pc, #432] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800274e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002752: f023 020c bic.w r2, r3, #12
8002756: 687b ldr r3, [r7, #4]
8002758: 6c1b ldr r3, [r3, #64] @ 0x40
800275a: 4969 ldr r1, [pc, #420] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800275c: 4313 orrs r3, r2
800275e: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
8002762: 687b ldr r3, [r7, #4]
8002764: 681b ldr r3, [r3, #0]
8002766: f403 7380 and.w r3, r3, #256 @ 0x100
800276a: 2b00 cmp r3, #0
800276c: d00a beq.n 8002784 <HAL_RCCEx_PeriphCLKConfig+0x2e0>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
800276e: 4b64 ldr r3, [pc, #400] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002770: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002774: f023 0230 bic.w r2, r3, #48 @ 0x30
8002778: 687b ldr r3, [r7, #4]
800277a: 6c5b ldr r3, [r3, #68] @ 0x44
800277c: 4960 ldr r1, [pc, #384] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800277e: 4313 orrs r3, r2
8002780: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
8002784: 687b ldr r3, [r7, #4]
8002786: 681b ldr r3, [r3, #0]
8002788: f403 7300 and.w r3, r3, #512 @ 0x200
800278c: 2b00 cmp r3, #0
800278e: d00a beq.n 80027a6 <HAL_RCCEx_PeriphCLKConfig+0x302>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
8002790: 4b5b ldr r3, [pc, #364] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002792: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002796: f023 02c0 bic.w r2, r3, #192 @ 0xc0
800279a: 687b ldr r3, [r7, #4]
800279c: 6c9b ldr r3, [r3, #72] @ 0x48
800279e: 4958 ldr r1, [pc, #352] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80027a0: 4313 orrs r3, r2
80027a2: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART5 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
80027a6: 687b ldr r3, [r7, #4]
80027a8: 681b ldr r3, [r3, #0]
80027aa: f403 6380 and.w r3, r3, #1024 @ 0x400
80027ae: 2b00 cmp r3, #0
80027b0: d00a beq.n 80027c8 <HAL_RCCEx_PeriphCLKConfig+0x324>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
80027b2: 4b53 ldr r3, [pc, #332] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80027b4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80027b8: f423 7240 bic.w r2, r3, #768 @ 0x300
80027bc: 687b ldr r3, [r7, #4]
80027be: 6cdb ldr r3, [r3, #76] @ 0x4c
80027c0: 494f ldr r1, [pc, #316] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80027c2: 4313 orrs r3, r2
80027c4: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART6 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
80027c8: 687b ldr r3, [r7, #4]
80027ca: 681b ldr r3, [r3, #0]
80027cc: f403 6300 and.w r3, r3, #2048 @ 0x800
80027d0: 2b00 cmp r3, #0
80027d2: d00a beq.n 80027ea <HAL_RCCEx_PeriphCLKConfig+0x346>
{
/* Check the parameters */
assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
/* Configure the USART6 clock source */
__HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
80027d4: 4b4a ldr r3, [pc, #296] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80027d6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80027da: f423 6240 bic.w r2, r3, #3072 @ 0xc00
80027de: 687b ldr r3, [r7, #4]
80027e0: 6d1b ldr r3, [r3, #80] @ 0x50
80027e2: 4947 ldr r1, [pc, #284] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80027e4: 4313 orrs r3, r2
80027e6: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART7 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
80027ea: 687b ldr r3, [r7, #4]
80027ec: 681b ldr r3, [r3, #0]
80027ee: f403 5380 and.w r3, r3, #4096 @ 0x1000
80027f2: 2b00 cmp r3, #0
80027f4: d00a beq.n 800280c <HAL_RCCEx_PeriphCLKConfig+0x368>
{
/* Check the parameters */
assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
/* Configure the UART7 clock source */
__HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
80027f6: 4b42 ldr r3, [pc, #264] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80027f8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80027fc: f423 5240 bic.w r2, r3, #12288 @ 0x3000
8002800: 687b ldr r3, [r7, #4]
8002802: 6d5b ldr r3, [r3, #84] @ 0x54
8002804: 493e ldr r1, [pc, #248] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002806: 4313 orrs r3, r2
8002808: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART8 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
800280c: 687b ldr r3, [r7, #4]
800280e: 681b ldr r3, [r3, #0]
8002810: f403 5300 and.w r3, r3, #8192 @ 0x2000
8002814: 2b00 cmp r3, #0
8002816: d00a beq.n 800282e <HAL_RCCEx_PeriphCLKConfig+0x38a>
{
/* Check the parameters */
assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
/* Configure the UART8 clock source */
__HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
8002818: 4b39 ldr r3, [pc, #228] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800281a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800281e: f423 4240 bic.w r2, r3, #49152 @ 0xc000
8002822: 687b ldr r3, [r7, #4]
8002824: 6d9b ldr r3, [r3, #88] @ 0x58
8002826: 4936 ldr r1, [pc, #216] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002828: 4313 orrs r3, r2
800282a: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- CK48 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
800282e: 687b ldr r3, [r7, #4]
8002830: 681b ldr r3, [r3, #0]
8002832: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8002836: 2b00 cmp r3, #0
8002838: d011 beq.n 800285e <HAL_RCCEx_PeriphCLKConfig+0x3ba>
{
/* Check the parameters */
assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
/* Configure the CLK48 source */
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
800283a: 4b31 ldr r3, [pc, #196] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800283c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002840: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000
8002844: 687b ldr r3, [r7, #4]
8002846: 6f5b ldr r3, [r3, #116] @ 0x74
8002848: 492d ldr r1, [pc, #180] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800284a: 4313 orrs r3, r2
800284c: f8c1 3090 str.w r3, [r1, #144] @ 0x90
/* Enable the PLLSAI when it's used as clock source for CK48 */
if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
8002850: 687b ldr r3, [r7, #4]
8002852: 6f5b ldr r3, [r3, #116] @ 0x74
8002854: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
8002858: d101 bne.n 800285e <HAL_RCCEx_PeriphCLKConfig+0x3ba>
{
pllsaiused = 1;
800285a: 2301 movs r3, #1
800285c: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
800285e: 687b ldr r3, [r7, #4]
8002860: 681b ldr r3, [r3, #0]
8002862: f403 2380 and.w r3, r3, #262144 @ 0x40000
8002866: 2b00 cmp r3, #0
8002868: d00a beq.n 8002880 <HAL_RCCEx_PeriphCLKConfig+0x3dc>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LTPIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
800286a: 4b25 ldr r3, [pc, #148] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800286c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002870: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
8002874: 687b ldr r3, [r7, #4]
8002876: 6edb ldr r3, [r3, #108] @ 0x6c
8002878: 4921 ldr r1, [pc, #132] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800287a: 4313 orrs r3, r2
800287c: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*------------------------------------- SDMMC1 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
8002880: 687b ldr r3, [r7, #4]
8002882: 681b ldr r3, [r3, #0]
8002884: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8002888: 2b00 cmp r3, #0
800288a: d00a beq.n 80028a2 <HAL_RCCEx_PeriphCLKConfig+0x3fe>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
/* Configure the SDMMC1 clock source */
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
800288c: 4b1c ldr r3, [pc, #112] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800288e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002892: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000
8002896: 687b ldr r3, [r7, #4]
8002898: 6f9b ldr r3, [r3, #120] @ 0x78
800289a: 4919 ldr r1, [pc, #100] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800289c: 4313 orrs r3, r2
800289e: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*------------------------------------- SDMMC2 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
80028a2: 687b ldr r3, [r7, #4]
80028a4: 681b ldr r3, [r3, #0]
80028a6: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
80028aa: 2b00 cmp r3, #0
80028ac: d00a beq.n 80028c4 <HAL_RCCEx_PeriphCLKConfig+0x420>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
/* Configure the SDMMC2 clock source */
__HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
80028ae: 4b14 ldr r3, [pc, #80] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80028b0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80028b4: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000
80028b8: 687b ldr r3, [r7, #4]
80028ba: 6fdb ldr r3, [r3, #124] @ 0x7c
80028bc: 4910 ldr r1, [pc, #64] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80028be: 4313 orrs r3, r2
80028c0: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */
if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
80028c4: 69fb ldr r3, [r7, #28]
80028c6: 2b01 cmp r3, #1
80028c8: d006 beq.n 80028d8 <HAL_RCCEx_PeriphCLKConfig+0x434>
80028ca: 687b ldr r3, [r7, #4]
80028cc: 681b ldr r3, [r3, #0]
80028ce: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80028d2: 2b00 cmp r3, #0
80028d4: f000 809d beq.w 8002a12 <HAL_RCCEx_PeriphCLKConfig+0x56e>
{
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
80028d8: 4b09 ldr r3, [pc, #36] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80028da: 681b ldr r3, [r3, #0]
80028dc: 4a08 ldr r2, [pc, #32] @ (8002900 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80028de: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
80028e2: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80028e4: f7fe fdec bl 80014c0 <HAL_GetTick>
80028e8: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
80028ea: e00b b.n 8002904 <HAL_RCCEx_PeriphCLKConfig+0x460>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
80028ec: f7fe fde8 bl 80014c0 <HAL_GetTick>
80028f0: 4602 mov r2, r0
80028f2: 697b ldr r3, [r7, #20]
80028f4: 1ad3 subs r3, r2, r3
80028f6: 2b64 cmp r3, #100 @ 0x64
80028f8: d904 bls.n 8002904 <HAL_RCCEx_PeriphCLKConfig+0x460>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
80028fa: 2303 movs r3, #3
80028fc: e116 b.n 8002b2c <HAL_RCCEx_PeriphCLKConfig+0x688>
80028fe: bf00 nop
8002900: 40023800 .word 0x40023800
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8002904: 4b8b ldr r3, [pc, #556] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002906: 681b ldr r3, [r3, #0]
8002908: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
800290c: 2b00 cmp r3, #0
800290e: d1ed bne.n 80028ec <HAL_RCCEx_PeriphCLKConfig+0x448>
/* check for common PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
/*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
8002910: 687b ldr r3, [r7, #4]
8002912: 681b ldr r3, [r3, #0]
8002914: f003 0301 and.w r3, r3, #1
8002918: 2b00 cmp r3, #0
800291a: d017 beq.n 800294c <HAL_RCCEx_PeriphCLKConfig+0x4a8>
800291c: 687b ldr r3, [r7, #4]
800291e: 6adb ldr r3, [r3, #44] @ 0x2c
8002920: 2b00 cmp r3, #0
8002922: d113 bne.n 800294c <HAL_RCCEx_PeriphCLKConfig+0x4a8>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
8002924: 4b83 ldr r3, [pc, #524] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002926: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
800292a: 0e1b lsrs r3, r3, #24
800292c: f003 030f and.w r3, r3, #15
8002930: 613b str r3, [r7, #16]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2SR);
8002932: 687b ldr r3, [r7, #4]
8002934: 685b ldr r3, [r3, #4]
8002936: 019a lsls r2, r3, #6
8002938: 693b ldr r3, [r7, #16]
800293a: 061b lsls r3, r3, #24
800293c: 431a orrs r2, r3
800293e: 687b ldr r3, [r7, #4]
8002940: 689b ldr r3, [r3, #8]
8002942: 071b lsls r3, r3, #28
8002944: 497b ldr r1, [pc, #492] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002946: 4313 orrs r3, r2
8002948: f8c1 3084 str.w r3, [r1, #132] @ 0x84
}
/*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
800294c: 687b ldr r3, [r7, #4]
800294e: 681b ldr r3, [r3, #0]
8002950: f403 2300 and.w r3, r3, #524288 @ 0x80000
8002954: 2b00 cmp r3, #0
8002956: d004 beq.n 8002962 <HAL_RCCEx_PeriphCLKConfig+0x4be>
8002958: 687b ldr r3, [r7, #4]
800295a: 6b5b ldr r3, [r3, #52] @ 0x34
800295c: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8002960: d00a beq.n 8002978 <HAL_RCCEx_PeriphCLKConfig+0x4d4>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
8002962: 687b ldr r3, [r7, #4]
8002964: 681b ldr r3, [r3, #0]
8002966: f403 1380 and.w r3, r3, #1048576 @ 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
800296a: 2b00 cmp r3, #0
800296c: d024 beq.n 80029b8 <HAL_RCCEx_PeriphCLKConfig+0x514>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
800296e: 687b ldr r3, [r7, #4]
8002970: 6b9b ldr r3, [r3, #56] @ 0x38
8002972: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8002976: d11f bne.n 80029b8 <HAL_RCCEx_PeriphCLKConfig+0x514>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Check for PLLI2S/DIVQ parameters */
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
8002978: 4b6e ldr r3, [pc, #440] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800297a: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
800297e: 0f1b lsrs r3, r3, #28
8002980: f003 0307 and.w r3, r3, #7
8002984: 613b str r3, [r7, #16]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0);
8002986: 687b ldr r3, [r7, #4]
8002988: 685b ldr r3, [r3, #4]
800298a: 019a lsls r2, r3, #6
800298c: 687b ldr r3, [r7, #4]
800298e: 68db ldr r3, [r3, #12]
8002990: 061b lsls r3, r3, #24
8002992: 431a orrs r2, r3
8002994: 693b ldr r3, [r7, #16]
8002996: 071b lsls r3, r3, #28
8002998: 4966 ldr r1, [pc, #408] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800299a: 4313 orrs r3, r2
800299c: f8c1 3084 str.w r3, [r1, #132] @ 0x84
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
80029a0: 4b64 ldr r3, [pc, #400] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80029a2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
80029a6: f023 021f bic.w r2, r3, #31
80029aa: 687b ldr r3, [r7, #4]
80029ac: 69db ldr r3, [r3, #28]
80029ae: 3b01 subs r3, #1
80029b0: 4960 ldr r1, [pc, #384] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80029b2: 4313 orrs r3, r2
80029b4: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
80029b8: 687b ldr r3, [r7, #4]
80029ba: 681b ldr r3, [r3, #0]
80029bc: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80029c0: 2b00 cmp r3, #0
80029c2: d00d beq.n 80029e0 <HAL_RCCEx_PeriphCLKConfig+0x53c>
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
80029c4: 687b ldr r3, [r7, #4]
80029c6: 685b ldr r3, [r3, #4]
80029c8: 019a lsls r2, r3, #6
80029ca: 687b ldr r3, [r7, #4]
80029cc: 68db ldr r3, [r3, #12]
80029ce: 061b lsls r3, r3, #24
80029d0: 431a orrs r2, r3
80029d2: 687b ldr r3, [r7, #4]
80029d4: 689b ldr r3, [r3, #8]
80029d6: 071b lsls r3, r3, #28
80029d8: 4956 ldr r1, [pc, #344] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80029da: 4313 orrs r3, r2
80029dc: f8c1 3084 str.w r3, [r1, #132] @ 0x84
}
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
80029e0: 4b54 ldr r3, [pc, #336] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80029e2: 681b ldr r3, [r3, #0]
80029e4: 4a53 ldr r2, [pc, #332] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80029e6: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
80029ea: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80029ec: f7fe fd68 bl 80014c0 <HAL_GetTick>
80029f0: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
80029f2: e008 b.n 8002a06 <HAL_RCCEx_PeriphCLKConfig+0x562>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
80029f4: f7fe fd64 bl 80014c0 <HAL_GetTick>
80029f8: 4602 mov r2, r0
80029fa: 697b ldr r3, [r7, #20]
80029fc: 1ad3 subs r3, r2, r3
80029fe: 2b64 cmp r3, #100 @ 0x64
8002a00: d901 bls.n 8002a06 <HAL_RCCEx_PeriphCLKConfig+0x562>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8002a02: 2303 movs r3, #3
8002a04: e092 b.n 8002b2c <HAL_RCCEx_PeriphCLKConfig+0x688>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
8002a06: 4b4b ldr r3, [pc, #300] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002a08: 681b ldr r3, [r3, #0]
8002a0a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
8002a0e: 2b00 cmp r3, #0
8002a10: d0f0 beq.n 80029f4 <HAL_RCCEx_PeriphCLKConfig+0x550>
}
}
/*-------------------------------------- PLLSAI Configuration ---------------------------------*/
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
if(pllsaiused == 1)
8002a12: 69bb ldr r3, [r7, #24]
8002a14: 2b01 cmp r3, #1
8002a16: f040 8088 bne.w 8002b2a <HAL_RCCEx_PeriphCLKConfig+0x686>
{
/* Disable PLLSAI Clock */
__HAL_RCC_PLLSAI_DISABLE();
8002a1a: 4b46 ldr r3, [pc, #280] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002a1c: 681b ldr r3, [r3, #0]
8002a1e: 4a45 ldr r2, [pc, #276] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002a20: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8002a24: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002a26: f7fe fd4b bl 80014c0 <HAL_GetTick>
8002a2a: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
8002a2c: e008 b.n 8002a40 <HAL_RCCEx_PeriphCLKConfig+0x59c>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
8002a2e: f7fe fd47 bl 80014c0 <HAL_GetTick>
8002a32: 4602 mov r2, r0
8002a34: 697b ldr r3, [r7, #20]
8002a36: 1ad3 subs r3, r2, r3
8002a38: 2b64 cmp r3, #100 @ 0x64
8002a3a: d901 bls.n 8002a40 <HAL_RCCEx_PeriphCLKConfig+0x59c>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8002a3c: 2303 movs r3, #3
8002a3e: e075 b.n 8002b2c <HAL_RCCEx_PeriphCLKConfig+0x688>
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
8002a40: 4b3c ldr r3, [pc, #240] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002a42: 681b ldr r3, [r3, #0]
8002a44: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
8002a48: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8002a4c: d0ef beq.n 8002a2e <HAL_RCCEx_PeriphCLKConfig+0x58a>
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
/*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
8002a4e: 687b ldr r3, [r7, #4]
8002a50: 681b ldr r3, [r3, #0]
8002a52: f403 2300 and.w r3, r3, #524288 @ 0x80000
8002a56: 2b00 cmp r3, #0
8002a58: d003 beq.n 8002a62 <HAL_RCCEx_PeriphCLKConfig+0x5be>
8002a5a: 687b ldr r3, [r7, #4]
8002a5c: 6b5b ldr r3, [r3, #52] @ 0x34
8002a5e: 2b00 cmp r3, #0
8002a60: d009 beq.n 8002a76 <HAL_RCCEx_PeriphCLKConfig+0x5d2>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
8002a62: 687b ldr r3, [r7, #4]
8002a64: 681b ldr r3, [r3, #0]
8002a66: f403 1380 and.w r3, r3, #1048576 @ 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
8002a6a: 2b00 cmp r3, #0
8002a6c: d024 beq.n 8002ab8 <HAL_RCCEx_PeriphCLKConfig+0x614>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
8002a6e: 687b ldr r3, [r7, #4]
8002a70: 6b9b ldr r3, [r3, #56] @ 0x38
8002a72: 2b00 cmp r3, #0
8002a74: d120 bne.n 8002ab8 <HAL_RCCEx_PeriphCLKConfig+0x614>
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
/* check for PLLSAI/DIVQ Parameter */
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
8002a76: 4b2f ldr r3, [pc, #188] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002a78: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8002a7c: 0c1b lsrs r3, r3, #16
8002a7e: f003 0303 and.w r3, r3, #3
8002a82: 613b str r3, [r7, #16]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ);
8002a84: 687b ldr r3, [r7, #4]
8002a86: 691b ldr r3, [r3, #16]
8002a88: 019a lsls r2, r3, #6
8002a8a: 693b ldr r3, [r7, #16]
8002a8c: 041b lsls r3, r3, #16
8002a8e: 431a orrs r2, r3
8002a90: 687b ldr r3, [r7, #4]
8002a92: 695b ldr r3, [r3, #20]
8002a94: 061b lsls r3, r3, #24
8002a96: 4927 ldr r1, [pc, #156] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002a98: 4313 orrs r3, r2
8002a9a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
8002a9e: 4b25 ldr r3, [pc, #148] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002aa0: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8002aa4: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
8002aa8: 687b ldr r3, [r7, #4]
8002aaa: 6a1b ldr r3, [r3, #32]
8002aac: 3b01 subs r3, #1
8002aae: 021b lsls r3, r3, #8
8002ab0: 4920 ldr r1, [pc, #128] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002ab2: 4313 orrs r3, r2
8002ab4: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
/* In Case of PLLI2S is selected as source clock for CK48 */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
8002ab8: 687b ldr r3, [r7, #4]
8002aba: 681b ldr r3, [r3, #0]
8002abc: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8002ac0: 2b00 cmp r3, #0
8002ac2: d018 beq.n 8002af6 <HAL_RCCEx_PeriphCLKConfig+0x652>
8002ac4: 687b ldr r3, [r7, #4]
8002ac6: 6f5b ldr r3, [r3, #116] @ 0x74
8002ac8: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
8002acc: d113 bne.n 8002af6 <HAL_RCCEx_PeriphCLKConfig+0x652>
{
/* check for Parameters */
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
8002ace: 4b19 ldr r3, [pc, #100] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002ad0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8002ad4: 0e1b lsrs r3, r3, #24
8002ad6: f003 030f and.w r3, r3, #15
8002ada: 613b str r3, [r7, #16]
/* Configure the PLLSAI division factors */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0);
8002adc: 687b ldr r3, [r7, #4]
8002ade: 691b ldr r3, [r3, #16]
8002ae0: 019a lsls r2, r3, #6
8002ae2: 687b ldr r3, [r7, #4]
8002ae4: 699b ldr r3, [r3, #24]
8002ae6: 041b lsls r3, r3, #16
8002ae8: 431a orrs r2, r3
8002aea: 693b ldr r3, [r7, #16]
8002aec: 061b lsls r3, r3, #24
8002aee: 4911 ldr r1, [pc, #68] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002af0: 4313 orrs r3, r2
8002af2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
8002af6: 4b0f ldr r3, [pc, #60] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002af8: 681b ldr r3, [r3, #0]
8002afa: 4a0e ldr r2, [pc, #56] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002afc: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002b00: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002b02: f7fe fcdd bl 80014c0 <HAL_GetTick>
8002b06: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is ready */
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
8002b08: e008 b.n 8002b1c <HAL_RCCEx_PeriphCLKConfig+0x678>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
8002b0a: f7fe fcd9 bl 80014c0 <HAL_GetTick>
8002b0e: 4602 mov r2, r0
8002b10: 697b ldr r3, [r7, #20]
8002b12: 1ad3 subs r3, r2, r3
8002b14: 2b64 cmp r3, #100 @ 0x64
8002b16: d901 bls.n 8002b1c <HAL_RCCEx_PeriphCLKConfig+0x678>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8002b18: 2303 movs r3, #3
8002b1a: e007 b.n 8002b2c <HAL_RCCEx_PeriphCLKConfig+0x688>
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
8002b1c: 4b05 ldr r3, [pc, #20] @ (8002b34 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002b1e: 681b ldr r3, [r3, #0]
8002b20: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
8002b24: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8002b28: d1ef bne.n 8002b0a <HAL_RCCEx_PeriphCLKConfig+0x666>
}
}
}
return HAL_OK;
8002b2a: 2300 movs r3, #0
}
8002b2c: 4618 mov r0, r3
8002b2e: 3720 adds r7, #32
8002b30: 46bd mov sp, r7
8002b32: bd80 pop {r7, pc}
8002b34: 40023800 .word 0x40023800
08002b38 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8002b38: b580 push {r7, lr}
8002b3a: b082 sub sp, #8
8002b3c: af00 add r7, sp, #0
8002b3e: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8002b40: 687b ldr r3, [r7, #4]
8002b42: 2b00 cmp r3, #0
8002b44: d101 bne.n 8002b4a <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8002b46: 2301 movs r3, #1
8002b48: e049 b.n 8002bde <HAL_TIM_Base_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8002b4a: 687b ldr r3, [r7, #4]
8002b4c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8002b50: b2db uxtb r3, r3
8002b52: 2b00 cmp r3, #0
8002b54: d106 bne.n 8002b64 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8002b56: 687b ldr r3, [r7, #4]
8002b58: 2200 movs r2, #0
8002b5a: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8002b5e: 6878 ldr r0, [r7, #4]
8002b60: f000 f841 bl 8002be6 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002b64: 687b ldr r3, [r7, #4]
8002b66: 2202 movs r2, #2
8002b68: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8002b6c: 687b ldr r3, [r7, #4]
8002b6e: 681a ldr r2, [r3, #0]
8002b70: 687b ldr r3, [r7, #4]
8002b72: 3304 adds r3, #4
8002b74: 4619 mov r1, r3
8002b76: 4610 mov r0, r2
8002b78: f000 f9e8 bl 8002f4c <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8002b7c: 687b ldr r3, [r7, #4]
8002b7e: 2201 movs r2, #1
8002b80: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002b84: 687b ldr r3, [r7, #4]
8002b86: 2201 movs r2, #1
8002b88: f883 203e strb.w r2, [r3, #62] @ 0x3e
8002b8c: 687b ldr r3, [r7, #4]
8002b8e: 2201 movs r2, #1
8002b90: f883 203f strb.w r2, [r3, #63] @ 0x3f
8002b94: 687b ldr r3, [r7, #4]
8002b96: 2201 movs r2, #1
8002b98: f883 2040 strb.w r2, [r3, #64] @ 0x40
8002b9c: 687b ldr r3, [r7, #4]
8002b9e: 2201 movs r2, #1
8002ba0: f883 2041 strb.w r2, [r3, #65] @ 0x41
8002ba4: 687b ldr r3, [r7, #4]
8002ba6: 2201 movs r2, #1
8002ba8: f883 2042 strb.w r2, [r3, #66] @ 0x42
8002bac: 687b ldr r3, [r7, #4]
8002bae: 2201 movs r2, #1
8002bb0: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002bb4: 687b ldr r3, [r7, #4]
8002bb6: 2201 movs r2, #1
8002bb8: f883 2044 strb.w r2, [r3, #68] @ 0x44
8002bbc: 687b ldr r3, [r7, #4]
8002bbe: 2201 movs r2, #1
8002bc0: f883 2045 strb.w r2, [r3, #69] @ 0x45
8002bc4: 687b ldr r3, [r7, #4]
8002bc6: 2201 movs r2, #1
8002bc8: f883 2046 strb.w r2, [r3, #70] @ 0x46
8002bcc: 687b ldr r3, [r7, #4]
8002bce: 2201 movs r2, #1
8002bd0: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8002bd4: 687b ldr r3, [r7, #4]
8002bd6: 2201 movs r2, #1
8002bd8: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8002bdc: 2300 movs r3, #0
}
8002bde: 4618 mov r0, r3
8002be0: 3708 adds r7, #8
8002be2: 46bd mov sp, r7
8002be4: bd80 pop {r7, pc}
08002be6 <HAL_TIM_Base_MspInit>:
* @brief Initializes the TIM Base MSP.
* @param htim TIM Base handle
* @retval None
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
8002be6: b480 push {r7}
8002be8: b083 sub sp, #12
8002bea: af00 add r7, sp, #0
8002bec: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Base_MspInit could be implemented in the user file
*/
}
8002bee: bf00 nop
8002bf0: 370c adds r7, #12
8002bf2: 46bd mov sp, r7
8002bf4: f85d 7b04 ldr.w r7, [sp], #4
8002bf8: 4770 bx lr
...
08002bfc <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8002bfc: b480 push {r7}
8002bfe: b085 sub sp, #20
8002c00: af00 add r7, sp, #0
8002c02: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
8002c04: 687b ldr r3, [r7, #4]
8002c06: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8002c0a: b2db uxtb r3, r3
8002c0c: 2b01 cmp r3, #1
8002c0e: d001 beq.n 8002c14 <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
8002c10: 2301 movs r3, #1
8002c12: e054 b.n 8002cbe <HAL_TIM_Base_Start_IT+0xc2>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002c14: 687b ldr r3, [r7, #4]
8002c16: 2202 movs r2, #2
8002c18: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8002c1c: 687b ldr r3, [r7, #4]
8002c1e: 681b ldr r3, [r3, #0]
8002c20: 68da ldr r2, [r3, #12]
8002c22: 687b ldr r3, [r7, #4]
8002c24: 681b ldr r3, [r3, #0]
8002c26: f042 0201 orr.w r2, r2, #1
8002c2a: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8002c2c: 687b ldr r3, [r7, #4]
8002c2e: 681b ldr r3, [r3, #0]
8002c30: 4a26 ldr r2, [pc, #152] @ (8002ccc <HAL_TIM_Base_Start_IT+0xd0>)
8002c32: 4293 cmp r3, r2
8002c34: d022 beq.n 8002c7c <HAL_TIM_Base_Start_IT+0x80>
8002c36: 687b ldr r3, [r7, #4]
8002c38: 681b ldr r3, [r3, #0]
8002c3a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8002c3e: d01d beq.n 8002c7c <HAL_TIM_Base_Start_IT+0x80>
8002c40: 687b ldr r3, [r7, #4]
8002c42: 681b ldr r3, [r3, #0]
8002c44: 4a22 ldr r2, [pc, #136] @ (8002cd0 <HAL_TIM_Base_Start_IT+0xd4>)
8002c46: 4293 cmp r3, r2
8002c48: d018 beq.n 8002c7c <HAL_TIM_Base_Start_IT+0x80>
8002c4a: 687b ldr r3, [r7, #4]
8002c4c: 681b ldr r3, [r3, #0]
8002c4e: 4a21 ldr r2, [pc, #132] @ (8002cd4 <HAL_TIM_Base_Start_IT+0xd8>)
8002c50: 4293 cmp r3, r2
8002c52: d013 beq.n 8002c7c <HAL_TIM_Base_Start_IT+0x80>
8002c54: 687b ldr r3, [r7, #4]
8002c56: 681b ldr r3, [r3, #0]
8002c58: 4a1f ldr r2, [pc, #124] @ (8002cd8 <HAL_TIM_Base_Start_IT+0xdc>)
8002c5a: 4293 cmp r3, r2
8002c5c: d00e beq.n 8002c7c <HAL_TIM_Base_Start_IT+0x80>
8002c5e: 687b ldr r3, [r7, #4]
8002c60: 681b ldr r3, [r3, #0]
8002c62: 4a1e ldr r2, [pc, #120] @ (8002cdc <HAL_TIM_Base_Start_IT+0xe0>)
8002c64: 4293 cmp r3, r2
8002c66: d009 beq.n 8002c7c <HAL_TIM_Base_Start_IT+0x80>
8002c68: 687b ldr r3, [r7, #4]
8002c6a: 681b ldr r3, [r3, #0]
8002c6c: 4a1c ldr r2, [pc, #112] @ (8002ce0 <HAL_TIM_Base_Start_IT+0xe4>)
8002c6e: 4293 cmp r3, r2
8002c70: d004 beq.n 8002c7c <HAL_TIM_Base_Start_IT+0x80>
8002c72: 687b ldr r3, [r7, #4]
8002c74: 681b ldr r3, [r3, #0]
8002c76: 4a1b ldr r2, [pc, #108] @ (8002ce4 <HAL_TIM_Base_Start_IT+0xe8>)
8002c78: 4293 cmp r3, r2
8002c7a: d115 bne.n 8002ca8 <HAL_TIM_Base_Start_IT+0xac>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8002c7c: 687b ldr r3, [r7, #4]
8002c7e: 681b ldr r3, [r3, #0]
8002c80: 689a ldr r2, [r3, #8]
8002c82: 4b19 ldr r3, [pc, #100] @ (8002ce8 <HAL_TIM_Base_Start_IT+0xec>)
8002c84: 4013 ands r3, r2
8002c86: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002c88: 68fb ldr r3, [r7, #12]
8002c8a: 2b06 cmp r3, #6
8002c8c: d015 beq.n 8002cba <HAL_TIM_Base_Start_IT+0xbe>
8002c8e: 68fb ldr r3, [r7, #12]
8002c90: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8002c94: d011 beq.n 8002cba <HAL_TIM_Base_Start_IT+0xbe>
{
__HAL_TIM_ENABLE(htim);
8002c96: 687b ldr r3, [r7, #4]
8002c98: 681b ldr r3, [r3, #0]
8002c9a: 681a ldr r2, [r3, #0]
8002c9c: 687b ldr r3, [r7, #4]
8002c9e: 681b ldr r3, [r3, #0]
8002ca0: f042 0201 orr.w r2, r2, #1
8002ca4: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002ca6: e008 b.n 8002cba <HAL_TIM_Base_Start_IT+0xbe>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8002ca8: 687b ldr r3, [r7, #4]
8002caa: 681b ldr r3, [r3, #0]
8002cac: 681a ldr r2, [r3, #0]
8002cae: 687b ldr r3, [r7, #4]
8002cb0: 681b ldr r3, [r3, #0]
8002cb2: f042 0201 orr.w r2, r2, #1
8002cb6: 601a str r2, [r3, #0]
8002cb8: e000 b.n 8002cbc <HAL_TIM_Base_Start_IT+0xc0>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002cba: bf00 nop
}
/* Return function status */
return HAL_OK;
8002cbc: 2300 movs r3, #0
}
8002cbe: 4618 mov r0, r3
8002cc0: 3714 adds r7, #20
8002cc2: 46bd mov sp, r7
8002cc4: f85d 7b04 ldr.w r7, [sp], #4
8002cc8: 4770 bx lr
8002cca: bf00 nop
8002ccc: 40010000 .word 0x40010000
8002cd0: 40000400 .word 0x40000400
8002cd4: 40000800 .word 0x40000800
8002cd8: 40000c00 .word 0x40000c00
8002cdc: 40010400 .word 0x40010400
8002ce0: 40014000 .word 0x40014000
8002ce4: 40001800 .word 0x40001800
8002ce8: 00010007 .word 0x00010007
08002cec <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8002cec: b580 push {r7, lr}
8002cee: b084 sub sp, #16
8002cf0: af00 add r7, sp, #0
8002cf2: 6078 str r0, [r7, #4]
uint32_t itsource = htim->Instance->DIER;
8002cf4: 687b ldr r3, [r7, #4]
8002cf6: 681b ldr r3, [r3, #0]
8002cf8: 68db ldr r3, [r3, #12]
8002cfa: 60fb str r3, [r7, #12]
uint32_t itflag = htim->Instance->SR;
8002cfc: 687b ldr r3, [r7, #4]
8002cfe: 681b ldr r3, [r3, #0]
8002d00: 691b ldr r3, [r3, #16]
8002d02: 60bb str r3, [r7, #8]
/* Capture compare 1 event */
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
8002d04: 68bb ldr r3, [r7, #8]
8002d06: f003 0302 and.w r3, r3, #2
8002d0a: 2b00 cmp r3, #0
8002d0c: d020 beq.n 8002d50 <HAL_TIM_IRQHandler+0x64>
{
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
8002d0e: 68fb ldr r3, [r7, #12]
8002d10: f003 0302 and.w r3, r3, #2
8002d14: 2b00 cmp r3, #0
8002d16: d01b beq.n 8002d50 <HAL_TIM_IRQHandler+0x64>
{
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
8002d18: 687b ldr r3, [r7, #4]
8002d1a: 681b ldr r3, [r3, #0]
8002d1c: f06f 0202 mvn.w r2, #2
8002d20: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8002d22: 687b ldr r3, [r7, #4]
8002d24: 2201 movs r2, #1
8002d26: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8002d28: 687b ldr r3, [r7, #4]
8002d2a: 681b ldr r3, [r3, #0]
8002d2c: 699b ldr r3, [r3, #24]
8002d2e: f003 0303 and.w r3, r3, #3
8002d32: 2b00 cmp r3, #0
8002d34: d003 beq.n 8002d3e <HAL_TIM_IRQHandler+0x52>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002d36: 6878 ldr r0, [r7, #4]
8002d38: f000 f8e9 bl 8002f0e <HAL_TIM_IC_CaptureCallback>
8002d3c: e005 b.n 8002d4a <HAL_TIM_IRQHandler+0x5e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002d3e: 6878 ldr r0, [r7, #4]
8002d40: f000 f8db bl 8002efa <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002d44: 6878 ldr r0, [r7, #4]
8002d46: f000 f8ec bl 8002f22 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002d4a: 687b ldr r3, [r7, #4]
8002d4c: 2200 movs r2, #0
8002d4e: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
8002d50: 68bb ldr r3, [r7, #8]
8002d52: f003 0304 and.w r3, r3, #4
8002d56: 2b00 cmp r3, #0
8002d58: d020 beq.n 8002d9c <HAL_TIM_IRQHandler+0xb0>
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
8002d5a: 68fb ldr r3, [r7, #12]
8002d5c: f003 0304 and.w r3, r3, #4
8002d60: 2b00 cmp r3, #0
8002d62: d01b beq.n 8002d9c <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
8002d64: 687b ldr r3, [r7, #4]
8002d66: 681b ldr r3, [r3, #0]
8002d68: f06f 0204 mvn.w r2, #4
8002d6c: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8002d6e: 687b ldr r3, [r7, #4]
8002d70: 2202 movs r2, #2
8002d72: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8002d74: 687b ldr r3, [r7, #4]
8002d76: 681b ldr r3, [r3, #0]
8002d78: 699b ldr r3, [r3, #24]
8002d7a: f403 7340 and.w r3, r3, #768 @ 0x300
8002d7e: 2b00 cmp r3, #0
8002d80: d003 beq.n 8002d8a <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002d82: 6878 ldr r0, [r7, #4]
8002d84: f000 f8c3 bl 8002f0e <HAL_TIM_IC_CaptureCallback>
8002d88: e005 b.n 8002d96 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002d8a: 6878 ldr r0, [r7, #4]
8002d8c: f000 f8b5 bl 8002efa <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002d90: 6878 ldr r0, [r7, #4]
8002d92: f000 f8c6 bl 8002f22 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002d96: 687b ldr r3, [r7, #4]
8002d98: 2200 movs r2, #0
8002d9a: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
8002d9c: 68bb ldr r3, [r7, #8]
8002d9e: f003 0308 and.w r3, r3, #8
8002da2: 2b00 cmp r3, #0
8002da4: d020 beq.n 8002de8 <HAL_TIM_IRQHandler+0xfc>
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
8002da6: 68fb ldr r3, [r7, #12]
8002da8: f003 0308 and.w r3, r3, #8
8002dac: 2b00 cmp r3, #0
8002dae: d01b beq.n 8002de8 <HAL_TIM_IRQHandler+0xfc>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
8002db0: 687b ldr r3, [r7, #4]
8002db2: 681b ldr r3, [r3, #0]
8002db4: f06f 0208 mvn.w r2, #8
8002db8: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8002dba: 687b ldr r3, [r7, #4]
8002dbc: 2204 movs r2, #4
8002dbe: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8002dc0: 687b ldr r3, [r7, #4]
8002dc2: 681b ldr r3, [r3, #0]
8002dc4: 69db ldr r3, [r3, #28]
8002dc6: f003 0303 and.w r3, r3, #3
8002dca: 2b00 cmp r3, #0
8002dcc: d003 beq.n 8002dd6 <HAL_TIM_IRQHandler+0xea>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002dce: 6878 ldr r0, [r7, #4]
8002dd0: f000 f89d bl 8002f0e <HAL_TIM_IC_CaptureCallback>
8002dd4: e005 b.n 8002de2 <HAL_TIM_IRQHandler+0xf6>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002dd6: 6878 ldr r0, [r7, #4]
8002dd8: f000 f88f bl 8002efa <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002ddc: 6878 ldr r0, [r7, #4]
8002dde: f000 f8a0 bl 8002f22 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002de2: 687b ldr r3, [r7, #4]
8002de4: 2200 movs r2, #0
8002de6: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
8002de8: 68bb ldr r3, [r7, #8]
8002dea: f003 0310 and.w r3, r3, #16
8002dee: 2b00 cmp r3, #0
8002df0: d020 beq.n 8002e34 <HAL_TIM_IRQHandler+0x148>
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
8002df2: 68fb ldr r3, [r7, #12]
8002df4: f003 0310 and.w r3, r3, #16
8002df8: 2b00 cmp r3, #0
8002dfa: d01b beq.n 8002e34 <HAL_TIM_IRQHandler+0x148>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
8002dfc: 687b ldr r3, [r7, #4]
8002dfe: 681b ldr r3, [r3, #0]
8002e00: f06f 0210 mvn.w r2, #16
8002e04: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8002e06: 687b ldr r3, [r7, #4]
8002e08: 2208 movs r2, #8
8002e0a: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8002e0c: 687b ldr r3, [r7, #4]
8002e0e: 681b ldr r3, [r3, #0]
8002e10: 69db ldr r3, [r3, #28]
8002e12: f403 7340 and.w r3, r3, #768 @ 0x300
8002e16: 2b00 cmp r3, #0
8002e18: d003 beq.n 8002e22 <HAL_TIM_IRQHandler+0x136>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002e1a: 6878 ldr r0, [r7, #4]
8002e1c: f000 f877 bl 8002f0e <HAL_TIM_IC_CaptureCallback>
8002e20: e005 b.n 8002e2e <HAL_TIM_IRQHandler+0x142>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002e22: 6878 ldr r0, [r7, #4]
8002e24: f000 f869 bl 8002efa <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002e28: 6878 ldr r0, [r7, #4]
8002e2a: f000 f87a bl 8002f22 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002e2e: 687b ldr r3, [r7, #4]
8002e30: 2200 movs r2, #0
8002e32: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
8002e34: 68bb ldr r3, [r7, #8]
8002e36: f003 0301 and.w r3, r3, #1
8002e3a: 2b00 cmp r3, #0
8002e3c: d00c beq.n 8002e58 <HAL_TIM_IRQHandler+0x16c>
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
8002e3e: 68fb ldr r3, [r7, #12]
8002e40: f003 0301 and.w r3, r3, #1
8002e44: 2b00 cmp r3, #0
8002e46: d007 beq.n 8002e58 <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
8002e48: 687b ldr r3, [r7, #4]
8002e4a: 681b ldr r3, [r3, #0]
8002e4c: f06f 0201 mvn.w r2, #1
8002e50: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8002e52: 6878 ldr r0, [r7, #4]
8002e54: f7fe f912 bl 800107c <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
8002e58: 68bb ldr r3, [r7, #8]
8002e5a: f003 0380 and.w r3, r3, #128 @ 0x80
8002e5e: 2b00 cmp r3, #0
8002e60: d104 bne.n 8002e6c <HAL_TIM_IRQHandler+0x180>
((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
8002e62: 68bb ldr r3, [r7, #8]
8002e64: f403 5300 and.w r3, r3, #8192 @ 0x2000
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
8002e68: 2b00 cmp r3, #0
8002e6a: d00c beq.n 8002e86 <HAL_TIM_IRQHandler+0x19a>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
8002e6c: 68fb ldr r3, [r7, #12]
8002e6e: f003 0380 and.w r3, r3, #128 @ 0x80
8002e72: 2b00 cmp r3, #0
8002e74: d007 beq.n 8002e86 <HAL_TIM_IRQHandler+0x19a>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
8002e76: 687b ldr r3, [r7, #4]
8002e78: 681b ldr r3, [r3, #0]
8002e7a: f46f 5202 mvn.w r2, #8320 @ 0x2080
8002e7e: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8002e80: 6878 ldr r0, [r7, #4]
8002e82: f000 f913 bl 80030ac <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
8002e86: 68bb ldr r3, [r7, #8]
8002e88: f403 7380 and.w r3, r3, #256 @ 0x100
8002e8c: 2b00 cmp r3, #0
8002e8e: d00c beq.n 8002eaa <HAL_TIM_IRQHandler+0x1be>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
8002e90: 68fb ldr r3, [r7, #12]
8002e92: f003 0380 and.w r3, r3, #128 @ 0x80
8002e96: 2b00 cmp r3, #0
8002e98: d007 beq.n 8002eaa <HAL_TIM_IRQHandler+0x1be>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
8002e9a: 687b ldr r3, [r7, #4]
8002e9c: 681b ldr r3, [r3, #0]
8002e9e: f46f 7280 mvn.w r2, #256 @ 0x100
8002ea2: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
8002ea4: 6878 ldr r0, [r7, #4]
8002ea6: f000 f90b bl 80030c0 <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
8002eaa: 68bb ldr r3, [r7, #8]
8002eac: f003 0340 and.w r3, r3, #64 @ 0x40
8002eb0: 2b00 cmp r3, #0
8002eb2: d00c beq.n 8002ece <HAL_TIM_IRQHandler+0x1e2>
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
8002eb4: 68fb ldr r3, [r7, #12]
8002eb6: f003 0340 and.w r3, r3, #64 @ 0x40
8002eba: 2b00 cmp r3, #0
8002ebc: d007 beq.n 8002ece <HAL_TIM_IRQHandler+0x1e2>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
8002ebe: 687b ldr r3, [r7, #4]
8002ec0: 681b ldr r3, [r3, #0]
8002ec2: f06f 0240 mvn.w r2, #64 @ 0x40
8002ec6: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8002ec8: 6878 ldr r0, [r7, #4]
8002eca: f000 f834 bl 8002f36 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
8002ece: 68bb ldr r3, [r7, #8]
8002ed0: f003 0320 and.w r3, r3, #32
8002ed4: 2b00 cmp r3, #0
8002ed6: d00c beq.n 8002ef2 <HAL_TIM_IRQHandler+0x206>
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
8002ed8: 68fb ldr r3, [r7, #12]
8002eda: f003 0320 and.w r3, r3, #32
8002ede: 2b00 cmp r3, #0
8002ee0: d007 beq.n 8002ef2 <HAL_TIM_IRQHandler+0x206>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
8002ee2: 687b ldr r3, [r7, #4]
8002ee4: 681b ldr r3, [r3, #0]
8002ee6: f06f 0220 mvn.w r2, #32
8002eea: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8002eec: 6878 ldr r0, [r7, #4]
8002eee: f000 f8d3 bl 8003098 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8002ef2: bf00 nop
8002ef4: 3710 adds r7, #16
8002ef6: 46bd mov sp, r7
8002ef8: bd80 pop {r7, pc}
08002efa <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8002efa: b480 push {r7}
8002efc: b083 sub sp, #12
8002efe: af00 add r7, sp, #0
8002f00: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8002f02: bf00 nop
8002f04: 370c adds r7, #12
8002f06: 46bd mov sp, r7
8002f08: f85d 7b04 ldr.w r7, [sp], #4
8002f0c: 4770 bx lr
08002f0e <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8002f0e: b480 push {r7}
8002f10: b083 sub sp, #12
8002f12: af00 add r7, sp, #0
8002f14: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8002f16: bf00 nop
8002f18: 370c adds r7, #12
8002f1a: 46bd mov sp, r7
8002f1c: f85d 7b04 ldr.w r7, [sp], #4
8002f20: 4770 bx lr
08002f22 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8002f22: b480 push {r7}
8002f24: b083 sub sp, #12
8002f26: af00 add r7, sp, #0
8002f28: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8002f2a: bf00 nop
8002f2c: 370c adds r7, #12
8002f2e: 46bd mov sp, r7
8002f30: f85d 7b04 ldr.w r7, [sp], #4
8002f34: 4770 bx lr
08002f36 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8002f36: b480 push {r7}
8002f38: b083 sub sp, #12
8002f3a: af00 add r7, sp, #0
8002f3c: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8002f3e: bf00 nop
8002f40: 370c adds r7, #12
8002f42: 46bd mov sp, r7
8002f44: f85d 7b04 ldr.w r7, [sp], #4
8002f48: 4770 bx lr
...
08002f4c <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8002f4c: b480 push {r7}
8002f4e: b085 sub sp, #20
8002f50: af00 add r7, sp, #0
8002f52: 6078 str r0, [r7, #4]
8002f54: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8002f56: 687b ldr r3, [r7, #4]
8002f58: 681b ldr r3, [r3, #0]
8002f5a: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8002f5c: 687b ldr r3, [r7, #4]
8002f5e: 4a43 ldr r2, [pc, #268] @ (800306c <TIM_Base_SetConfig+0x120>)
8002f60: 4293 cmp r3, r2
8002f62: d013 beq.n 8002f8c <TIM_Base_SetConfig+0x40>
8002f64: 687b ldr r3, [r7, #4]
8002f66: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8002f6a: d00f beq.n 8002f8c <TIM_Base_SetConfig+0x40>
8002f6c: 687b ldr r3, [r7, #4]
8002f6e: 4a40 ldr r2, [pc, #256] @ (8003070 <TIM_Base_SetConfig+0x124>)
8002f70: 4293 cmp r3, r2
8002f72: d00b beq.n 8002f8c <TIM_Base_SetConfig+0x40>
8002f74: 687b ldr r3, [r7, #4]
8002f76: 4a3f ldr r2, [pc, #252] @ (8003074 <TIM_Base_SetConfig+0x128>)
8002f78: 4293 cmp r3, r2
8002f7a: d007 beq.n 8002f8c <TIM_Base_SetConfig+0x40>
8002f7c: 687b ldr r3, [r7, #4]
8002f7e: 4a3e ldr r2, [pc, #248] @ (8003078 <TIM_Base_SetConfig+0x12c>)
8002f80: 4293 cmp r3, r2
8002f82: d003 beq.n 8002f8c <TIM_Base_SetConfig+0x40>
8002f84: 687b ldr r3, [r7, #4]
8002f86: 4a3d ldr r2, [pc, #244] @ (800307c <TIM_Base_SetConfig+0x130>)
8002f88: 4293 cmp r3, r2
8002f8a: d108 bne.n 8002f9e <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8002f8c: 68fb ldr r3, [r7, #12]
8002f8e: f023 0370 bic.w r3, r3, #112 @ 0x70
8002f92: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8002f94: 683b ldr r3, [r7, #0]
8002f96: 685b ldr r3, [r3, #4]
8002f98: 68fa ldr r2, [r7, #12]
8002f9a: 4313 orrs r3, r2
8002f9c: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8002f9e: 687b ldr r3, [r7, #4]
8002fa0: 4a32 ldr r2, [pc, #200] @ (800306c <TIM_Base_SetConfig+0x120>)
8002fa2: 4293 cmp r3, r2
8002fa4: d02b beq.n 8002ffe <TIM_Base_SetConfig+0xb2>
8002fa6: 687b ldr r3, [r7, #4]
8002fa8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8002fac: d027 beq.n 8002ffe <TIM_Base_SetConfig+0xb2>
8002fae: 687b ldr r3, [r7, #4]
8002fb0: 4a2f ldr r2, [pc, #188] @ (8003070 <TIM_Base_SetConfig+0x124>)
8002fb2: 4293 cmp r3, r2
8002fb4: d023 beq.n 8002ffe <TIM_Base_SetConfig+0xb2>
8002fb6: 687b ldr r3, [r7, #4]
8002fb8: 4a2e ldr r2, [pc, #184] @ (8003074 <TIM_Base_SetConfig+0x128>)
8002fba: 4293 cmp r3, r2
8002fbc: d01f beq.n 8002ffe <TIM_Base_SetConfig+0xb2>
8002fbe: 687b ldr r3, [r7, #4]
8002fc0: 4a2d ldr r2, [pc, #180] @ (8003078 <TIM_Base_SetConfig+0x12c>)
8002fc2: 4293 cmp r3, r2
8002fc4: d01b beq.n 8002ffe <TIM_Base_SetConfig+0xb2>
8002fc6: 687b ldr r3, [r7, #4]
8002fc8: 4a2c ldr r2, [pc, #176] @ (800307c <TIM_Base_SetConfig+0x130>)
8002fca: 4293 cmp r3, r2
8002fcc: d017 beq.n 8002ffe <TIM_Base_SetConfig+0xb2>
8002fce: 687b ldr r3, [r7, #4]
8002fd0: 4a2b ldr r2, [pc, #172] @ (8003080 <TIM_Base_SetConfig+0x134>)
8002fd2: 4293 cmp r3, r2
8002fd4: d013 beq.n 8002ffe <TIM_Base_SetConfig+0xb2>
8002fd6: 687b ldr r3, [r7, #4]
8002fd8: 4a2a ldr r2, [pc, #168] @ (8003084 <TIM_Base_SetConfig+0x138>)
8002fda: 4293 cmp r3, r2
8002fdc: d00f beq.n 8002ffe <TIM_Base_SetConfig+0xb2>
8002fde: 687b ldr r3, [r7, #4]
8002fe0: 4a29 ldr r2, [pc, #164] @ (8003088 <TIM_Base_SetConfig+0x13c>)
8002fe2: 4293 cmp r3, r2
8002fe4: d00b beq.n 8002ffe <TIM_Base_SetConfig+0xb2>
8002fe6: 687b ldr r3, [r7, #4]
8002fe8: 4a28 ldr r2, [pc, #160] @ (800308c <TIM_Base_SetConfig+0x140>)
8002fea: 4293 cmp r3, r2
8002fec: d007 beq.n 8002ffe <TIM_Base_SetConfig+0xb2>
8002fee: 687b ldr r3, [r7, #4]
8002ff0: 4a27 ldr r2, [pc, #156] @ (8003090 <TIM_Base_SetConfig+0x144>)
8002ff2: 4293 cmp r3, r2
8002ff4: d003 beq.n 8002ffe <TIM_Base_SetConfig+0xb2>
8002ff6: 687b ldr r3, [r7, #4]
8002ff8: 4a26 ldr r2, [pc, #152] @ (8003094 <TIM_Base_SetConfig+0x148>)
8002ffa: 4293 cmp r3, r2
8002ffc: d108 bne.n 8003010 <TIM_Base_SetConfig+0xc4>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8002ffe: 68fb ldr r3, [r7, #12]
8003000: f423 7340 bic.w r3, r3, #768 @ 0x300
8003004: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8003006: 683b ldr r3, [r7, #0]
8003008: 68db ldr r3, [r3, #12]
800300a: 68fa ldr r2, [r7, #12]
800300c: 4313 orrs r3, r2
800300e: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8003010: 68fb ldr r3, [r7, #12]
8003012: f023 0280 bic.w r2, r3, #128 @ 0x80
8003016: 683b ldr r3, [r7, #0]
8003018: 695b ldr r3, [r3, #20]
800301a: 4313 orrs r3, r2
800301c: 60fb str r3, [r7, #12]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
800301e: 683b ldr r3, [r7, #0]
8003020: 689a ldr r2, [r3, #8]
8003022: 687b ldr r3, [r7, #4]
8003024: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8003026: 683b ldr r3, [r7, #0]
8003028: 681a ldr r2, [r3, #0]
800302a: 687b ldr r3, [r7, #4]
800302c: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
800302e: 687b ldr r3, [r7, #4]
8003030: 4a0e ldr r2, [pc, #56] @ (800306c <TIM_Base_SetConfig+0x120>)
8003032: 4293 cmp r3, r2
8003034: d003 beq.n 800303e <TIM_Base_SetConfig+0xf2>
8003036: 687b ldr r3, [r7, #4]
8003038: 4a10 ldr r2, [pc, #64] @ (800307c <TIM_Base_SetConfig+0x130>)
800303a: 4293 cmp r3, r2
800303c: d103 bne.n 8003046 <TIM_Base_SetConfig+0xfa>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
800303e: 683b ldr r3, [r7, #0]
8003040: 691a ldr r2, [r3, #16]
8003042: 687b ldr r3, [r7, #4]
8003044: 631a str r2, [r3, #48] @ 0x30
}
/* Disable Update Event (UEV) with Update Generation (UG)
by changing Update Request Source (URS) to avoid Update flag (UIF) */
SET_BIT(TIMx->CR1, TIM_CR1_URS);
8003046: 687b ldr r3, [r7, #4]
8003048: 681b ldr r3, [r3, #0]
800304a: f043 0204 orr.w r2, r3, #4
800304e: 687b ldr r3, [r7, #4]
8003050: 601a str r2, [r3, #0]
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8003052: 687b ldr r3, [r7, #4]
8003054: 2201 movs r2, #1
8003056: 615a str r2, [r3, #20]
TIMx->CR1 = tmpcr1;
8003058: 687b ldr r3, [r7, #4]
800305a: 68fa ldr r2, [r7, #12]
800305c: 601a str r2, [r3, #0]
}
800305e: bf00 nop
8003060: 3714 adds r7, #20
8003062: 46bd mov sp, r7
8003064: f85d 7b04 ldr.w r7, [sp], #4
8003068: 4770 bx lr
800306a: bf00 nop
800306c: 40010000 .word 0x40010000
8003070: 40000400 .word 0x40000400
8003074: 40000800 .word 0x40000800
8003078: 40000c00 .word 0x40000c00
800307c: 40010400 .word 0x40010400
8003080: 40014000 .word 0x40014000
8003084: 40014400 .word 0x40014400
8003088: 40014800 .word 0x40014800
800308c: 40001800 .word 0x40001800
8003090: 40001c00 .word 0x40001c00
8003094: 40002000 .word 0x40002000
08003098 <HAL_TIMEx_CommutCallback>:
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8003098: b480 push {r7}
800309a: b083 sub sp, #12
800309c: af00 add r7, sp, #0
800309e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
80030a0: bf00 nop
80030a2: 370c adds r7, #12
80030a4: 46bd mov sp, r7
80030a6: f85d 7b04 ldr.w r7, [sp], #4
80030aa: 4770 bx lr
080030ac <HAL_TIMEx_BreakCallback>:
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
80030ac: b480 push {r7}
80030ae: b083 sub sp, #12
80030b0: af00 add r7, sp, #0
80030b2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
80030b4: bf00 nop
80030b6: 370c adds r7, #12
80030b8: 46bd mov sp, r7
80030ba: f85d 7b04 ldr.w r7, [sp], #4
80030be: 4770 bx lr
080030c0 <HAL_TIMEx_Break2Callback>:
* @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
80030c0: b480 push {r7}
80030c2: b083 sub sp, #12
80030c4: af00 add r7, sp, #0
80030c6: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
80030c8: bf00 nop
80030ca: 370c adds r7, #12
80030cc: 46bd mov sp, r7
80030ce: f85d 7b04 ldr.w r7, [sp], #4
80030d2: 4770 bx lr
080030d4 <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
80030d4: b580 push {r7, lr}
80030d6: b082 sub sp, #8
80030d8: af00 add r7, sp, #0
80030da: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
80030dc: 687b ldr r3, [r7, #4]
80030de: 2b00 cmp r3, #0
80030e0: d101 bne.n 80030e6 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
80030e2: 2301 movs r3, #1
80030e4: e040 b.n 8003168 <HAL_UART_Init+0x94>
{
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
}
if (huart->gState == HAL_UART_STATE_RESET)
80030e6: 687b ldr r3, [r7, #4]
80030e8: 6fdb ldr r3, [r3, #124] @ 0x7c
80030ea: 2b00 cmp r3, #0
80030ec: d106 bne.n 80030fc <HAL_UART_Init+0x28>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
80030ee: 687b ldr r3, [r7, #4]
80030f0: 2200 movs r2, #0
80030f2: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
80030f6: 6878 ldr r0, [r7, #4]
80030f8: f7fe f800 bl 80010fc <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
80030fc: 687b ldr r3, [r7, #4]
80030fe: 2224 movs r2, #36 @ 0x24
8003100: 67da str r2, [r3, #124] @ 0x7c
__HAL_UART_DISABLE(huart);
8003102: 687b ldr r3, [r7, #4]
8003104: 681b ldr r3, [r3, #0]
8003106: 681a ldr r2, [r3, #0]
8003108: 687b ldr r3, [r7, #4]
800310a: 681b ldr r3, [r3, #0]
800310c: f022 0201 bic.w r2, r2, #1
8003110: 601a str r2, [r3, #0]
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
8003112: 687b ldr r3, [r7, #4]
8003114: 6a5b ldr r3, [r3, #36] @ 0x24
8003116: 2b00 cmp r3, #0
8003118: d002 beq.n 8003120 <HAL_UART_Init+0x4c>
{
UART_AdvFeatureConfig(huart);
800311a: 6878 ldr r0, [r7, #4]
800311c: f000 fb16 bl 800374c <UART_AdvFeatureConfig>
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
8003120: 6878 ldr r0, [r7, #4]
8003122: f000 f8af bl 8003284 <UART_SetConfig>
8003126: 4603 mov r3, r0
8003128: 2b01 cmp r3, #1
800312a: d101 bne.n 8003130 <HAL_UART_Init+0x5c>
{
return HAL_ERROR;
800312c: 2301 movs r3, #1
800312e: e01b b.n 8003168 <HAL_UART_Init+0x94>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8003130: 687b ldr r3, [r7, #4]
8003132: 681b ldr r3, [r3, #0]
8003134: 685a ldr r2, [r3, #4]
8003136: 687b ldr r3, [r7, #4]
8003138: 681b ldr r3, [r3, #0]
800313a: f422 4290 bic.w r2, r2, #18432 @ 0x4800
800313e: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8003140: 687b ldr r3, [r7, #4]
8003142: 681b ldr r3, [r3, #0]
8003144: 689a ldr r2, [r3, #8]
8003146: 687b ldr r3, [r7, #4]
8003148: 681b ldr r3, [r3, #0]
800314a: f022 022a bic.w r2, r2, #42 @ 0x2a
800314e: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
8003150: 687b ldr r3, [r7, #4]
8003152: 681b ldr r3, [r3, #0]
8003154: 681a ldr r2, [r3, #0]
8003156: 687b ldr r3, [r7, #4]
8003158: 681b ldr r3, [r3, #0]
800315a: f042 0201 orr.w r2, r2, #1
800315e: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
8003160: 6878 ldr r0, [r7, #4]
8003162: f000 fb95 bl 8003890 <UART_CheckIdleState>
8003166: 4603 mov r3, r0
}
8003168: 4618 mov r0, r3
800316a: 3708 adds r7, #8
800316c: 46bd mov sp, r7
800316e: bd80 pop {r7, pc}
08003170 <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8003170: b580 push {r7, lr}
8003172: b08a sub sp, #40 @ 0x28
8003174: af02 add r7, sp, #8
8003176: 60f8 str r0, [r7, #12]
8003178: 60b9 str r1, [r7, #8]
800317a: 603b str r3, [r7, #0]
800317c: 4613 mov r3, r2
800317e: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
8003180: 68fb ldr r3, [r7, #12]
8003182: 6fdb ldr r3, [r3, #124] @ 0x7c
8003184: 2b20 cmp r3, #32
8003186: d177 bne.n 8003278 <HAL_UART_Transmit+0x108>
{
if ((pData == NULL) || (Size == 0U))
8003188: 68bb ldr r3, [r7, #8]
800318a: 2b00 cmp r3, #0
800318c: d002 beq.n 8003194 <HAL_UART_Transmit+0x24>
800318e: 88fb ldrh r3, [r7, #6]
8003190: 2b00 cmp r3, #0
8003192: d101 bne.n 8003198 <HAL_UART_Transmit+0x28>
{
return HAL_ERROR;
8003194: 2301 movs r3, #1
8003196: e070 b.n 800327a <HAL_UART_Transmit+0x10a>
}
huart->ErrorCode = HAL_UART_ERROR_NONE;
8003198: 68fb ldr r3, [r7, #12]
800319a: 2200 movs r2, #0
800319c: f8c3 2084 str.w r2, [r3, #132] @ 0x84
huart->gState = HAL_UART_STATE_BUSY_TX;
80031a0: 68fb ldr r3, [r7, #12]
80031a2: 2221 movs r2, #33 @ 0x21
80031a4: 67da str r2, [r3, #124] @ 0x7c
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
80031a6: f7fe f98b bl 80014c0 <HAL_GetTick>
80031aa: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
80031ac: 68fb ldr r3, [r7, #12]
80031ae: 88fa ldrh r2, [r7, #6]
80031b0: f8a3 2050 strh.w r2, [r3, #80] @ 0x50
huart->TxXferCount = Size;
80031b4: 68fb ldr r3, [r7, #12]
80031b6: 88fa ldrh r2, [r7, #6]
80031b8: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
80031bc: 68fb ldr r3, [r7, #12]
80031be: 689b ldr r3, [r3, #8]
80031c0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80031c4: d108 bne.n 80031d8 <HAL_UART_Transmit+0x68>
80031c6: 68fb ldr r3, [r7, #12]
80031c8: 691b ldr r3, [r3, #16]
80031ca: 2b00 cmp r3, #0
80031cc: d104 bne.n 80031d8 <HAL_UART_Transmit+0x68>
{
pdata8bits = NULL;
80031ce: 2300 movs r3, #0
80031d0: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
80031d2: 68bb ldr r3, [r7, #8]
80031d4: 61bb str r3, [r7, #24]
80031d6: e003 b.n 80031e0 <HAL_UART_Transmit+0x70>
}
else
{
pdata8bits = pData;
80031d8: 68bb ldr r3, [r7, #8]
80031da: 61fb str r3, [r7, #28]
pdata16bits = NULL;
80031dc: 2300 movs r3, #0
80031de: 61bb str r3, [r7, #24]
}
while (huart->TxXferCount > 0U)
80031e0: e02f b.n 8003242 <HAL_UART_Transmit+0xd2>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
80031e2: 683b ldr r3, [r7, #0]
80031e4: 9300 str r3, [sp, #0]
80031e6: 697b ldr r3, [r7, #20]
80031e8: 2200 movs r2, #0
80031ea: 2180 movs r1, #128 @ 0x80
80031ec: 68f8 ldr r0, [r7, #12]
80031ee: f000 fba6 bl 800393e <UART_WaitOnFlagUntilTimeout>
80031f2: 4603 mov r3, r0
80031f4: 2b00 cmp r3, #0
80031f6: d004 beq.n 8003202 <HAL_UART_Transmit+0x92>
{
huart->gState = HAL_UART_STATE_READY;
80031f8: 68fb ldr r3, [r7, #12]
80031fa: 2220 movs r2, #32
80031fc: 67da str r2, [r3, #124] @ 0x7c
return HAL_TIMEOUT;
80031fe: 2303 movs r3, #3
8003200: e03b b.n 800327a <HAL_UART_Transmit+0x10a>
}
if (pdata8bits == NULL)
8003202: 69fb ldr r3, [r7, #28]
8003204: 2b00 cmp r3, #0
8003206: d10b bne.n 8003220 <HAL_UART_Transmit+0xb0>
{
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
8003208: 69bb ldr r3, [r7, #24]
800320a: 881b ldrh r3, [r3, #0]
800320c: 461a mov r2, r3
800320e: 68fb ldr r3, [r7, #12]
8003210: 681b ldr r3, [r3, #0]
8003212: f3c2 0208 ubfx r2, r2, #0, #9
8003216: 629a str r2, [r3, #40] @ 0x28
pdata16bits++;
8003218: 69bb ldr r3, [r7, #24]
800321a: 3302 adds r3, #2
800321c: 61bb str r3, [r7, #24]
800321e: e007 b.n 8003230 <HAL_UART_Transmit+0xc0>
}
else
{
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
8003220: 69fb ldr r3, [r7, #28]
8003222: 781a ldrb r2, [r3, #0]
8003224: 68fb ldr r3, [r7, #12]
8003226: 681b ldr r3, [r3, #0]
8003228: 629a str r2, [r3, #40] @ 0x28
pdata8bits++;
800322a: 69fb ldr r3, [r7, #28]
800322c: 3301 adds r3, #1
800322e: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
8003230: 68fb ldr r3, [r7, #12]
8003232: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
8003236: b29b uxth r3, r3
8003238: 3b01 subs r3, #1
800323a: b29a uxth r2, r3
800323c: 68fb ldr r3, [r7, #12]
800323e: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
while (huart->TxXferCount > 0U)
8003242: 68fb ldr r3, [r7, #12]
8003244: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
8003248: b29b uxth r3, r3
800324a: 2b00 cmp r3, #0
800324c: d1c9 bne.n 80031e2 <HAL_UART_Transmit+0x72>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
800324e: 683b ldr r3, [r7, #0]
8003250: 9300 str r3, [sp, #0]
8003252: 697b ldr r3, [r7, #20]
8003254: 2200 movs r2, #0
8003256: 2140 movs r1, #64 @ 0x40
8003258: 68f8 ldr r0, [r7, #12]
800325a: f000 fb70 bl 800393e <UART_WaitOnFlagUntilTimeout>
800325e: 4603 mov r3, r0
8003260: 2b00 cmp r3, #0
8003262: d004 beq.n 800326e <HAL_UART_Transmit+0xfe>
{
huart->gState = HAL_UART_STATE_READY;
8003264: 68fb ldr r3, [r7, #12]
8003266: 2220 movs r2, #32
8003268: 67da str r2, [r3, #124] @ 0x7c
return HAL_TIMEOUT;
800326a: 2303 movs r3, #3
800326c: e005 b.n 800327a <HAL_UART_Transmit+0x10a>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
800326e: 68fb ldr r3, [r7, #12]
8003270: 2220 movs r2, #32
8003272: 67da str r2, [r3, #124] @ 0x7c
return HAL_OK;
8003274: 2300 movs r3, #0
8003276: e000 b.n 800327a <HAL_UART_Transmit+0x10a>
}
else
{
return HAL_BUSY;
8003278: 2302 movs r3, #2
}
}
800327a: 4618 mov r0, r3
800327c: 3720 adds r7, #32
800327e: 46bd mov sp, r7
8003280: bd80 pop {r7, pc}
...
08003284 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8003284: b580 push {r7, lr}
8003286: b088 sub sp, #32
8003288: af00 add r7, sp, #0
800328a: 6078 str r0, [r7, #4]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
800328c: 2300 movs r3, #0
800328e: 77bb strb r3, [r7, #30]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8003290: 687b ldr r3, [r7, #4]
8003292: 689a ldr r2, [r3, #8]
8003294: 687b ldr r3, [r7, #4]
8003296: 691b ldr r3, [r3, #16]
8003298: 431a orrs r2, r3
800329a: 687b ldr r3, [r7, #4]
800329c: 695b ldr r3, [r3, #20]
800329e: 431a orrs r2, r3
80032a0: 687b ldr r3, [r7, #4]
80032a2: 69db ldr r3, [r3, #28]
80032a4: 4313 orrs r3, r2
80032a6: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
80032a8: 687b ldr r3, [r7, #4]
80032aa: 681b ldr r3, [r3, #0]
80032ac: 681a ldr r2, [r3, #0]
80032ae: 4ba6 ldr r3, [pc, #664] @ (8003548 <UART_SetConfig+0x2c4>)
80032b0: 4013 ands r3, r2
80032b2: 687a ldr r2, [r7, #4]
80032b4: 6812 ldr r2, [r2, #0]
80032b6: 6979 ldr r1, [r7, #20]
80032b8: 430b orrs r3, r1
80032ba: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
80032bc: 687b ldr r3, [r7, #4]
80032be: 681b ldr r3, [r3, #0]
80032c0: 685b ldr r3, [r3, #4]
80032c2: f423 5140 bic.w r1, r3, #12288 @ 0x3000
80032c6: 687b ldr r3, [r7, #4]
80032c8: 68da ldr r2, [r3, #12]
80032ca: 687b ldr r3, [r7, #4]
80032cc: 681b ldr r3, [r3, #0]
80032ce: 430a orrs r2, r1
80032d0: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
80032d2: 687b ldr r3, [r7, #4]
80032d4: 699b ldr r3, [r3, #24]
80032d6: 617b str r3, [r7, #20]
tmpreg |= huart->Init.OneBitSampling;
80032d8: 687b ldr r3, [r7, #4]
80032da: 6a1b ldr r3, [r3, #32]
80032dc: 697a ldr r2, [r7, #20]
80032de: 4313 orrs r3, r2
80032e0: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
80032e2: 687b ldr r3, [r7, #4]
80032e4: 681b ldr r3, [r3, #0]
80032e6: 689b ldr r3, [r3, #8]
80032e8: f423 6130 bic.w r1, r3, #2816 @ 0xb00
80032ec: 687b ldr r3, [r7, #4]
80032ee: 681b ldr r3, [r3, #0]
80032f0: 697a ldr r2, [r7, #20]
80032f2: 430a orrs r2, r1
80032f4: 609a str r2, [r3, #8]
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
80032f6: 687b ldr r3, [r7, #4]
80032f8: 681b ldr r3, [r3, #0]
80032fa: 4a94 ldr r2, [pc, #592] @ (800354c <UART_SetConfig+0x2c8>)
80032fc: 4293 cmp r3, r2
80032fe: d120 bne.n 8003342 <UART_SetConfig+0xbe>
8003300: 4b93 ldr r3, [pc, #588] @ (8003550 <UART_SetConfig+0x2cc>)
8003302: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003306: f003 0303 and.w r3, r3, #3
800330a: 2b03 cmp r3, #3
800330c: d816 bhi.n 800333c <UART_SetConfig+0xb8>
800330e: a201 add r2, pc, #4 @ (adr r2, 8003314 <UART_SetConfig+0x90>)
8003310: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003314: 08003325 .word 0x08003325
8003318: 08003331 .word 0x08003331
800331c: 0800332b .word 0x0800332b
8003320: 08003337 .word 0x08003337
8003324: 2301 movs r3, #1
8003326: 77fb strb r3, [r7, #31]
8003328: e150 b.n 80035cc <UART_SetConfig+0x348>
800332a: 2302 movs r3, #2
800332c: 77fb strb r3, [r7, #31]
800332e: e14d b.n 80035cc <UART_SetConfig+0x348>
8003330: 2304 movs r3, #4
8003332: 77fb strb r3, [r7, #31]
8003334: e14a b.n 80035cc <UART_SetConfig+0x348>
8003336: 2308 movs r3, #8
8003338: 77fb strb r3, [r7, #31]
800333a: e147 b.n 80035cc <UART_SetConfig+0x348>
800333c: 2310 movs r3, #16
800333e: 77fb strb r3, [r7, #31]
8003340: e144 b.n 80035cc <UART_SetConfig+0x348>
8003342: 687b ldr r3, [r7, #4]
8003344: 681b ldr r3, [r3, #0]
8003346: 4a83 ldr r2, [pc, #524] @ (8003554 <UART_SetConfig+0x2d0>)
8003348: 4293 cmp r3, r2
800334a: d132 bne.n 80033b2 <UART_SetConfig+0x12e>
800334c: 4b80 ldr r3, [pc, #512] @ (8003550 <UART_SetConfig+0x2cc>)
800334e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003352: f003 030c and.w r3, r3, #12
8003356: 2b0c cmp r3, #12
8003358: d828 bhi.n 80033ac <UART_SetConfig+0x128>
800335a: a201 add r2, pc, #4 @ (adr r2, 8003360 <UART_SetConfig+0xdc>)
800335c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003360: 08003395 .word 0x08003395
8003364: 080033ad .word 0x080033ad
8003368: 080033ad .word 0x080033ad
800336c: 080033ad .word 0x080033ad
8003370: 080033a1 .word 0x080033a1
8003374: 080033ad .word 0x080033ad
8003378: 080033ad .word 0x080033ad
800337c: 080033ad .word 0x080033ad
8003380: 0800339b .word 0x0800339b
8003384: 080033ad .word 0x080033ad
8003388: 080033ad .word 0x080033ad
800338c: 080033ad .word 0x080033ad
8003390: 080033a7 .word 0x080033a7
8003394: 2300 movs r3, #0
8003396: 77fb strb r3, [r7, #31]
8003398: e118 b.n 80035cc <UART_SetConfig+0x348>
800339a: 2302 movs r3, #2
800339c: 77fb strb r3, [r7, #31]
800339e: e115 b.n 80035cc <UART_SetConfig+0x348>
80033a0: 2304 movs r3, #4
80033a2: 77fb strb r3, [r7, #31]
80033a4: e112 b.n 80035cc <UART_SetConfig+0x348>
80033a6: 2308 movs r3, #8
80033a8: 77fb strb r3, [r7, #31]
80033aa: e10f b.n 80035cc <UART_SetConfig+0x348>
80033ac: 2310 movs r3, #16
80033ae: 77fb strb r3, [r7, #31]
80033b0: e10c b.n 80035cc <UART_SetConfig+0x348>
80033b2: 687b ldr r3, [r7, #4]
80033b4: 681b ldr r3, [r3, #0]
80033b6: 4a68 ldr r2, [pc, #416] @ (8003558 <UART_SetConfig+0x2d4>)
80033b8: 4293 cmp r3, r2
80033ba: d120 bne.n 80033fe <UART_SetConfig+0x17a>
80033bc: 4b64 ldr r3, [pc, #400] @ (8003550 <UART_SetConfig+0x2cc>)
80033be: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80033c2: f003 0330 and.w r3, r3, #48 @ 0x30
80033c6: 2b30 cmp r3, #48 @ 0x30
80033c8: d013 beq.n 80033f2 <UART_SetConfig+0x16e>
80033ca: 2b30 cmp r3, #48 @ 0x30
80033cc: d814 bhi.n 80033f8 <UART_SetConfig+0x174>
80033ce: 2b20 cmp r3, #32
80033d0: d009 beq.n 80033e6 <UART_SetConfig+0x162>
80033d2: 2b20 cmp r3, #32
80033d4: d810 bhi.n 80033f8 <UART_SetConfig+0x174>
80033d6: 2b00 cmp r3, #0
80033d8: d002 beq.n 80033e0 <UART_SetConfig+0x15c>
80033da: 2b10 cmp r3, #16
80033dc: d006 beq.n 80033ec <UART_SetConfig+0x168>
80033de: e00b b.n 80033f8 <UART_SetConfig+0x174>
80033e0: 2300 movs r3, #0
80033e2: 77fb strb r3, [r7, #31]
80033e4: e0f2 b.n 80035cc <UART_SetConfig+0x348>
80033e6: 2302 movs r3, #2
80033e8: 77fb strb r3, [r7, #31]
80033ea: e0ef b.n 80035cc <UART_SetConfig+0x348>
80033ec: 2304 movs r3, #4
80033ee: 77fb strb r3, [r7, #31]
80033f0: e0ec b.n 80035cc <UART_SetConfig+0x348>
80033f2: 2308 movs r3, #8
80033f4: 77fb strb r3, [r7, #31]
80033f6: e0e9 b.n 80035cc <UART_SetConfig+0x348>
80033f8: 2310 movs r3, #16
80033fa: 77fb strb r3, [r7, #31]
80033fc: e0e6 b.n 80035cc <UART_SetConfig+0x348>
80033fe: 687b ldr r3, [r7, #4]
8003400: 681b ldr r3, [r3, #0]
8003402: 4a56 ldr r2, [pc, #344] @ (800355c <UART_SetConfig+0x2d8>)
8003404: 4293 cmp r3, r2
8003406: d120 bne.n 800344a <UART_SetConfig+0x1c6>
8003408: 4b51 ldr r3, [pc, #324] @ (8003550 <UART_SetConfig+0x2cc>)
800340a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800340e: f003 03c0 and.w r3, r3, #192 @ 0xc0
8003412: 2bc0 cmp r3, #192 @ 0xc0
8003414: d013 beq.n 800343e <UART_SetConfig+0x1ba>
8003416: 2bc0 cmp r3, #192 @ 0xc0
8003418: d814 bhi.n 8003444 <UART_SetConfig+0x1c0>
800341a: 2b80 cmp r3, #128 @ 0x80
800341c: d009 beq.n 8003432 <UART_SetConfig+0x1ae>
800341e: 2b80 cmp r3, #128 @ 0x80
8003420: d810 bhi.n 8003444 <UART_SetConfig+0x1c0>
8003422: 2b00 cmp r3, #0
8003424: d002 beq.n 800342c <UART_SetConfig+0x1a8>
8003426: 2b40 cmp r3, #64 @ 0x40
8003428: d006 beq.n 8003438 <UART_SetConfig+0x1b4>
800342a: e00b b.n 8003444 <UART_SetConfig+0x1c0>
800342c: 2300 movs r3, #0
800342e: 77fb strb r3, [r7, #31]
8003430: e0cc b.n 80035cc <UART_SetConfig+0x348>
8003432: 2302 movs r3, #2
8003434: 77fb strb r3, [r7, #31]
8003436: e0c9 b.n 80035cc <UART_SetConfig+0x348>
8003438: 2304 movs r3, #4
800343a: 77fb strb r3, [r7, #31]
800343c: e0c6 b.n 80035cc <UART_SetConfig+0x348>
800343e: 2308 movs r3, #8
8003440: 77fb strb r3, [r7, #31]
8003442: e0c3 b.n 80035cc <UART_SetConfig+0x348>
8003444: 2310 movs r3, #16
8003446: 77fb strb r3, [r7, #31]
8003448: e0c0 b.n 80035cc <UART_SetConfig+0x348>
800344a: 687b ldr r3, [r7, #4]
800344c: 681b ldr r3, [r3, #0]
800344e: 4a44 ldr r2, [pc, #272] @ (8003560 <UART_SetConfig+0x2dc>)
8003450: 4293 cmp r3, r2
8003452: d125 bne.n 80034a0 <UART_SetConfig+0x21c>
8003454: 4b3e ldr r3, [pc, #248] @ (8003550 <UART_SetConfig+0x2cc>)
8003456: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800345a: f403 7340 and.w r3, r3, #768 @ 0x300
800345e: f5b3 7f40 cmp.w r3, #768 @ 0x300
8003462: d017 beq.n 8003494 <UART_SetConfig+0x210>
8003464: f5b3 7f40 cmp.w r3, #768 @ 0x300
8003468: d817 bhi.n 800349a <UART_SetConfig+0x216>
800346a: f5b3 7f00 cmp.w r3, #512 @ 0x200
800346e: d00b beq.n 8003488 <UART_SetConfig+0x204>
8003470: f5b3 7f00 cmp.w r3, #512 @ 0x200
8003474: d811 bhi.n 800349a <UART_SetConfig+0x216>
8003476: 2b00 cmp r3, #0
8003478: d003 beq.n 8003482 <UART_SetConfig+0x1fe>
800347a: f5b3 7f80 cmp.w r3, #256 @ 0x100
800347e: d006 beq.n 800348e <UART_SetConfig+0x20a>
8003480: e00b b.n 800349a <UART_SetConfig+0x216>
8003482: 2300 movs r3, #0
8003484: 77fb strb r3, [r7, #31]
8003486: e0a1 b.n 80035cc <UART_SetConfig+0x348>
8003488: 2302 movs r3, #2
800348a: 77fb strb r3, [r7, #31]
800348c: e09e b.n 80035cc <UART_SetConfig+0x348>
800348e: 2304 movs r3, #4
8003490: 77fb strb r3, [r7, #31]
8003492: e09b b.n 80035cc <UART_SetConfig+0x348>
8003494: 2308 movs r3, #8
8003496: 77fb strb r3, [r7, #31]
8003498: e098 b.n 80035cc <UART_SetConfig+0x348>
800349a: 2310 movs r3, #16
800349c: 77fb strb r3, [r7, #31]
800349e: e095 b.n 80035cc <UART_SetConfig+0x348>
80034a0: 687b ldr r3, [r7, #4]
80034a2: 681b ldr r3, [r3, #0]
80034a4: 4a2f ldr r2, [pc, #188] @ (8003564 <UART_SetConfig+0x2e0>)
80034a6: 4293 cmp r3, r2
80034a8: d125 bne.n 80034f6 <UART_SetConfig+0x272>
80034aa: 4b29 ldr r3, [pc, #164] @ (8003550 <UART_SetConfig+0x2cc>)
80034ac: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80034b0: f403 6340 and.w r3, r3, #3072 @ 0xc00
80034b4: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
80034b8: d017 beq.n 80034ea <UART_SetConfig+0x266>
80034ba: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
80034be: d817 bhi.n 80034f0 <UART_SetConfig+0x26c>
80034c0: f5b3 6f00 cmp.w r3, #2048 @ 0x800
80034c4: d00b beq.n 80034de <UART_SetConfig+0x25a>
80034c6: f5b3 6f00 cmp.w r3, #2048 @ 0x800
80034ca: d811 bhi.n 80034f0 <UART_SetConfig+0x26c>
80034cc: 2b00 cmp r3, #0
80034ce: d003 beq.n 80034d8 <UART_SetConfig+0x254>
80034d0: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80034d4: d006 beq.n 80034e4 <UART_SetConfig+0x260>
80034d6: e00b b.n 80034f0 <UART_SetConfig+0x26c>
80034d8: 2301 movs r3, #1
80034da: 77fb strb r3, [r7, #31]
80034dc: e076 b.n 80035cc <UART_SetConfig+0x348>
80034de: 2302 movs r3, #2
80034e0: 77fb strb r3, [r7, #31]
80034e2: e073 b.n 80035cc <UART_SetConfig+0x348>
80034e4: 2304 movs r3, #4
80034e6: 77fb strb r3, [r7, #31]
80034e8: e070 b.n 80035cc <UART_SetConfig+0x348>
80034ea: 2308 movs r3, #8
80034ec: 77fb strb r3, [r7, #31]
80034ee: e06d b.n 80035cc <UART_SetConfig+0x348>
80034f0: 2310 movs r3, #16
80034f2: 77fb strb r3, [r7, #31]
80034f4: e06a b.n 80035cc <UART_SetConfig+0x348>
80034f6: 687b ldr r3, [r7, #4]
80034f8: 681b ldr r3, [r3, #0]
80034fa: 4a1b ldr r2, [pc, #108] @ (8003568 <UART_SetConfig+0x2e4>)
80034fc: 4293 cmp r3, r2
80034fe: d138 bne.n 8003572 <UART_SetConfig+0x2ee>
8003500: 4b13 ldr r3, [pc, #76] @ (8003550 <UART_SetConfig+0x2cc>)
8003502: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003506: f403 5340 and.w r3, r3, #12288 @ 0x3000
800350a: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
800350e: d017 beq.n 8003540 <UART_SetConfig+0x2bc>
8003510: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
8003514: d82a bhi.n 800356c <UART_SetConfig+0x2e8>
8003516: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
800351a: d00b beq.n 8003534 <UART_SetConfig+0x2b0>
800351c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8003520: d824 bhi.n 800356c <UART_SetConfig+0x2e8>
8003522: 2b00 cmp r3, #0
8003524: d003 beq.n 800352e <UART_SetConfig+0x2aa>
8003526: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800352a: d006 beq.n 800353a <UART_SetConfig+0x2b6>
800352c: e01e b.n 800356c <UART_SetConfig+0x2e8>
800352e: 2300 movs r3, #0
8003530: 77fb strb r3, [r7, #31]
8003532: e04b b.n 80035cc <UART_SetConfig+0x348>
8003534: 2302 movs r3, #2
8003536: 77fb strb r3, [r7, #31]
8003538: e048 b.n 80035cc <UART_SetConfig+0x348>
800353a: 2304 movs r3, #4
800353c: 77fb strb r3, [r7, #31]
800353e: e045 b.n 80035cc <UART_SetConfig+0x348>
8003540: 2308 movs r3, #8
8003542: 77fb strb r3, [r7, #31]
8003544: e042 b.n 80035cc <UART_SetConfig+0x348>
8003546: bf00 nop
8003548: efff69f3 .word 0xefff69f3
800354c: 40011000 .word 0x40011000
8003550: 40023800 .word 0x40023800
8003554: 40004400 .word 0x40004400
8003558: 40004800 .word 0x40004800
800355c: 40004c00 .word 0x40004c00
8003560: 40005000 .word 0x40005000
8003564: 40011400 .word 0x40011400
8003568: 40007800 .word 0x40007800
800356c: 2310 movs r3, #16
800356e: 77fb strb r3, [r7, #31]
8003570: e02c b.n 80035cc <UART_SetConfig+0x348>
8003572: 687b ldr r3, [r7, #4]
8003574: 681b ldr r3, [r3, #0]
8003576: 4a72 ldr r2, [pc, #456] @ (8003740 <UART_SetConfig+0x4bc>)
8003578: 4293 cmp r3, r2
800357a: d125 bne.n 80035c8 <UART_SetConfig+0x344>
800357c: 4b71 ldr r3, [pc, #452] @ (8003744 <UART_SetConfig+0x4c0>)
800357e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003582: f403 4340 and.w r3, r3, #49152 @ 0xc000
8003586: f5b3 4f40 cmp.w r3, #49152 @ 0xc000
800358a: d017 beq.n 80035bc <UART_SetConfig+0x338>
800358c: f5b3 4f40 cmp.w r3, #49152 @ 0xc000
8003590: d817 bhi.n 80035c2 <UART_SetConfig+0x33e>
8003592: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8003596: d00b beq.n 80035b0 <UART_SetConfig+0x32c>
8003598: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
800359c: d811 bhi.n 80035c2 <UART_SetConfig+0x33e>
800359e: 2b00 cmp r3, #0
80035a0: d003 beq.n 80035aa <UART_SetConfig+0x326>
80035a2: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
80035a6: d006 beq.n 80035b6 <UART_SetConfig+0x332>
80035a8: e00b b.n 80035c2 <UART_SetConfig+0x33e>
80035aa: 2300 movs r3, #0
80035ac: 77fb strb r3, [r7, #31]
80035ae: e00d b.n 80035cc <UART_SetConfig+0x348>
80035b0: 2302 movs r3, #2
80035b2: 77fb strb r3, [r7, #31]
80035b4: e00a b.n 80035cc <UART_SetConfig+0x348>
80035b6: 2304 movs r3, #4
80035b8: 77fb strb r3, [r7, #31]
80035ba: e007 b.n 80035cc <UART_SetConfig+0x348>
80035bc: 2308 movs r3, #8
80035be: 77fb strb r3, [r7, #31]
80035c0: e004 b.n 80035cc <UART_SetConfig+0x348>
80035c2: 2310 movs r3, #16
80035c4: 77fb strb r3, [r7, #31]
80035c6: e001 b.n 80035cc <UART_SetConfig+0x348>
80035c8: 2310 movs r3, #16
80035ca: 77fb strb r3, [r7, #31]
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
80035cc: 687b ldr r3, [r7, #4]
80035ce: 69db ldr r3, [r3, #28]
80035d0: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
80035d4: d15b bne.n 800368e <UART_SetConfig+0x40a>
{
switch (clocksource)
80035d6: 7ffb ldrb r3, [r7, #31]
80035d8: 2b08 cmp r3, #8
80035da: d828 bhi.n 800362e <UART_SetConfig+0x3aa>
80035dc: a201 add r2, pc, #4 @ (adr r2, 80035e4 <UART_SetConfig+0x360>)
80035de: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80035e2: bf00 nop
80035e4: 08003609 .word 0x08003609
80035e8: 08003611 .word 0x08003611
80035ec: 08003619 .word 0x08003619
80035f0: 0800362f .word 0x0800362f
80035f4: 0800361f .word 0x0800361f
80035f8: 0800362f .word 0x0800362f
80035fc: 0800362f .word 0x0800362f
8003600: 0800362f .word 0x0800362f
8003604: 08003627 .word 0x08003627
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8003608: f7fe fef2 bl 80023f0 <HAL_RCC_GetPCLK1Freq>
800360c: 61b8 str r0, [r7, #24]
break;
800360e: e013 b.n 8003638 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8003610: f7fe ff02 bl 8002418 <HAL_RCC_GetPCLK2Freq>
8003614: 61b8 str r0, [r7, #24]
break;
8003616: e00f b.n 8003638 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8003618: 4b4b ldr r3, [pc, #300] @ (8003748 <UART_SetConfig+0x4c4>)
800361a: 61bb str r3, [r7, #24]
break;
800361c: e00c b.n 8003638 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
800361e: f7fe fe15 bl 800224c <HAL_RCC_GetSysClockFreq>
8003622: 61b8 str r0, [r7, #24]
break;
8003624: e008 b.n 8003638 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8003626: f44f 4300 mov.w r3, #32768 @ 0x8000
800362a: 61bb str r3, [r7, #24]
break;
800362c: e004 b.n 8003638 <UART_SetConfig+0x3b4>
default:
pclk = 0U;
800362e: 2300 movs r3, #0
8003630: 61bb str r3, [r7, #24]
ret = HAL_ERROR;
8003632: 2301 movs r3, #1
8003634: 77bb strb r3, [r7, #30]
break;
8003636: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
8003638: 69bb ldr r3, [r7, #24]
800363a: 2b00 cmp r3, #0
800363c: d074 beq.n 8003728 <UART_SetConfig+0x4a4>
{
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
800363e: 69bb ldr r3, [r7, #24]
8003640: 005a lsls r2, r3, #1
8003642: 687b ldr r3, [r7, #4]
8003644: 685b ldr r3, [r3, #4]
8003646: 085b lsrs r3, r3, #1
8003648: 441a add r2, r3
800364a: 687b ldr r3, [r7, #4]
800364c: 685b ldr r3, [r3, #4]
800364e: fbb2 f3f3 udiv r3, r2, r3
8003652: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8003654: 693b ldr r3, [r7, #16]
8003656: 2b0f cmp r3, #15
8003658: d916 bls.n 8003688 <UART_SetConfig+0x404>
800365a: 693b ldr r3, [r7, #16]
800365c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8003660: d212 bcs.n 8003688 <UART_SetConfig+0x404>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
8003662: 693b ldr r3, [r7, #16]
8003664: b29b uxth r3, r3
8003666: f023 030f bic.w r3, r3, #15
800366a: 81fb strh r3, [r7, #14]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
800366c: 693b ldr r3, [r7, #16]
800366e: 085b lsrs r3, r3, #1
8003670: b29b uxth r3, r3
8003672: f003 0307 and.w r3, r3, #7
8003676: b29a uxth r2, r3
8003678: 89fb ldrh r3, [r7, #14]
800367a: 4313 orrs r3, r2
800367c: 81fb strh r3, [r7, #14]
huart->Instance->BRR = brrtemp;
800367e: 687b ldr r3, [r7, #4]
8003680: 681b ldr r3, [r3, #0]
8003682: 89fa ldrh r2, [r7, #14]
8003684: 60da str r2, [r3, #12]
8003686: e04f b.n 8003728 <UART_SetConfig+0x4a4>
}
else
{
ret = HAL_ERROR;
8003688: 2301 movs r3, #1
800368a: 77bb strb r3, [r7, #30]
800368c: e04c b.n 8003728 <UART_SetConfig+0x4a4>
}
}
}
else
{
switch (clocksource)
800368e: 7ffb ldrb r3, [r7, #31]
8003690: 2b08 cmp r3, #8
8003692: d828 bhi.n 80036e6 <UART_SetConfig+0x462>
8003694: a201 add r2, pc, #4 @ (adr r2, 800369c <UART_SetConfig+0x418>)
8003696: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800369a: bf00 nop
800369c: 080036c1 .word 0x080036c1
80036a0: 080036c9 .word 0x080036c9
80036a4: 080036d1 .word 0x080036d1
80036a8: 080036e7 .word 0x080036e7
80036ac: 080036d7 .word 0x080036d7
80036b0: 080036e7 .word 0x080036e7
80036b4: 080036e7 .word 0x080036e7
80036b8: 080036e7 .word 0x080036e7
80036bc: 080036df .word 0x080036df
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
80036c0: f7fe fe96 bl 80023f0 <HAL_RCC_GetPCLK1Freq>
80036c4: 61b8 str r0, [r7, #24]
break;
80036c6: e013 b.n 80036f0 <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
80036c8: f7fe fea6 bl 8002418 <HAL_RCC_GetPCLK2Freq>
80036cc: 61b8 str r0, [r7, #24]
break;
80036ce: e00f b.n 80036f0 <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
80036d0: 4b1d ldr r3, [pc, #116] @ (8003748 <UART_SetConfig+0x4c4>)
80036d2: 61bb str r3, [r7, #24]
break;
80036d4: e00c b.n 80036f0 <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80036d6: f7fe fdb9 bl 800224c <HAL_RCC_GetSysClockFreq>
80036da: 61b8 str r0, [r7, #24]
break;
80036dc: e008 b.n 80036f0 <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
80036de: f44f 4300 mov.w r3, #32768 @ 0x8000
80036e2: 61bb str r3, [r7, #24]
break;
80036e4: e004 b.n 80036f0 <UART_SetConfig+0x46c>
default:
pclk = 0U;
80036e6: 2300 movs r3, #0
80036e8: 61bb str r3, [r7, #24]
ret = HAL_ERROR;
80036ea: 2301 movs r3, #1
80036ec: 77bb strb r3, [r7, #30]
break;
80036ee: bf00 nop
}
if (pclk != 0U)
80036f0: 69bb ldr r3, [r7, #24]
80036f2: 2b00 cmp r3, #0
80036f4: d018 beq.n 8003728 <UART_SetConfig+0x4a4>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
80036f6: 687b ldr r3, [r7, #4]
80036f8: 685b ldr r3, [r3, #4]
80036fa: 085a lsrs r2, r3, #1
80036fc: 69bb ldr r3, [r7, #24]
80036fe: 441a add r2, r3
8003700: 687b ldr r3, [r7, #4]
8003702: 685b ldr r3, [r3, #4]
8003704: fbb2 f3f3 udiv r3, r2, r3
8003708: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
800370a: 693b ldr r3, [r7, #16]
800370c: 2b0f cmp r3, #15
800370e: d909 bls.n 8003724 <UART_SetConfig+0x4a0>
8003710: 693b ldr r3, [r7, #16]
8003712: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8003716: d205 bcs.n 8003724 <UART_SetConfig+0x4a0>
{
huart->Instance->BRR = (uint16_t)usartdiv;
8003718: 693b ldr r3, [r7, #16]
800371a: b29a uxth r2, r3
800371c: 687b ldr r3, [r7, #4]
800371e: 681b ldr r3, [r3, #0]
8003720: 60da str r2, [r3, #12]
8003722: e001 b.n 8003728 <UART_SetConfig+0x4a4>
}
else
{
ret = HAL_ERROR;
8003724: 2301 movs r3, #1
8003726: 77bb strb r3, [r7, #30]
}
}
/* Clear ISR function pointers */
huart->RxISR = NULL;
8003728: 687b ldr r3, [r7, #4]
800372a: 2200 movs r2, #0
800372c: 669a str r2, [r3, #104] @ 0x68
huart->TxISR = NULL;
800372e: 687b ldr r3, [r7, #4]
8003730: 2200 movs r2, #0
8003732: 66da str r2, [r3, #108] @ 0x6c
return ret;
8003734: 7fbb ldrb r3, [r7, #30]
}
8003736: 4618 mov r0, r3
8003738: 3720 adds r7, #32
800373a: 46bd mov sp, r7
800373c: bd80 pop {r7, pc}
800373e: bf00 nop
8003740: 40007c00 .word 0x40007c00
8003744: 40023800 .word 0x40023800
8003748: 00f42400 .word 0x00f42400
0800374c <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
800374c: b480 push {r7}
800374e: b083 sub sp, #12
8003750: af00 add r7, sp, #0
8003752: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
8003754: 687b ldr r3, [r7, #4]
8003756: 6a5b ldr r3, [r3, #36] @ 0x24
8003758: f003 0308 and.w r3, r3, #8
800375c: 2b00 cmp r3, #0
800375e: d00a beq.n 8003776 <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
8003760: 687b ldr r3, [r7, #4]
8003762: 681b ldr r3, [r3, #0]
8003764: 685b ldr r3, [r3, #4]
8003766: f423 4100 bic.w r1, r3, #32768 @ 0x8000
800376a: 687b ldr r3, [r7, #4]
800376c: 6b5a ldr r2, [r3, #52] @ 0x34
800376e: 687b ldr r3, [r7, #4]
8003770: 681b ldr r3, [r3, #0]
8003772: 430a orrs r2, r1
8003774: 605a str r2, [r3, #4]
}
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
8003776: 687b ldr r3, [r7, #4]
8003778: 6a5b ldr r3, [r3, #36] @ 0x24
800377a: f003 0301 and.w r3, r3, #1
800377e: 2b00 cmp r3, #0
8003780: d00a beq.n 8003798 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
8003782: 687b ldr r3, [r7, #4]
8003784: 681b ldr r3, [r3, #0]
8003786: 685b ldr r3, [r3, #4]
8003788: f423 3100 bic.w r1, r3, #131072 @ 0x20000
800378c: 687b ldr r3, [r7, #4]
800378e: 6a9a ldr r2, [r3, #40] @ 0x28
8003790: 687b ldr r3, [r7, #4]
8003792: 681b ldr r3, [r3, #0]
8003794: 430a orrs r2, r1
8003796: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
8003798: 687b ldr r3, [r7, #4]
800379a: 6a5b ldr r3, [r3, #36] @ 0x24
800379c: f003 0302 and.w r3, r3, #2
80037a0: 2b00 cmp r3, #0
80037a2: d00a beq.n 80037ba <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
80037a4: 687b ldr r3, [r7, #4]
80037a6: 681b ldr r3, [r3, #0]
80037a8: 685b ldr r3, [r3, #4]
80037aa: f423 3180 bic.w r1, r3, #65536 @ 0x10000
80037ae: 687b ldr r3, [r7, #4]
80037b0: 6ada ldr r2, [r3, #44] @ 0x2c
80037b2: 687b ldr r3, [r7, #4]
80037b4: 681b ldr r3, [r3, #0]
80037b6: 430a orrs r2, r1
80037b8: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
80037ba: 687b ldr r3, [r7, #4]
80037bc: 6a5b ldr r3, [r3, #36] @ 0x24
80037be: f003 0304 and.w r3, r3, #4
80037c2: 2b00 cmp r3, #0
80037c4: d00a beq.n 80037dc <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
80037c6: 687b ldr r3, [r7, #4]
80037c8: 681b ldr r3, [r3, #0]
80037ca: 685b ldr r3, [r3, #4]
80037cc: f423 2180 bic.w r1, r3, #262144 @ 0x40000
80037d0: 687b ldr r3, [r7, #4]
80037d2: 6b1a ldr r2, [r3, #48] @ 0x30
80037d4: 687b ldr r3, [r7, #4]
80037d6: 681b ldr r3, [r3, #0]
80037d8: 430a orrs r2, r1
80037da: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
80037dc: 687b ldr r3, [r7, #4]
80037de: 6a5b ldr r3, [r3, #36] @ 0x24
80037e0: f003 0310 and.w r3, r3, #16
80037e4: 2b00 cmp r3, #0
80037e6: d00a beq.n 80037fe <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
80037e8: 687b ldr r3, [r7, #4]
80037ea: 681b ldr r3, [r3, #0]
80037ec: 689b ldr r3, [r3, #8]
80037ee: f423 5180 bic.w r1, r3, #4096 @ 0x1000
80037f2: 687b ldr r3, [r7, #4]
80037f4: 6b9a ldr r2, [r3, #56] @ 0x38
80037f6: 687b ldr r3, [r7, #4]
80037f8: 681b ldr r3, [r3, #0]
80037fa: 430a orrs r2, r1
80037fc: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
80037fe: 687b ldr r3, [r7, #4]
8003800: 6a5b ldr r3, [r3, #36] @ 0x24
8003802: f003 0320 and.w r3, r3, #32
8003806: 2b00 cmp r3, #0
8003808: d00a beq.n 8003820 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
800380a: 687b ldr r3, [r7, #4]
800380c: 681b ldr r3, [r3, #0]
800380e: 689b ldr r3, [r3, #8]
8003810: f423 5100 bic.w r1, r3, #8192 @ 0x2000
8003814: 687b ldr r3, [r7, #4]
8003816: 6bda ldr r2, [r3, #60] @ 0x3c
8003818: 687b ldr r3, [r7, #4]
800381a: 681b ldr r3, [r3, #0]
800381c: 430a orrs r2, r1
800381e: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
8003820: 687b ldr r3, [r7, #4]
8003822: 6a5b ldr r3, [r3, #36] @ 0x24
8003824: f003 0340 and.w r3, r3, #64 @ 0x40
8003828: 2b00 cmp r3, #0
800382a: d01a beq.n 8003862 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
800382c: 687b ldr r3, [r7, #4]
800382e: 681b ldr r3, [r3, #0]
8003830: 685b ldr r3, [r3, #4]
8003832: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
8003836: 687b ldr r3, [r7, #4]
8003838: 6c1a ldr r2, [r3, #64] @ 0x40
800383a: 687b ldr r3, [r7, #4]
800383c: 681b ldr r3, [r3, #0]
800383e: 430a orrs r2, r1
8003840: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
8003842: 687b ldr r3, [r7, #4]
8003844: 6c1b ldr r3, [r3, #64] @ 0x40
8003846: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
800384a: d10a bne.n 8003862 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
800384c: 687b ldr r3, [r7, #4]
800384e: 681b ldr r3, [r3, #0]
8003850: 685b ldr r3, [r3, #4]
8003852: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
8003856: 687b ldr r3, [r7, #4]
8003858: 6c5a ldr r2, [r3, #68] @ 0x44
800385a: 687b ldr r3, [r7, #4]
800385c: 681b ldr r3, [r3, #0]
800385e: 430a orrs r2, r1
8003860: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
8003862: 687b ldr r3, [r7, #4]
8003864: 6a5b ldr r3, [r3, #36] @ 0x24
8003866: f003 0380 and.w r3, r3, #128 @ 0x80
800386a: 2b00 cmp r3, #0
800386c: d00a beq.n 8003884 <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
800386e: 687b ldr r3, [r7, #4]
8003870: 681b ldr r3, [r3, #0]
8003872: 685b ldr r3, [r3, #4]
8003874: f423 2100 bic.w r1, r3, #524288 @ 0x80000
8003878: 687b ldr r3, [r7, #4]
800387a: 6c9a ldr r2, [r3, #72] @ 0x48
800387c: 687b ldr r3, [r7, #4]
800387e: 681b ldr r3, [r3, #0]
8003880: 430a orrs r2, r1
8003882: 605a str r2, [r3, #4]
}
}
8003884: bf00 nop
8003886: 370c adds r7, #12
8003888: 46bd mov sp, r7
800388a: f85d 7b04 ldr.w r7, [sp], #4
800388e: 4770 bx lr
08003890 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
8003890: b580 push {r7, lr}
8003892: b08c sub sp, #48 @ 0x30
8003894: af02 add r7, sp, #8
8003896: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8003898: 687b ldr r3, [r7, #4]
800389a: 2200 movs r2, #0
800389c: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
80038a0: f7fd fe0e bl 80014c0 <HAL_GetTick>
80038a4: 6278 str r0, [r7, #36] @ 0x24
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
80038a6: 687b ldr r3, [r7, #4]
80038a8: 681b ldr r3, [r3, #0]
80038aa: 681b ldr r3, [r3, #0]
80038ac: f003 0308 and.w r3, r3, #8
80038b0: 2b08 cmp r3, #8
80038b2: d12e bne.n 8003912 <UART_CheckIdleState+0x82>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
80038b4: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
80038b8: 9300 str r3, [sp, #0]
80038ba: 6a7b ldr r3, [r7, #36] @ 0x24
80038bc: 2200 movs r2, #0
80038be: f44f 1100 mov.w r1, #2097152 @ 0x200000
80038c2: 6878 ldr r0, [r7, #4]
80038c4: f000 f83b bl 800393e <UART_WaitOnFlagUntilTimeout>
80038c8: 4603 mov r3, r0
80038ca: 2b00 cmp r3, #0
80038cc: d021 beq.n 8003912 <UART_CheckIdleState+0x82>
{
/* Disable TXE interrupt for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
80038ce: 687b ldr r3, [r7, #4]
80038d0: 681b ldr r3, [r3, #0]
80038d2: 613b str r3, [r7, #16]
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80038d4: 693b ldr r3, [r7, #16]
80038d6: e853 3f00 ldrex r3, [r3]
80038da: 60fb str r3, [r7, #12]
return(result);
80038dc: 68fb ldr r3, [r7, #12]
80038de: f023 0380 bic.w r3, r3, #128 @ 0x80
80038e2: 623b str r3, [r7, #32]
80038e4: 687b ldr r3, [r7, #4]
80038e6: 681b ldr r3, [r3, #0]
80038e8: 461a mov r2, r3
80038ea: 6a3b ldr r3, [r7, #32]
80038ec: 61fb str r3, [r7, #28]
80038ee: 61ba str r2, [r7, #24]
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80038f0: 69b9 ldr r1, [r7, #24]
80038f2: 69fa ldr r2, [r7, #28]
80038f4: e841 2300 strex r3, r2, [r1]
80038f8: 617b str r3, [r7, #20]
return(result);
80038fa: 697b ldr r3, [r7, #20]
80038fc: 2b00 cmp r3, #0
80038fe: d1e6 bne.n 80038ce <UART_CheckIdleState+0x3e>
huart->gState = HAL_UART_STATE_READY;
8003900: 687b ldr r3, [r7, #4]
8003902: 2220 movs r2, #32
8003904: 67da str r2, [r3, #124] @ 0x7c
__HAL_UNLOCK(huart);
8003906: 687b ldr r3, [r7, #4]
8003908: 2200 movs r2, #0
800390a: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Timeout occurred */
return HAL_TIMEOUT;
800390e: 2303 movs r3, #3
8003910: e011 b.n 8003936 <UART_CheckIdleState+0xa6>
}
}
#endif /* USART_ISR_REACK */
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
8003912: 687b ldr r3, [r7, #4]
8003914: 2220 movs r2, #32
8003916: 67da str r2, [r3, #124] @ 0x7c
huart->RxState = HAL_UART_STATE_READY;
8003918: 687b ldr r3, [r7, #4]
800391a: 2220 movs r2, #32
800391c: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8003920: 687b ldr r3, [r7, #4]
8003922: 2200 movs r2, #0
8003924: 661a str r2, [r3, #96] @ 0x60
huart->RxEventType = HAL_UART_RXEVENT_TC;
8003926: 687b ldr r3, [r7, #4]
8003928: 2200 movs r2, #0
800392a: 665a str r2, [r3, #100] @ 0x64
__HAL_UNLOCK(huart);
800392c: 687b ldr r3, [r7, #4]
800392e: 2200 movs r2, #0
8003930: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_OK;
8003934: 2300 movs r3, #0
}
8003936: 4618 mov r0, r3
8003938: 3728 adds r7, #40 @ 0x28
800393a: 46bd mov sp, r7
800393c: bd80 pop {r7, pc}
0800393e <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
800393e: b580 push {r7, lr}
8003940: b084 sub sp, #16
8003942: af00 add r7, sp, #0
8003944: 60f8 str r0, [r7, #12]
8003946: 60b9 str r1, [r7, #8]
8003948: 603b str r3, [r7, #0]
800394a: 4613 mov r3, r2
800394c: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
800394e: e04f b.n 80039f0 <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8003950: 69bb ldr r3, [r7, #24]
8003952: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8003956: d04b beq.n 80039f0 <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8003958: f7fd fdb2 bl 80014c0 <HAL_GetTick>
800395c: 4602 mov r2, r0
800395e: 683b ldr r3, [r7, #0]
8003960: 1ad3 subs r3, r2, r3
8003962: 69ba ldr r2, [r7, #24]
8003964: 429a cmp r2, r3
8003966: d302 bcc.n 800396e <UART_WaitOnFlagUntilTimeout+0x30>
8003968: 69bb ldr r3, [r7, #24]
800396a: 2b00 cmp r3, #0
800396c: d101 bne.n 8003972 <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
800396e: 2303 movs r3, #3
8003970: e04e b.n 8003a10 <UART_WaitOnFlagUntilTimeout+0xd2>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
8003972: 68fb ldr r3, [r7, #12]
8003974: 681b ldr r3, [r3, #0]
8003976: 681b ldr r3, [r3, #0]
8003978: f003 0304 and.w r3, r3, #4
800397c: 2b00 cmp r3, #0
800397e: d037 beq.n 80039f0 <UART_WaitOnFlagUntilTimeout+0xb2>
8003980: 68bb ldr r3, [r7, #8]
8003982: 2b80 cmp r3, #128 @ 0x80
8003984: d034 beq.n 80039f0 <UART_WaitOnFlagUntilTimeout+0xb2>
8003986: 68bb ldr r3, [r7, #8]
8003988: 2b40 cmp r3, #64 @ 0x40
800398a: d031 beq.n 80039f0 <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
800398c: 68fb ldr r3, [r7, #12]
800398e: 681b ldr r3, [r3, #0]
8003990: 69db ldr r3, [r3, #28]
8003992: f003 0308 and.w r3, r3, #8
8003996: 2b08 cmp r3, #8
8003998: d110 bne.n 80039bc <UART_WaitOnFlagUntilTimeout+0x7e>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
800399a: 68fb ldr r3, [r7, #12]
800399c: 681b ldr r3, [r3, #0]
800399e: 2208 movs r2, #8
80039a0: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
80039a2: 68f8 ldr r0, [r7, #12]
80039a4: f000 f838 bl 8003a18 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
80039a8: 68fb ldr r3, [r7, #12]
80039aa: 2208 movs r2, #8
80039ac: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
80039b0: 68fb ldr r3, [r7, #12]
80039b2: 2200 movs r2, #0
80039b4: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_ERROR;
80039b8: 2301 movs r3, #1
80039ba: e029 b.n 8003a10 <UART_WaitOnFlagUntilTimeout+0xd2>
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
80039bc: 68fb ldr r3, [r7, #12]
80039be: 681b ldr r3, [r3, #0]
80039c0: 69db ldr r3, [r3, #28]
80039c2: f403 6300 and.w r3, r3, #2048 @ 0x800
80039c6: f5b3 6f00 cmp.w r3, #2048 @ 0x800
80039ca: d111 bne.n 80039f0 <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
80039cc: 68fb ldr r3, [r7, #12]
80039ce: 681b ldr r3, [r3, #0]
80039d0: f44f 6200 mov.w r2, #2048 @ 0x800
80039d4: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
80039d6: 68f8 ldr r0, [r7, #12]
80039d8: f000 f81e bl 8003a18 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
80039dc: 68fb ldr r3, [r7, #12]
80039de: 2220 movs r2, #32
80039e0: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
80039e4: 68fb ldr r3, [r7, #12]
80039e6: 2200 movs r2, #0
80039e8: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_TIMEOUT;
80039ec: 2303 movs r3, #3
80039ee: e00f b.n 8003a10 <UART_WaitOnFlagUntilTimeout+0xd2>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80039f0: 68fb ldr r3, [r7, #12]
80039f2: 681b ldr r3, [r3, #0]
80039f4: 69da ldr r2, [r3, #28]
80039f6: 68bb ldr r3, [r7, #8]
80039f8: 4013 ands r3, r2
80039fa: 68ba ldr r2, [r7, #8]
80039fc: 429a cmp r2, r3
80039fe: bf0c ite eq
8003a00: 2301 moveq r3, #1
8003a02: 2300 movne r3, #0
8003a04: b2db uxtb r3, r3
8003a06: 461a mov r2, r3
8003a08: 79fb ldrb r3, [r7, #7]
8003a0a: 429a cmp r2, r3
8003a0c: d0a0 beq.n 8003950 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8003a0e: 2300 movs r3, #0
}
8003a10: 4618 mov r0, r3
8003a12: 3710 adds r7, #16
8003a14: 46bd mov sp, r7
8003a16: bd80 pop {r7, pc}
08003a18 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8003a18: b480 push {r7}
8003a1a: b095 sub sp, #84 @ 0x54
8003a1c: af00 add r7, sp, #0
8003a1e: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8003a20: 687b ldr r3, [r7, #4]
8003a22: 681b ldr r3, [r3, #0]
8003a24: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8003a26: 6b7b ldr r3, [r7, #52] @ 0x34
8003a28: e853 3f00 ldrex r3, [r3]
8003a2c: 633b str r3, [r7, #48] @ 0x30
return(result);
8003a2e: 6b3b ldr r3, [r7, #48] @ 0x30
8003a30: f423 7390 bic.w r3, r3, #288 @ 0x120
8003a34: 64fb str r3, [r7, #76] @ 0x4c
8003a36: 687b ldr r3, [r7, #4]
8003a38: 681b ldr r3, [r3, #0]
8003a3a: 461a mov r2, r3
8003a3c: 6cfb ldr r3, [r7, #76] @ 0x4c
8003a3e: 643b str r3, [r7, #64] @ 0x40
8003a40: 63fa str r2, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003a42: 6bf9 ldr r1, [r7, #60] @ 0x3c
8003a44: 6c3a ldr r2, [r7, #64] @ 0x40
8003a46: e841 2300 strex r3, r2, [r1]
8003a4a: 63bb str r3, [r7, #56] @ 0x38
return(result);
8003a4c: 6bbb ldr r3, [r7, #56] @ 0x38
8003a4e: 2b00 cmp r3, #0
8003a50: d1e6 bne.n 8003a20 <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8003a52: 687b ldr r3, [r7, #4]
8003a54: 681b ldr r3, [r3, #0]
8003a56: 3308 adds r3, #8
8003a58: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8003a5a: 6a3b ldr r3, [r7, #32]
8003a5c: e853 3f00 ldrex r3, [r3]
8003a60: 61fb str r3, [r7, #28]
return(result);
8003a62: 69fb ldr r3, [r7, #28]
8003a64: f023 0301 bic.w r3, r3, #1
8003a68: 64bb str r3, [r7, #72] @ 0x48
8003a6a: 687b ldr r3, [r7, #4]
8003a6c: 681b ldr r3, [r3, #0]
8003a6e: 3308 adds r3, #8
8003a70: 6cba ldr r2, [r7, #72] @ 0x48
8003a72: 62fa str r2, [r7, #44] @ 0x2c
8003a74: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003a76: 6ab9 ldr r1, [r7, #40] @ 0x28
8003a78: 6afa ldr r2, [r7, #44] @ 0x2c
8003a7a: e841 2300 strex r3, r2, [r1]
8003a7e: 627b str r3, [r7, #36] @ 0x24
return(result);
8003a80: 6a7b ldr r3, [r7, #36] @ 0x24
8003a82: 2b00 cmp r3, #0
8003a84: d1e5 bne.n 8003a52 <UART_EndRxTransfer+0x3a>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8003a86: 687b ldr r3, [r7, #4]
8003a88: 6e1b ldr r3, [r3, #96] @ 0x60
8003a8a: 2b01 cmp r3, #1
8003a8c: d118 bne.n 8003ac0 <UART_EndRxTransfer+0xa8>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8003a8e: 687b ldr r3, [r7, #4]
8003a90: 681b ldr r3, [r3, #0]
8003a92: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8003a94: 68fb ldr r3, [r7, #12]
8003a96: e853 3f00 ldrex r3, [r3]
8003a9a: 60bb str r3, [r7, #8]
return(result);
8003a9c: 68bb ldr r3, [r7, #8]
8003a9e: f023 0310 bic.w r3, r3, #16
8003aa2: 647b str r3, [r7, #68] @ 0x44
8003aa4: 687b ldr r3, [r7, #4]
8003aa6: 681b ldr r3, [r3, #0]
8003aa8: 461a mov r2, r3
8003aaa: 6c7b ldr r3, [r7, #68] @ 0x44
8003aac: 61bb str r3, [r7, #24]
8003aae: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003ab0: 6979 ldr r1, [r7, #20]
8003ab2: 69ba ldr r2, [r7, #24]
8003ab4: e841 2300 strex r3, r2, [r1]
8003ab8: 613b str r3, [r7, #16]
return(result);
8003aba: 693b ldr r3, [r7, #16]
8003abc: 2b00 cmp r3, #0
8003abe: d1e6 bne.n 8003a8e <UART_EndRxTransfer+0x76>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8003ac0: 687b ldr r3, [r7, #4]
8003ac2: 2220 movs r2, #32
8003ac4: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8003ac8: 687b ldr r3, [r7, #4]
8003aca: 2200 movs r2, #0
8003acc: 661a str r2, [r3, #96] @ 0x60
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
8003ace: 687b ldr r3, [r7, #4]
8003ad0: 2200 movs r2, #0
8003ad2: 669a str r2, [r3, #104] @ 0x68
}
8003ad4: bf00 nop
8003ad6: 3754 adds r7, #84 @ 0x54
8003ad8: 46bd mov sp, r7
8003ada: f85d 7b04 ldr.w r7, [sp], #4
8003ade: 4770 bx lr
08003ae0 <SVC_Setup>:
#endif /* SysTick */
/*
Setup SVC to reset value.
*/
__STATIC_INLINE void SVC_Setup (void) {
8003ae0: b480 push {r7}
8003ae2: af00 add r7, sp, #0
* The issue was logged under:https://github.com/ARM-software/CMSIS-FreeRTOS/issues/35
* until it is correctly fixed, the code below is commented
*/
/* NVIC_SetPriority (SVCall_IRQn, 0U); */
#endif
}
8003ae4: bf00 nop
8003ae6: 46bd mov sp, r7
8003ae8: f85d 7b04 ldr.w r7, [sp], #4
8003aec: 4770 bx lr
...
08003af0 <osKernelInitialize>:
/*---------------------------------------------------------------------------*/
osStatus_t osKernelInitialize (void) {
8003af0: b480 push {r7}
8003af2: b085 sub sp, #20
8003af4: af00 add r7, sp, #0
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
8003af6: f3ef 8305 mrs r3, IPSR
8003afa: 60bb str r3, [r7, #8]
return(result);
8003afc: 68bb ldr r3, [r7, #8]
osStatus_t stat;
if (IS_IRQ()) {
8003afe: 2b00 cmp r3, #0
8003b00: d10f bne.n 8003b22 <osKernelInitialize+0x32>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8003b02: f3ef 8310 mrs r3, PRIMASK
8003b06: 607b str r3, [r7, #4]
return(result);
8003b08: 687b ldr r3, [r7, #4]
8003b0a: 2b00 cmp r3, #0
8003b0c: d105 bne.n 8003b1a <osKernelInitialize+0x2a>
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
8003b0e: f3ef 8311 mrs r3, BASEPRI
8003b12: 603b str r3, [r7, #0]
return(result);
8003b14: 683b ldr r3, [r7, #0]
8003b16: 2b00 cmp r3, #0
8003b18: d007 beq.n 8003b2a <osKernelInitialize+0x3a>
8003b1a: 4b0e ldr r3, [pc, #56] @ (8003b54 <osKernelInitialize+0x64>)
8003b1c: 681b ldr r3, [r3, #0]
8003b1e: 2b02 cmp r3, #2
8003b20: d103 bne.n 8003b2a <osKernelInitialize+0x3a>
stat = osErrorISR;
8003b22: f06f 0305 mvn.w r3, #5
8003b26: 60fb str r3, [r7, #12]
8003b28: e00c b.n 8003b44 <osKernelInitialize+0x54>
}
else {
if (KernelState == osKernelInactive) {
8003b2a: 4b0a ldr r3, [pc, #40] @ (8003b54 <osKernelInitialize+0x64>)
8003b2c: 681b ldr r3, [r3, #0]
8003b2e: 2b00 cmp r3, #0
8003b30: d105 bne.n 8003b3e <osKernelInitialize+0x4e>
#if defined(USE_FREERTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
vPortDefineHeapRegions (configHEAP_5_REGIONS);
#endif
KernelState = osKernelReady;
8003b32: 4b08 ldr r3, [pc, #32] @ (8003b54 <osKernelInitialize+0x64>)
8003b34: 2201 movs r2, #1
8003b36: 601a str r2, [r3, #0]
stat = osOK;
8003b38: 2300 movs r3, #0
8003b3a: 60fb str r3, [r7, #12]
8003b3c: e002 b.n 8003b44 <osKernelInitialize+0x54>
} else {
stat = osError;
8003b3e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
8003b42: 60fb str r3, [r7, #12]
}
}
return (stat);
8003b44: 68fb ldr r3, [r7, #12]
}
8003b46: 4618 mov r0, r3
8003b48: 3714 adds r7, #20
8003b4a: 46bd mov sp, r7
8003b4c: f85d 7b04 ldr.w r7, [sp], #4
8003b50: 4770 bx lr
8003b52: bf00 nop
8003b54: 2000016c .word 0x2000016c
08003b58 <osKernelStart>:
}
return (state);
}
osStatus_t osKernelStart (void) {
8003b58: b580 push {r7, lr}
8003b5a: b084 sub sp, #16
8003b5c: af00 add r7, sp, #0
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
8003b5e: f3ef 8305 mrs r3, IPSR
8003b62: 60bb str r3, [r7, #8]
return(result);
8003b64: 68bb ldr r3, [r7, #8]
osStatus_t stat;
if (IS_IRQ()) {
8003b66: 2b00 cmp r3, #0
8003b68: d10f bne.n 8003b8a <osKernelStart+0x32>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8003b6a: f3ef 8310 mrs r3, PRIMASK
8003b6e: 607b str r3, [r7, #4]
return(result);
8003b70: 687b ldr r3, [r7, #4]
8003b72: 2b00 cmp r3, #0
8003b74: d105 bne.n 8003b82 <osKernelStart+0x2a>
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
8003b76: f3ef 8311 mrs r3, BASEPRI
8003b7a: 603b str r3, [r7, #0]
return(result);
8003b7c: 683b ldr r3, [r7, #0]
8003b7e: 2b00 cmp r3, #0
8003b80: d007 beq.n 8003b92 <osKernelStart+0x3a>
8003b82: 4b0f ldr r3, [pc, #60] @ (8003bc0 <osKernelStart+0x68>)
8003b84: 681b ldr r3, [r3, #0]
8003b86: 2b02 cmp r3, #2
8003b88: d103 bne.n 8003b92 <osKernelStart+0x3a>
stat = osErrorISR;
8003b8a: f06f 0305 mvn.w r3, #5
8003b8e: 60fb str r3, [r7, #12]
8003b90: e010 b.n 8003bb4 <osKernelStart+0x5c>
}
else {
if (KernelState == osKernelReady) {
8003b92: 4b0b ldr r3, [pc, #44] @ (8003bc0 <osKernelStart+0x68>)
8003b94: 681b ldr r3, [r3, #0]
8003b96: 2b01 cmp r3, #1
8003b98: d109 bne.n 8003bae <osKernelStart+0x56>
/* Ensure SVC priority is at the reset value */
SVC_Setup();
8003b9a: f7ff ffa1 bl 8003ae0 <SVC_Setup>
/* Change state to enable IRQ masking check */
KernelState = osKernelRunning;
8003b9e: 4b08 ldr r3, [pc, #32] @ (8003bc0 <osKernelStart+0x68>)
8003ba0: 2202 movs r2, #2
8003ba2: 601a str r2, [r3, #0]
/* Start the kernel scheduler */
vTaskStartScheduler();
8003ba4: f001 f8ca bl 8004d3c <vTaskStartScheduler>
stat = osOK;
8003ba8: 2300 movs r3, #0
8003baa: 60fb str r3, [r7, #12]
8003bac: e002 b.n 8003bb4 <osKernelStart+0x5c>
} else {
stat = osError;
8003bae: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
8003bb2: 60fb str r3, [r7, #12]
}
}
return (stat);
8003bb4: 68fb ldr r3, [r7, #12]
}
8003bb6: 4618 mov r0, r3
8003bb8: 3710 adds r7, #16
8003bba: 46bd mov sp, r7
8003bbc: bd80 pop {r7, pc}
8003bbe: bf00 nop
8003bc0: 2000016c .word 0x2000016c
08003bc4 <osThreadNew>:
return (configCPU_CLOCK_HZ);
}
/*---------------------------------------------------------------------------*/
osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
8003bc4: b580 push {r7, lr}
8003bc6: b090 sub sp, #64 @ 0x40
8003bc8: af04 add r7, sp, #16
8003bca: 60f8 str r0, [r7, #12]
8003bcc: 60b9 str r1, [r7, #8]
8003bce: 607a str r2, [r7, #4]
uint32_t stack;
TaskHandle_t hTask;
UBaseType_t prio;
int32_t mem;
hTask = NULL;
8003bd0: 2300 movs r3, #0
8003bd2: 613b str r3, [r7, #16]
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
8003bd4: f3ef 8305 mrs r3, IPSR
8003bd8: 61fb str r3, [r7, #28]
return(result);
8003bda: 69fb ldr r3, [r7, #28]
if (!IS_IRQ() && (func != NULL)) {
8003bdc: 2b00 cmp r3, #0
8003bde: f040 8090 bne.w 8003d02 <osThreadNew+0x13e>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8003be2: f3ef 8310 mrs r3, PRIMASK
8003be6: 61bb str r3, [r7, #24]
return(result);
8003be8: 69bb ldr r3, [r7, #24]
8003bea: 2b00 cmp r3, #0
8003bec: d105 bne.n 8003bfa <osThreadNew+0x36>
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
8003bee: f3ef 8311 mrs r3, BASEPRI
8003bf2: 617b str r3, [r7, #20]
return(result);
8003bf4: 697b ldr r3, [r7, #20]
8003bf6: 2b00 cmp r3, #0
8003bf8: d003 beq.n 8003c02 <osThreadNew+0x3e>
8003bfa: 4b44 ldr r3, [pc, #272] @ (8003d0c <osThreadNew+0x148>)
8003bfc: 681b ldr r3, [r3, #0]
8003bfe: 2b02 cmp r3, #2
8003c00: d07f beq.n 8003d02 <osThreadNew+0x13e>
8003c02: 68fb ldr r3, [r7, #12]
8003c04: 2b00 cmp r3, #0
8003c06: d07c beq.n 8003d02 <osThreadNew+0x13e>
stack = configMINIMAL_STACK_SIZE;
8003c08: f44f 7380 mov.w r3, #256 @ 0x100
8003c0c: 62bb str r3, [r7, #40] @ 0x28
prio = (UBaseType_t)osPriorityNormal;
8003c0e: 2318 movs r3, #24
8003c10: 627b str r3, [r7, #36] @ 0x24
name = NULL;
8003c12: 2300 movs r3, #0
8003c14: 62fb str r3, [r7, #44] @ 0x2c
mem = -1;
8003c16: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
8003c1a: 623b str r3, [r7, #32]
if (attr != NULL) {
8003c1c: 687b ldr r3, [r7, #4]
8003c1e: 2b00 cmp r3, #0
8003c20: d045 beq.n 8003cae <osThreadNew+0xea>
if (attr->name != NULL) {
8003c22: 687b ldr r3, [r7, #4]
8003c24: 681b ldr r3, [r3, #0]
8003c26: 2b00 cmp r3, #0
8003c28: d002 beq.n 8003c30 <osThreadNew+0x6c>
name = attr->name;
8003c2a: 687b ldr r3, [r7, #4]
8003c2c: 681b ldr r3, [r3, #0]
8003c2e: 62fb str r3, [r7, #44] @ 0x2c
}
if (attr->priority != osPriorityNone) {
8003c30: 687b ldr r3, [r7, #4]
8003c32: 699b ldr r3, [r3, #24]
8003c34: 2b00 cmp r3, #0
8003c36: d002 beq.n 8003c3e <osThreadNew+0x7a>
prio = (UBaseType_t)attr->priority;
8003c38: 687b ldr r3, [r7, #4]
8003c3a: 699b ldr r3, [r3, #24]
8003c3c: 627b str r3, [r7, #36] @ 0x24
}
if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {
8003c3e: 6a7b ldr r3, [r7, #36] @ 0x24
8003c40: 2b00 cmp r3, #0
8003c42: d008 beq.n 8003c56 <osThreadNew+0x92>
8003c44: 6a7b ldr r3, [r7, #36] @ 0x24
8003c46: 2b38 cmp r3, #56 @ 0x38
8003c48: d805 bhi.n 8003c56 <osThreadNew+0x92>
8003c4a: 687b ldr r3, [r7, #4]
8003c4c: 685b ldr r3, [r3, #4]
8003c4e: f003 0301 and.w r3, r3, #1
8003c52: 2b00 cmp r3, #0
8003c54: d001 beq.n 8003c5a <osThreadNew+0x96>
return (NULL);
8003c56: 2300 movs r3, #0
8003c58: e054 b.n 8003d04 <osThreadNew+0x140>
}
if (attr->stack_size > 0U) {
8003c5a: 687b ldr r3, [r7, #4]
8003c5c: 695b ldr r3, [r3, #20]
8003c5e: 2b00 cmp r3, #0
8003c60: d003 beq.n 8003c6a <osThreadNew+0xa6>
/* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */
/* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */
stack = attr->stack_size / sizeof(StackType_t);
8003c62: 687b ldr r3, [r7, #4]
8003c64: 695b ldr r3, [r3, #20]
8003c66: 089b lsrs r3, r3, #2
8003c68: 62bb str r3, [r7, #40] @ 0x28
}
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) &&
8003c6a: 687b ldr r3, [r7, #4]
8003c6c: 689b ldr r3, [r3, #8]
8003c6e: 2b00 cmp r3, #0
8003c70: d00e beq.n 8003c90 <osThreadNew+0xcc>
8003c72: 687b ldr r3, [r7, #4]
8003c74: 68db ldr r3, [r3, #12]
8003c76: 2b5b cmp r3, #91 @ 0x5b
8003c78: d90a bls.n 8003c90 <osThreadNew+0xcc>
(attr->stack_mem != NULL) && (attr->stack_size > 0U)) {
8003c7a: 687b ldr r3, [r7, #4]
8003c7c: 691b ldr r3, [r3, #16]
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) &&
8003c7e: 2b00 cmp r3, #0
8003c80: d006 beq.n 8003c90 <osThreadNew+0xcc>
(attr->stack_mem != NULL) && (attr->stack_size > 0U)) {
8003c82: 687b ldr r3, [r7, #4]
8003c84: 695b ldr r3, [r3, #20]
8003c86: 2b00 cmp r3, #0
8003c88: d002 beq.n 8003c90 <osThreadNew+0xcc>
mem = 1;
8003c8a: 2301 movs r3, #1
8003c8c: 623b str r3, [r7, #32]
8003c8e: e010 b.n 8003cb2 <osThreadNew+0xee>
}
else {
if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {
8003c90: 687b ldr r3, [r7, #4]
8003c92: 689b ldr r3, [r3, #8]
8003c94: 2b00 cmp r3, #0
8003c96: d10c bne.n 8003cb2 <osThreadNew+0xee>
8003c98: 687b ldr r3, [r7, #4]
8003c9a: 68db ldr r3, [r3, #12]
8003c9c: 2b00 cmp r3, #0
8003c9e: d108 bne.n 8003cb2 <osThreadNew+0xee>
8003ca0: 687b ldr r3, [r7, #4]
8003ca2: 691b ldr r3, [r3, #16]
8003ca4: 2b00 cmp r3, #0
8003ca6: d104 bne.n 8003cb2 <osThreadNew+0xee>
mem = 0;
8003ca8: 2300 movs r3, #0
8003caa: 623b str r3, [r7, #32]
8003cac: e001 b.n 8003cb2 <osThreadNew+0xee>
}
}
}
else {
mem = 0;
8003cae: 2300 movs r3, #0
8003cb0: 623b str r3, [r7, #32]
}
if (mem == 1) {
8003cb2: 6a3b ldr r3, [r7, #32]
8003cb4: 2b01 cmp r3, #1
8003cb6: d110 bne.n 8003cda <osThreadNew+0x116>
hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem,
8003cb8: 687b ldr r3, [r7, #4]
8003cba: 691b ldr r3, [r3, #16]
(StaticTask_t *)attr->cb_mem);
8003cbc: 687a ldr r2, [r7, #4]
8003cbe: 6892 ldr r2, [r2, #8]
hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem,
8003cc0: 9202 str r2, [sp, #8]
8003cc2: 9301 str r3, [sp, #4]
8003cc4: 6a7b ldr r3, [r7, #36] @ 0x24
8003cc6: 9300 str r3, [sp, #0]
8003cc8: 68bb ldr r3, [r7, #8]
8003cca: 6aba ldr r2, [r7, #40] @ 0x28
8003ccc: 6af9 ldr r1, [r7, #44] @ 0x2c
8003cce: 68f8 ldr r0, [r7, #12]
8003cd0: f000 fe4e bl 8004970 <xTaskCreateStatic>
8003cd4: 4603 mov r3, r0
8003cd6: 613b str r3, [r7, #16]
8003cd8: e013 b.n 8003d02 <osThreadNew+0x13e>
}
else {
if (mem == 0) {
8003cda: 6a3b ldr r3, [r7, #32]
8003cdc: 2b00 cmp r3, #0
8003cde: d110 bne.n 8003d02 <osThreadNew+0x13e>
if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) {
8003ce0: 6abb ldr r3, [r7, #40] @ 0x28
8003ce2: b29a uxth r2, r3
8003ce4: f107 0310 add.w r3, r7, #16
8003ce8: 9301 str r3, [sp, #4]
8003cea: 6a7b ldr r3, [r7, #36] @ 0x24
8003cec: 9300 str r3, [sp, #0]
8003cee: 68bb ldr r3, [r7, #8]
8003cf0: 6af9 ldr r1, [r7, #44] @ 0x2c
8003cf2: 68f8 ldr r0, [r7, #12]
8003cf4: f000 fea2 bl 8004a3c <xTaskCreate>
8003cf8: 4603 mov r3, r0
8003cfa: 2b01 cmp r3, #1
8003cfc: d001 beq.n 8003d02 <osThreadNew+0x13e>
hTask = NULL;
8003cfe: 2300 movs r3, #0
8003d00: 613b str r3, [r7, #16]
}
}
}
}
return ((osThreadId_t)hTask);
8003d02: 693b ldr r3, [r7, #16]
}
8003d04: 4618 mov r0, r3
8003d06: 3730 adds r7, #48 @ 0x30
8003d08: 46bd mov sp, r7
8003d0a: bd80 pop {r7, pc}
8003d0c: 2000016c .word 0x2000016c
08003d10 <osDelay>:
/* Return flags before clearing */
return (rflags);
}
osStatus_t osDelay (uint32_t ticks) {
8003d10: b580 push {r7, lr}
8003d12: b086 sub sp, #24
8003d14: af00 add r7, sp, #0
8003d16: 6078 str r0, [r7, #4]
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
8003d18: f3ef 8305 mrs r3, IPSR
8003d1c: 613b str r3, [r7, #16]
return(result);
8003d1e: 693b ldr r3, [r7, #16]
osStatus_t stat;
if (IS_IRQ()) {
8003d20: 2b00 cmp r3, #0
8003d22: d10f bne.n 8003d44 <osDelay+0x34>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8003d24: f3ef 8310 mrs r3, PRIMASK
8003d28: 60fb str r3, [r7, #12]
return(result);
8003d2a: 68fb ldr r3, [r7, #12]
8003d2c: 2b00 cmp r3, #0
8003d2e: d105 bne.n 8003d3c <osDelay+0x2c>
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
8003d30: f3ef 8311 mrs r3, BASEPRI
8003d34: 60bb str r3, [r7, #8]
return(result);
8003d36: 68bb ldr r3, [r7, #8]
8003d38: 2b00 cmp r3, #0
8003d3a: d007 beq.n 8003d4c <osDelay+0x3c>
8003d3c: 4b0a ldr r3, [pc, #40] @ (8003d68 <osDelay+0x58>)
8003d3e: 681b ldr r3, [r3, #0]
8003d40: 2b02 cmp r3, #2
8003d42: d103 bne.n 8003d4c <osDelay+0x3c>
stat = osErrorISR;
8003d44: f06f 0305 mvn.w r3, #5
8003d48: 617b str r3, [r7, #20]
8003d4a: e007 b.n 8003d5c <osDelay+0x4c>
}
else {
stat = osOK;
8003d4c: 2300 movs r3, #0
8003d4e: 617b str r3, [r7, #20]
if (ticks != 0U) {
8003d50: 687b ldr r3, [r7, #4]
8003d52: 2b00 cmp r3, #0
8003d54: d002 beq.n 8003d5c <osDelay+0x4c>
vTaskDelay(ticks);
8003d56: 6878 ldr r0, [r7, #4]
8003d58: f000 ffb8 bl 8004ccc <vTaskDelay>
}
}
return (stat);
8003d5c: 697b ldr r3, [r7, #20]
}
8003d5e: 4618 mov r0, r3
8003d60: 3718 adds r7, #24
8003d62: 46bd mov sp, r7
8003d64: bd80 pop {r7, pc}
8003d66: bf00 nop
8003d68: 2000016c .word 0x2000016c
08003d6c <vApplicationGetIdleTaskMemory>:
/*
vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
equals to 1 and is required for static memory allocation support.
*/
void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
8003d6c: b480 push {r7}
8003d6e: b085 sub sp, #20
8003d70: af00 add r7, sp, #0
8003d72: 60f8 str r0, [r7, #12]
8003d74: 60b9 str r1, [r7, #8]
8003d76: 607a str r2, [r7, #4]
*ppxIdleTaskTCBBuffer = &Idle_TCB;
8003d78: 68fb ldr r3, [r7, #12]
8003d7a: 4a07 ldr r2, [pc, #28] @ (8003d98 <vApplicationGetIdleTaskMemory+0x2c>)
8003d7c: 601a str r2, [r3, #0]
*ppxIdleTaskStackBuffer = &Idle_Stack[0];
8003d7e: 68bb ldr r3, [r7, #8]
8003d80: 4a06 ldr r2, [pc, #24] @ (8003d9c <vApplicationGetIdleTaskMemory+0x30>)
8003d82: 601a str r2, [r3, #0]
*pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE;
8003d84: 687b ldr r3, [r7, #4]
8003d86: f44f 7280 mov.w r2, #256 @ 0x100
8003d8a: 601a str r2, [r3, #0]
}
8003d8c: bf00 nop
8003d8e: 3714 adds r7, #20
8003d90: 46bd mov sp, r7
8003d92: f85d 7b04 ldr.w r7, [sp], #4
8003d96: 4770 bx lr
8003d98: 20000170 .word 0x20000170
8003d9c: 200001cc .word 0x200001cc
08003da0 <vApplicationGetTimerTaskMemory>:
/*
vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
equals to 1 and is required for static memory allocation support.
*/
void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
8003da0: b480 push {r7}
8003da2: b085 sub sp, #20
8003da4: af00 add r7, sp, #0
8003da6: 60f8 str r0, [r7, #12]
8003da8: 60b9 str r1, [r7, #8]
8003daa: 607a str r2, [r7, #4]
*ppxTimerTaskTCBBuffer = &Timer_TCB;
8003dac: 68fb ldr r3, [r7, #12]
8003dae: 4a07 ldr r2, [pc, #28] @ (8003dcc <vApplicationGetTimerTaskMemory+0x2c>)
8003db0: 601a str r2, [r3, #0]
*ppxTimerTaskStackBuffer = &Timer_Stack[0];
8003db2: 68bb ldr r3, [r7, #8]
8003db4: 4a06 ldr r2, [pc, #24] @ (8003dd0 <vApplicationGetTimerTaskMemory+0x30>)
8003db6: 601a str r2, [r3, #0]
*pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH;
8003db8: 687b ldr r3, [r7, #4]
8003dba: f44f 7200 mov.w r2, #512 @ 0x200
8003dbe: 601a str r2, [r3, #0]
}
8003dc0: bf00 nop
8003dc2: 3714 adds r7, #20
8003dc4: 46bd mov sp, r7
8003dc6: f85d 7b04 ldr.w r7, [sp], #4
8003dca: 4770 bx lr
8003dcc: 200005cc .word 0x200005cc
8003dd0: 20000628 .word 0x20000628
08003dd4 <vListInitialise>:
/*-----------------------------------------------------------
* PUBLIC LIST API documented in list.h
*----------------------------------------------------------*/
void vListInitialise( List_t * const pxList )
{
8003dd4: b480 push {r7}
8003dd6: b083 sub sp, #12
8003dd8: af00 add r7, sp, #0
8003dda: 6078 str r0, [r7, #4]
/* The list structure contains a list item which is used to mark the
end of the list. To initialise the list the list end is inserted
as the only list entry. */
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
8003ddc: 687b ldr r3, [r7, #4]
8003dde: f103 0208 add.w r2, r3, #8
8003de2: 687b ldr r3, [r7, #4]
8003de4: 605a str r2, [r3, #4]
/* The list end value is the highest possible value in the list to
ensure it remains at the end of the list. */
pxList->xListEnd.xItemValue = portMAX_DELAY;
8003de6: 687b ldr r3, [r7, #4]
8003de8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8003dec: 609a str r2, [r3, #8]
/* The list end next and previous pointers point to itself so we know
when the list is empty. */
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
8003dee: 687b ldr r3, [r7, #4]
8003df0: f103 0208 add.w r2, r3, #8
8003df4: 687b ldr r3, [r7, #4]
8003df6: 60da str r2, [r3, #12]
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
8003df8: 687b ldr r3, [r7, #4]
8003dfa: f103 0208 add.w r2, r3, #8
8003dfe: 687b ldr r3, [r7, #4]
8003e00: 611a str r2, [r3, #16]
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
8003e02: 687b ldr r3, [r7, #4]
8003e04: 2200 movs r2, #0
8003e06: 601a str r2, [r3, #0]
/* Write known values into the list if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
}
8003e08: bf00 nop
8003e0a: 370c adds r7, #12
8003e0c: 46bd mov sp, r7
8003e0e: f85d 7b04 ldr.w r7, [sp], #4
8003e12: 4770 bx lr
08003e14 <vListInitialiseItem>:
/*-----------------------------------------------------------*/
void vListInitialiseItem( ListItem_t * const pxItem )
{
8003e14: b480 push {r7}
8003e16: b083 sub sp, #12
8003e18: af00 add r7, sp, #0
8003e1a: 6078 str r0, [r7, #4]
/* Make sure the list item is not recorded as being on a list. */
pxItem->pxContainer = NULL;
8003e1c: 687b ldr r3, [r7, #4]
8003e1e: 2200 movs r2, #0
8003e20: 611a str r2, [r3, #16]
/* Write known values into the list item if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
}
8003e22: bf00 nop
8003e24: 370c adds r7, #12
8003e26: 46bd mov sp, r7
8003e28: f85d 7b04 ldr.w r7, [sp], #4
8003e2c: 4770 bx lr
08003e2e <vListInsertEnd>:
/*-----------------------------------------------------------*/
void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
{
8003e2e: b480 push {r7}
8003e30: b085 sub sp, #20
8003e32: af00 add r7, sp, #0
8003e34: 6078 str r0, [r7, #4]
8003e36: 6039 str r1, [r7, #0]
ListItem_t * const pxIndex = pxList->pxIndex;
8003e38: 687b ldr r3, [r7, #4]
8003e3a: 685b ldr r3, [r3, #4]
8003e3c: 60fb str r3, [r7, #12]
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
/* Insert a new list item into pxList, but rather than sort the list,
makes the new list item the last item to be removed by a call to
listGET_OWNER_OF_NEXT_ENTRY(). */
pxNewListItem->pxNext = pxIndex;
8003e3e: 683b ldr r3, [r7, #0]
8003e40: 68fa ldr r2, [r7, #12]
8003e42: 605a str r2, [r3, #4]
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
8003e44: 68fb ldr r3, [r7, #12]
8003e46: 689a ldr r2, [r3, #8]
8003e48: 683b ldr r3, [r7, #0]
8003e4a: 609a str r2, [r3, #8]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
pxIndex->pxPrevious->pxNext = pxNewListItem;
8003e4c: 68fb ldr r3, [r7, #12]
8003e4e: 689b ldr r3, [r3, #8]
8003e50: 683a ldr r2, [r7, #0]
8003e52: 605a str r2, [r3, #4]
pxIndex->pxPrevious = pxNewListItem;
8003e54: 68fb ldr r3, [r7, #12]
8003e56: 683a ldr r2, [r7, #0]
8003e58: 609a str r2, [r3, #8]
/* Remember which list the item is in. */
pxNewListItem->pxContainer = pxList;
8003e5a: 683b ldr r3, [r7, #0]
8003e5c: 687a ldr r2, [r7, #4]
8003e5e: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
8003e60: 687b ldr r3, [r7, #4]
8003e62: 681b ldr r3, [r3, #0]
8003e64: 1c5a adds r2, r3, #1
8003e66: 687b ldr r3, [r7, #4]
8003e68: 601a str r2, [r3, #0]
}
8003e6a: bf00 nop
8003e6c: 3714 adds r7, #20
8003e6e: 46bd mov sp, r7
8003e70: f85d 7b04 ldr.w r7, [sp], #4
8003e74: 4770 bx lr
08003e76 <vListInsert>:
/*-----------------------------------------------------------*/
void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
{
8003e76: b480 push {r7}
8003e78: b085 sub sp, #20
8003e7a: af00 add r7, sp, #0
8003e7c: 6078 str r0, [r7, #4]
8003e7e: 6039 str r1, [r7, #0]
ListItem_t *pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
8003e80: 683b ldr r3, [r7, #0]
8003e82: 681b ldr r3, [r3, #0]
8003e84: 60bb str r3, [r7, #8]
new list item should be placed after it. This ensures that TCBs which are
stored in ready lists (all of which have the same xItemValue value) get a
share of the CPU. However, if the xItemValue is the same as the back marker
the iteration loop below will not end. Therefore the value is checked
first, and the algorithm slightly modified if necessary. */
if( xValueOfInsertion == portMAX_DELAY )
8003e86: 68bb ldr r3, [r7, #8]
8003e88: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8003e8c: d103 bne.n 8003e96 <vListInsert+0x20>
{
pxIterator = pxList->xListEnd.pxPrevious;
8003e8e: 687b ldr r3, [r7, #4]
8003e90: 691b ldr r3, [r3, #16]
8003e92: 60fb str r3, [r7, #12]
8003e94: e00c b.n 8003eb0 <vListInsert+0x3a>
4) Using a queue or semaphore before it has been initialised or
before the scheduler has been started (are interrupts firing
before vTaskStartScheduler() has been called?).
**********************************************************************/
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
8003e96: 687b ldr r3, [r7, #4]
8003e98: 3308 adds r3, #8
8003e9a: 60fb str r3, [r7, #12]
8003e9c: e002 b.n 8003ea4 <vListInsert+0x2e>
8003e9e: 68fb ldr r3, [r7, #12]
8003ea0: 685b ldr r3, [r3, #4]
8003ea2: 60fb str r3, [r7, #12]
8003ea4: 68fb ldr r3, [r7, #12]
8003ea6: 685b ldr r3, [r3, #4]
8003ea8: 681b ldr r3, [r3, #0]
8003eaa: 68ba ldr r2, [r7, #8]
8003eac: 429a cmp r2, r3
8003eae: d2f6 bcs.n 8003e9e <vListInsert+0x28>
/* There is nothing to do here, just iterating to the wanted
insertion position. */
}
}
pxNewListItem->pxNext = pxIterator->pxNext;
8003eb0: 68fb ldr r3, [r7, #12]
8003eb2: 685a ldr r2, [r3, #4]
8003eb4: 683b ldr r3, [r7, #0]
8003eb6: 605a str r2, [r3, #4]
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
8003eb8: 683b ldr r3, [r7, #0]
8003eba: 685b ldr r3, [r3, #4]
8003ebc: 683a ldr r2, [r7, #0]
8003ebe: 609a str r2, [r3, #8]
pxNewListItem->pxPrevious = pxIterator;
8003ec0: 683b ldr r3, [r7, #0]
8003ec2: 68fa ldr r2, [r7, #12]
8003ec4: 609a str r2, [r3, #8]
pxIterator->pxNext = pxNewListItem;
8003ec6: 68fb ldr r3, [r7, #12]
8003ec8: 683a ldr r2, [r7, #0]
8003eca: 605a str r2, [r3, #4]
/* Remember which list the item is in. This allows fast removal of the
item later. */
pxNewListItem->pxContainer = pxList;
8003ecc: 683b ldr r3, [r7, #0]
8003ece: 687a ldr r2, [r7, #4]
8003ed0: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
8003ed2: 687b ldr r3, [r7, #4]
8003ed4: 681b ldr r3, [r3, #0]
8003ed6: 1c5a adds r2, r3, #1
8003ed8: 687b ldr r3, [r7, #4]
8003eda: 601a str r2, [r3, #0]
}
8003edc: bf00 nop
8003ede: 3714 adds r7, #20
8003ee0: 46bd mov sp, r7
8003ee2: f85d 7b04 ldr.w r7, [sp], #4
8003ee6: 4770 bx lr
08003ee8 <uxListRemove>:
/*-----------------------------------------------------------*/
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
8003ee8: b480 push {r7}
8003eea: b085 sub sp, #20
8003eec: af00 add r7, sp, #0
8003eee: 6078 str r0, [r7, #4]
/* The list item knows which list it is in. Obtain the list from the list
item. */
List_t * const pxList = pxItemToRemove->pxContainer;
8003ef0: 687b ldr r3, [r7, #4]
8003ef2: 691b ldr r3, [r3, #16]
8003ef4: 60fb str r3, [r7, #12]
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
8003ef6: 687b ldr r3, [r7, #4]
8003ef8: 685b ldr r3, [r3, #4]
8003efa: 687a ldr r2, [r7, #4]
8003efc: 6892 ldr r2, [r2, #8]
8003efe: 609a str r2, [r3, #8]
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
8003f00: 687b ldr r3, [r7, #4]
8003f02: 689b ldr r3, [r3, #8]
8003f04: 687a ldr r2, [r7, #4]
8003f06: 6852 ldr r2, [r2, #4]
8003f08: 605a str r2, [r3, #4]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
/* Make sure the index is left pointing to a valid item. */
if( pxList->pxIndex == pxItemToRemove )
8003f0a: 68fb ldr r3, [r7, #12]
8003f0c: 685b ldr r3, [r3, #4]
8003f0e: 687a ldr r2, [r7, #4]
8003f10: 429a cmp r2, r3
8003f12: d103 bne.n 8003f1c <uxListRemove+0x34>
{
pxList->pxIndex = pxItemToRemove->pxPrevious;
8003f14: 687b ldr r3, [r7, #4]
8003f16: 689a ldr r2, [r3, #8]
8003f18: 68fb ldr r3, [r7, #12]
8003f1a: 605a str r2, [r3, #4]
else
{
mtCOVERAGE_TEST_MARKER();
}
pxItemToRemove->pxContainer = NULL;
8003f1c: 687b ldr r3, [r7, #4]
8003f1e: 2200 movs r2, #0
8003f20: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )--;
8003f22: 68fb ldr r3, [r7, #12]
8003f24: 681b ldr r3, [r3, #0]
8003f26: 1e5a subs r2, r3, #1
8003f28: 68fb ldr r3, [r7, #12]
8003f2a: 601a str r2, [r3, #0]
return pxList->uxNumberOfItems;
8003f2c: 68fb ldr r3, [r7, #12]
8003f2e: 681b ldr r3, [r3, #0]
}
8003f30: 4618 mov r0, r3
8003f32: 3714 adds r7, #20
8003f34: 46bd mov sp, r7
8003f36: f85d 7b04 ldr.w r7, [sp], #4
8003f3a: 4770 bx lr
08003f3c <xQueueGenericReset>:
} \
taskEXIT_CRITICAL()
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
{
8003f3c: b580 push {r7, lr}
8003f3e: b084 sub sp, #16
8003f40: af00 add r7, sp, #0
8003f42: 6078 str r0, [r7, #4]
8003f44: 6039 str r1, [r7, #0]
Queue_t * const pxQueue = xQueue;
8003f46: 687b ldr r3, [r7, #4]
8003f48: 60fb str r3, [r7, #12]
configASSERT( pxQueue );
8003f4a: 68fb ldr r3, [r7, #12]
8003f4c: 2b00 cmp r3, #0
8003f4e: d10d bne.n 8003f6c <xQueueGenericReset+0x30>
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;
__asm volatile
8003f50: f04f 0350 mov.w r3, #80 @ 0x50
8003f54: b672 cpsid i
8003f56: f383 8811 msr BASEPRI, r3
8003f5a: f3bf 8f6f isb sy
8003f5e: f3bf 8f4f dsb sy
8003f62: b662 cpsie i
8003f64: 60bb str r3, [r7, #8]
" isb \n" \
" dsb \n" \
" cpsie i \n" \
:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
}
8003f66: bf00 nop
8003f68: bf00 nop
8003f6a: e7fd b.n 8003f68 <xQueueGenericReset+0x2c>
taskENTER_CRITICAL();
8003f6c: f002 f8a6 bl 80060bc <vPortEnterCritical>
{
pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
8003f70: 68fb ldr r3, [r7, #12]
8003f72: 681a ldr r2, [r3, #0]
8003f74: 68fb ldr r3, [r7, #12]
8003f76: 6bdb ldr r3, [r3, #60] @ 0x3c
8003f78: 68f9 ldr r1, [r7, #12]
8003f7a: 6c09 ldr r1, [r1, #64] @ 0x40
8003f7c: fb01 f303 mul.w r3, r1, r3
8003f80: 441a add r2, r3
8003f82: 68fb ldr r3, [r7, #12]
8003f84: 609a str r2, [r3, #8]
pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
8003f86: 68fb ldr r3, [r7, #12]
8003f88: 2200 movs r2, #0
8003f8a: 639a str r2, [r3, #56] @ 0x38
pxQueue->pcWriteTo = pxQueue->pcHead;
8003f8c: 68fb ldr r3, [r7, #12]
8003f8e: 681a ldr r2, [r3, #0]
8003f90: 68fb ldr r3, [r7, #12]
8003f92: 605a str r2, [r3, #4]
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
8003f94: 68fb ldr r3, [r7, #12]
8003f96: 681a ldr r2, [r3, #0]
8003f98: 68fb ldr r3, [r7, #12]
8003f9a: 6bdb ldr r3, [r3, #60] @ 0x3c
8003f9c: 3b01 subs r3, #1
8003f9e: 68f9 ldr r1, [r7, #12]
8003fa0: 6c09 ldr r1, [r1, #64] @ 0x40
8003fa2: fb01 f303 mul.w r3, r1, r3
8003fa6: 441a add r2, r3
8003fa8: 68fb ldr r3, [r7, #12]
8003faa: 60da str r2, [r3, #12]
pxQueue->cRxLock = queueUNLOCKED;
8003fac: 68fb ldr r3, [r7, #12]
8003fae: 22ff movs r2, #255 @ 0xff
8003fb0: f883 2044 strb.w r2, [r3, #68] @ 0x44
pxQueue->cTxLock = queueUNLOCKED;
8003fb4: 68fb ldr r3, [r7, #12]
8003fb6: 22ff movs r2, #255 @ 0xff
8003fb8: f883 2045 strb.w r2, [r3, #69] @ 0x45
if( xNewQueue == pdFALSE )
8003fbc: 683b ldr r3, [r7, #0]
8003fbe: 2b00 cmp r3, #0
8003fc0: d114 bne.n 8003fec <xQueueGenericReset+0xb0>
/* If there are tasks blocked waiting to read from the queue, then
the tasks will remain blocked as after this function exits the queue
will still be empty. If there are tasks blocked waiting to write to
the queue, then one should be unblocked as after this function exits
it will be possible to write to it. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
8003fc2: 68fb ldr r3, [r7, #12]
8003fc4: 691b ldr r3, [r3, #16]
8003fc6: 2b00 cmp r3, #0
8003fc8: d01a beq.n 8004000 <xQueueGenericReset+0xc4>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
8003fca: 68fb ldr r3, [r7, #12]
8003fcc: 3310 adds r3, #16
8003fce: 4618 mov r0, r3
8003fd0: f001 f950 bl 8005274 <xTaskRemoveFromEventList>
8003fd4: 4603 mov r3, r0
8003fd6: 2b00 cmp r3, #0
8003fd8: d012 beq.n 8004000 <xQueueGenericReset+0xc4>
{
queueYIELD_IF_USING_PREEMPTION();
8003fda: 4b0d ldr r3, [pc, #52] @ (8004010 <xQueueGenericReset+0xd4>)
8003fdc: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8003fe0: 601a str r2, [r3, #0]
8003fe2: f3bf 8f4f dsb sy
8003fe6: f3bf 8f6f isb sy
8003fea: e009 b.n 8004000 <xQueueGenericReset+0xc4>
}
}
else
{
/* Ensure the event queues start in the correct state. */
vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
8003fec: 68fb ldr r3, [r7, #12]
8003fee: 3310 adds r3, #16
8003ff0: 4618 mov r0, r3
8003ff2: f7ff feef bl 8003dd4 <vListInitialise>
vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
8003ff6: 68fb ldr r3, [r7, #12]
8003ff8: 3324 adds r3, #36 @ 0x24
8003ffa: 4618 mov r0, r3
8003ffc: f7ff feea bl 8003dd4 <vListInitialise>
}
}
taskEXIT_CRITICAL();
8004000: f002 f892 bl 8006128 <vPortExitCritical>
/* A value is returned for calling semantic consistency with previous
versions. */
return pdPASS;
8004004: 2301 movs r3, #1
}
8004006: 4618 mov r0, r3
8004008: 3710 adds r7, #16
800400a: 46bd mov sp, r7
800400c: bd80 pop {r7, pc}
800400e: bf00 nop
8004010: e000ed04 .word 0xe000ed04
08004014 <xQueueGenericCreateStatic>:
/*-----------------------------------------------------------*/
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
{
8004014: b580 push {r7, lr}
8004016: b08e sub sp, #56 @ 0x38
8004018: af02 add r7, sp, #8
800401a: 60f8 str r0, [r7, #12]
800401c: 60b9 str r1, [r7, #8]
800401e: 607a str r2, [r7, #4]
8004020: 603b str r3, [r7, #0]
Queue_t *pxNewQueue;
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
8004022: 68fb ldr r3, [r7, #12]
8004024: 2b00 cmp r3, #0
8004026: d10d bne.n 8004044 <xQueueGenericCreateStatic+0x30>
__asm volatile
8004028: f04f 0350 mov.w r3, #80 @ 0x50
800402c: b672 cpsid i
800402e: f383 8811 msr BASEPRI, r3
8004032: f3bf 8f6f isb sy
8004036: f3bf 8f4f dsb sy
800403a: b662 cpsie i
800403c: 62bb str r3, [r7, #40] @ 0x28
}
800403e: bf00 nop
8004040: bf00 nop
8004042: e7fd b.n 8004040 <xQueueGenericCreateStatic+0x2c>
/* The StaticQueue_t structure and the queue storage area must be
supplied. */
configASSERT( pxStaticQueue != NULL );
8004044: 683b ldr r3, [r7, #0]
8004046: 2b00 cmp r3, #0
8004048: d10d bne.n 8004066 <xQueueGenericCreateStatic+0x52>
__asm volatile
800404a: f04f 0350 mov.w r3, #80 @ 0x50
800404e: b672 cpsid i
8004050: f383 8811 msr BASEPRI, r3
8004054: f3bf 8f6f isb sy
8004058: f3bf 8f4f dsb sy
800405c: b662 cpsie i
800405e: 627b str r3, [r7, #36] @ 0x24
}
8004060: bf00 nop
8004062: bf00 nop
8004064: e7fd b.n 8004062 <xQueueGenericCreateStatic+0x4e>
/* A queue storage area should be provided if the item size is not 0, and
should not be provided if the item size is 0. */
configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
8004066: 687b ldr r3, [r7, #4]
8004068: 2b00 cmp r3, #0
800406a: d002 beq.n 8004072 <xQueueGenericCreateStatic+0x5e>
800406c: 68bb ldr r3, [r7, #8]
800406e: 2b00 cmp r3, #0
8004070: d001 beq.n 8004076 <xQueueGenericCreateStatic+0x62>
8004072: 2301 movs r3, #1
8004074: e000 b.n 8004078 <xQueueGenericCreateStatic+0x64>
8004076: 2300 movs r3, #0
8004078: 2b00 cmp r3, #0
800407a: d10d bne.n 8004098 <xQueueGenericCreateStatic+0x84>
__asm volatile
800407c: f04f 0350 mov.w r3, #80 @ 0x50
8004080: b672 cpsid i
8004082: f383 8811 msr BASEPRI, r3
8004086: f3bf 8f6f isb sy
800408a: f3bf 8f4f dsb sy
800408e: b662 cpsie i
8004090: 623b str r3, [r7, #32]
}
8004092: bf00 nop
8004094: bf00 nop
8004096: e7fd b.n 8004094 <xQueueGenericCreateStatic+0x80>
configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
8004098: 687b ldr r3, [r7, #4]
800409a: 2b00 cmp r3, #0
800409c: d102 bne.n 80040a4 <xQueueGenericCreateStatic+0x90>
800409e: 68bb ldr r3, [r7, #8]
80040a0: 2b00 cmp r3, #0
80040a2: d101 bne.n 80040a8 <xQueueGenericCreateStatic+0x94>
80040a4: 2301 movs r3, #1
80040a6: e000 b.n 80040aa <xQueueGenericCreateStatic+0x96>
80040a8: 2300 movs r3, #0
80040aa: 2b00 cmp r3, #0
80040ac: d10d bne.n 80040ca <xQueueGenericCreateStatic+0xb6>
__asm volatile
80040ae: f04f 0350 mov.w r3, #80 @ 0x50
80040b2: b672 cpsid i
80040b4: f383 8811 msr BASEPRI, r3
80040b8: f3bf 8f6f isb sy
80040bc: f3bf 8f4f dsb sy
80040c0: b662 cpsie i
80040c2: 61fb str r3, [r7, #28]
}
80040c4: bf00 nop
80040c6: bf00 nop
80040c8: e7fd b.n 80040c6 <xQueueGenericCreateStatic+0xb2>
#if( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
variable of type StaticQueue_t or StaticSemaphore_t equals the size of
the real queue and semaphore structures. */
volatile size_t xSize = sizeof( StaticQueue_t );
80040ca: 2350 movs r3, #80 @ 0x50
80040cc: 617b str r3, [r7, #20]
configASSERT( xSize == sizeof( Queue_t ) );
80040ce: 697b ldr r3, [r7, #20]
80040d0: 2b50 cmp r3, #80 @ 0x50
80040d2: d00d beq.n 80040f0 <xQueueGenericCreateStatic+0xdc>
__asm volatile
80040d4: f04f 0350 mov.w r3, #80 @ 0x50
80040d8: b672 cpsid i
80040da: f383 8811 msr BASEPRI, r3
80040de: f3bf 8f6f isb sy
80040e2: f3bf 8f4f dsb sy
80040e6: b662 cpsie i
80040e8: 61bb str r3, [r7, #24]
}
80040ea: bf00 nop
80040ec: bf00 nop
80040ee: e7fd b.n 80040ec <xQueueGenericCreateStatic+0xd8>
( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
80040f0: 697b ldr r3, [r7, #20]
#endif /* configASSERT_DEFINED */
/* The address of a statically allocated queue was passed in, use it.
The address of a statically allocated storage area was also passed in
but is already set. */
pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
80040f2: 683b ldr r3, [r7, #0]
80040f4: 62fb str r3, [r7, #44] @ 0x2c
if( pxNewQueue != NULL )
80040f6: 6afb ldr r3, [r7, #44] @ 0x2c
80040f8: 2b00 cmp r3, #0
80040fa: d00d beq.n 8004118 <xQueueGenericCreateStatic+0x104>
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
{
/* Queues can be allocated wither statically or dynamically, so
note this queue was allocated statically in case the queue is
later deleted. */
pxNewQueue->ucStaticallyAllocated = pdTRUE;
80040fc: 6afb ldr r3, [r7, #44] @ 0x2c
80040fe: 2201 movs r2, #1
8004100: f883 2046 strb.w r2, [r3, #70] @ 0x46
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
8004104: f897 2038 ldrb.w r2, [r7, #56] @ 0x38
8004108: 6afb ldr r3, [r7, #44] @ 0x2c
800410a: 9300 str r3, [sp, #0]
800410c: 4613 mov r3, r2
800410e: 687a ldr r2, [r7, #4]
8004110: 68b9 ldr r1, [r7, #8]
8004112: 68f8 ldr r0, [r7, #12]
8004114: f000 f805 bl 8004122 <prvInitialiseNewQueue>
{
traceQUEUE_CREATE_FAILED( ucQueueType );
mtCOVERAGE_TEST_MARKER();
}
return pxNewQueue;
8004118: 6afb ldr r3, [r7, #44] @ 0x2c
}
800411a: 4618 mov r0, r3
800411c: 3730 adds r7, #48 @ 0x30
800411e: 46bd mov sp, r7
8004120: bd80 pop {r7, pc}
08004122 <prvInitialiseNewQueue>:
#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
{
8004122: b580 push {r7, lr}
8004124: b084 sub sp, #16
8004126: af00 add r7, sp, #0
8004128: 60f8 str r0, [r7, #12]
800412a: 60b9 str r1, [r7, #8]
800412c: 607a str r2, [r7, #4]
800412e: 70fb strb r3, [r7, #3]
/* Remove compiler warnings about unused parameters should
configUSE_TRACE_FACILITY not be set to 1. */
( void ) ucQueueType;
if( uxItemSize == ( UBaseType_t ) 0 )
8004130: 68bb ldr r3, [r7, #8]
8004132: 2b00 cmp r3, #0
8004134: d103 bne.n 800413e <prvInitialiseNewQueue+0x1c>
{
/* No RAM was allocated for the queue storage area, but PC head cannot
be set to NULL because NULL is used as a key to say the queue is used as
a mutex. Therefore just set pcHead to point to the queue as a benign
value that is known to be within the memory map. */
pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
8004136: 69bb ldr r3, [r7, #24]
8004138: 69ba ldr r2, [r7, #24]
800413a: 601a str r2, [r3, #0]
800413c: e002 b.n 8004144 <prvInitialiseNewQueue+0x22>
}
else
{
/* Set the head to the start of the queue storage area. */
pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
800413e: 69bb ldr r3, [r7, #24]
8004140: 687a ldr r2, [r7, #4]
8004142: 601a str r2, [r3, #0]
}
/* Initialise the queue members as described where the queue type is
defined. */
pxNewQueue->uxLength = uxQueueLength;
8004144: 69bb ldr r3, [r7, #24]
8004146: 68fa ldr r2, [r7, #12]
8004148: 63da str r2, [r3, #60] @ 0x3c
pxNewQueue->uxItemSize = uxItemSize;
800414a: 69bb ldr r3, [r7, #24]
800414c: 68ba ldr r2, [r7, #8]
800414e: 641a str r2, [r3, #64] @ 0x40
( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
8004150: 2101 movs r1, #1
8004152: 69b8 ldr r0, [r7, #24]
8004154: f7ff fef2 bl 8003f3c <xQueueGenericReset>
#if ( configUSE_TRACE_FACILITY == 1 )
{
pxNewQueue->ucQueueType = ucQueueType;
8004158: 69bb ldr r3, [r7, #24]
800415a: 78fa ldrb r2, [r7, #3]
800415c: f883 204c strb.w r2, [r3, #76] @ 0x4c
pxNewQueue->pxQueueSetContainer = NULL;
}
#endif /* configUSE_QUEUE_SETS */
traceQUEUE_CREATE( pxNewQueue );
}
8004160: bf00 nop
8004162: 3710 adds r7, #16
8004164: 46bd mov sp, r7
8004166: bd80 pop {r7, pc}
08004168 <xQueueGenericSend>:
#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
{
8004168: b580 push {r7, lr}
800416a: b08e sub sp, #56 @ 0x38
800416c: af00 add r7, sp, #0
800416e: 60f8 str r0, [r7, #12]
8004170: 60b9 str r1, [r7, #8]
8004172: 607a str r2, [r7, #4]
8004174: 603b str r3, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
8004176: 2300 movs r3, #0
8004178: 637b str r3, [r7, #52] @ 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
800417a: 68fb ldr r3, [r7, #12]
800417c: 633b str r3, [r7, #48] @ 0x30
configASSERT( pxQueue );
800417e: 6b3b ldr r3, [r7, #48] @ 0x30
8004180: 2b00 cmp r3, #0
8004182: d10d bne.n 80041a0 <xQueueGenericSend+0x38>
__asm volatile
8004184: f04f 0350 mov.w r3, #80 @ 0x50
8004188: b672 cpsid i
800418a: f383 8811 msr BASEPRI, r3
800418e: f3bf 8f6f isb sy
8004192: f3bf 8f4f dsb sy
8004196: b662 cpsie i
8004198: 62bb str r3, [r7, #40] @ 0x28
}
800419a: bf00 nop
800419c: bf00 nop
800419e: e7fd b.n 800419c <xQueueGenericSend+0x34>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
80041a0: 68bb ldr r3, [r7, #8]
80041a2: 2b00 cmp r3, #0
80041a4: d103 bne.n 80041ae <xQueueGenericSend+0x46>
80041a6: 6b3b ldr r3, [r7, #48] @ 0x30
80041a8: 6c1b ldr r3, [r3, #64] @ 0x40
80041aa: 2b00 cmp r3, #0
80041ac: d101 bne.n 80041b2 <xQueueGenericSend+0x4a>
80041ae: 2301 movs r3, #1
80041b0: e000 b.n 80041b4 <xQueueGenericSend+0x4c>
80041b2: 2300 movs r3, #0
80041b4: 2b00 cmp r3, #0
80041b6: d10d bne.n 80041d4 <xQueueGenericSend+0x6c>
__asm volatile
80041b8: f04f 0350 mov.w r3, #80 @ 0x50
80041bc: b672 cpsid i
80041be: f383 8811 msr BASEPRI, r3
80041c2: f3bf 8f6f isb sy
80041c6: f3bf 8f4f dsb sy
80041ca: b662 cpsie i
80041cc: 627b str r3, [r7, #36] @ 0x24
}
80041ce: bf00 nop
80041d0: bf00 nop
80041d2: e7fd b.n 80041d0 <xQueueGenericSend+0x68>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
80041d4: 683b ldr r3, [r7, #0]
80041d6: 2b02 cmp r3, #2
80041d8: d103 bne.n 80041e2 <xQueueGenericSend+0x7a>
80041da: 6b3b ldr r3, [r7, #48] @ 0x30
80041dc: 6bdb ldr r3, [r3, #60] @ 0x3c
80041de: 2b01 cmp r3, #1
80041e0: d101 bne.n 80041e6 <xQueueGenericSend+0x7e>
80041e2: 2301 movs r3, #1
80041e4: e000 b.n 80041e8 <xQueueGenericSend+0x80>
80041e6: 2300 movs r3, #0
80041e8: 2b00 cmp r3, #0
80041ea: d10d bne.n 8004208 <xQueueGenericSend+0xa0>
__asm volatile
80041ec: f04f 0350 mov.w r3, #80 @ 0x50
80041f0: b672 cpsid i
80041f2: f383 8811 msr BASEPRI, r3
80041f6: f3bf 8f6f isb sy
80041fa: f3bf 8f4f dsb sy
80041fe: b662 cpsie i
8004200: 623b str r3, [r7, #32]
}
8004202: bf00 nop
8004204: bf00 nop
8004206: e7fd b.n 8004204 <xQueueGenericSend+0x9c>
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
8004208: f001 f9fc bl 8005604 <xTaskGetSchedulerState>
800420c: 4603 mov r3, r0
800420e: 2b00 cmp r3, #0
8004210: d102 bne.n 8004218 <xQueueGenericSend+0xb0>
8004212: 687b ldr r3, [r7, #4]
8004214: 2b00 cmp r3, #0
8004216: d101 bne.n 800421c <xQueueGenericSend+0xb4>
8004218: 2301 movs r3, #1
800421a: e000 b.n 800421e <xQueueGenericSend+0xb6>
800421c: 2300 movs r3, #0
800421e: 2b00 cmp r3, #0
8004220: d10d bne.n 800423e <xQueueGenericSend+0xd6>
__asm volatile
8004222: f04f 0350 mov.w r3, #80 @ 0x50
8004226: b672 cpsid i
8004228: f383 8811 msr BASEPRI, r3
800422c: f3bf 8f6f isb sy
8004230: f3bf 8f4f dsb sy
8004234: b662 cpsie i
8004236: 61fb str r3, [r7, #28]
}
8004238: bf00 nop
800423a: bf00 nop
800423c: e7fd b.n 800423a <xQueueGenericSend+0xd2>
/*lint -save -e904 This function relaxes the coding standard somewhat to
allow return statements within the function itself. This is done in the
interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
800423e: f001 ff3d bl 80060bc <vPortEnterCritical>
{
/* Is there room on the queue now? The running task must be the
highest priority task wanting to access the queue. If the head item
in the queue is to be overwritten then it does not matter if the
queue is full. */
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
8004242: 6b3b ldr r3, [r7, #48] @ 0x30
8004244: 6b9a ldr r2, [r3, #56] @ 0x38
8004246: 6b3b ldr r3, [r7, #48] @ 0x30
8004248: 6bdb ldr r3, [r3, #60] @ 0x3c
800424a: 429a cmp r2, r3
800424c: d302 bcc.n 8004254 <xQueueGenericSend+0xec>
800424e: 683b ldr r3, [r7, #0]
8004250: 2b02 cmp r3, #2
8004252: d129 bne.n 80042a8 <xQueueGenericSend+0x140>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
8004254: 683a ldr r2, [r7, #0]
8004256: 68b9 ldr r1, [r7, #8]
8004258: 6b38 ldr r0, [r7, #48] @ 0x30
800425a: f000 fa1b bl 8004694 <prvCopyDataToQueue>
800425e: 62f8 str r0, [r7, #44] @ 0x2c
/* If there was a task waiting for data to arrive on the
queue then unblock it now. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
8004260: 6b3b ldr r3, [r7, #48] @ 0x30
8004262: 6a5b ldr r3, [r3, #36] @ 0x24
8004264: 2b00 cmp r3, #0
8004266: d010 beq.n 800428a <xQueueGenericSend+0x122>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
8004268: 6b3b ldr r3, [r7, #48] @ 0x30
800426a: 3324 adds r3, #36 @ 0x24
800426c: 4618 mov r0, r3
800426e: f001 f801 bl 8005274 <xTaskRemoveFromEventList>
8004272: 4603 mov r3, r0
8004274: 2b00 cmp r3, #0
8004276: d013 beq.n 80042a0 <xQueueGenericSend+0x138>
{
/* The unblocked task has a priority higher than
our own so yield immediately. Yes it is ok to do
this from within the critical section - the kernel
takes care of that. */
queueYIELD_IF_USING_PREEMPTION();
8004278: 4b3f ldr r3, [pc, #252] @ (8004378 <xQueueGenericSend+0x210>)
800427a: f04f 5280 mov.w r2, #268435456 @ 0x10000000
800427e: 601a str r2, [r3, #0]
8004280: f3bf 8f4f dsb sy
8004284: f3bf 8f6f isb sy
8004288: e00a b.n 80042a0 <xQueueGenericSend+0x138>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else if( xYieldRequired != pdFALSE )
800428a: 6afb ldr r3, [r7, #44] @ 0x2c
800428c: 2b00 cmp r3, #0
800428e: d007 beq.n 80042a0 <xQueueGenericSend+0x138>
{
/* This path is a special case that will only get
executed if the task was holding multiple mutexes and
the mutexes were given back in an order that is
different to that in which they were taken. */
queueYIELD_IF_USING_PREEMPTION();
8004290: 4b39 ldr r3, [pc, #228] @ (8004378 <xQueueGenericSend+0x210>)
8004292: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8004296: 601a str r2, [r3, #0]
8004298: f3bf 8f4f dsb sy
800429c: f3bf 8f6f isb sy
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_QUEUE_SETS */
taskEXIT_CRITICAL();
80042a0: f001 ff42 bl 8006128 <vPortExitCritical>
return pdPASS;
80042a4: 2301 movs r3, #1
80042a6: e063 b.n 8004370 <xQueueGenericSend+0x208>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
80042a8: 687b ldr r3, [r7, #4]
80042aa: 2b00 cmp r3, #0
80042ac: d103 bne.n 80042b6 <xQueueGenericSend+0x14e>
{
/* The queue was full and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
80042ae: f001 ff3b bl 8006128 <vPortExitCritical>
/* Return to the original privilege level before exiting
the function. */
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
80042b2: 2300 movs r3, #0
80042b4: e05c b.n 8004370 <xQueueGenericSend+0x208>
}
else if( xEntryTimeSet == pdFALSE )
80042b6: 6b7b ldr r3, [r7, #52] @ 0x34
80042b8: 2b00 cmp r3, #0
80042ba: d106 bne.n 80042ca <xQueueGenericSend+0x162>
{
/* The queue was full and a block time was specified so
configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
80042bc: f107 0314 add.w r3, r7, #20
80042c0: 4618 mov r0, r3
80042c2: f001 f83d bl 8005340 <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
80042c6: 2301 movs r3, #1
80042c8: 637b str r3, [r7, #52] @ 0x34
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
80042ca: f001 ff2d bl 8006128 <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
80042ce: f000 fda1 bl 8004e14 <vTaskSuspendAll>
prvLockQueue( pxQueue );
80042d2: f001 fef3 bl 80060bc <vPortEnterCritical>
80042d6: 6b3b ldr r3, [r7, #48] @ 0x30
80042d8: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
80042dc: b25b sxtb r3, r3
80042de: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80042e2: d103 bne.n 80042ec <xQueueGenericSend+0x184>
80042e4: 6b3b ldr r3, [r7, #48] @ 0x30
80042e6: 2200 movs r2, #0
80042e8: f883 2044 strb.w r2, [r3, #68] @ 0x44
80042ec: 6b3b ldr r3, [r7, #48] @ 0x30
80042ee: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
80042f2: b25b sxtb r3, r3
80042f4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80042f8: d103 bne.n 8004302 <xQueueGenericSend+0x19a>
80042fa: 6b3b ldr r3, [r7, #48] @ 0x30
80042fc: 2200 movs r2, #0
80042fe: f883 2045 strb.w r2, [r3, #69] @ 0x45
8004302: f001 ff11 bl 8006128 <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
8004306: 1d3a adds r2, r7, #4
8004308: f107 0314 add.w r3, r7, #20
800430c: 4611 mov r1, r2
800430e: 4618 mov r0, r3
8004310: f001 f82c bl 800536c <xTaskCheckForTimeOut>
8004314: 4603 mov r3, r0
8004316: 2b00 cmp r3, #0
8004318: d124 bne.n 8004364 <xQueueGenericSend+0x1fc>
{
if( prvIsQueueFull( pxQueue ) != pdFALSE )
800431a: 6b38 ldr r0, [r7, #48] @ 0x30
800431c: f000 fab2 bl 8004884 <prvIsQueueFull>
8004320: 4603 mov r3, r0
8004322: 2b00 cmp r3, #0
8004324: d018 beq.n 8004358 <xQueueGenericSend+0x1f0>
{
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
8004326: 6b3b ldr r3, [r7, #48] @ 0x30
8004328: 3310 adds r3, #16
800432a: 687a ldr r2, [r7, #4]
800432c: 4611 mov r1, r2
800432e: 4618 mov r0, r3
8004330: f000 ff4a bl 80051c8 <vTaskPlaceOnEventList>
/* Unlocking the queue means queue events can effect the
event list. It is possible that interrupts occurring now
remove this task from the event list again - but as the
scheduler is suspended the task will go onto the pending
ready last instead of the actual ready list. */
prvUnlockQueue( pxQueue );
8004334: 6b38 ldr r0, [r7, #48] @ 0x30
8004336: f000 fa3d bl 80047b4 <prvUnlockQueue>
/* Resuming the scheduler will move tasks from the pending
ready list into the ready list - so it is feasible that this
task is already in a ready list before it yields - in which
case the yield will not cause a context switch unless there
is also a higher priority task in the pending ready list. */
if( xTaskResumeAll() == pdFALSE )
800433a: f000 fd79 bl 8004e30 <xTaskResumeAll>
800433e: 4603 mov r3, r0
8004340: 2b00 cmp r3, #0
8004342: f47f af7c bne.w 800423e <xQueueGenericSend+0xd6>
{
portYIELD_WITHIN_API();
8004346: 4b0c ldr r3, [pc, #48] @ (8004378 <xQueueGenericSend+0x210>)
8004348: f04f 5280 mov.w r2, #268435456 @ 0x10000000
800434c: 601a str r2, [r3, #0]
800434e: f3bf 8f4f dsb sy
8004352: f3bf 8f6f isb sy
8004356: e772 b.n 800423e <xQueueGenericSend+0xd6>
}
}
else
{
/* Try again. */
prvUnlockQueue( pxQueue );
8004358: 6b38 ldr r0, [r7, #48] @ 0x30
800435a: f000 fa2b bl 80047b4 <prvUnlockQueue>
( void ) xTaskResumeAll();
800435e: f000 fd67 bl 8004e30 <xTaskResumeAll>
8004362: e76c b.n 800423e <xQueueGenericSend+0xd6>
}
}
else
{
/* The timeout has expired. */
prvUnlockQueue( pxQueue );
8004364: 6b38 ldr r0, [r7, #48] @ 0x30
8004366: f000 fa25 bl 80047b4 <prvUnlockQueue>
( void ) xTaskResumeAll();
800436a: f000 fd61 bl 8004e30 <xTaskResumeAll>
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
800436e: 2300 movs r3, #0
}
} /*lint -restore */
}
8004370: 4618 mov r0, r3
8004372: 3738 adds r7, #56 @ 0x38
8004374: 46bd mov sp, r7
8004376: bd80 pop {r7, pc}
8004378: e000ed04 .word 0xe000ed04
0800437c <xQueueGenericSendFromISR>:
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
{
800437c: b580 push {r7, lr}
800437e: b08e sub sp, #56 @ 0x38
8004380: af00 add r7, sp, #0
8004382: 60f8 str r0, [r7, #12]
8004384: 60b9 str r1, [r7, #8]
8004386: 607a str r2, [r7, #4]
8004388: 603b str r3, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
800438a: 68fb ldr r3, [r7, #12]
800438c: 633b str r3, [r7, #48] @ 0x30
configASSERT( pxQueue );
800438e: 6b3b ldr r3, [r7, #48] @ 0x30
8004390: 2b00 cmp r3, #0
8004392: d10d bne.n 80043b0 <xQueueGenericSendFromISR+0x34>
__asm volatile
8004394: f04f 0350 mov.w r3, #80 @ 0x50
8004398: b672 cpsid i
800439a: f383 8811 msr BASEPRI, r3
800439e: f3bf 8f6f isb sy
80043a2: f3bf 8f4f dsb sy
80043a6: b662 cpsie i
80043a8: 627b str r3, [r7, #36] @ 0x24
}
80043aa: bf00 nop
80043ac: bf00 nop
80043ae: e7fd b.n 80043ac <xQueueGenericSendFromISR+0x30>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
80043b0: 68bb ldr r3, [r7, #8]
80043b2: 2b00 cmp r3, #0
80043b4: d103 bne.n 80043be <xQueueGenericSendFromISR+0x42>
80043b6: 6b3b ldr r3, [r7, #48] @ 0x30
80043b8: 6c1b ldr r3, [r3, #64] @ 0x40
80043ba: 2b00 cmp r3, #0
80043bc: d101 bne.n 80043c2 <xQueueGenericSendFromISR+0x46>
80043be: 2301 movs r3, #1
80043c0: e000 b.n 80043c4 <xQueueGenericSendFromISR+0x48>
80043c2: 2300 movs r3, #0
80043c4: 2b00 cmp r3, #0
80043c6: d10d bne.n 80043e4 <xQueueGenericSendFromISR+0x68>
__asm volatile
80043c8: f04f 0350 mov.w r3, #80 @ 0x50
80043cc: b672 cpsid i
80043ce: f383 8811 msr BASEPRI, r3
80043d2: f3bf 8f6f isb sy
80043d6: f3bf 8f4f dsb sy
80043da: b662 cpsie i
80043dc: 623b str r3, [r7, #32]
}
80043de: bf00 nop
80043e0: bf00 nop
80043e2: e7fd b.n 80043e0 <xQueueGenericSendFromISR+0x64>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
80043e4: 683b ldr r3, [r7, #0]
80043e6: 2b02 cmp r3, #2
80043e8: d103 bne.n 80043f2 <xQueueGenericSendFromISR+0x76>
80043ea: 6b3b ldr r3, [r7, #48] @ 0x30
80043ec: 6bdb ldr r3, [r3, #60] @ 0x3c
80043ee: 2b01 cmp r3, #1
80043f0: d101 bne.n 80043f6 <xQueueGenericSendFromISR+0x7a>
80043f2: 2301 movs r3, #1
80043f4: e000 b.n 80043f8 <xQueueGenericSendFromISR+0x7c>
80043f6: 2300 movs r3, #0
80043f8: 2b00 cmp r3, #0
80043fa: d10d bne.n 8004418 <xQueueGenericSendFromISR+0x9c>
__asm volatile
80043fc: f04f 0350 mov.w r3, #80 @ 0x50
8004400: b672 cpsid i
8004402: f383 8811 msr BASEPRI, r3
8004406: f3bf 8f6f isb sy
800440a: f3bf 8f4f dsb sy
800440e: b662 cpsie i
8004410: 61fb str r3, [r7, #28]
}
8004412: bf00 nop
8004414: bf00 nop
8004416: e7fd b.n 8004414 <xQueueGenericSendFromISR+0x98>
that have been assigned a priority at or (logically) below the maximum
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
8004418: f001 ff38 bl 800628c <vPortValidateInterruptPriority>
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
__asm volatile
800441c: f3ef 8211 mrs r2, BASEPRI
8004420: f04f 0350 mov.w r3, #80 @ 0x50
8004424: b672 cpsid i
8004426: f383 8811 msr BASEPRI, r3
800442a: f3bf 8f6f isb sy
800442e: f3bf 8f4f dsb sy
8004432: b662 cpsie i
8004434: 61ba str r2, [r7, #24]
8004436: 617b str r3, [r7, #20]
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
/* This return will not be reached but is necessary to prevent compiler
warnings. */
return ulOriginalBASEPRI;
8004438: 69bb ldr r3, [r7, #24]
/* Similar to xQueueGenericSend, except without blocking if there is no room
in the queue. Also don't directly wake a task that was blocked on a queue
read, instead return a flag to say whether a context switch is required or
not (i.e. has a task with a higher priority than us been woken by this
post). */
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
800443a: 62fb str r3, [r7, #44] @ 0x2c
{
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
800443c: 6b3b ldr r3, [r7, #48] @ 0x30
800443e: 6b9a ldr r2, [r3, #56] @ 0x38
8004440: 6b3b ldr r3, [r7, #48] @ 0x30
8004442: 6bdb ldr r3, [r3, #60] @ 0x3c
8004444: 429a cmp r2, r3
8004446: d302 bcc.n 800444e <xQueueGenericSendFromISR+0xd2>
8004448: 683b ldr r3, [r7, #0]
800444a: 2b02 cmp r3, #2
800444c: d12c bne.n 80044a8 <xQueueGenericSendFromISR+0x12c>
{
const int8_t cTxLock = pxQueue->cTxLock;
800444e: 6b3b ldr r3, [r7, #48] @ 0x30
8004450: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
8004454: f887 302b strb.w r3, [r7, #43] @ 0x2b
/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
semaphore or mutex. That means prvCopyDataToQueue() cannot result
in a task disinheriting a priority and prvCopyDataToQueue() can be
called here even though the disinherit function does not check if
the scheduler is suspended before accessing the ready lists. */
( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
8004458: 683a ldr r2, [r7, #0]
800445a: 68b9 ldr r1, [r7, #8]
800445c: 6b38 ldr r0, [r7, #48] @ 0x30
800445e: f000 f919 bl 8004694 <prvCopyDataToQueue>
/* The event list is not altered if the queue is locked. This will
be done when the queue is unlocked later. */
if( cTxLock == queueUNLOCKED )
8004462: f997 302b ldrsb.w r3, [r7, #43] @ 0x2b
8004466: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
800446a: d112 bne.n 8004492 <xQueueGenericSendFromISR+0x116>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800446c: 6b3b ldr r3, [r7, #48] @ 0x30
800446e: 6a5b ldr r3, [r3, #36] @ 0x24
8004470: 2b00 cmp r3, #0
8004472: d016 beq.n 80044a2 <xQueueGenericSendFromISR+0x126>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
8004474: 6b3b ldr r3, [r7, #48] @ 0x30
8004476: 3324 adds r3, #36 @ 0x24
8004478: 4618 mov r0, r3
800447a: f000 fefb bl 8005274 <xTaskRemoveFromEventList>
800447e: 4603 mov r3, r0
8004480: 2b00 cmp r3, #0
8004482: d00e beq.n 80044a2 <xQueueGenericSendFromISR+0x126>
{
/* The task waiting has a higher priority so record that a
context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
8004484: 687b ldr r3, [r7, #4]
8004486: 2b00 cmp r3, #0
8004488: d00b beq.n 80044a2 <xQueueGenericSendFromISR+0x126>
{
*pxHigherPriorityTaskWoken = pdTRUE;
800448a: 687b ldr r3, [r7, #4]
800448c: 2201 movs r2, #1
800448e: 601a str r2, [r3, #0]
8004490: e007 b.n 80044a2 <xQueueGenericSendFromISR+0x126>
}
else
{
/* Increment the lock count so the task that unlocks the queue
knows that data was posted while it was locked. */
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
8004492: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
8004496: 3301 adds r3, #1
8004498: b2db uxtb r3, r3
800449a: b25a sxtb r2, r3
800449c: 6b3b ldr r3, [r7, #48] @ 0x30
800449e: f883 2045 strb.w r2, [r3, #69] @ 0x45
}
xReturn = pdPASS;
80044a2: 2301 movs r3, #1
80044a4: 637b str r3, [r7, #52] @ 0x34
{
80044a6: e001 b.n 80044ac <xQueueGenericSendFromISR+0x130>
}
else
{
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
xReturn = errQUEUE_FULL;
80044a8: 2300 movs r3, #0
80044aa: 637b str r3, [r7, #52] @ 0x34
80044ac: 6afb ldr r3, [r7, #44] @ 0x2c
80044ae: 613b str r3, [r7, #16]
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
__asm volatile
80044b0: 693b ldr r3, [r7, #16]
80044b2: f383 8811 msr BASEPRI, r3
(
" msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"
);
}
80044b6: bf00 nop
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
80044b8: 6b7b ldr r3, [r7, #52] @ 0x34
}
80044ba: 4618 mov r0, r3
80044bc: 3738 adds r7, #56 @ 0x38
80044be: 46bd mov sp, r7
80044c0: bd80 pop {r7, pc}
...
080044c4 <xQueueReceive>:
return xReturn;
}
/*-----------------------------------------------------------*/
BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
{
80044c4: b580 push {r7, lr}
80044c6: b08c sub sp, #48 @ 0x30
80044c8: af00 add r7, sp, #0
80044ca: 60f8 str r0, [r7, #12]
80044cc: 60b9 str r1, [r7, #8]
80044ce: 607a str r2, [r7, #4]
BaseType_t xEntryTimeSet = pdFALSE;
80044d0: 2300 movs r3, #0
80044d2: 62fb str r3, [r7, #44] @ 0x2c
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
80044d4: 68fb ldr r3, [r7, #12]
80044d6: 62bb str r3, [r7, #40] @ 0x28
/* Check the pointer is not NULL. */
configASSERT( ( pxQueue ) );
80044d8: 6abb ldr r3, [r7, #40] @ 0x28
80044da: 2b00 cmp r3, #0
80044dc: d10d bne.n 80044fa <xQueueReceive+0x36>
__asm volatile
80044de: f04f 0350 mov.w r3, #80 @ 0x50
80044e2: b672 cpsid i
80044e4: f383 8811 msr BASEPRI, r3
80044e8: f3bf 8f6f isb sy
80044ec: f3bf 8f4f dsb sy
80044f0: b662 cpsie i
80044f2: 623b str r3, [r7, #32]
}
80044f4: bf00 nop
80044f6: bf00 nop
80044f8: e7fd b.n 80044f6 <xQueueReceive+0x32>
/* The buffer into which data is received can only be NULL if the data size
is zero (so no data is copied into the buffer. */
configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
80044fa: 68bb ldr r3, [r7, #8]
80044fc: 2b00 cmp r3, #0
80044fe: d103 bne.n 8004508 <xQueueReceive+0x44>
8004500: 6abb ldr r3, [r7, #40] @ 0x28
8004502: 6c1b ldr r3, [r3, #64] @ 0x40
8004504: 2b00 cmp r3, #0
8004506: d101 bne.n 800450c <xQueueReceive+0x48>
8004508: 2301 movs r3, #1
800450a: e000 b.n 800450e <xQueueReceive+0x4a>
800450c: 2300 movs r3, #0
800450e: 2b00 cmp r3, #0
8004510: d10d bne.n 800452e <xQueueReceive+0x6a>
__asm volatile
8004512: f04f 0350 mov.w r3, #80 @ 0x50
8004516: b672 cpsid i
8004518: f383 8811 msr BASEPRI, r3
800451c: f3bf 8f6f isb sy
8004520: f3bf 8f4f dsb sy
8004524: b662 cpsie i
8004526: 61fb str r3, [r7, #28]
}
8004528: bf00 nop
800452a: bf00 nop
800452c: e7fd b.n 800452a <xQueueReceive+0x66>
/* Cannot block if the scheduler is suspended. */
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
800452e: f001 f869 bl 8005604 <xTaskGetSchedulerState>
8004532: 4603 mov r3, r0
8004534: 2b00 cmp r3, #0
8004536: d102 bne.n 800453e <xQueueReceive+0x7a>
8004538: 687b ldr r3, [r7, #4]
800453a: 2b00 cmp r3, #0
800453c: d101 bne.n 8004542 <xQueueReceive+0x7e>
800453e: 2301 movs r3, #1
8004540: e000 b.n 8004544 <xQueueReceive+0x80>
8004542: 2300 movs r3, #0
8004544: 2b00 cmp r3, #0
8004546: d10d bne.n 8004564 <xQueueReceive+0xa0>
__asm volatile
8004548: f04f 0350 mov.w r3, #80 @ 0x50
800454c: b672 cpsid i
800454e: f383 8811 msr BASEPRI, r3
8004552: f3bf 8f6f isb sy
8004556: f3bf 8f4f dsb sy
800455a: b662 cpsie i
800455c: 61bb str r3, [r7, #24]
}
800455e: bf00 nop
8004560: bf00 nop
8004562: e7fd b.n 8004560 <xQueueReceive+0x9c>
/*lint -save -e904 This function relaxes the coding standard somewhat to
allow return statements within the function itself. This is done in the
interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
8004564: f001 fdaa bl 80060bc <vPortEnterCritical>
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
8004568: 6abb ldr r3, [r7, #40] @ 0x28
800456a: 6b9b ldr r3, [r3, #56] @ 0x38
800456c: 627b str r3, [r7, #36] @ 0x24
/* Is there data in the queue now? To be running the calling task
must be the highest priority task wanting to access the queue. */
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
800456e: 6a7b ldr r3, [r7, #36] @ 0x24
8004570: 2b00 cmp r3, #0
8004572: d01f beq.n 80045b4 <xQueueReceive+0xf0>
{
/* Data available, remove one item. */
prvCopyDataFromQueue( pxQueue, pvBuffer );
8004574: 68b9 ldr r1, [r7, #8]
8004576: 6ab8 ldr r0, [r7, #40] @ 0x28
8004578: f000 f8f6 bl 8004768 <prvCopyDataFromQueue>
traceQUEUE_RECEIVE( pxQueue );
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
800457c: 6a7b ldr r3, [r7, #36] @ 0x24
800457e: 1e5a subs r2, r3, #1
8004580: 6abb ldr r3, [r7, #40] @ 0x28
8004582: 639a str r2, [r3, #56] @ 0x38
/* There is now space in the queue, were any tasks waiting to
post to the queue? If so, unblock the highest priority waiting
task. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
8004584: 6abb ldr r3, [r7, #40] @ 0x28
8004586: 691b ldr r3, [r3, #16]
8004588: 2b00 cmp r3, #0
800458a: d00f beq.n 80045ac <xQueueReceive+0xe8>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800458c: 6abb ldr r3, [r7, #40] @ 0x28
800458e: 3310 adds r3, #16
8004590: 4618 mov r0, r3
8004592: f000 fe6f bl 8005274 <xTaskRemoveFromEventList>
8004596: 4603 mov r3, r0
8004598: 2b00 cmp r3, #0
800459a: d007 beq.n 80045ac <xQueueReceive+0xe8>
{
queueYIELD_IF_USING_PREEMPTION();
800459c: 4b3c ldr r3, [pc, #240] @ (8004690 <xQueueReceive+0x1cc>)
800459e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
80045a2: 601a str r2, [r3, #0]
80045a4: f3bf 8f4f dsb sy
80045a8: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
taskEXIT_CRITICAL();
80045ac: f001 fdbc bl 8006128 <vPortExitCritical>
return pdPASS;
80045b0: 2301 movs r3, #1
80045b2: e069 b.n 8004688 <xQueueReceive+0x1c4>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
80045b4: 687b ldr r3, [r7, #4]
80045b6: 2b00 cmp r3, #0
80045b8: d103 bne.n 80045c2 <xQueueReceive+0xfe>
{
/* The queue was empty and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
80045ba: f001 fdb5 bl 8006128 <vPortExitCritical>
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
80045be: 2300 movs r3, #0
80045c0: e062 b.n 8004688 <xQueueReceive+0x1c4>
}
else if( xEntryTimeSet == pdFALSE )
80045c2: 6afb ldr r3, [r7, #44] @ 0x2c
80045c4: 2b00 cmp r3, #0
80045c6: d106 bne.n 80045d6 <xQueueReceive+0x112>
{
/* The queue was empty and a block time was specified so
configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
80045c8: f107 0310 add.w r3, r7, #16
80045cc: 4618 mov r0, r3
80045ce: f000 feb7 bl 8005340 <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
80045d2: 2301 movs r3, #1
80045d4: 62fb str r3, [r7, #44] @ 0x2c
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
80045d6: f001 fda7 bl 8006128 <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
80045da: f000 fc1b bl 8004e14 <vTaskSuspendAll>
prvLockQueue( pxQueue );
80045de: f001 fd6d bl 80060bc <vPortEnterCritical>
80045e2: 6abb ldr r3, [r7, #40] @ 0x28
80045e4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
80045e8: b25b sxtb r3, r3
80045ea: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80045ee: d103 bne.n 80045f8 <xQueueReceive+0x134>
80045f0: 6abb ldr r3, [r7, #40] @ 0x28
80045f2: 2200 movs r2, #0
80045f4: f883 2044 strb.w r2, [r3, #68] @ 0x44
80045f8: 6abb ldr r3, [r7, #40] @ 0x28
80045fa: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
80045fe: b25b sxtb r3, r3
8004600: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8004604: d103 bne.n 800460e <xQueueReceive+0x14a>
8004606: 6abb ldr r3, [r7, #40] @ 0x28
8004608: 2200 movs r2, #0
800460a: f883 2045 strb.w r2, [r3, #69] @ 0x45
800460e: f001 fd8b bl 8006128 <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
8004612: 1d3a adds r2, r7, #4
8004614: f107 0310 add.w r3, r7, #16
8004618: 4611 mov r1, r2
800461a: 4618 mov r0, r3
800461c: f000 fea6 bl 800536c <xTaskCheckForTimeOut>
8004620: 4603 mov r3, r0
8004622: 2b00 cmp r3, #0
8004624: d123 bne.n 800466e <xQueueReceive+0x1aa>
{
/* The timeout has not expired. If the queue is still empty place
the task on the list of tasks waiting to receive from the queue. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
8004626: 6ab8 ldr r0, [r7, #40] @ 0x28
8004628: f000 f916 bl 8004858 <prvIsQueueEmpty>
800462c: 4603 mov r3, r0
800462e: 2b00 cmp r3, #0
8004630: d017 beq.n 8004662 <xQueueReceive+0x19e>
{
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
8004632: 6abb ldr r3, [r7, #40] @ 0x28
8004634: 3324 adds r3, #36 @ 0x24
8004636: 687a ldr r2, [r7, #4]
8004638: 4611 mov r1, r2
800463a: 4618 mov r0, r3
800463c: f000 fdc4 bl 80051c8 <vTaskPlaceOnEventList>
prvUnlockQueue( pxQueue );
8004640: 6ab8 ldr r0, [r7, #40] @ 0x28
8004642: f000 f8b7 bl 80047b4 <prvUnlockQueue>
if( xTaskResumeAll() == pdFALSE )
8004646: f000 fbf3 bl 8004e30 <xTaskResumeAll>
800464a: 4603 mov r3, r0
800464c: 2b00 cmp r3, #0
800464e: d189 bne.n 8004564 <xQueueReceive+0xa0>
{
portYIELD_WITHIN_API();
8004650: 4b0f ldr r3, [pc, #60] @ (8004690 <xQueueReceive+0x1cc>)
8004652: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8004656: 601a str r2, [r3, #0]
8004658: f3bf 8f4f dsb sy
800465c: f3bf 8f6f isb sy
8004660: e780 b.n 8004564 <xQueueReceive+0xa0>
}
else
{
/* The queue contains data again. Loop back to try and read the
data. */
prvUnlockQueue( pxQueue );
8004662: 6ab8 ldr r0, [r7, #40] @ 0x28
8004664: f000 f8a6 bl 80047b4 <prvUnlockQueue>
( void ) xTaskResumeAll();
8004668: f000 fbe2 bl 8004e30 <xTaskResumeAll>
800466c: e77a b.n 8004564 <xQueueReceive+0xa0>
}
else
{
/* Timed out. If there is no data in the queue exit, otherwise loop
back and attempt to read the data. */
prvUnlockQueue( pxQueue );
800466e: 6ab8 ldr r0, [r7, #40] @ 0x28
8004670: f000 f8a0 bl 80047b4 <prvUnlockQueue>
( void ) xTaskResumeAll();
8004674: f000 fbdc bl 8004e30 <xTaskResumeAll>
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
8004678: 6ab8 ldr r0, [r7, #40] @ 0x28
800467a: f000 f8ed bl 8004858 <prvIsQueueEmpty>
800467e: 4603 mov r3, r0
8004680: 2b00 cmp r3, #0
8004682: f43f af6f beq.w 8004564 <xQueueReceive+0xa0>
{
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
8004686: 2300 movs r3, #0
{
mtCOVERAGE_TEST_MARKER();
}
}
} /*lint -restore */
}
8004688: 4618 mov r0, r3
800468a: 3730 adds r7, #48 @ 0x30
800468c: 46bd mov sp, r7
800468e: bd80 pop {r7, pc}
8004690: e000ed04 .word 0xe000ed04
08004694 <prvCopyDataToQueue>:
#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/
static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
{
8004694: b580 push {r7, lr}
8004696: b086 sub sp, #24
8004698: af00 add r7, sp, #0
800469a: 60f8 str r0, [r7, #12]
800469c: 60b9 str r1, [r7, #8]
800469e: 607a str r2, [r7, #4]
BaseType_t xReturn = pdFALSE;
80046a0: 2300 movs r3, #0
80046a2: 617b str r3, [r7, #20]
UBaseType_t uxMessagesWaiting;
/* This function is called from a critical section. */
uxMessagesWaiting = pxQueue->uxMessagesWaiting;
80046a4: 68fb ldr r3, [r7, #12]
80046a6: 6b9b ldr r3, [r3, #56] @ 0x38
80046a8: 613b str r3, [r7, #16]
if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
80046aa: 68fb ldr r3, [r7, #12]
80046ac: 6c1b ldr r3, [r3, #64] @ 0x40
80046ae: 2b00 cmp r3, #0
80046b0: d10d bne.n 80046ce <prvCopyDataToQueue+0x3a>
{
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
80046b2: 68fb ldr r3, [r7, #12]
80046b4: 681b ldr r3, [r3, #0]
80046b6: 2b00 cmp r3, #0
80046b8: d14d bne.n 8004756 <prvCopyDataToQueue+0xc2>
{
/* The mutex is no longer being held. */
xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
80046ba: 68fb ldr r3, [r7, #12]
80046bc: 689b ldr r3, [r3, #8]
80046be: 4618 mov r0, r3
80046c0: f000 ffbe bl 8005640 <xTaskPriorityDisinherit>
80046c4: 6178 str r0, [r7, #20]
pxQueue->u.xSemaphore.xMutexHolder = NULL;
80046c6: 68fb ldr r3, [r7, #12]
80046c8: 2200 movs r2, #0
80046ca: 609a str r2, [r3, #8]
80046cc: e043 b.n 8004756 <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_MUTEXES */
}
else if( xPosition == queueSEND_TO_BACK )
80046ce: 687b ldr r3, [r7, #4]
80046d0: 2b00 cmp r3, #0
80046d2: d119 bne.n 8004708 <prvCopyDataToQueue+0x74>
{
( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
80046d4: 68fb ldr r3, [r7, #12]
80046d6: 6858 ldr r0, [r3, #4]
80046d8: 68fb ldr r3, [r7, #12]
80046da: 6c1b ldr r3, [r3, #64] @ 0x40
80046dc: 461a mov r2, r3
80046de: 68b9 ldr r1, [r7, #8]
80046e0: f002 f997 bl 8006a12 <memcpy>
pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
80046e4: 68fb ldr r3, [r7, #12]
80046e6: 685a ldr r2, [r3, #4]
80046e8: 68fb ldr r3, [r7, #12]
80046ea: 6c1b ldr r3, [r3, #64] @ 0x40
80046ec: 441a add r2, r3
80046ee: 68fb ldr r3, [r7, #12]
80046f0: 605a str r2, [r3, #4]
if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
80046f2: 68fb ldr r3, [r7, #12]
80046f4: 685a ldr r2, [r3, #4]
80046f6: 68fb ldr r3, [r7, #12]
80046f8: 689b ldr r3, [r3, #8]
80046fa: 429a cmp r2, r3
80046fc: d32b bcc.n 8004756 <prvCopyDataToQueue+0xc2>
{
pxQueue->pcWriteTo = pxQueue->pcHead;
80046fe: 68fb ldr r3, [r7, #12]
8004700: 681a ldr r2, [r3, #0]
8004702: 68fb ldr r3, [r7, #12]
8004704: 605a str r2, [r3, #4]
8004706: e026 b.n 8004756 <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
else
{
( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
8004708: 68fb ldr r3, [r7, #12]
800470a: 68d8 ldr r0, [r3, #12]
800470c: 68fb ldr r3, [r7, #12]
800470e: 6c1b ldr r3, [r3, #64] @ 0x40
8004710: 461a mov r2, r3
8004712: 68b9 ldr r1, [r7, #8]
8004714: f002 f97d bl 8006a12 <memcpy>
pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
8004718: 68fb ldr r3, [r7, #12]
800471a: 68da ldr r2, [r3, #12]
800471c: 68fb ldr r3, [r7, #12]
800471e: 6c1b ldr r3, [r3, #64] @ 0x40
8004720: 425b negs r3, r3
8004722: 441a add r2, r3
8004724: 68fb ldr r3, [r7, #12]
8004726: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
8004728: 68fb ldr r3, [r7, #12]
800472a: 68da ldr r2, [r3, #12]
800472c: 68fb ldr r3, [r7, #12]
800472e: 681b ldr r3, [r3, #0]
8004730: 429a cmp r2, r3
8004732: d207 bcs.n 8004744 <prvCopyDataToQueue+0xb0>
{
pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
8004734: 68fb ldr r3, [r7, #12]
8004736: 689a ldr r2, [r3, #8]
8004738: 68fb ldr r3, [r7, #12]
800473a: 6c1b ldr r3, [r3, #64] @ 0x40
800473c: 425b negs r3, r3
800473e: 441a add r2, r3
8004740: 68fb ldr r3, [r7, #12]
8004742: 60da str r2, [r3, #12]
else
{
mtCOVERAGE_TEST_MARKER();
}
if( xPosition == queueOVERWRITE )
8004744: 687b ldr r3, [r7, #4]
8004746: 2b02 cmp r3, #2
8004748: d105 bne.n 8004756 <prvCopyDataToQueue+0xc2>
{
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
800474a: 693b ldr r3, [r7, #16]
800474c: 2b00 cmp r3, #0
800474e: d002 beq.n 8004756 <prvCopyDataToQueue+0xc2>
{
/* An item is not being added but overwritten, so subtract
one from the recorded number of items in the queue so when
one is added again below the number of recorded items remains
correct. */
--uxMessagesWaiting;
8004750: 693b ldr r3, [r7, #16]
8004752: 3b01 subs r3, #1
8004754: 613b str r3, [r7, #16]
{
mtCOVERAGE_TEST_MARKER();
}
}
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
8004756: 693b ldr r3, [r7, #16]
8004758: 1c5a adds r2, r3, #1
800475a: 68fb ldr r3, [r7, #12]
800475c: 639a str r2, [r3, #56] @ 0x38
return xReturn;
800475e: 697b ldr r3, [r7, #20]
}
8004760: 4618 mov r0, r3
8004762: 3718 adds r7, #24
8004764: 46bd mov sp, r7
8004766: bd80 pop {r7, pc}
08004768 <prvCopyDataFromQueue>:
/*-----------------------------------------------------------*/
static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
{
8004768: b580 push {r7, lr}
800476a: b082 sub sp, #8
800476c: af00 add r7, sp, #0
800476e: 6078 str r0, [r7, #4]
8004770: 6039 str r1, [r7, #0]
if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
8004772: 687b ldr r3, [r7, #4]
8004774: 6c1b ldr r3, [r3, #64] @ 0x40
8004776: 2b00 cmp r3, #0
8004778: d018 beq.n 80047ac <prvCopyDataFromQueue+0x44>
{
pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
800477a: 687b ldr r3, [r7, #4]
800477c: 68da ldr r2, [r3, #12]
800477e: 687b ldr r3, [r7, #4]
8004780: 6c1b ldr r3, [r3, #64] @ 0x40
8004782: 441a add r2, r3
8004784: 687b ldr r3, [r7, #4]
8004786: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
8004788: 687b ldr r3, [r7, #4]
800478a: 68da ldr r2, [r3, #12]
800478c: 687b ldr r3, [r7, #4]
800478e: 689b ldr r3, [r3, #8]
8004790: 429a cmp r2, r3
8004792: d303 bcc.n 800479c <prvCopyDataFromQueue+0x34>
{
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
8004794: 687b ldr r3, [r7, #4]
8004796: 681a ldr r2, [r3, #0]
8004798: 687b ldr r3, [r7, #4]
800479a: 60da str r2, [r3, #12]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
800479c: 687b ldr r3, [r7, #4]
800479e: 68d9 ldr r1, [r3, #12]
80047a0: 687b ldr r3, [r7, #4]
80047a2: 6c1b ldr r3, [r3, #64] @ 0x40
80047a4: 461a mov r2, r3
80047a6: 6838 ldr r0, [r7, #0]
80047a8: f002 f933 bl 8006a12 <memcpy>
}
}
80047ac: bf00 nop
80047ae: 3708 adds r7, #8
80047b0: 46bd mov sp, r7
80047b2: bd80 pop {r7, pc}
080047b4 <prvUnlockQueue>:
/*-----------------------------------------------------------*/
static void prvUnlockQueue( Queue_t * const pxQueue )
{
80047b4: b580 push {r7, lr}
80047b6: b084 sub sp, #16
80047b8: af00 add r7, sp, #0
80047ba: 6078 str r0, [r7, #4]
/* The lock counts contains the number of extra data items placed or
removed from the queue while the queue was locked. When a queue is
locked items can be added or removed, but the event lists cannot be
updated. */
taskENTER_CRITICAL();
80047bc: f001 fc7e bl 80060bc <vPortEnterCritical>
{
int8_t cTxLock = pxQueue->cTxLock;
80047c0: 687b ldr r3, [r7, #4]
80047c2: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
80047c6: 73fb strb r3, [r7, #15]
/* See if data was added to the queue while it was locked. */
while( cTxLock > queueLOCKED_UNMODIFIED )
80047c8: e011 b.n 80047ee <prvUnlockQueue+0x3a>
}
#else /* configUSE_QUEUE_SETS */
{
/* Tasks that are removed from the event list will get added to
the pending ready list as the scheduler is still suspended. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
80047ca: 687b ldr r3, [r7, #4]
80047cc: 6a5b ldr r3, [r3, #36] @ 0x24
80047ce: 2b00 cmp r3, #0
80047d0: d012 beq.n 80047f8 <prvUnlockQueue+0x44>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
80047d2: 687b ldr r3, [r7, #4]
80047d4: 3324 adds r3, #36 @ 0x24
80047d6: 4618 mov r0, r3
80047d8: f000 fd4c bl 8005274 <xTaskRemoveFromEventList>
80047dc: 4603 mov r3, r0
80047de: 2b00 cmp r3, #0
80047e0: d001 beq.n 80047e6 <prvUnlockQueue+0x32>
{
/* The task waiting has a higher priority so record that
a context switch is required. */
vTaskMissedYield();
80047e2: f000 fe2b bl 800543c <vTaskMissedYield>
break;
}
}
#endif /* configUSE_QUEUE_SETS */
--cTxLock;
80047e6: 7bfb ldrb r3, [r7, #15]
80047e8: 3b01 subs r3, #1
80047ea: b2db uxtb r3, r3
80047ec: 73fb strb r3, [r7, #15]
while( cTxLock > queueLOCKED_UNMODIFIED )
80047ee: f997 300f ldrsb.w r3, [r7, #15]
80047f2: 2b00 cmp r3, #0
80047f4: dce9 bgt.n 80047ca <prvUnlockQueue+0x16>
80047f6: e000 b.n 80047fa <prvUnlockQueue+0x46>
break;
80047f8: bf00 nop
}
pxQueue->cTxLock = queueUNLOCKED;
80047fa: 687b ldr r3, [r7, #4]
80047fc: 22ff movs r2, #255 @ 0xff
80047fe: f883 2045 strb.w r2, [r3, #69] @ 0x45
}
taskEXIT_CRITICAL();
8004802: f001 fc91 bl 8006128 <vPortExitCritical>
/* Do the same for the Rx lock. */
taskENTER_CRITICAL();
8004806: f001 fc59 bl 80060bc <vPortEnterCritical>
{
int8_t cRxLock = pxQueue->cRxLock;
800480a: 687b ldr r3, [r7, #4]
800480c: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
8004810: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
8004812: e011 b.n 8004838 <prvUnlockQueue+0x84>
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
8004814: 687b ldr r3, [r7, #4]
8004816: 691b ldr r3, [r3, #16]
8004818: 2b00 cmp r3, #0
800481a: d012 beq.n 8004842 <prvUnlockQueue+0x8e>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800481c: 687b ldr r3, [r7, #4]
800481e: 3310 adds r3, #16
8004820: 4618 mov r0, r3
8004822: f000 fd27 bl 8005274 <xTaskRemoveFromEventList>
8004826: 4603 mov r3, r0
8004828: 2b00 cmp r3, #0
800482a: d001 beq.n 8004830 <prvUnlockQueue+0x7c>
{
vTaskMissedYield();
800482c: f000 fe06 bl 800543c <vTaskMissedYield>
else
{
mtCOVERAGE_TEST_MARKER();
}
--cRxLock;
8004830: 7bbb ldrb r3, [r7, #14]
8004832: 3b01 subs r3, #1
8004834: b2db uxtb r3, r3
8004836: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
8004838: f997 300e ldrsb.w r3, [r7, #14]
800483c: 2b00 cmp r3, #0
800483e: dce9 bgt.n 8004814 <prvUnlockQueue+0x60>
8004840: e000 b.n 8004844 <prvUnlockQueue+0x90>
}
else
{
break;
8004842: bf00 nop
}
}
pxQueue->cRxLock = queueUNLOCKED;
8004844: 687b ldr r3, [r7, #4]
8004846: 22ff movs r2, #255 @ 0xff
8004848: f883 2044 strb.w r2, [r3, #68] @ 0x44
}
taskEXIT_CRITICAL();
800484c: f001 fc6c bl 8006128 <vPortExitCritical>
}
8004850: bf00 nop
8004852: 3710 adds r7, #16
8004854: 46bd mov sp, r7
8004856: bd80 pop {r7, pc}
08004858 <prvIsQueueEmpty>:
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
{
8004858: b580 push {r7, lr}
800485a: b084 sub sp, #16
800485c: af00 add r7, sp, #0
800485e: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
8004860: f001 fc2c bl 80060bc <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
8004864: 687b ldr r3, [r7, #4]
8004866: 6b9b ldr r3, [r3, #56] @ 0x38
8004868: 2b00 cmp r3, #0
800486a: d102 bne.n 8004872 <prvIsQueueEmpty+0x1a>
{
xReturn = pdTRUE;
800486c: 2301 movs r3, #1
800486e: 60fb str r3, [r7, #12]
8004870: e001 b.n 8004876 <prvIsQueueEmpty+0x1e>
}
else
{
xReturn = pdFALSE;
8004872: 2300 movs r3, #0
8004874: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
8004876: f001 fc57 bl 8006128 <vPortExitCritical>
return xReturn;
800487a: 68fb ldr r3, [r7, #12]
}
800487c: 4618 mov r0, r3
800487e: 3710 adds r7, #16
8004880: 46bd mov sp, r7
8004882: bd80 pop {r7, pc}
08004884 <prvIsQueueFull>:
return xReturn;
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
{
8004884: b580 push {r7, lr}
8004886: b084 sub sp, #16
8004888: af00 add r7, sp, #0
800488a: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
800488c: f001 fc16 bl 80060bc <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
8004890: 687b ldr r3, [r7, #4]
8004892: 6b9a ldr r2, [r3, #56] @ 0x38
8004894: 687b ldr r3, [r7, #4]
8004896: 6bdb ldr r3, [r3, #60] @ 0x3c
8004898: 429a cmp r2, r3
800489a: d102 bne.n 80048a2 <prvIsQueueFull+0x1e>
{
xReturn = pdTRUE;
800489c: 2301 movs r3, #1
800489e: 60fb str r3, [r7, #12]
80048a0: e001 b.n 80048a6 <prvIsQueueFull+0x22>
}
else
{
xReturn = pdFALSE;
80048a2: 2300 movs r3, #0
80048a4: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
80048a6: f001 fc3f bl 8006128 <vPortExitCritical>
return xReturn;
80048aa: 68fb ldr r3, [r7, #12]
}
80048ac: 4618 mov r0, r3
80048ae: 3710 adds r7, #16
80048b0: 46bd mov sp, r7
80048b2: bd80 pop {r7, pc}
080048b4 <vQueueAddToRegistry>:
/*-----------------------------------------------------------*/
#if ( configQUEUE_REGISTRY_SIZE > 0 )
void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
{
80048b4: b480 push {r7}
80048b6: b085 sub sp, #20
80048b8: af00 add r7, sp, #0
80048ba: 6078 str r0, [r7, #4]
80048bc: 6039 str r1, [r7, #0]
UBaseType_t ux;
/* See if there is an empty space in the registry. A NULL name denotes
a free slot. */
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
80048be: 2300 movs r3, #0
80048c0: 60fb str r3, [r7, #12]
80048c2: e014 b.n 80048ee <vQueueAddToRegistry+0x3a>
{
if( xQueueRegistry[ ux ].pcQueueName == NULL )
80048c4: 4a0f ldr r2, [pc, #60] @ (8004904 <vQueueAddToRegistry+0x50>)
80048c6: 68fb ldr r3, [r7, #12]
80048c8: f852 3033 ldr.w r3, [r2, r3, lsl #3]
80048cc: 2b00 cmp r3, #0
80048ce: d10b bne.n 80048e8 <vQueueAddToRegistry+0x34>
{
/* Store the information on this queue. */
xQueueRegistry[ ux ].pcQueueName = pcQueueName;
80048d0: 490c ldr r1, [pc, #48] @ (8004904 <vQueueAddToRegistry+0x50>)
80048d2: 68fb ldr r3, [r7, #12]
80048d4: 683a ldr r2, [r7, #0]
80048d6: f841 2033 str.w r2, [r1, r3, lsl #3]
xQueueRegistry[ ux ].xHandle = xQueue;
80048da: 4a0a ldr r2, [pc, #40] @ (8004904 <vQueueAddToRegistry+0x50>)
80048dc: 68fb ldr r3, [r7, #12]
80048de: 00db lsls r3, r3, #3
80048e0: 4413 add r3, r2
80048e2: 687a ldr r2, [r7, #4]
80048e4: 605a str r2, [r3, #4]
traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
break;
80048e6: e006 b.n 80048f6 <vQueueAddToRegistry+0x42>
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
80048e8: 68fb ldr r3, [r7, #12]
80048ea: 3301 adds r3, #1
80048ec: 60fb str r3, [r7, #12]
80048ee: 68fb ldr r3, [r7, #12]
80048f0: 2b07 cmp r3, #7
80048f2: d9e7 bls.n 80048c4 <vQueueAddToRegistry+0x10>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
}
80048f4: bf00 nop
80048f6: bf00 nop
80048f8: 3714 adds r7, #20
80048fa: 46bd mov sp, r7
80048fc: f85d 7b04 ldr.w r7, [sp], #4
8004900: 4770 bx lr
8004902: bf00 nop
8004904: 20000e28 .word 0x20000e28
08004908 <vQueueWaitForMessageRestricted>:
/*-----------------------------------------------------------*/
#if ( configUSE_TIMERS == 1 )
void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
{
8004908: b580 push {r7, lr}
800490a: b086 sub sp, #24
800490c: af00 add r7, sp, #0
800490e: 60f8 str r0, [r7, #12]
8004910: 60b9 str r1, [r7, #8]
8004912: 607a str r2, [r7, #4]
Queue_t * const pxQueue = xQueue;
8004914: 68fb ldr r3, [r7, #12]
8004916: 617b str r3, [r7, #20]
will not actually cause the task to block, just place it on a blocked
list. It will not block until the scheduler is unlocked - at which
time a yield will be performed. If an item is added to the queue while
the queue is locked, and the calling task blocks on the queue, then the
calling task will be immediately unblocked when the queue is unlocked. */
prvLockQueue( pxQueue );
8004918: f001 fbd0 bl 80060bc <vPortEnterCritical>
800491c: 697b ldr r3, [r7, #20]
800491e: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
8004922: b25b sxtb r3, r3
8004924: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8004928: d103 bne.n 8004932 <vQueueWaitForMessageRestricted+0x2a>
800492a: 697b ldr r3, [r7, #20]
800492c: 2200 movs r2, #0
800492e: f883 2044 strb.w r2, [r3, #68] @ 0x44
8004932: 697b ldr r3, [r7, #20]
8004934: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
8004938: b25b sxtb r3, r3
800493a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
800493e: d103 bne.n 8004948 <vQueueWaitForMessageRestricted+0x40>
8004940: 697b ldr r3, [r7, #20]
8004942: 2200 movs r2, #0
8004944: f883 2045 strb.w r2, [r3, #69] @ 0x45
8004948: f001 fbee bl 8006128 <vPortExitCritical>
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
800494c: 697b ldr r3, [r7, #20]
800494e: 6b9b ldr r3, [r3, #56] @ 0x38
8004950: 2b00 cmp r3, #0
8004952: d106 bne.n 8004962 <vQueueWaitForMessageRestricted+0x5a>
{
/* There is nothing in the queue, block for the specified period. */
vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
8004954: 697b ldr r3, [r7, #20]
8004956: 3324 adds r3, #36 @ 0x24
8004958: 687a ldr r2, [r7, #4]
800495a: 68b9 ldr r1, [r7, #8]
800495c: 4618 mov r0, r3
800495e: f000 fc5b bl 8005218 <vTaskPlaceOnEventListRestricted>
}
else
{
mtCOVERAGE_TEST_MARKER();
}
prvUnlockQueue( pxQueue );
8004962: 6978 ldr r0, [r7, #20]
8004964: f7ff ff26 bl 80047b4 <prvUnlockQueue>
}
8004968: bf00 nop
800496a: 3718 adds r7, #24
800496c: 46bd mov sp, r7
800496e: bd80 pop {r7, pc}
08004970 <xTaskCreateStatic>:
const uint32_t ulStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
StackType_t * const puxStackBuffer,
StaticTask_t * const pxTaskBuffer )
{
8004970: b580 push {r7, lr}
8004972: b08e sub sp, #56 @ 0x38
8004974: af04 add r7, sp, #16
8004976: 60f8 str r0, [r7, #12]
8004978: 60b9 str r1, [r7, #8]
800497a: 607a str r2, [r7, #4]
800497c: 603b str r3, [r7, #0]
TCB_t *pxNewTCB;
TaskHandle_t xReturn;
configASSERT( puxStackBuffer != NULL );
800497e: 6b7b ldr r3, [r7, #52] @ 0x34
8004980: 2b00 cmp r3, #0
8004982: d10d bne.n 80049a0 <xTaskCreateStatic+0x30>
__asm volatile
8004984: f04f 0350 mov.w r3, #80 @ 0x50
8004988: b672 cpsid i
800498a: f383 8811 msr BASEPRI, r3
800498e: f3bf 8f6f isb sy
8004992: f3bf 8f4f dsb sy
8004996: b662 cpsie i
8004998: 623b str r3, [r7, #32]
}
800499a: bf00 nop
800499c: bf00 nop
800499e: e7fd b.n 800499c <xTaskCreateStatic+0x2c>
configASSERT( pxTaskBuffer != NULL );
80049a0: 6bbb ldr r3, [r7, #56] @ 0x38
80049a2: 2b00 cmp r3, #0
80049a4: d10d bne.n 80049c2 <xTaskCreateStatic+0x52>
__asm volatile
80049a6: f04f 0350 mov.w r3, #80 @ 0x50
80049aa: b672 cpsid i
80049ac: f383 8811 msr BASEPRI, r3
80049b0: f3bf 8f6f isb sy
80049b4: f3bf 8f4f dsb sy
80049b8: b662 cpsie i
80049ba: 61fb str r3, [r7, #28]
}
80049bc: bf00 nop
80049be: bf00 nop
80049c0: e7fd b.n 80049be <xTaskCreateStatic+0x4e>
#if( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
variable of type StaticTask_t equals the size of the real task
structure. */
volatile size_t xSize = sizeof( StaticTask_t );
80049c2: 235c movs r3, #92 @ 0x5c
80049c4: 613b str r3, [r7, #16]
configASSERT( xSize == sizeof( TCB_t ) );
80049c6: 693b ldr r3, [r7, #16]
80049c8: 2b5c cmp r3, #92 @ 0x5c
80049ca: d00d beq.n 80049e8 <xTaskCreateStatic+0x78>
__asm volatile
80049cc: f04f 0350 mov.w r3, #80 @ 0x50
80049d0: b672 cpsid i
80049d2: f383 8811 msr BASEPRI, r3
80049d6: f3bf 8f6f isb sy
80049da: f3bf 8f4f dsb sy
80049de: b662 cpsie i
80049e0: 61bb str r3, [r7, #24]
}
80049e2: bf00 nop
80049e4: bf00 nop
80049e6: e7fd b.n 80049e4 <xTaskCreateStatic+0x74>
( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
80049e8: 693b ldr r3, [r7, #16]
}
#endif /* configASSERT_DEFINED */
if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
80049ea: 6bbb ldr r3, [r7, #56] @ 0x38
80049ec: 2b00 cmp r3, #0
80049ee: d01e beq.n 8004a2e <xTaskCreateStatic+0xbe>
80049f0: 6b7b ldr r3, [r7, #52] @ 0x34
80049f2: 2b00 cmp r3, #0
80049f4: d01b beq.n 8004a2e <xTaskCreateStatic+0xbe>
{
/* The memory used for the task's TCB and stack are passed into this
function - use them. */
pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
80049f6: 6bbb ldr r3, [r7, #56] @ 0x38
80049f8: 627b str r3, [r7, #36] @ 0x24
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
80049fa: 6a7b ldr r3, [r7, #36] @ 0x24
80049fc: 6b7a ldr r2, [r7, #52] @ 0x34
80049fe: 631a str r2, [r3, #48] @ 0x30
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created statically in case the task is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
8004a00: 6a7b ldr r3, [r7, #36] @ 0x24
8004a02: 2202 movs r2, #2
8004a04: f883 2059 strb.w r2, [r3, #89] @ 0x59
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
8004a08: 2300 movs r3, #0
8004a0a: 9303 str r3, [sp, #12]
8004a0c: 6a7b ldr r3, [r7, #36] @ 0x24
8004a0e: 9302 str r3, [sp, #8]
8004a10: f107 0314 add.w r3, r7, #20
8004a14: 9301 str r3, [sp, #4]
8004a16: 6b3b ldr r3, [r7, #48] @ 0x30
8004a18: 9300 str r3, [sp, #0]
8004a1a: 683b ldr r3, [r7, #0]
8004a1c: 687a ldr r2, [r7, #4]
8004a1e: 68b9 ldr r1, [r7, #8]
8004a20: 68f8 ldr r0, [r7, #12]
8004a22: f000 f850 bl 8004ac6 <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
8004a26: 6a78 ldr r0, [r7, #36] @ 0x24
8004a28: f000 f8e0 bl 8004bec <prvAddNewTaskToReadyList>
8004a2c: e001 b.n 8004a32 <xTaskCreateStatic+0xc2>
}
else
{
xReturn = NULL;
8004a2e: 2300 movs r3, #0
8004a30: 617b str r3, [r7, #20]
}
return xReturn;
8004a32: 697b ldr r3, [r7, #20]
}
8004a34: 4618 mov r0, r3
8004a36: 3728 adds r7, #40 @ 0x28
8004a38: 46bd mov sp, r7
8004a3a: bd80 pop {r7, pc}
08004a3c <xTaskCreate>:
const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
const configSTACK_DEPTH_TYPE usStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask )
{
8004a3c: b580 push {r7, lr}
8004a3e: b08c sub sp, #48 @ 0x30
8004a40: af04 add r7, sp, #16
8004a42: 60f8 str r0, [r7, #12]
8004a44: 60b9 str r1, [r7, #8]
8004a46: 603b str r3, [r7, #0]
8004a48: 4613 mov r3, r2
8004a4a: 80fb strh r3, [r7, #6]
#else /* portSTACK_GROWTH */
{
StackType_t *pxStack;
/* Allocate space for the stack used by the task being created. */
pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
8004a4c: 88fb ldrh r3, [r7, #6]
8004a4e: 009b lsls r3, r3, #2
8004a50: 4618 mov r0, r3
8004a52: f001 fc61 bl 8006318 <pvPortMalloc>
8004a56: 6178 str r0, [r7, #20]
if( pxStack != NULL )
8004a58: 697b ldr r3, [r7, #20]
8004a5a: 2b00 cmp r3, #0
8004a5c: d00e beq.n 8004a7c <xTaskCreate+0x40>
{
/* Allocate space for the TCB. */
pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
8004a5e: 205c movs r0, #92 @ 0x5c
8004a60: f001 fc5a bl 8006318 <pvPortMalloc>
8004a64: 61f8 str r0, [r7, #28]
if( pxNewTCB != NULL )
8004a66: 69fb ldr r3, [r7, #28]
8004a68: 2b00 cmp r3, #0
8004a6a: d003 beq.n 8004a74 <xTaskCreate+0x38>
{
/* Store the stack location in the TCB. */
pxNewTCB->pxStack = pxStack;
8004a6c: 69fb ldr r3, [r7, #28]
8004a6e: 697a ldr r2, [r7, #20]
8004a70: 631a str r2, [r3, #48] @ 0x30
8004a72: e005 b.n 8004a80 <xTaskCreate+0x44>
}
else
{
/* The stack cannot be used as the TCB was not created. Free
it again. */
vPortFree( pxStack );
8004a74: 6978 ldr r0, [r7, #20]
8004a76: f001 fd1d bl 80064b4 <vPortFree>
8004a7a: e001 b.n 8004a80 <xTaskCreate+0x44>
}
}
else
{
pxNewTCB = NULL;
8004a7c: 2300 movs r3, #0
8004a7e: 61fb str r3, [r7, #28]
}
}
#endif /* portSTACK_GROWTH */
if( pxNewTCB != NULL )
8004a80: 69fb ldr r3, [r7, #28]
8004a82: 2b00 cmp r3, #0
8004a84: d017 beq.n 8004ab6 <xTaskCreate+0x7a>
{
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created dynamically in case it is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
8004a86: 69fb ldr r3, [r7, #28]
8004a88: 2200 movs r2, #0
8004a8a: f883 2059 strb.w r2, [r3, #89] @ 0x59
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
8004a8e: 88fa ldrh r2, [r7, #6]
8004a90: 2300 movs r3, #0
8004a92: 9303 str r3, [sp, #12]
8004a94: 69fb ldr r3, [r7, #28]
8004a96: 9302 str r3, [sp, #8]
8004a98: 6afb ldr r3, [r7, #44] @ 0x2c
8004a9a: 9301 str r3, [sp, #4]
8004a9c: 6abb ldr r3, [r7, #40] @ 0x28
8004a9e: 9300 str r3, [sp, #0]
8004aa0: 683b ldr r3, [r7, #0]
8004aa2: 68b9 ldr r1, [r7, #8]
8004aa4: 68f8 ldr r0, [r7, #12]
8004aa6: f000 f80e bl 8004ac6 <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
8004aaa: 69f8 ldr r0, [r7, #28]
8004aac: f000 f89e bl 8004bec <prvAddNewTaskToReadyList>
xReturn = pdPASS;
8004ab0: 2301 movs r3, #1
8004ab2: 61bb str r3, [r7, #24]
8004ab4: e002 b.n 8004abc <xTaskCreate+0x80>
}
else
{
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
8004ab6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
8004aba: 61bb str r3, [r7, #24]
}
return xReturn;
8004abc: 69bb ldr r3, [r7, #24]
}
8004abe: 4618 mov r0, r3
8004ac0: 3720 adds r7, #32
8004ac2: 46bd mov sp, r7
8004ac4: bd80 pop {r7, pc}
08004ac6 <prvInitialiseNewTask>:
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask,
TCB_t *pxNewTCB,
const MemoryRegion_t * const xRegions )
{
8004ac6: b580 push {r7, lr}
8004ac8: b088 sub sp, #32
8004aca: af00 add r7, sp, #0
8004acc: 60f8 str r0, [r7, #12]
8004ace: 60b9 str r1, [r7, #8]
8004ad0: 607a str r2, [r7, #4]
8004ad2: 603b str r3, [r7, #0]
/* Avoid dependency on memset() if it is not required. */
#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
{
/* Fill the stack with a known value to assist debugging. */
( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
8004ad4: 6b3b ldr r3, [r7, #48] @ 0x30
8004ad6: 6b18 ldr r0, [r3, #48] @ 0x30
8004ad8: 687b ldr r3, [r7, #4]
8004ada: 009b lsls r3, r3, #2
8004adc: 461a mov r2, r3
8004ade: 21a5 movs r1, #165 @ 0xa5
8004ae0: f001 ff1b bl 800691a <memset>
grows from high memory to low (as per the 80x86) or vice versa.
portSTACK_GROWTH is used to make the result positive or negative as required
by the port. */
#if( portSTACK_GROWTH < 0 )
{
pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
8004ae4: 6b3b ldr r3, [r7, #48] @ 0x30
8004ae6: 6b1a ldr r2, [r3, #48] @ 0x30
8004ae8: 6879 ldr r1, [r7, #4]
8004aea: f06f 4340 mvn.w r3, #3221225472 @ 0xc0000000
8004aee: 440b add r3, r1
8004af0: 009b lsls r3, r3, #2
8004af2: 4413 add r3, r2
8004af4: 61bb str r3, [r7, #24]
pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
8004af6: 69bb ldr r3, [r7, #24]
8004af8: f023 0307 bic.w r3, r3, #7
8004afc: 61bb str r3, [r7, #24]
/* Check the alignment of the calculated top of stack is correct. */
configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
8004afe: 69bb ldr r3, [r7, #24]
8004b00: f003 0307 and.w r3, r3, #7
8004b04: 2b00 cmp r3, #0
8004b06: d00d beq.n 8004b24 <prvInitialiseNewTask+0x5e>
__asm volatile
8004b08: f04f 0350 mov.w r3, #80 @ 0x50
8004b0c: b672 cpsid i
8004b0e: f383 8811 msr BASEPRI, r3
8004b12: f3bf 8f6f isb sy
8004b16: f3bf 8f4f dsb sy
8004b1a: b662 cpsie i
8004b1c: 617b str r3, [r7, #20]
}
8004b1e: bf00 nop
8004b20: bf00 nop
8004b22: e7fd b.n 8004b20 <prvInitialiseNewTask+0x5a>
pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
}
#endif /* portSTACK_GROWTH */
/* Store the task name in the TCB. */
if( pcName != NULL )
8004b24: 68bb ldr r3, [r7, #8]
8004b26: 2b00 cmp r3, #0
8004b28: d01f beq.n 8004b6a <prvInitialiseNewTask+0xa4>
{
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
8004b2a: 2300 movs r3, #0
8004b2c: 61fb str r3, [r7, #28]
8004b2e: e012 b.n 8004b56 <prvInitialiseNewTask+0x90>
{
pxNewTCB->pcTaskName[ x ] = pcName[ x ];
8004b30: 68ba ldr r2, [r7, #8]
8004b32: 69fb ldr r3, [r7, #28]
8004b34: 4413 add r3, r2
8004b36: 7819 ldrb r1, [r3, #0]
8004b38: 6b3a ldr r2, [r7, #48] @ 0x30
8004b3a: 69fb ldr r3, [r7, #28]
8004b3c: 4413 add r3, r2
8004b3e: 3334 adds r3, #52 @ 0x34
8004b40: 460a mov r2, r1
8004b42: 701a strb r2, [r3, #0]
/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
configMAX_TASK_NAME_LEN characters just in case the memory after the
string is not accessible (extremely unlikely). */
if( pcName[ x ] == ( char ) 0x00 )
8004b44: 68ba ldr r2, [r7, #8]
8004b46: 69fb ldr r3, [r7, #28]
8004b48: 4413 add r3, r2
8004b4a: 781b ldrb r3, [r3, #0]
8004b4c: 2b00 cmp r3, #0
8004b4e: d006 beq.n 8004b5e <prvInitialiseNewTask+0x98>
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
8004b50: 69fb ldr r3, [r7, #28]
8004b52: 3301 adds r3, #1
8004b54: 61fb str r3, [r7, #28]
8004b56: 69fb ldr r3, [r7, #28]
8004b58: 2b0f cmp r3, #15
8004b5a: d9e9 bls.n 8004b30 <prvInitialiseNewTask+0x6a>
8004b5c: e000 b.n 8004b60 <prvInitialiseNewTask+0x9a>
{
break;
8004b5e: bf00 nop
}
}
/* Ensure the name string is terminated in the case that the string length
was greater or equal to configMAX_TASK_NAME_LEN. */
pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
8004b60: 6b3b ldr r3, [r7, #48] @ 0x30
8004b62: 2200 movs r2, #0
8004b64: f883 2043 strb.w r2, [r3, #67] @ 0x43
8004b68: e003 b.n 8004b72 <prvInitialiseNewTask+0xac>
}
else
{
/* The task has not been given a name, so just ensure there is a NULL
terminator when it is read out. */
pxNewTCB->pcTaskName[ 0 ] = 0x00;
8004b6a: 6b3b ldr r3, [r7, #48] @ 0x30
8004b6c: 2200 movs r2, #0
8004b6e: f883 2034 strb.w r2, [r3, #52] @ 0x34
}
/* This is used as an array index so must ensure it's not too large. First
remove the privilege bit if one is present. */
if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
8004b72: 6abb ldr r3, [r7, #40] @ 0x28
8004b74: 2b37 cmp r3, #55 @ 0x37
8004b76: d901 bls.n 8004b7c <prvInitialiseNewTask+0xb6>
{
uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
8004b78: 2337 movs r3, #55 @ 0x37
8004b7a: 62bb str r3, [r7, #40] @ 0x28
else
{
mtCOVERAGE_TEST_MARKER();
}
pxNewTCB->uxPriority = uxPriority;
8004b7c: 6b3b ldr r3, [r7, #48] @ 0x30
8004b7e: 6aba ldr r2, [r7, #40] @ 0x28
8004b80: 62da str r2, [r3, #44] @ 0x2c
#if ( configUSE_MUTEXES == 1 )
{
pxNewTCB->uxBasePriority = uxPriority;
8004b82: 6b3b ldr r3, [r7, #48] @ 0x30
8004b84: 6aba ldr r2, [r7, #40] @ 0x28
8004b86: 64da str r2, [r3, #76] @ 0x4c
pxNewTCB->uxMutexesHeld = 0;
8004b88: 6b3b ldr r3, [r7, #48] @ 0x30
8004b8a: 2200 movs r2, #0
8004b8c: 651a str r2, [r3, #80] @ 0x50
}
#endif /* configUSE_MUTEXES */
vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
8004b8e: 6b3b ldr r3, [r7, #48] @ 0x30
8004b90: 3304 adds r3, #4
8004b92: 4618 mov r0, r3
8004b94: f7ff f93e bl 8003e14 <vListInitialiseItem>
vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
8004b98: 6b3b ldr r3, [r7, #48] @ 0x30
8004b9a: 3318 adds r3, #24
8004b9c: 4618 mov r0, r3
8004b9e: f7ff f939 bl 8003e14 <vListInitialiseItem>
/* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get
back to the containing TCB from a generic item in a list. */
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
8004ba2: 6b3b ldr r3, [r7, #48] @ 0x30
8004ba4: 6b3a ldr r2, [r7, #48] @ 0x30
8004ba6: 611a str r2, [r3, #16]
/* Event lists are always in priority order. */
listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8004ba8: 6abb ldr r3, [r7, #40] @ 0x28
8004baa: f1c3 0238 rsb r2, r3, #56 @ 0x38
8004bae: 6b3b ldr r3, [r7, #48] @ 0x30
8004bb0: 619a str r2, [r3, #24]
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
8004bb2: 6b3b ldr r3, [r7, #48] @ 0x30
8004bb4: 6b3a ldr r2, [r7, #48] @ 0x30
8004bb6: 625a str r2, [r3, #36] @ 0x24
}
#endif
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
{
pxNewTCB->ulNotifiedValue = 0;
8004bb8: 6b3b ldr r3, [r7, #48] @ 0x30
8004bba: 2200 movs r2, #0
8004bbc: 655a str r2, [r3, #84] @ 0x54
pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
8004bbe: 6b3b ldr r3, [r7, #48] @ 0x30
8004bc0: 2200 movs r2, #0
8004bc2: f883 2058 strb.w r2, [r3, #88] @ 0x58
}
#endif /* portSTACK_GROWTH */
}
#else /* portHAS_STACK_OVERFLOW_CHECKING */
{
pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
8004bc6: 683a ldr r2, [r7, #0]
8004bc8: 68f9 ldr r1, [r7, #12]
8004bca: 69b8 ldr r0, [r7, #24]
8004bcc: f001 f968 bl 8005ea0 <pxPortInitialiseStack>
8004bd0: 4602 mov r2, r0
8004bd2: 6b3b ldr r3, [r7, #48] @ 0x30
8004bd4: 601a str r2, [r3, #0]
}
#endif /* portHAS_STACK_OVERFLOW_CHECKING */
}
#endif /* portUSING_MPU_WRAPPERS */
if( pxCreatedTask != NULL )
8004bd6: 6afb ldr r3, [r7, #44] @ 0x2c
8004bd8: 2b00 cmp r3, #0
8004bda: d002 beq.n 8004be2 <prvInitialiseNewTask+0x11c>
{
/* Pass the handle out in an anonymous way. The handle can be used to
change the created task's priority, delete the created task, etc.*/
*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
8004bdc: 6afb ldr r3, [r7, #44] @ 0x2c
8004bde: 6b3a ldr r2, [r7, #48] @ 0x30
8004be0: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8004be2: bf00 nop
8004be4: 3720 adds r7, #32
8004be6: 46bd mov sp, r7
8004be8: bd80 pop {r7, pc}
...
08004bec <prvAddNewTaskToReadyList>:
/*-----------------------------------------------------------*/
static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
{
8004bec: b580 push {r7, lr}
8004bee: b082 sub sp, #8
8004bf0: af00 add r7, sp, #0
8004bf2: 6078 str r0, [r7, #4]
/* Ensure interrupts don't access the task lists while the lists are being
updated. */
taskENTER_CRITICAL();
8004bf4: f001 fa62 bl 80060bc <vPortEnterCritical>
{
uxCurrentNumberOfTasks++;
8004bf8: 4b2d ldr r3, [pc, #180] @ (8004cb0 <prvAddNewTaskToReadyList+0xc4>)
8004bfa: 681b ldr r3, [r3, #0]
8004bfc: 3301 adds r3, #1
8004bfe: 4a2c ldr r2, [pc, #176] @ (8004cb0 <prvAddNewTaskToReadyList+0xc4>)
8004c00: 6013 str r3, [r2, #0]
if( pxCurrentTCB == NULL )
8004c02: 4b2c ldr r3, [pc, #176] @ (8004cb4 <prvAddNewTaskToReadyList+0xc8>)
8004c04: 681b ldr r3, [r3, #0]
8004c06: 2b00 cmp r3, #0
8004c08: d109 bne.n 8004c1e <prvAddNewTaskToReadyList+0x32>
{
/* There are no other tasks, or all the other tasks are in
the suspended state - make this the current task. */
pxCurrentTCB = pxNewTCB;
8004c0a: 4a2a ldr r2, [pc, #168] @ (8004cb4 <prvAddNewTaskToReadyList+0xc8>)
8004c0c: 687b ldr r3, [r7, #4]
8004c0e: 6013 str r3, [r2, #0]
if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
8004c10: 4b27 ldr r3, [pc, #156] @ (8004cb0 <prvAddNewTaskToReadyList+0xc4>)
8004c12: 681b ldr r3, [r3, #0]
8004c14: 2b01 cmp r3, #1
8004c16: d110 bne.n 8004c3a <prvAddNewTaskToReadyList+0x4e>
{
/* This is the first task to be created so do the preliminary
initialisation required. We will not recover if this call
fails, but we will report the failure. */
prvInitialiseTaskLists();
8004c18: f000 fc34 bl 8005484 <prvInitialiseTaskLists>
8004c1c: e00d b.n 8004c3a <prvAddNewTaskToReadyList+0x4e>
else
{
/* If the scheduler is not already running, make this task the
current task if it is the highest priority task to be created
so far. */
if( xSchedulerRunning == pdFALSE )
8004c1e: 4b26 ldr r3, [pc, #152] @ (8004cb8 <prvAddNewTaskToReadyList+0xcc>)
8004c20: 681b ldr r3, [r3, #0]
8004c22: 2b00 cmp r3, #0
8004c24: d109 bne.n 8004c3a <prvAddNewTaskToReadyList+0x4e>
{
if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
8004c26: 4b23 ldr r3, [pc, #140] @ (8004cb4 <prvAddNewTaskToReadyList+0xc8>)
8004c28: 681b ldr r3, [r3, #0]
8004c2a: 6ada ldr r2, [r3, #44] @ 0x2c
8004c2c: 687b ldr r3, [r7, #4]
8004c2e: 6adb ldr r3, [r3, #44] @ 0x2c
8004c30: 429a cmp r2, r3
8004c32: d802 bhi.n 8004c3a <prvAddNewTaskToReadyList+0x4e>
{
pxCurrentTCB = pxNewTCB;
8004c34: 4a1f ldr r2, [pc, #124] @ (8004cb4 <prvAddNewTaskToReadyList+0xc8>)
8004c36: 687b ldr r3, [r7, #4]
8004c38: 6013 str r3, [r2, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
uxTaskNumber++;
8004c3a: 4b20 ldr r3, [pc, #128] @ (8004cbc <prvAddNewTaskToReadyList+0xd0>)
8004c3c: 681b ldr r3, [r3, #0]
8004c3e: 3301 adds r3, #1
8004c40: 4a1e ldr r2, [pc, #120] @ (8004cbc <prvAddNewTaskToReadyList+0xd0>)
8004c42: 6013 str r3, [r2, #0]
#if ( configUSE_TRACE_FACILITY == 1 )
{
/* Add a counter into the TCB for tracing only. */
pxNewTCB->uxTCBNumber = uxTaskNumber;
8004c44: 4b1d ldr r3, [pc, #116] @ (8004cbc <prvAddNewTaskToReadyList+0xd0>)
8004c46: 681a ldr r2, [r3, #0]
8004c48: 687b ldr r3, [r7, #4]
8004c4a: 645a str r2, [r3, #68] @ 0x44
}
#endif /* configUSE_TRACE_FACILITY */
traceTASK_CREATE( pxNewTCB );
prvAddTaskToReadyList( pxNewTCB );
8004c4c: 687b ldr r3, [r7, #4]
8004c4e: 6ada ldr r2, [r3, #44] @ 0x2c
8004c50: 4b1b ldr r3, [pc, #108] @ (8004cc0 <prvAddNewTaskToReadyList+0xd4>)
8004c52: 681b ldr r3, [r3, #0]
8004c54: 429a cmp r2, r3
8004c56: d903 bls.n 8004c60 <prvAddNewTaskToReadyList+0x74>
8004c58: 687b ldr r3, [r7, #4]
8004c5a: 6adb ldr r3, [r3, #44] @ 0x2c
8004c5c: 4a18 ldr r2, [pc, #96] @ (8004cc0 <prvAddNewTaskToReadyList+0xd4>)
8004c5e: 6013 str r3, [r2, #0]
8004c60: 687b ldr r3, [r7, #4]
8004c62: 6ada ldr r2, [r3, #44] @ 0x2c
8004c64: 4613 mov r3, r2
8004c66: 009b lsls r3, r3, #2
8004c68: 4413 add r3, r2
8004c6a: 009b lsls r3, r3, #2
8004c6c: 4a15 ldr r2, [pc, #84] @ (8004cc4 <prvAddNewTaskToReadyList+0xd8>)
8004c6e: 441a add r2, r3
8004c70: 687b ldr r3, [r7, #4]
8004c72: 3304 adds r3, #4
8004c74: 4619 mov r1, r3
8004c76: 4610 mov r0, r2
8004c78: f7ff f8d9 bl 8003e2e <vListInsertEnd>
portSETUP_TCB( pxNewTCB );
}
taskEXIT_CRITICAL();
8004c7c: f001 fa54 bl 8006128 <vPortExitCritical>
if( xSchedulerRunning != pdFALSE )
8004c80: 4b0d ldr r3, [pc, #52] @ (8004cb8 <prvAddNewTaskToReadyList+0xcc>)
8004c82: 681b ldr r3, [r3, #0]
8004c84: 2b00 cmp r3, #0
8004c86: d00e beq.n 8004ca6 <prvAddNewTaskToReadyList+0xba>
{
/* If the created task is of a higher priority than the current task
then it should run now. */
if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
8004c88: 4b0a ldr r3, [pc, #40] @ (8004cb4 <prvAddNewTaskToReadyList+0xc8>)
8004c8a: 681b ldr r3, [r3, #0]
8004c8c: 6ada ldr r2, [r3, #44] @ 0x2c
8004c8e: 687b ldr r3, [r7, #4]
8004c90: 6adb ldr r3, [r3, #44] @ 0x2c
8004c92: 429a cmp r2, r3
8004c94: d207 bcs.n 8004ca6 <prvAddNewTaskToReadyList+0xba>
{
taskYIELD_IF_USING_PREEMPTION();
8004c96: 4b0c ldr r3, [pc, #48] @ (8004cc8 <prvAddNewTaskToReadyList+0xdc>)
8004c98: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8004c9c: 601a str r2, [r3, #0]
8004c9e: f3bf 8f4f dsb sy
8004ca2: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8004ca6: bf00 nop
8004ca8: 3708 adds r7, #8
8004caa: 46bd mov sp, r7
8004cac: bd80 pop {r7, pc}
8004cae: bf00 nop
8004cb0: 2000133c .word 0x2000133c
8004cb4: 20000e68 .word 0x20000e68
8004cb8: 20001348 .word 0x20001348
8004cbc: 20001358 .word 0x20001358
8004cc0: 20001344 .word 0x20001344
8004cc4: 20000e6c .word 0x20000e6c
8004cc8: e000ed04 .word 0xe000ed04
08004ccc <vTaskDelay>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelay == 1 )
void vTaskDelay( const TickType_t xTicksToDelay )
{
8004ccc: b580 push {r7, lr}
8004cce: b084 sub sp, #16
8004cd0: af00 add r7, sp, #0
8004cd2: 6078 str r0, [r7, #4]
BaseType_t xAlreadyYielded = pdFALSE;
8004cd4: 2300 movs r3, #0
8004cd6: 60fb str r3, [r7, #12]
/* A delay time of zero just forces a reschedule. */
if( xTicksToDelay > ( TickType_t ) 0U )
8004cd8: 687b ldr r3, [r7, #4]
8004cda: 2b00 cmp r3, #0
8004cdc: d01a beq.n 8004d14 <vTaskDelay+0x48>
{
configASSERT( uxSchedulerSuspended == 0 );
8004cde: 4b15 ldr r3, [pc, #84] @ (8004d34 <vTaskDelay+0x68>)
8004ce0: 681b ldr r3, [r3, #0]
8004ce2: 2b00 cmp r3, #0
8004ce4: d00d beq.n 8004d02 <vTaskDelay+0x36>
__asm volatile
8004ce6: f04f 0350 mov.w r3, #80 @ 0x50
8004cea: b672 cpsid i
8004cec: f383 8811 msr BASEPRI, r3
8004cf0: f3bf 8f6f isb sy
8004cf4: f3bf 8f4f dsb sy
8004cf8: b662 cpsie i
8004cfa: 60bb str r3, [r7, #8]
}
8004cfc: bf00 nop
8004cfe: bf00 nop
8004d00: e7fd b.n 8004cfe <vTaskDelay+0x32>
vTaskSuspendAll();
8004d02: f000 f887 bl 8004e14 <vTaskSuspendAll>
list or removed from the blocked list until the scheduler
is resumed.
This task cannot be in an event list as it is the currently
executing task. */
prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
8004d06: 2100 movs r1, #0
8004d08: 6878 ldr r0, [r7, #4]
8004d0a: f000 fd0d bl 8005728 <prvAddCurrentTaskToDelayedList>
}
xAlreadyYielded = xTaskResumeAll();
8004d0e: f000 f88f bl 8004e30 <xTaskResumeAll>
8004d12: 60f8 str r0, [r7, #12]
mtCOVERAGE_TEST_MARKER();
}
/* Force a reschedule if xTaskResumeAll has not already done so, we may
have put ourselves to sleep. */
if( xAlreadyYielded == pdFALSE )
8004d14: 68fb ldr r3, [r7, #12]
8004d16: 2b00 cmp r3, #0
8004d18: d107 bne.n 8004d2a <vTaskDelay+0x5e>
{
portYIELD_WITHIN_API();
8004d1a: 4b07 ldr r3, [pc, #28] @ (8004d38 <vTaskDelay+0x6c>)
8004d1c: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8004d20: 601a str r2, [r3, #0]
8004d22: f3bf 8f4f dsb sy
8004d26: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8004d2a: bf00 nop
8004d2c: 3710 adds r7, #16
8004d2e: 46bd mov sp, r7
8004d30: bd80 pop {r7, pc}
8004d32: bf00 nop
8004d34: 20001364 .word 0x20001364
8004d38: e000ed04 .word 0xe000ed04
08004d3c <vTaskStartScheduler>:
#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
/*-----------------------------------------------------------*/
void vTaskStartScheduler( void )
{
8004d3c: b580 push {r7, lr}
8004d3e: b08a sub sp, #40 @ 0x28
8004d40: af04 add r7, sp, #16
BaseType_t xReturn;
/* Add the idle task at the lowest priority. */
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
{
StaticTask_t *pxIdleTaskTCBBuffer = NULL;
8004d42: 2300 movs r3, #0
8004d44: 60bb str r3, [r7, #8]
StackType_t *pxIdleTaskStackBuffer = NULL;
8004d46: 2300 movs r3, #0
8004d48: 607b str r3, [r7, #4]
uint32_t ulIdleTaskStackSize;
/* The Idle task is created using user provided RAM - obtain the
address of the RAM then create the idle task. */
vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
8004d4a: 463a mov r2, r7
8004d4c: 1d39 adds r1, r7, #4
8004d4e: f107 0308 add.w r3, r7, #8
8004d52: 4618 mov r0, r3
8004d54: f7ff f80a bl 8003d6c <vApplicationGetIdleTaskMemory>
xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
8004d58: 6839 ldr r1, [r7, #0]
8004d5a: 687b ldr r3, [r7, #4]
8004d5c: 68ba ldr r2, [r7, #8]
8004d5e: 9202 str r2, [sp, #8]
8004d60: 9301 str r3, [sp, #4]
8004d62: 2300 movs r3, #0
8004d64: 9300 str r3, [sp, #0]
8004d66: 2300 movs r3, #0
8004d68: 460a mov r2, r1
8004d6a: 4924 ldr r1, [pc, #144] @ (8004dfc <vTaskStartScheduler+0xc0>)
8004d6c: 4824 ldr r0, [pc, #144] @ (8004e00 <vTaskStartScheduler+0xc4>)
8004d6e: f7ff fdff bl 8004970 <xTaskCreateStatic>
8004d72: 4603 mov r3, r0
8004d74: 4a23 ldr r2, [pc, #140] @ (8004e04 <vTaskStartScheduler+0xc8>)
8004d76: 6013 str r3, [r2, #0]
( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
pxIdleTaskStackBuffer,
pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
if( xIdleTaskHandle != NULL )
8004d78: 4b22 ldr r3, [pc, #136] @ (8004e04 <vTaskStartScheduler+0xc8>)
8004d7a: 681b ldr r3, [r3, #0]
8004d7c: 2b00 cmp r3, #0
8004d7e: d002 beq.n 8004d86 <vTaskStartScheduler+0x4a>
{
xReturn = pdPASS;
8004d80: 2301 movs r3, #1
8004d82: 617b str r3, [r7, #20]
8004d84: e001 b.n 8004d8a <vTaskStartScheduler+0x4e>
}
else
{
xReturn = pdFAIL;
8004d86: 2300 movs r3, #0
8004d88: 617b str r3, [r7, #20]
}
#endif /* configSUPPORT_STATIC_ALLOCATION */
#if ( configUSE_TIMERS == 1 )
{
if( xReturn == pdPASS )
8004d8a: 697b ldr r3, [r7, #20]
8004d8c: 2b01 cmp r3, #1
8004d8e: d102 bne.n 8004d96 <vTaskStartScheduler+0x5a>
{
xReturn = xTimerCreateTimerTask();
8004d90: f000 fd1e bl 80057d0 <xTimerCreateTimerTask>
8004d94: 6178 str r0, [r7, #20]
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_TIMERS */
if( xReturn == pdPASS )
8004d96: 697b ldr r3, [r7, #20]
8004d98: 2b01 cmp r3, #1
8004d9a: d118 bne.n 8004dce <vTaskStartScheduler+0x92>
__asm volatile
8004d9c: f04f 0350 mov.w r3, #80 @ 0x50
8004da0: b672 cpsid i
8004da2: f383 8811 msr BASEPRI, r3
8004da6: f3bf 8f6f isb sy
8004daa: f3bf 8f4f dsb sy
8004dae: b662 cpsie i
8004db0: 613b str r3, [r7, #16]
}
8004db2: bf00 nop
structure specific to the task that will run first. */
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
}
#endif /* configUSE_NEWLIB_REENTRANT */
xNextTaskUnblockTime = portMAX_DELAY;
8004db4: 4b14 ldr r3, [pc, #80] @ (8004e08 <vTaskStartScheduler+0xcc>)
8004db6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8004dba: 601a str r2, [r3, #0]
xSchedulerRunning = pdTRUE;
8004dbc: 4b13 ldr r3, [pc, #76] @ (8004e0c <vTaskStartScheduler+0xd0>)
8004dbe: 2201 movs r2, #1
8004dc0: 601a str r2, [r3, #0]
xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
8004dc2: 4b13 ldr r3, [pc, #76] @ (8004e10 <vTaskStartScheduler+0xd4>)
8004dc4: 2200 movs r2, #0
8004dc6: 601a str r2, [r3, #0]
traceTASK_SWITCHED_IN();
/* Setting up the timer tick is hardware specific and thus in the
portable interface. */
if( xPortStartScheduler() != pdFALSE )
8004dc8: f001 f8fa bl 8005fc0 <xPortStartScheduler>
}
/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
meaning xIdleTaskHandle is not used anywhere else. */
( void ) xIdleTaskHandle;
}
8004dcc: e011 b.n 8004df2 <vTaskStartScheduler+0xb6>
configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
8004dce: 697b ldr r3, [r7, #20]
8004dd0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8004dd4: d10d bne.n 8004df2 <vTaskStartScheduler+0xb6>
__asm volatile
8004dd6: f04f 0350 mov.w r3, #80 @ 0x50
8004dda: b672 cpsid i
8004ddc: f383 8811 msr BASEPRI, r3
8004de0: f3bf 8f6f isb sy
8004de4: f3bf 8f4f dsb sy
8004de8: b662 cpsie i
8004dea: 60fb str r3, [r7, #12]
}
8004dec: bf00 nop
8004dee: bf00 nop
8004df0: e7fd b.n 8004dee <vTaskStartScheduler+0xb2>
}
8004df2: bf00 nop
8004df4: 3718 adds r7, #24
8004df6: 46bd mov sp, r7
8004df8: bd80 pop {r7, pc}
8004dfa: bf00 nop
8004dfc: 080075c8 .word 0x080075c8
8004e00: 08005455 .word 0x08005455
8004e04: 20001360 .word 0x20001360
8004e08: 2000135c .word 0x2000135c
8004e0c: 20001348 .word 0x20001348
8004e10: 20001340 .word 0x20001340
08004e14 <vTaskSuspendAll>:
vPortEndScheduler();
}
/*----------------------------------------------------------*/
void vTaskSuspendAll( void )
{
8004e14: b480 push {r7}
8004e16: af00 add r7, sp, #0
/* A critical section is not required as the variable is of type
BaseType_t. Please read Richard Barry's reply in the following link to a
post in the FreeRTOS support forum before reporting this as a bug! -
http://goo.gl/wu4acr */
++uxSchedulerSuspended;
8004e18: 4b04 ldr r3, [pc, #16] @ (8004e2c <vTaskSuspendAll+0x18>)
8004e1a: 681b ldr r3, [r3, #0]
8004e1c: 3301 adds r3, #1
8004e1e: 4a03 ldr r2, [pc, #12] @ (8004e2c <vTaskSuspendAll+0x18>)
8004e20: 6013 str r3, [r2, #0]
portMEMORY_BARRIER();
}
8004e22: bf00 nop
8004e24: 46bd mov sp, r7
8004e26: f85d 7b04 ldr.w r7, [sp], #4
8004e2a: 4770 bx lr
8004e2c: 20001364 .word 0x20001364
08004e30 <xTaskResumeAll>:
#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/
BaseType_t xTaskResumeAll( void )
{
8004e30: b580 push {r7, lr}
8004e32: b084 sub sp, #16
8004e34: af00 add r7, sp, #0
TCB_t *pxTCB = NULL;
8004e36: 2300 movs r3, #0
8004e38: 60fb str r3, [r7, #12]
BaseType_t xAlreadyYielded = pdFALSE;
8004e3a: 2300 movs r3, #0
8004e3c: 60bb str r3, [r7, #8]
/* If uxSchedulerSuspended is zero then this function does not match a
previous call to vTaskSuspendAll(). */
configASSERT( uxSchedulerSuspended );
8004e3e: 4b43 ldr r3, [pc, #268] @ (8004f4c <xTaskResumeAll+0x11c>)
8004e40: 681b ldr r3, [r3, #0]
8004e42: 2b00 cmp r3, #0
8004e44: d10d bne.n 8004e62 <xTaskResumeAll+0x32>
__asm volatile
8004e46: f04f 0350 mov.w r3, #80 @ 0x50
8004e4a: b672 cpsid i
8004e4c: f383 8811 msr BASEPRI, r3
8004e50: f3bf 8f6f isb sy
8004e54: f3bf 8f4f dsb sy
8004e58: b662 cpsie i
8004e5a: 603b str r3, [r7, #0]
}
8004e5c: bf00 nop
8004e5e: bf00 nop
8004e60: e7fd b.n 8004e5e <xTaskResumeAll+0x2e>
/* It is possible that an ISR caused a task to be removed from an event
list while the scheduler was suspended. If this was the case then the
removed task will have been added to the xPendingReadyList. Once the
scheduler has been resumed it is safe to move all the pending ready
tasks from this list into their appropriate ready list. */
taskENTER_CRITICAL();
8004e62: f001 f92b bl 80060bc <vPortEnterCritical>
{
--uxSchedulerSuspended;
8004e66: 4b39 ldr r3, [pc, #228] @ (8004f4c <xTaskResumeAll+0x11c>)
8004e68: 681b ldr r3, [r3, #0]
8004e6a: 3b01 subs r3, #1
8004e6c: 4a37 ldr r2, [pc, #220] @ (8004f4c <xTaskResumeAll+0x11c>)
8004e6e: 6013 str r3, [r2, #0]
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8004e70: 4b36 ldr r3, [pc, #216] @ (8004f4c <xTaskResumeAll+0x11c>)
8004e72: 681b ldr r3, [r3, #0]
8004e74: 2b00 cmp r3, #0
8004e76: d162 bne.n 8004f3e <xTaskResumeAll+0x10e>
{
if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
8004e78: 4b35 ldr r3, [pc, #212] @ (8004f50 <xTaskResumeAll+0x120>)
8004e7a: 681b ldr r3, [r3, #0]
8004e7c: 2b00 cmp r3, #0
8004e7e: d05e beq.n 8004f3e <xTaskResumeAll+0x10e>
{
/* Move any readied tasks from the pending list into the
appropriate ready list. */
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
8004e80: e02f b.n 8004ee2 <xTaskResumeAll+0xb2>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8004e82: 4b34 ldr r3, [pc, #208] @ (8004f54 <xTaskResumeAll+0x124>)
8004e84: 68db ldr r3, [r3, #12]
8004e86: 68db ldr r3, [r3, #12]
8004e88: 60fb str r3, [r7, #12]
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
8004e8a: 68fb ldr r3, [r7, #12]
8004e8c: 3318 adds r3, #24
8004e8e: 4618 mov r0, r3
8004e90: f7ff f82a bl 8003ee8 <uxListRemove>
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
8004e94: 68fb ldr r3, [r7, #12]
8004e96: 3304 adds r3, #4
8004e98: 4618 mov r0, r3
8004e9a: f7ff f825 bl 8003ee8 <uxListRemove>
prvAddTaskToReadyList( pxTCB );
8004e9e: 68fb ldr r3, [r7, #12]
8004ea0: 6ada ldr r2, [r3, #44] @ 0x2c
8004ea2: 4b2d ldr r3, [pc, #180] @ (8004f58 <xTaskResumeAll+0x128>)
8004ea4: 681b ldr r3, [r3, #0]
8004ea6: 429a cmp r2, r3
8004ea8: d903 bls.n 8004eb2 <xTaskResumeAll+0x82>
8004eaa: 68fb ldr r3, [r7, #12]
8004eac: 6adb ldr r3, [r3, #44] @ 0x2c
8004eae: 4a2a ldr r2, [pc, #168] @ (8004f58 <xTaskResumeAll+0x128>)
8004eb0: 6013 str r3, [r2, #0]
8004eb2: 68fb ldr r3, [r7, #12]
8004eb4: 6ada ldr r2, [r3, #44] @ 0x2c
8004eb6: 4613 mov r3, r2
8004eb8: 009b lsls r3, r3, #2
8004eba: 4413 add r3, r2
8004ebc: 009b lsls r3, r3, #2
8004ebe: 4a27 ldr r2, [pc, #156] @ (8004f5c <xTaskResumeAll+0x12c>)
8004ec0: 441a add r2, r3
8004ec2: 68fb ldr r3, [r7, #12]
8004ec4: 3304 adds r3, #4
8004ec6: 4619 mov r1, r3
8004ec8: 4610 mov r0, r2
8004eca: f7fe ffb0 bl 8003e2e <vListInsertEnd>
/* If the moved task has a priority higher than the current
task then a yield must be performed. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
8004ece: 68fb ldr r3, [r7, #12]
8004ed0: 6ada ldr r2, [r3, #44] @ 0x2c
8004ed2: 4b23 ldr r3, [pc, #140] @ (8004f60 <xTaskResumeAll+0x130>)
8004ed4: 681b ldr r3, [r3, #0]
8004ed6: 6adb ldr r3, [r3, #44] @ 0x2c
8004ed8: 429a cmp r2, r3
8004eda: d302 bcc.n 8004ee2 <xTaskResumeAll+0xb2>
{
xYieldPending = pdTRUE;
8004edc: 4b21 ldr r3, [pc, #132] @ (8004f64 <xTaskResumeAll+0x134>)
8004ede: 2201 movs r2, #1
8004ee0: 601a str r2, [r3, #0]
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
8004ee2: 4b1c ldr r3, [pc, #112] @ (8004f54 <xTaskResumeAll+0x124>)
8004ee4: 681b ldr r3, [r3, #0]
8004ee6: 2b00 cmp r3, #0
8004ee8: d1cb bne.n 8004e82 <xTaskResumeAll+0x52>
{
mtCOVERAGE_TEST_MARKER();
}
}
if( pxTCB != NULL )
8004eea: 68fb ldr r3, [r7, #12]
8004eec: 2b00 cmp r3, #0
8004eee: d001 beq.n 8004ef4 <xTaskResumeAll+0xc4>
which may have prevented the next unblock time from being
re-calculated, in which case re-calculate it now. Mainly
important for low power tickless implementations, where
this can prevent an unnecessary exit from low power
state. */
prvResetNextTaskUnblockTime();
8004ef0: f000 fb68 bl 80055c4 <prvResetNextTaskUnblockTime>
/* If any ticks occurred while the scheduler was suspended then
they should be processed now. This ensures the tick count does
not slip, and that any delayed tasks are resumed at the correct
time. */
{
UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */
8004ef4: 4b1c ldr r3, [pc, #112] @ (8004f68 <xTaskResumeAll+0x138>)
8004ef6: 681b ldr r3, [r3, #0]
8004ef8: 607b str r3, [r7, #4]
if( uxPendedCounts > ( UBaseType_t ) 0U )
8004efa: 687b ldr r3, [r7, #4]
8004efc: 2b00 cmp r3, #0
8004efe: d010 beq.n 8004f22 <xTaskResumeAll+0xf2>
{
do
{
if( xTaskIncrementTick() != pdFALSE )
8004f00: f000 f846 bl 8004f90 <xTaskIncrementTick>
8004f04: 4603 mov r3, r0
8004f06: 2b00 cmp r3, #0
8004f08: d002 beq.n 8004f10 <xTaskResumeAll+0xe0>
{
xYieldPending = pdTRUE;
8004f0a: 4b16 ldr r3, [pc, #88] @ (8004f64 <xTaskResumeAll+0x134>)
8004f0c: 2201 movs r2, #1
8004f0e: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
--uxPendedCounts;
8004f10: 687b ldr r3, [r7, #4]
8004f12: 3b01 subs r3, #1
8004f14: 607b str r3, [r7, #4]
} while( uxPendedCounts > ( UBaseType_t ) 0U );
8004f16: 687b ldr r3, [r7, #4]
8004f18: 2b00 cmp r3, #0
8004f1a: d1f1 bne.n 8004f00 <xTaskResumeAll+0xd0>
uxPendedTicks = 0;
8004f1c: 4b12 ldr r3, [pc, #72] @ (8004f68 <xTaskResumeAll+0x138>)
8004f1e: 2200 movs r2, #0
8004f20: 601a str r2, [r3, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
if( xYieldPending != pdFALSE )
8004f22: 4b10 ldr r3, [pc, #64] @ (8004f64 <xTaskResumeAll+0x134>)
8004f24: 681b ldr r3, [r3, #0]
8004f26: 2b00 cmp r3, #0
8004f28: d009 beq.n 8004f3e <xTaskResumeAll+0x10e>
{
#if( configUSE_PREEMPTION != 0 )
{
xAlreadyYielded = pdTRUE;
8004f2a: 2301 movs r3, #1
8004f2c: 60bb str r3, [r7, #8]
}
#endif
taskYIELD_IF_USING_PREEMPTION();
8004f2e: 4b0f ldr r3, [pc, #60] @ (8004f6c <xTaskResumeAll+0x13c>)
8004f30: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8004f34: 601a str r2, [r3, #0]
8004f36: f3bf 8f4f dsb sy
8004f3a: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
8004f3e: f001 f8f3 bl 8006128 <vPortExitCritical>
return xAlreadyYielded;
8004f42: 68bb ldr r3, [r7, #8]
}
8004f44: 4618 mov r0, r3
8004f46: 3710 adds r7, #16
8004f48: 46bd mov sp, r7
8004f4a: bd80 pop {r7, pc}
8004f4c: 20001364 .word 0x20001364
8004f50: 2000133c .word 0x2000133c
8004f54: 200012fc .word 0x200012fc
8004f58: 20001344 .word 0x20001344
8004f5c: 20000e6c .word 0x20000e6c
8004f60: 20000e68 .word 0x20000e68
8004f64: 20001350 .word 0x20001350
8004f68: 2000134c .word 0x2000134c
8004f6c: e000ed04 .word 0xe000ed04
08004f70 <xTaskGetTickCount>:
/*-----------------------------------------------------------*/
TickType_t xTaskGetTickCount( void )
{
8004f70: b480 push {r7}
8004f72: b083 sub sp, #12
8004f74: af00 add r7, sp, #0
TickType_t xTicks;
/* Critical section required if running on a 16 bit processor. */
portTICK_TYPE_ENTER_CRITICAL();
{
xTicks = xTickCount;
8004f76: 4b05 ldr r3, [pc, #20] @ (8004f8c <xTaskGetTickCount+0x1c>)
8004f78: 681b ldr r3, [r3, #0]
8004f7a: 607b str r3, [r7, #4]
}
portTICK_TYPE_EXIT_CRITICAL();
return xTicks;
8004f7c: 687b ldr r3, [r7, #4]
}
8004f7e: 4618 mov r0, r3
8004f80: 370c adds r7, #12
8004f82: 46bd mov sp, r7
8004f84: f85d 7b04 ldr.w r7, [sp], #4
8004f88: 4770 bx lr
8004f8a: bf00 nop
8004f8c: 20001340 .word 0x20001340
08004f90 <xTaskIncrementTick>:
#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/
BaseType_t xTaskIncrementTick( void )
{
8004f90: b580 push {r7, lr}
8004f92: b086 sub sp, #24
8004f94: af00 add r7, sp, #0
TCB_t * pxTCB;
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
8004f96: 2300 movs r3, #0
8004f98: 617b str r3, [r7, #20]
/* Called by the portable layer each time a tick interrupt occurs.
Increments the tick then checks to see if the new tick value will cause any
tasks to be unblocked. */
traceTASK_INCREMENT_TICK( xTickCount );
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8004f9a: 4b50 ldr r3, [pc, #320] @ (80050dc <xTaskIncrementTick+0x14c>)
8004f9c: 681b ldr r3, [r3, #0]
8004f9e: 2b00 cmp r3, #0
8004fa0: f040 808c bne.w 80050bc <xTaskIncrementTick+0x12c>
{
/* Minor optimisation. The tick count cannot change in this
block. */
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
8004fa4: 4b4e ldr r3, [pc, #312] @ (80050e0 <xTaskIncrementTick+0x150>)
8004fa6: 681b ldr r3, [r3, #0]
8004fa8: 3301 adds r3, #1
8004faa: 613b str r3, [r7, #16]
/* Increment the RTOS tick, switching the delayed and overflowed
delayed lists if it wraps to 0. */
xTickCount = xConstTickCount;
8004fac: 4a4c ldr r2, [pc, #304] @ (80050e0 <xTaskIncrementTick+0x150>)
8004fae: 693b ldr r3, [r7, #16]
8004fb0: 6013 str r3, [r2, #0]
if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
8004fb2: 693b ldr r3, [r7, #16]
8004fb4: 2b00 cmp r3, #0
8004fb6: d123 bne.n 8005000 <xTaskIncrementTick+0x70>
{
taskSWITCH_DELAYED_LISTS();
8004fb8: 4b4a ldr r3, [pc, #296] @ (80050e4 <xTaskIncrementTick+0x154>)
8004fba: 681b ldr r3, [r3, #0]
8004fbc: 681b ldr r3, [r3, #0]
8004fbe: 2b00 cmp r3, #0
8004fc0: d00d beq.n 8004fde <xTaskIncrementTick+0x4e>
__asm volatile
8004fc2: f04f 0350 mov.w r3, #80 @ 0x50
8004fc6: b672 cpsid i
8004fc8: f383 8811 msr BASEPRI, r3
8004fcc: f3bf 8f6f isb sy
8004fd0: f3bf 8f4f dsb sy
8004fd4: b662 cpsie i
8004fd6: 603b str r3, [r7, #0]
}
8004fd8: bf00 nop
8004fda: bf00 nop
8004fdc: e7fd b.n 8004fda <xTaskIncrementTick+0x4a>
8004fde: 4b41 ldr r3, [pc, #260] @ (80050e4 <xTaskIncrementTick+0x154>)
8004fe0: 681b ldr r3, [r3, #0]
8004fe2: 60fb str r3, [r7, #12]
8004fe4: 4b40 ldr r3, [pc, #256] @ (80050e8 <xTaskIncrementTick+0x158>)
8004fe6: 681b ldr r3, [r3, #0]
8004fe8: 4a3e ldr r2, [pc, #248] @ (80050e4 <xTaskIncrementTick+0x154>)
8004fea: 6013 str r3, [r2, #0]
8004fec: 4a3e ldr r2, [pc, #248] @ (80050e8 <xTaskIncrementTick+0x158>)
8004fee: 68fb ldr r3, [r7, #12]
8004ff0: 6013 str r3, [r2, #0]
8004ff2: 4b3e ldr r3, [pc, #248] @ (80050ec <xTaskIncrementTick+0x15c>)
8004ff4: 681b ldr r3, [r3, #0]
8004ff6: 3301 adds r3, #1
8004ff8: 4a3c ldr r2, [pc, #240] @ (80050ec <xTaskIncrementTick+0x15c>)
8004ffa: 6013 str r3, [r2, #0]
8004ffc: f000 fae2 bl 80055c4 <prvResetNextTaskUnblockTime>
/* See if this tick has made a timeout expire. Tasks are stored in
the queue in the order of their wake time - meaning once one task
has been found whose block time has not expired there is no need to
look any further down the list. */
if( xConstTickCount >= xNextTaskUnblockTime )
8005000: 4b3b ldr r3, [pc, #236] @ (80050f0 <xTaskIncrementTick+0x160>)
8005002: 681b ldr r3, [r3, #0]
8005004: 693a ldr r2, [r7, #16]
8005006: 429a cmp r2, r3
8005008: d349 bcc.n 800509e <xTaskIncrementTick+0x10e>
{
for( ;; )
{
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
800500a: 4b36 ldr r3, [pc, #216] @ (80050e4 <xTaskIncrementTick+0x154>)
800500c: 681b ldr r3, [r3, #0]
800500e: 681b ldr r3, [r3, #0]
8005010: 2b00 cmp r3, #0
8005012: d104 bne.n 800501e <xTaskIncrementTick+0x8e>
/* The delayed list is empty. Set xNextTaskUnblockTime
to the maximum possible value so it is extremely
unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass
next time through. */
xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8005014: 4b36 ldr r3, [pc, #216] @ (80050f0 <xTaskIncrementTick+0x160>)
8005016: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
800501a: 601a str r2, [r3, #0]
break;
800501c: e03f b.n 800509e <xTaskIncrementTick+0x10e>
{
/* The delayed list is not empty, get the value of the
item at the head of the delayed list. This is the time
at which the task at the head of the delayed list must
be removed from the Blocked state. */
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800501e: 4b31 ldr r3, [pc, #196] @ (80050e4 <xTaskIncrementTick+0x154>)
8005020: 681b ldr r3, [r3, #0]
8005022: 68db ldr r3, [r3, #12]
8005024: 68db ldr r3, [r3, #12]
8005026: 60bb str r3, [r7, #8]
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
8005028: 68bb ldr r3, [r7, #8]
800502a: 685b ldr r3, [r3, #4]
800502c: 607b str r3, [r7, #4]
if( xConstTickCount < xItemValue )
800502e: 693a ldr r2, [r7, #16]
8005030: 687b ldr r3, [r7, #4]
8005032: 429a cmp r2, r3
8005034: d203 bcs.n 800503e <xTaskIncrementTick+0xae>
/* It is not time to unblock this item yet, but the
item value is the time at which the task at the head
of the blocked list must be removed from the Blocked
state - so record the item value in
xNextTaskUnblockTime. */
xNextTaskUnblockTime = xItemValue;
8005036: 4a2e ldr r2, [pc, #184] @ (80050f0 <xTaskIncrementTick+0x160>)
8005038: 687b ldr r3, [r7, #4]
800503a: 6013 str r3, [r2, #0]
break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
800503c: e02f b.n 800509e <xTaskIncrementTick+0x10e>
{
mtCOVERAGE_TEST_MARKER();
}
/* It is time to remove the item from the Blocked state. */
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
800503e: 68bb ldr r3, [r7, #8]
8005040: 3304 adds r3, #4
8005042: 4618 mov r0, r3
8005044: f7fe ff50 bl 8003ee8 <uxListRemove>
/* Is the task waiting on an event also? If so remove
it from the event list. */
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
8005048: 68bb ldr r3, [r7, #8]
800504a: 6a9b ldr r3, [r3, #40] @ 0x28
800504c: 2b00 cmp r3, #0
800504e: d004 beq.n 800505a <xTaskIncrementTick+0xca>
{
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
8005050: 68bb ldr r3, [r7, #8]
8005052: 3318 adds r3, #24
8005054: 4618 mov r0, r3
8005056: f7fe ff47 bl 8003ee8 <uxListRemove>
mtCOVERAGE_TEST_MARKER();
}
/* Place the unblocked task into the appropriate ready
list. */
prvAddTaskToReadyList( pxTCB );
800505a: 68bb ldr r3, [r7, #8]
800505c: 6ada ldr r2, [r3, #44] @ 0x2c
800505e: 4b25 ldr r3, [pc, #148] @ (80050f4 <xTaskIncrementTick+0x164>)
8005060: 681b ldr r3, [r3, #0]
8005062: 429a cmp r2, r3
8005064: d903 bls.n 800506e <xTaskIncrementTick+0xde>
8005066: 68bb ldr r3, [r7, #8]
8005068: 6adb ldr r3, [r3, #44] @ 0x2c
800506a: 4a22 ldr r2, [pc, #136] @ (80050f4 <xTaskIncrementTick+0x164>)
800506c: 6013 str r3, [r2, #0]
800506e: 68bb ldr r3, [r7, #8]
8005070: 6ada ldr r2, [r3, #44] @ 0x2c
8005072: 4613 mov r3, r2
8005074: 009b lsls r3, r3, #2
8005076: 4413 add r3, r2
8005078: 009b lsls r3, r3, #2
800507a: 4a1f ldr r2, [pc, #124] @ (80050f8 <xTaskIncrementTick+0x168>)
800507c: 441a add r2, r3
800507e: 68bb ldr r3, [r7, #8]
8005080: 3304 adds r3, #4
8005082: 4619 mov r1, r3
8005084: 4610 mov r0, r2
8005086: f7fe fed2 bl 8003e2e <vListInsertEnd>
{
/* Preemption is on, but a context switch should
only be performed if the unblocked task has a
priority that is equal to or higher than the
currently executing task. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
800508a: 68bb ldr r3, [r7, #8]
800508c: 6ada ldr r2, [r3, #44] @ 0x2c
800508e: 4b1b ldr r3, [pc, #108] @ (80050fc <xTaskIncrementTick+0x16c>)
8005090: 681b ldr r3, [r3, #0]
8005092: 6adb ldr r3, [r3, #44] @ 0x2c
8005094: 429a cmp r2, r3
8005096: d3b8 bcc.n 800500a <xTaskIncrementTick+0x7a>
{
xSwitchRequired = pdTRUE;
8005098: 2301 movs r3, #1
800509a: 617b str r3, [r7, #20]
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
800509c: e7b5 b.n 800500a <xTaskIncrementTick+0x7a>
/* Tasks of equal priority to the currently running task will share
processing time (time slice) if preemption is on, and the application
writer has not explicitly turned time slicing off. */
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
{
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
800509e: 4b17 ldr r3, [pc, #92] @ (80050fc <xTaskIncrementTick+0x16c>)
80050a0: 681b ldr r3, [r3, #0]
80050a2: 6ada ldr r2, [r3, #44] @ 0x2c
80050a4: 4914 ldr r1, [pc, #80] @ (80050f8 <xTaskIncrementTick+0x168>)
80050a6: 4613 mov r3, r2
80050a8: 009b lsls r3, r3, #2
80050aa: 4413 add r3, r2
80050ac: 009b lsls r3, r3, #2
80050ae: 440b add r3, r1
80050b0: 681b ldr r3, [r3, #0]
80050b2: 2b01 cmp r3, #1
80050b4: d907 bls.n 80050c6 <xTaskIncrementTick+0x136>
{
xSwitchRequired = pdTRUE;
80050b6: 2301 movs r3, #1
80050b8: 617b str r3, [r7, #20]
80050ba: e004 b.n 80050c6 <xTaskIncrementTick+0x136>
}
#endif /* configUSE_TICK_HOOK */
}
else
{
++uxPendedTicks;
80050bc: 4b10 ldr r3, [pc, #64] @ (8005100 <xTaskIncrementTick+0x170>)
80050be: 681b ldr r3, [r3, #0]
80050c0: 3301 adds r3, #1
80050c2: 4a0f ldr r2, [pc, #60] @ (8005100 <xTaskIncrementTick+0x170>)
80050c4: 6013 str r3, [r2, #0]
#endif
}
#if ( configUSE_PREEMPTION == 1 )
{
if( xYieldPending != pdFALSE )
80050c6: 4b0f ldr r3, [pc, #60] @ (8005104 <xTaskIncrementTick+0x174>)
80050c8: 681b ldr r3, [r3, #0]
80050ca: 2b00 cmp r3, #0
80050cc: d001 beq.n 80050d2 <xTaskIncrementTick+0x142>
{
xSwitchRequired = pdTRUE;
80050ce: 2301 movs r3, #1
80050d0: 617b str r3, [r7, #20]
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_PREEMPTION */
return xSwitchRequired;
80050d2: 697b ldr r3, [r7, #20]
}
80050d4: 4618 mov r0, r3
80050d6: 3718 adds r7, #24
80050d8: 46bd mov sp, r7
80050da: bd80 pop {r7, pc}
80050dc: 20001364 .word 0x20001364
80050e0: 20001340 .word 0x20001340
80050e4: 200012f4 .word 0x200012f4
80050e8: 200012f8 .word 0x200012f8
80050ec: 20001354 .word 0x20001354
80050f0: 2000135c .word 0x2000135c
80050f4: 20001344 .word 0x20001344
80050f8: 20000e6c .word 0x20000e6c
80050fc: 20000e68 .word 0x20000e68
8005100: 2000134c .word 0x2000134c
8005104: 20001350 .word 0x20001350
08005108 <vTaskSwitchContext>:
#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/
void vTaskSwitchContext( void )
{
8005108: b480 push {r7}
800510a: b085 sub sp, #20
800510c: af00 add r7, sp, #0
if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
800510e: 4b29 ldr r3, [pc, #164] @ (80051b4 <vTaskSwitchContext+0xac>)
8005110: 681b ldr r3, [r3, #0]
8005112: 2b00 cmp r3, #0
8005114: d003 beq.n 800511e <vTaskSwitchContext+0x16>
{
/* The scheduler is currently suspended - do not allow a context
switch. */
xYieldPending = pdTRUE;
8005116: 4b28 ldr r3, [pc, #160] @ (80051b8 <vTaskSwitchContext+0xb0>)
8005118: 2201 movs r2, #1
800511a: 601a str r2, [r3, #0]
structure specific to this task. */
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
}
#endif /* configUSE_NEWLIB_REENTRANT */
}
}
800511c: e044 b.n 80051a8 <vTaskSwitchContext+0xa0>
xYieldPending = pdFALSE;
800511e: 4b26 ldr r3, [pc, #152] @ (80051b8 <vTaskSwitchContext+0xb0>)
8005120: 2200 movs r2, #0
8005122: 601a str r2, [r3, #0]
taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8005124: 4b25 ldr r3, [pc, #148] @ (80051bc <vTaskSwitchContext+0xb4>)
8005126: 681b ldr r3, [r3, #0]
8005128: 60fb str r3, [r7, #12]
800512a: e013 b.n 8005154 <vTaskSwitchContext+0x4c>
800512c: 68fb ldr r3, [r7, #12]
800512e: 2b00 cmp r3, #0
8005130: d10d bne.n 800514e <vTaskSwitchContext+0x46>
__asm volatile
8005132: f04f 0350 mov.w r3, #80 @ 0x50
8005136: b672 cpsid i
8005138: f383 8811 msr BASEPRI, r3
800513c: f3bf 8f6f isb sy
8005140: f3bf 8f4f dsb sy
8005144: b662 cpsie i
8005146: 607b str r3, [r7, #4]
}
8005148: bf00 nop
800514a: bf00 nop
800514c: e7fd b.n 800514a <vTaskSwitchContext+0x42>
800514e: 68fb ldr r3, [r7, #12]
8005150: 3b01 subs r3, #1
8005152: 60fb str r3, [r7, #12]
8005154: 491a ldr r1, [pc, #104] @ (80051c0 <vTaskSwitchContext+0xb8>)
8005156: 68fa ldr r2, [r7, #12]
8005158: 4613 mov r3, r2
800515a: 009b lsls r3, r3, #2
800515c: 4413 add r3, r2
800515e: 009b lsls r3, r3, #2
8005160: 440b add r3, r1
8005162: 681b ldr r3, [r3, #0]
8005164: 2b00 cmp r3, #0
8005166: d0e1 beq.n 800512c <vTaskSwitchContext+0x24>
8005168: 68fa ldr r2, [r7, #12]
800516a: 4613 mov r3, r2
800516c: 009b lsls r3, r3, #2
800516e: 4413 add r3, r2
8005170: 009b lsls r3, r3, #2
8005172: 4a13 ldr r2, [pc, #76] @ (80051c0 <vTaskSwitchContext+0xb8>)
8005174: 4413 add r3, r2
8005176: 60bb str r3, [r7, #8]
8005178: 68bb ldr r3, [r7, #8]
800517a: 685b ldr r3, [r3, #4]
800517c: 685a ldr r2, [r3, #4]
800517e: 68bb ldr r3, [r7, #8]
8005180: 605a str r2, [r3, #4]
8005182: 68bb ldr r3, [r7, #8]
8005184: 685a ldr r2, [r3, #4]
8005186: 68bb ldr r3, [r7, #8]
8005188: 3308 adds r3, #8
800518a: 429a cmp r2, r3
800518c: d104 bne.n 8005198 <vTaskSwitchContext+0x90>
800518e: 68bb ldr r3, [r7, #8]
8005190: 685b ldr r3, [r3, #4]
8005192: 685a ldr r2, [r3, #4]
8005194: 68bb ldr r3, [r7, #8]
8005196: 605a str r2, [r3, #4]
8005198: 68bb ldr r3, [r7, #8]
800519a: 685b ldr r3, [r3, #4]
800519c: 68db ldr r3, [r3, #12]
800519e: 4a09 ldr r2, [pc, #36] @ (80051c4 <vTaskSwitchContext+0xbc>)
80051a0: 6013 str r3, [r2, #0]
80051a2: 4a06 ldr r2, [pc, #24] @ (80051bc <vTaskSwitchContext+0xb4>)
80051a4: 68fb ldr r3, [r7, #12]
80051a6: 6013 str r3, [r2, #0]
}
80051a8: bf00 nop
80051aa: 3714 adds r7, #20
80051ac: 46bd mov sp, r7
80051ae: f85d 7b04 ldr.w r7, [sp], #4
80051b2: 4770 bx lr
80051b4: 20001364 .word 0x20001364
80051b8: 20001350 .word 0x20001350
80051bc: 20001344 .word 0x20001344
80051c0: 20000e6c .word 0x20000e6c
80051c4: 20000e68 .word 0x20000e68
080051c8 <vTaskPlaceOnEventList>:
/*-----------------------------------------------------------*/
void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
{
80051c8: b580 push {r7, lr}
80051ca: b084 sub sp, #16
80051cc: af00 add r7, sp, #0
80051ce: 6078 str r0, [r7, #4]
80051d0: 6039 str r1, [r7, #0]
configASSERT( pxEventList );
80051d2: 687b ldr r3, [r7, #4]
80051d4: 2b00 cmp r3, #0
80051d6: d10d bne.n 80051f4 <vTaskPlaceOnEventList+0x2c>
__asm volatile
80051d8: f04f 0350 mov.w r3, #80 @ 0x50
80051dc: b672 cpsid i
80051de: f383 8811 msr BASEPRI, r3
80051e2: f3bf 8f6f isb sy
80051e6: f3bf 8f4f dsb sy
80051ea: b662 cpsie i
80051ec: 60fb str r3, [r7, #12]
}
80051ee: bf00 nop
80051f0: bf00 nop
80051f2: e7fd b.n 80051f0 <vTaskPlaceOnEventList+0x28>
/* Place the event list item of the TCB in the appropriate event list.
This is placed in the list in priority order so the highest priority task
is the first to be woken by the event. The queue that contains the event
list is locked, preventing simultaneous access from interrupts. */
vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
80051f4: 4b07 ldr r3, [pc, #28] @ (8005214 <vTaskPlaceOnEventList+0x4c>)
80051f6: 681b ldr r3, [r3, #0]
80051f8: 3318 adds r3, #24
80051fa: 4619 mov r1, r3
80051fc: 6878 ldr r0, [r7, #4]
80051fe: f7fe fe3a bl 8003e76 <vListInsert>
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
8005202: 2101 movs r1, #1
8005204: 6838 ldr r0, [r7, #0]
8005206: f000 fa8f bl 8005728 <prvAddCurrentTaskToDelayedList>
}
800520a: bf00 nop
800520c: 3710 adds r7, #16
800520e: 46bd mov sp, r7
8005210: bd80 pop {r7, pc}
8005212: bf00 nop
8005214: 20000e68 .word 0x20000e68
08005218 <vTaskPlaceOnEventListRestricted>:
/*-----------------------------------------------------------*/
#if( configUSE_TIMERS == 1 )
void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
{
8005218: b580 push {r7, lr}
800521a: b086 sub sp, #24
800521c: af00 add r7, sp, #0
800521e: 60f8 str r0, [r7, #12]
8005220: 60b9 str r1, [r7, #8]
8005222: 607a str r2, [r7, #4]
configASSERT( pxEventList );
8005224: 68fb ldr r3, [r7, #12]
8005226: 2b00 cmp r3, #0
8005228: d10d bne.n 8005246 <vTaskPlaceOnEventListRestricted+0x2e>
__asm volatile
800522a: f04f 0350 mov.w r3, #80 @ 0x50
800522e: b672 cpsid i
8005230: f383 8811 msr BASEPRI, r3
8005234: f3bf 8f6f isb sy
8005238: f3bf 8f4f dsb sy
800523c: b662 cpsie i
800523e: 617b str r3, [r7, #20]
}
8005240: bf00 nop
8005242: bf00 nop
8005244: e7fd b.n 8005242 <vTaskPlaceOnEventListRestricted+0x2a>
/* Place the event list item of the TCB in the appropriate event list.
In this case it is assume that this is the only task that is going to
be waiting on this event list, so the faster vListInsertEnd() function
can be used in place of vListInsert. */
vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
8005246: 4b0a ldr r3, [pc, #40] @ (8005270 <vTaskPlaceOnEventListRestricted+0x58>)
8005248: 681b ldr r3, [r3, #0]
800524a: 3318 adds r3, #24
800524c: 4619 mov r1, r3
800524e: 68f8 ldr r0, [r7, #12]
8005250: f7fe fded bl 8003e2e <vListInsertEnd>
/* If the task should block indefinitely then set the block time to a
value that will be recognised as an indefinite delay inside the
prvAddCurrentTaskToDelayedList() function. */
if( xWaitIndefinitely != pdFALSE )
8005254: 687b ldr r3, [r7, #4]
8005256: 2b00 cmp r3, #0
8005258: d002 beq.n 8005260 <vTaskPlaceOnEventListRestricted+0x48>
{
xTicksToWait = portMAX_DELAY;
800525a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
800525e: 60bb str r3, [r7, #8]
}
traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
8005260: 6879 ldr r1, [r7, #4]
8005262: 68b8 ldr r0, [r7, #8]
8005264: f000 fa60 bl 8005728 <prvAddCurrentTaskToDelayedList>
}
8005268: bf00 nop
800526a: 3718 adds r7, #24
800526c: 46bd mov sp, r7
800526e: bd80 pop {r7, pc}
8005270: 20000e68 .word 0x20000e68
08005274 <xTaskRemoveFromEventList>:
#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/
BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
{
8005274: b580 push {r7, lr}
8005276: b086 sub sp, #24
8005278: af00 add r7, sp, #0
800527a: 6078 str r0, [r7, #4]
get called - the lock count on the queue will get modified instead. This
means exclusive access to the event list is guaranteed here.
This function assumes that a check has already been made to ensure that
pxEventList is not empty. */
pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800527c: 687b ldr r3, [r7, #4]
800527e: 68db ldr r3, [r3, #12]
8005280: 68db ldr r3, [r3, #12]
8005282: 613b str r3, [r7, #16]
configASSERT( pxUnblockedTCB );
8005284: 693b ldr r3, [r7, #16]
8005286: 2b00 cmp r3, #0
8005288: d10d bne.n 80052a6 <xTaskRemoveFromEventList+0x32>
__asm volatile
800528a: f04f 0350 mov.w r3, #80 @ 0x50
800528e: b672 cpsid i
8005290: f383 8811 msr BASEPRI, r3
8005294: f3bf 8f6f isb sy
8005298: f3bf 8f4f dsb sy
800529c: b662 cpsie i
800529e: 60fb str r3, [r7, #12]
}
80052a0: bf00 nop
80052a2: bf00 nop
80052a4: e7fd b.n 80052a2 <xTaskRemoveFromEventList+0x2e>
( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
80052a6: 693b ldr r3, [r7, #16]
80052a8: 3318 adds r3, #24
80052aa: 4618 mov r0, r3
80052ac: f7fe fe1c bl 8003ee8 <uxListRemove>
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
80052b0: 4b1d ldr r3, [pc, #116] @ (8005328 <xTaskRemoveFromEventList+0xb4>)
80052b2: 681b ldr r3, [r3, #0]
80052b4: 2b00 cmp r3, #0
80052b6: d11d bne.n 80052f4 <xTaskRemoveFromEventList+0x80>
{
( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
80052b8: 693b ldr r3, [r7, #16]
80052ba: 3304 adds r3, #4
80052bc: 4618 mov r0, r3
80052be: f7fe fe13 bl 8003ee8 <uxListRemove>
prvAddTaskToReadyList( pxUnblockedTCB );
80052c2: 693b ldr r3, [r7, #16]
80052c4: 6ada ldr r2, [r3, #44] @ 0x2c
80052c6: 4b19 ldr r3, [pc, #100] @ (800532c <xTaskRemoveFromEventList+0xb8>)
80052c8: 681b ldr r3, [r3, #0]
80052ca: 429a cmp r2, r3
80052cc: d903 bls.n 80052d6 <xTaskRemoveFromEventList+0x62>
80052ce: 693b ldr r3, [r7, #16]
80052d0: 6adb ldr r3, [r3, #44] @ 0x2c
80052d2: 4a16 ldr r2, [pc, #88] @ (800532c <xTaskRemoveFromEventList+0xb8>)
80052d4: 6013 str r3, [r2, #0]
80052d6: 693b ldr r3, [r7, #16]
80052d8: 6ada ldr r2, [r3, #44] @ 0x2c
80052da: 4613 mov r3, r2
80052dc: 009b lsls r3, r3, #2
80052de: 4413 add r3, r2
80052e0: 009b lsls r3, r3, #2
80052e2: 4a13 ldr r2, [pc, #76] @ (8005330 <xTaskRemoveFromEventList+0xbc>)
80052e4: 441a add r2, r3
80052e6: 693b ldr r3, [r7, #16]
80052e8: 3304 adds r3, #4
80052ea: 4619 mov r1, r3
80052ec: 4610 mov r0, r2
80052ee: f7fe fd9e bl 8003e2e <vListInsertEnd>
80052f2: e005 b.n 8005300 <xTaskRemoveFromEventList+0x8c>
}
else
{
/* The delayed and ready lists cannot be accessed, so hold this task
pending until the scheduler is resumed. */
vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
80052f4: 693b ldr r3, [r7, #16]
80052f6: 3318 adds r3, #24
80052f8: 4619 mov r1, r3
80052fa: 480e ldr r0, [pc, #56] @ (8005334 <xTaskRemoveFromEventList+0xc0>)
80052fc: f7fe fd97 bl 8003e2e <vListInsertEnd>
}
if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
8005300: 693b ldr r3, [r7, #16]
8005302: 6ada ldr r2, [r3, #44] @ 0x2c
8005304: 4b0c ldr r3, [pc, #48] @ (8005338 <xTaskRemoveFromEventList+0xc4>)
8005306: 681b ldr r3, [r3, #0]
8005308: 6adb ldr r3, [r3, #44] @ 0x2c
800530a: 429a cmp r2, r3
800530c: d905 bls.n 800531a <xTaskRemoveFromEventList+0xa6>
{
/* Return true if the task removed from the event list has a higher
priority than the calling task. This allows the calling task to know if
it should force a context switch now. */
xReturn = pdTRUE;
800530e: 2301 movs r3, #1
8005310: 617b str r3, [r7, #20]
/* Mark that a yield is pending in case the user is not using the
"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
xYieldPending = pdTRUE;
8005312: 4b0a ldr r3, [pc, #40] @ (800533c <xTaskRemoveFromEventList+0xc8>)
8005314: 2201 movs r2, #1
8005316: 601a str r2, [r3, #0]
8005318: e001 b.n 800531e <xTaskRemoveFromEventList+0xaa>
}
else
{
xReturn = pdFALSE;
800531a: 2300 movs r3, #0
800531c: 617b str r3, [r7, #20]
}
return xReturn;
800531e: 697b ldr r3, [r7, #20]
}
8005320: 4618 mov r0, r3
8005322: 3718 adds r7, #24
8005324: 46bd mov sp, r7
8005326: bd80 pop {r7, pc}
8005328: 20001364 .word 0x20001364
800532c: 20001344 .word 0x20001344
8005330: 20000e6c .word 0x20000e6c
8005334: 200012fc .word 0x200012fc
8005338: 20000e68 .word 0x20000e68
800533c: 20001350 .word 0x20001350
08005340 <vTaskInternalSetTimeOutState>:
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
8005340: b480 push {r7}
8005342: b083 sub sp, #12
8005344: af00 add r7, sp, #0
8005346: 6078 str r0, [r7, #4]
/* For internal use only as it does not use a critical section. */
pxTimeOut->xOverflowCount = xNumOfOverflows;
8005348: 4b06 ldr r3, [pc, #24] @ (8005364 <vTaskInternalSetTimeOutState+0x24>)
800534a: 681a ldr r2, [r3, #0]
800534c: 687b ldr r3, [r7, #4]
800534e: 601a str r2, [r3, #0]
pxTimeOut->xTimeOnEntering = xTickCount;
8005350: 4b05 ldr r3, [pc, #20] @ (8005368 <vTaskInternalSetTimeOutState+0x28>)
8005352: 681a ldr r2, [r3, #0]
8005354: 687b ldr r3, [r7, #4]
8005356: 605a str r2, [r3, #4]
}
8005358: bf00 nop
800535a: 370c adds r7, #12
800535c: 46bd mov sp, r7
800535e: f85d 7b04 ldr.w r7, [sp], #4
8005362: 4770 bx lr
8005364: 20001354 .word 0x20001354
8005368: 20001340 .word 0x20001340
0800536c <xTaskCheckForTimeOut>:
/*-----------------------------------------------------------*/
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
{
800536c: b580 push {r7, lr}
800536e: b088 sub sp, #32
8005370: af00 add r7, sp, #0
8005372: 6078 str r0, [r7, #4]
8005374: 6039 str r1, [r7, #0]
BaseType_t xReturn;
configASSERT( pxTimeOut );
8005376: 687b ldr r3, [r7, #4]
8005378: 2b00 cmp r3, #0
800537a: d10d bne.n 8005398 <xTaskCheckForTimeOut+0x2c>
__asm volatile
800537c: f04f 0350 mov.w r3, #80 @ 0x50
8005380: b672 cpsid i
8005382: f383 8811 msr BASEPRI, r3
8005386: f3bf 8f6f isb sy
800538a: f3bf 8f4f dsb sy
800538e: b662 cpsie i
8005390: 613b str r3, [r7, #16]
}
8005392: bf00 nop
8005394: bf00 nop
8005396: e7fd b.n 8005394 <xTaskCheckForTimeOut+0x28>
configASSERT( pxTicksToWait );
8005398: 683b ldr r3, [r7, #0]
800539a: 2b00 cmp r3, #0
800539c: d10d bne.n 80053ba <xTaskCheckForTimeOut+0x4e>
__asm volatile
800539e: f04f 0350 mov.w r3, #80 @ 0x50
80053a2: b672 cpsid i
80053a4: f383 8811 msr BASEPRI, r3
80053a8: f3bf 8f6f isb sy
80053ac: f3bf 8f4f dsb sy
80053b0: b662 cpsie i
80053b2: 60fb str r3, [r7, #12]
}
80053b4: bf00 nop
80053b6: bf00 nop
80053b8: e7fd b.n 80053b6 <xTaskCheckForTimeOut+0x4a>
taskENTER_CRITICAL();
80053ba: f000 fe7f bl 80060bc <vPortEnterCritical>
{
/* Minor optimisation. The tick count cannot change in this block. */
const TickType_t xConstTickCount = xTickCount;
80053be: 4b1d ldr r3, [pc, #116] @ (8005434 <xTaskCheckForTimeOut+0xc8>)
80053c0: 681b ldr r3, [r3, #0]
80053c2: 61bb str r3, [r7, #24]
const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
80053c4: 687b ldr r3, [r7, #4]
80053c6: 685b ldr r3, [r3, #4]
80053c8: 69ba ldr r2, [r7, #24]
80053ca: 1ad3 subs r3, r2, r3
80053cc: 617b str r3, [r7, #20]
}
else
#endif
#if ( INCLUDE_vTaskSuspend == 1 )
if( *pxTicksToWait == portMAX_DELAY )
80053ce: 683b ldr r3, [r7, #0]
80053d0: 681b ldr r3, [r3, #0]
80053d2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80053d6: d102 bne.n 80053de <xTaskCheckForTimeOut+0x72>
{
/* If INCLUDE_vTaskSuspend is set to 1 and the block time
specified is the maximum block time then the task should block
indefinitely, and therefore never time out. */
xReturn = pdFALSE;
80053d8: 2300 movs r3, #0
80053da: 61fb str r3, [r7, #28]
80053dc: e023 b.n 8005426 <xTaskCheckForTimeOut+0xba>
}
else
#endif
if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
80053de: 687b ldr r3, [r7, #4]
80053e0: 681a ldr r2, [r3, #0]
80053e2: 4b15 ldr r3, [pc, #84] @ (8005438 <xTaskCheckForTimeOut+0xcc>)
80053e4: 681b ldr r3, [r3, #0]
80053e6: 429a cmp r2, r3
80053e8: d007 beq.n 80053fa <xTaskCheckForTimeOut+0x8e>
80053ea: 687b ldr r3, [r7, #4]
80053ec: 685b ldr r3, [r3, #4]
80053ee: 69ba ldr r2, [r7, #24]
80053f0: 429a cmp r2, r3
80053f2: d302 bcc.n 80053fa <xTaskCheckForTimeOut+0x8e>
/* The tick count is greater than the time at which
vTaskSetTimeout() was called, but has also overflowed since
vTaskSetTimeOut() was called. It must have wrapped all the way
around and gone past again. This passed since vTaskSetTimeout()
was called. */
xReturn = pdTRUE;
80053f4: 2301 movs r3, #1
80053f6: 61fb str r3, [r7, #28]
80053f8: e015 b.n 8005426 <xTaskCheckForTimeOut+0xba>
}
else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
80053fa: 683b ldr r3, [r7, #0]
80053fc: 681b ldr r3, [r3, #0]
80053fe: 697a ldr r2, [r7, #20]
8005400: 429a cmp r2, r3
8005402: d20b bcs.n 800541c <xTaskCheckForTimeOut+0xb0>
{
/* Not a genuine timeout. Adjust parameters for time remaining. */
*pxTicksToWait -= xElapsedTime;
8005404: 683b ldr r3, [r7, #0]
8005406: 681a ldr r2, [r3, #0]
8005408: 697b ldr r3, [r7, #20]
800540a: 1ad2 subs r2, r2, r3
800540c: 683b ldr r3, [r7, #0]
800540e: 601a str r2, [r3, #0]
vTaskInternalSetTimeOutState( pxTimeOut );
8005410: 6878 ldr r0, [r7, #4]
8005412: f7ff ff95 bl 8005340 <vTaskInternalSetTimeOutState>
xReturn = pdFALSE;
8005416: 2300 movs r3, #0
8005418: 61fb str r3, [r7, #28]
800541a: e004 b.n 8005426 <xTaskCheckForTimeOut+0xba>
}
else
{
*pxTicksToWait = 0;
800541c: 683b ldr r3, [r7, #0]
800541e: 2200 movs r2, #0
8005420: 601a str r2, [r3, #0]
xReturn = pdTRUE;
8005422: 2301 movs r3, #1
8005424: 61fb str r3, [r7, #28]
}
}
taskEXIT_CRITICAL();
8005426: f000 fe7f bl 8006128 <vPortExitCritical>
return xReturn;
800542a: 69fb ldr r3, [r7, #28]
}
800542c: 4618 mov r0, r3
800542e: 3720 adds r7, #32
8005430: 46bd mov sp, r7
8005432: bd80 pop {r7, pc}
8005434: 20001340 .word 0x20001340
8005438: 20001354 .word 0x20001354
0800543c <vTaskMissedYield>:
/*-----------------------------------------------------------*/
void vTaskMissedYield( void )
{
800543c: b480 push {r7}
800543e: af00 add r7, sp, #0
xYieldPending = pdTRUE;
8005440: 4b03 ldr r3, [pc, #12] @ (8005450 <vTaskMissedYield+0x14>)
8005442: 2201 movs r2, #1
8005444: 601a str r2, [r3, #0]
}
8005446: bf00 nop
8005448: 46bd mov sp, r7
800544a: f85d 7b04 ldr.w r7, [sp], #4
800544e: 4770 bx lr
8005450: 20001350 .word 0x20001350
08005454 <prvIdleTask>:
*
* void prvIdleTask( void *pvParameters );
*
*/
static portTASK_FUNCTION( prvIdleTask, pvParameters )
{
8005454: b580 push {r7, lr}
8005456: b082 sub sp, #8
8005458: af00 add r7, sp, #0
800545a: 6078 str r0, [r7, #4]
for( ;; )
{
/* See if any tasks have deleted themselves - if so then the idle task
is responsible for freeing the deleted task's TCB and stack. */
prvCheckTasksWaitingTermination();
800545c: f000 f852 bl 8005504 <prvCheckTasksWaitingTermination>
A critical region is not required here as we are just reading from
the list, and an occasional incorrect value will not matter. If
the ready list at the idle priority contains more than one task
then a task other than the idle task is ready to execute. */
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
8005460: 4b06 ldr r3, [pc, #24] @ (800547c <prvIdleTask+0x28>)
8005462: 681b ldr r3, [r3, #0]
8005464: 2b01 cmp r3, #1
8005466: d9f9 bls.n 800545c <prvIdleTask+0x8>
{
taskYIELD();
8005468: 4b05 ldr r3, [pc, #20] @ (8005480 <prvIdleTask+0x2c>)
800546a: f04f 5280 mov.w r2, #268435456 @ 0x10000000
800546e: 601a str r2, [r3, #0]
8005470: f3bf 8f4f dsb sy
8005474: f3bf 8f6f isb sy
prvCheckTasksWaitingTermination();
8005478: e7f0 b.n 800545c <prvIdleTask+0x8>
800547a: bf00 nop
800547c: 20000e6c .word 0x20000e6c
8005480: e000ed04 .word 0xe000ed04
08005484 <prvInitialiseTaskLists>:
#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/
static void prvInitialiseTaskLists( void )
{
8005484: b580 push {r7, lr}
8005486: b082 sub sp, #8
8005488: af00 add r7, sp, #0
UBaseType_t uxPriority;
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
800548a: 2300 movs r3, #0
800548c: 607b str r3, [r7, #4]
800548e: e00c b.n 80054aa <prvInitialiseTaskLists+0x26>
{
vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
8005490: 687a ldr r2, [r7, #4]
8005492: 4613 mov r3, r2
8005494: 009b lsls r3, r3, #2
8005496: 4413 add r3, r2
8005498: 009b lsls r3, r3, #2
800549a: 4a12 ldr r2, [pc, #72] @ (80054e4 <prvInitialiseTaskLists+0x60>)
800549c: 4413 add r3, r2
800549e: 4618 mov r0, r3
80054a0: f7fe fc98 bl 8003dd4 <vListInitialise>
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
80054a4: 687b ldr r3, [r7, #4]
80054a6: 3301 adds r3, #1
80054a8: 607b str r3, [r7, #4]
80054aa: 687b ldr r3, [r7, #4]
80054ac: 2b37 cmp r3, #55 @ 0x37
80054ae: d9ef bls.n 8005490 <prvInitialiseTaskLists+0xc>
}
vListInitialise( &xDelayedTaskList1 );
80054b0: 480d ldr r0, [pc, #52] @ (80054e8 <prvInitialiseTaskLists+0x64>)
80054b2: f7fe fc8f bl 8003dd4 <vListInitialise>
vListInitialise( &xDelayedTaskList2 );
80054b6: 480d ldr r0, [pc, #52] @ (80054ec <prvInitialiseTaskLists+0x68>)
80054b8: f7fe fc8c bl 8003dd4 <vListInitialise>
vListInitialise( &xPendingReadyList );
80054bc: 480c ldr r0, [pc, #48] @ (80054f0 <prvInitialiseTaskLists+0x6c>)
80054be: f7fe fc89 bl 8003dd4 <vListInitialise>
#if ( INCLUDE_vTaskDelete == 1 )
{
vListInitialise( &xTasksWaitingTermination );
80054c2: 480c ldr r0, [pc, #48] @ (80054f4 <prvInitialiseTaskLists+0x70>)
80054c4: f7fe fc86 bl 8003dd4 <vListInitialise>
}
#endif /* INCLUDE_vTaskDelete */
#if ( INCLUDE_vTaskSuspend == 1 )
{
vListInitialise( &xSuspendedTaskList );
80054c8: 480b ldr r0, [pc, #44] @ (80054f8 <prvInitialiseTaskLists+0x74>)
80054ca: f7fe fc83 bl 8003dd4 <vListInitialise>
}
#endif /* INCLUDE_vTaskSuspend */
/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
using list2. */
pxDelayedTaskList = &xDelayedTaskList1;
80054ce: 4b0b ldr r3, [pc, #44] @ (80054fc <prvInitialiseTaskLists+0x78>)
80054d0: 4a05 ldr r2, [pc, #20] @ (80054e8 <prvInitialiseTaskLists+0x64>)
80054d2: 601a str r2, [r3, #0]
pxOverflowDelayedTaskList = &xDelayedTaskList2;
80054d4: 4b0a ldr r3, [pc, #40] @ (8005500 <prvInitialiseTaskLists+0x7c>)
80054d6: 4a05 ldr r2, [pc, #20] @ (80054ec <prvInitialiseTaskLists+0x68>)
80054d8: 601a str r2, [r3, #0]
}
80054da: bf00 nop
80054dc: 3708 adds r7, #8
80054de: 46bd mov sp, r7
80054e0: bd80 pop {r7, pc}
80054e2: bf00 nop
80054e4: 20000e6c .word 0x20000e6c
80054e8: 200012cc .word 0x200012cc
80054ec: 200012e0 .word 0x200012e0
80054f0: 200012fc .word 0x200012fc
80054f4: 20001310 .word 0x20001310
80054f8: 20001328 .word 0x20001328
80054fc: 200012f4 .word 0x200012f4
8005500: 200012f8 .word 0x200012f8
08005504 <prvCheckTasksWaitingTermination>:
/*-----------------------------------------------------------*/
static void prvCheckTasksWaitingTermination( void )
{
8005504: b580 push {r7, lr}
8005506: b082 sub sp, #8
8005508: af00 add r7, sp, #0
{
TCB_t *pxTCB;
/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
being called too often in the idle task. */
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
800550a: e019 b.n 8005540 <prvCheckTasksWaitingTermination+0x3c>
{
taskENTER_CRITICAL();
800550c: f000 fdd6 bl 80060bc <vPortEnterCritical>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8005510: 4b10 ldr r3, [pc, #64] @ (8005554 <prvCheckTasksWaitingTermination+0x50>)
8005512: 68db ldr r3, [r3, #12]
8005514: 68db ldr r3, [r3, #12]
8005516: 607b str r3, [r7, #4]
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
8005518: 687b ldr r3, [r7, #4]
800551a: 3304 adds r3, #4
800551c: 4618 mov r0, r3
800551e: f7fe fce3 bl 8003ee8 <uxListRemove>
--uxCurrentNumberOfTasks;
8005522: 4b0d ldr r3, [pc, #52] @ (8005558 <prvCheckTasksWaitingTermination+0x54>)
8005524: 681b ldr r3, [r3, #0]
8005526: 3b01 subs r3, #1
8005528: 4a0b ldr r2, [pc, #44] @ (8005558 <prvCheckTasksWaitingTermination+0x54>)
800552a: 6013 str r3, [r2, #0]
--uxDeletedTasksWaitingCleanUp;
800552c: 4b0b ldr r3, [pc, #44] @ (800555c <prvCheckTasksWaitingTermination+0x58>)
800552e: 681b ldr r3, [r3, #0]
8005530: 3b01 subs r3, #1
8005532: 4a0a ldr r2, [pc, #40] @ (800555c <prvCheckTasksWaitingTermination+0x58>)
8005534: 6013 str r3, [r2, #0]
}
taskEXIT_CRITICAL();
8005536: f000 fdf7 bl 8006128 <vPortExitCritical>
prvDeleteTCB( pxTCB );
800553a: 6878 ldr r0, [r7, #4]
800553c: f000 f810 bl 8005560 <prvDeleteTCB>
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
8005540: 4b06 ldr r3, [pc, #24] @ (800555c <prvCheckTasksWaitingTermination+0x58>)
8005542: 681b ldr r3, [r3, #0]
8005544: 2b00 cmp r3, #0
8005546: d1e1 bne.n 800550c <prvCheckTasksWaitingTermination+0x8>
}
}
#endif /* INCLUDE_vTaskDelete */
}
8005548: bf00 nop
800554a: bf00 nop
800554c: 3708 adds r7, #8
800554e: 46bd mov sp, r7
8005550: bd80 pop {r7, pc}
8005552: bf00 nop
8005554: 20001310 .word 0x20001310
8005558: 2000133c .word 0x2000133c
800555c: 20001324 .word 0x20001324
08005560 <prvDeleteTCB>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelete == 1 )
static void prvDeleteTCB( TCB_t *pxTCB )
{
8005560: b580 push {r7, lr}
8005562: b084 sub sp, #16
8005564: af00 add r7, sp, #0
8005566: 6078 str r0, [r7, #4]
#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* The task could have been allocated statically or dynamically, so
check what was statically allocated before trying to free the
memory. */
if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
8005568: 687b ldr r3, [r7, #4]
800556a: f893 3059 ldrb.w r3, [r3, #89] @ 0x59
800556e: 2b00 cmp r3, #0
8005570: d108 bne.n 8005584 <prvDeleteTCB+0x24>
{
/* Both the stack and TCB were allocated dynamically, so both
must be freed. */
vPortFree( pxTCB->pxStack );
8005572: 687b ldr r3, [r7, #4]
8005574: 6b1b ldr r3, [r3, #48] @ 0x30
8005576: 4618 mov r0, r3
8005578: f000 ff9c bl 80064b4 <vPortFree>
vPortFree( pxTCB );
800557c: 6878 ldr r0, [r7, #4]
800557e: f000 ff99 bl 80064b4 <vPortFree>
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
}
8005582: e01b b.n 80055bc <prvDeleteTCB+0x5c>
else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
8005584: 687b ldr r3, [r7, #4]
8005586: f893 3059 ldrb.w r3, [r3, #89] @ 0x59
800558a: 2b01 cmp r3, #1
800558c: d103 bne.n 8005596 <prvDeleteTCB+0x36>
vPortFree( pxTCB );
800558e: 6878 ldr r0, [r7, #4]
8005590: f000 ff90 bl 80064b4 <vPortFree>
}
8005594: e012 b.n 80055bc <prvDeleteTCB+0x5c>
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
8005596: 687b ldr r3, [r7, #4]
8005598: f893 3059 ldrb.w r3, [r3, #89] @ 0x59
800559c: 2b02 cmp r3, #2
800559e: d00d beq.n 80055bc <prvDeleteTCB+0x5c>
__asm volatile
80055a0: f04f 0350 mov.w r3, #80 @ 0x50
80055a4: b672 cpsid i
80055a6: f383 8811 msr BASEPRI, r3
80055aa: f3bf 8f6f isb sy
80055ae: f3bf 8f4f dsb sy
80055b2: b662 cpsie i
80055b4: 60fb str r3, [r7, #12]
}
80055b6: bf00 nop
80055b8: bf00 nop
80055ba: e7fd b.n 80055b8 <prvDeleteTCB+0x58>
}
80055bc: bf00 nop
80055be: 3710 adds r7, #16
80055c0: 46bd mov sp, r7
80055c2: bd80 pop {r7, pc}
080055c4 <prvResetNextTaskUnblockTime>:
#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/
static void prvResetNextTaskUnblockTime( void )
{
80055c4: b480 push {r7}
80055c6: b083 sub sp, #12
80055c8: af00 add r7, sp, #0
TCB_t *pxTCB;
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
80055ca: 4b0c ldr r3, [pc, #48] @ (80055fc <prvResetNextTaskUnblockTime+0x38>)
80055cc: 681b ldr r3, [r3, #0]
80055ce: 681b ldr r3, [r3, #0]
80055d0: 2b00 cmp r3, #0
80055d2: d104 bne.n 80055de <prvResetNextTaskUnblockTime+0x1a>
{
/* The new current delayed list is empty. Set xNextTaskUnblockTime to
the maximum possible value so it is extremely unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass until
there is an item in the delayed list. */
xNextTaskUnblockTime = portMAX_DELAY;
80055d4: 4b0a ldr r3, [pc, #40] @ (8005600 <prvResetNextTaskUnblockTime+0x3c>)
80055d6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
80055da: 601a str r2, [r3, #0]
which the task at the head of the delayed list should be removed
from the Blocked state. */
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
}
}
80055dc: e008 b.n 80055f0 <prvResetNextTaskUnblockTime+0x2c>
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
80055de: 4b07 ldr r3, [pc, #28] @ (80055fc <prvResetNextTaskUnblockTime+0x38>)
80055e0: 681b ldr r3, [r3, #0]
80055e2: 68db ldr r3, [r3, #12]
80055e4: 68db ldr r3, [r3, #12]
80055e6: 607b str r3, [r7, #4]
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
80055e8: 687b ldr r3, [r7, #4]
80055ea: 685b ldr r3, [r3, #4]
80055ec: 4a04 ldr r2, [pc, #16] @ (8005600 <prvResetNextTaskUnblockTime+0x3c>)
80055ee: 6013 str r3, [r2, #0]
}
80055f0: bf00 nop
80055f2: 370c adds r7, #12
80055f4: 46bd mov sp, r7
80055f6: f85d 7b04 ldr.w r7, [sp], #4
80055fa: 4770 bx lr
80055fc: 200012f4 .word 0x200012f4
8005600: 2000135c .word 0x2000135c
08005604 <xTaskGetSchedulerState>:
/*-----------------------------------------------------------*/
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
BaseType_t xTaskGetSchedulerState( void )
{
8005604: b480 push {r7}
8005606: b083 sub sp, #12
8005608: af00 add r7, sp, #0
BaseType_t xReturn;
if( xSchedulerRunning == pdFALSE )
800560a: 4b0b ldr r3, [pc, #44] @ (8005638 <xTaskGetSchedulerState+0x34>)
800560c: 681b ldr r3, [r3, #0]
800560e: 2b00 cmp r3, #0
8005610: d102 bne.n 8005618 <xTaskGetSchedulerState+0x14>
{
xReturn = taskSCHEDULER_NOT_STARTED;
8005612: 2301 movs r3, #1
8005614: 607b str r3, [r7, #4]
8005616: e008 b.n 800562a <xTaskGetSchedulerState+0x26>
}
else
{
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8005618: 4b08 ldr r3, [pc, #32] @ (800563c <xTaskGetSchedulerState+0x38>)
800561a: 681b ldr r3, [r3, #0]
800561c: 2b00 cmp r3, #0
800561e: d102 bne.n 8005626 <xTaskGetSchedulerState+0x22>
{
xReturn = taskSCHEDULER_RUNNING;
8005620: 2302 movs r3, #2
8005622: 607b str r3, [r7, #4]
8005624: e001 b.n 800562a <xTaskGetSchedulerState+0x26>
}
else
{
xReturn = taskSCHEDULER_SUSPENDED;
8005626: 2300 movs r3, #0
8005628: 607b str r3, [r7, #4]
}
}
return xReturn;
800562a: 687b ldr r3, [r7, #4]
}
800562c: 4618 mov r0, r3
800562e: 370c adds r7, #12
8005630: 46bd mov sp, r7
8005632: f85d 7b04 ldr.w r7, [sp], #4
8005636: 4770 bx lr
8005638: 20001348 .word 0x20001348
800563c: 20001364 .word 0x20001364
08005640 <xTaskPriorityDisinherit>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
{
8005640: b580 push {r7, lr}
8005642: b086 sub sp, #24
8005644: af00 add r7, sp, #0
8005646: 6078 str r0, [r7, #4]
TCB_t * const pxTCB = pxMutexHolder;
8005648: 687b ldr r3, [r7, #4]
800564a: 613b str r3, [r7, #16]
BaseType_t xReturn = pdFALSE;
800564c: 2300 movs r3, #0
800564e: 617b str r3, [r7, #20]
if( pxMutexHolder != NULL )
8005650: 687b ldr r3, [r7, #4]
8005652: 2b00 cmp r3, #0
8005654: d05c beq.n 8005710 <xTaskPriorityDisinherit+0xd0>
{
/* A task can only have an inherited priority if it holds the mutex.
If the mutex is held by a task then it cannot be given from an
interrupt, and if a mutex is given by the holding task then it must
be the running state task. */
configASSERT( pxTCB == pxCurrentTCB );
8005656: 4b31 ldr r3, [pc, #196] @ (800571c <xTaskPriorityDisinherit+0xdc>)
8005658: 681b ldr r3, [r3, #0]
800565a: 693a ldr r2, [r7, #16]
800565c: 429a cmp r2, r3
800565e: d00d beq.n 800567c <xTaskPriorityDisinherit+0x3c>
__asm volatile
8005660: f04f 0350 mov.w r3, #80 @ 0x50
8005664: b672 cpsid i
8005666: f383 8811 msr BASEPRI, r3
800566a: f3bf 8f6f isb sy
800566e: f3bf 8f4f dsb sy
8005672: b662 cpsie i
8005674: 60fb str r3, [r7, #12]
}
8005676: bf00 nop
8005678: bf00 nop
800567a: e7fd b.n 8005678 <xTaskPriorityDisinherit+0x38>
configASSERT( pxTCB->uxMutexesHeld );
800567c: 693b ldr r3, [r7, #16]
800567e: 6d1b ldr r3, [r3, #80] @ 0x50
8005680: 2b00 cmp r3, #0
8005682: d10d bne.n 80056a0 <xTaskPriorityDisinherit+0x60>
__asm volatile
8005684: f04f 0350 mov.w r3, #80 @ 0x50
8005688: b672 cpsid i
800568a: f383 8811 msr BASEPRI, r3
800568e: f3bf 8f6f isb sy
8005692: f3bf 8f4f dsb sy
8005696: b662 cpsie i
8005698: 60bb str r3, [r7, #8]
}
800569a: bf00 nop
800569c: bf00 nop
800569e: e7fd b.n 800569c <xTaskPriorityDisinherit+0x5c>
( pxTCB->uxMutexesHeld )--;
80056a0: 693b ldr r3, [r7, #16]
80056a2: 6d1b ldr r3, [r3, #80] @ 0x50
80056a4: 1e5a subs r2, r3, #1
80056a6: 693b ldr r3, [r7, #16]
80056a8: 651a str r2, [r3, #80] @ 0x50
/* Has the holder of the mutex inherited the priority of another
task? */
if( pxTCB->uxPriority != pxTCB->uxBasePriority )
80056aa: 693b ldr r3, [r7, #16]
80056ac: 6ada ldr r2, [r3, #44] @ 0x2c
80056ae: 693b ldr r3, [r7, #16]
80056b0: 6cdb ldr r3, [r3, #76] @ 0x4c
80056b2: 429a cmp r2, r3
80056b4: d02c beq.n 8005710 <xTaskPriorityDisinherit+0xd0>
{
/* Only disinherit if no other mutexes are held. */
if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
80056b6: 693b ldr r3, [r7, #16]
80056b8: 6d1b ldr r3, [r3, #80] @ 0x50
80056ba: 2b00 cmp r3, #0
80056bc: d128 bne.n 8005710 <xTaskPriorityDisinherit+0xd0>
/* A task can only have an inherited priority if it holds
the mutex. If the mutex is held by a task then it cannot be
given from an interrupt, and if a mutex is given by the
holding task then it must be the running state task. Remove
the holding task from the ready list. */
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
80056be: 693b ldr r3, [r7, #16]
80056c0: 3304 adds r3, #4
80056c2: 4618 mov r0, r3
80056c4: f7fe fc10 bl 8003ee8 <uxListRemove>
}
/* Disinherit the priority before adding the task into the
new ready list. */
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
pxTCB->uxPriority = pxTCB->uxBasePriority;
80056c8: 693b ldr r3, [r7, #16]
80056ca: 6cda ldr r2, [r3, #76] @ 0x4c
80056cc: 693b ldr r3, [r7, #16]
80056ce: 62da str r2, [r3, #44] @ 0x2c
/* Reset the event list item value. It cannot be in use for
any other purpose if this task is running, and it must be
running to give back the mutex. */
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
80056d0: 693b ldr r3, [r7, #16]
80056d2: 6adb ldr r3, [r3, #44] @ 0x2c
80056d4: f1c3 0238 rsb r2, r3, #56 @ 0x38
80056d8: 693b ldr r3, [r7, #16]
80056da: 619a str r2, [r3, #24]
prvAddTaskToReadyList( pxTCB );
80056dc: 693b ldr r3, [r7, #16]
80056de: 6ada ldr r2, [r3, #44] @ 0x2c
80056e0: 4b0f ldr r3, [pc, #60] @ (8005720 <xTaskPriorityDisinherit+0xe0>)
80056e2: 681b ldr r3, [r3, #0]
80056e4: 429a cmp r2, r3
80056e6: d903 bls.n 80056f0 <xTaskPriorityDisinherit+0xb0>
80056e8: 693b ldr r3, [r7, #16]
80056ea: 6adb ldr r3, [r3, #44] @ 0x2c
80056ec: 4a0c ldr r2, [pc, #48] @ (8005720 <xTaskPriorityDisinherit+0xe0>)
80056ee: 6013 str r3, [r2, #0]
80056f0: 693b ldr r3, [r7, #16]
80056f2: 6ada ldr r2, [r3, #44] @ 0x2c
80056f4: 4613 mov r3, r2
80056f6: 009b lsls r3, r3, #2
80056f8: 4413 add r3, r2
80056fa: 009b lsls r3, r3, #2
80056fc: 4a09 ldr r2, [pc, #36] @ (8005724 <xTaskPriorityDisinherit+0xe4>)
80056fe: 441a add r2, r3
8005700: 693b ldr r3, [r7, #16]
8005702: 3304 adds r3, #4
8005704: 4619 mov r1, r3
8005706: 4610 mov r0, r2
8005708: f7fe fb91 bl 8003e2e <vListInsertEnd>
in an order different to that in which they were taken.
If a context switch did not occur when the first mutex was
returned, even if a task was waiting on it, then a context
switch should occur when the last mutex is returned whether
a task is waiting on it or not. */
xReturn = pdTRUE;
800570c: 2301 movs r3, #1
800570e: 617b str r3, [r7, #20]
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
8005710: 697b ldr r3, [r7, #20]
}
8005712: 4618 mov r0, r3
8005714: 3718 adds r7, #24
8005716: 46bd mov sp, r7
8005718: bd80 pop {r7, pc}
800571a: bf00 nop
800571c: 20000e68 .word 0x20000e68
8005720: 20001344 .word 0x20001344
8005724: 20000e6c .word 0x20000e6c
08005728 <prvAddCurrentTaskToDelayedList>:
}
#endif
/*-----------------------------------------------------------*/
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
{
8005728: b580 push {r7, lr}
800572a: b084 sub sp, #16
800572c: af00 add r7, sp, #0
800572e: 6078 str r0, [r7, #4]
8005730: 6039 str r1, [r7, #0]
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
8005732: 4b21 ldr r3, [pc, #132] @ (80057b8 <prvAddCurrentTaskToDelayedList+0x90>)
8005734: 681b ldr r3, [r3, #0]
8005736: 60fb str r3, [r7, #12]
}
#endif
/* Remove the task from the ready list before adding it to the blocked list
as the same list item is used for both lists. */
if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
8005738: 4b20 ldr r3, [pc, #128] @ (80057bc <prvAddCurrentTaskToDelayedList+0x94>)
800573a: 681b ldr r3, [r3, #0]
800573c: 3304 adds r3, #4
800573e: 4618 mov r0, r3
8005740: f7fe fbd2 bl 8003ee8 <uxListRemove>
mtCOVERAGE_TEST_MARKER();
}
#if ( INCLUDE_vTaskSuspend == 1 )
{
if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
8005744: 687b ldr r3, [r7, #4]
8005746: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
800574a: d10a bne.n 8005762 <prvAddCurrentTaskToDelayedList+0x3a>
800574c: 683b ldr r3, [r7, #0]
800574e: 2b00 cmp r3, #0
8005750: d007 beq.n 8005762 <prvAddCurrentTaskToDelayedList+0x3a>
{
/* Add the task to the suspended task list instead of a delayed task
list to ensure it is not woken by a timing event. It will block
indefinitely. */
vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
8005752: 4b1a ldr r3, [pc, #104] @ (80057bc <prvAddCurrentTaskToDelayedList+0x94>)
8005754: 681b ldr r3, [r3, #0]
8005756: 3304 adds r3, #4
8005758: 4619 mov r1, r3
800575a: 4819 ldr r0, [pc, #100] @ (80057c0 <prvAddCurrentTaskToDelayedList+0x98>)
800575c: f7fe fb67 bl 8003e2e <vListInsertEnd>
/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
( void ) xCanBlockIndefinitely;
}
#endif /* INCLUDE_vTaskSuspend */
}
8005760: e026 b.n 80057b0 <prvAddCurrentTaskToDelayedList+0x88>
xTimeToWake = xConstTickCount + xTicksToWait;
8005762: 68fa ldr r2, [r7, #12]
8005764: 687b ldr r3, [r7, #4]
8005766: 4413 add r3, r2
8005768: 60bb str r3, [r7, #8]
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
800576a: 4b14 ldr r3, [pc, #80] @ (80057bc <prvAddCurrentTaskToDelayedList+0x94>)
800576c: 681b ldr r3, [r3, #0]
800576e: 68ba ldr r2, [r7, #8]
8005770: 605a str r2, [r3, #4]
if( xTimeToWake < xConstTickCount )
8005772: 68ba ldr r2, [r7, #8]
8005774: 68fb ldr r3, [r7, #12]
8005776: 429a cmp r2, r3
8005778: d209 bcs.n 800578e <prvAddCurrentTaskToDelayedList+0x66>
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
800577a: 4b12 ldr r3, [pc, #72] @ (80057c4 <prvAddCurrentTaskToDelayedList+0x9c>)
800577c: 681a ldr r2, [r3, #0]
800577e: 4b0f ldr r3, [pc, #60] @ (80057bc <prvAddCurrentTaskToDelayedList+0x94>)
8005780: 681b ldr r3, [r3, #0]
8005782: 3304 adds r3, #4
8005784: 4619 mov r1, r3
8005786: 4610 mov r0, r2
8005788: f7fe fb75 bl 8003e76 <vListInsert>
}
800578c: e010 b.n 80057b0 <prvAddCurrentTaskToDelayedList+0x88>
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
800578e: 4b0e ldr r3, [pc, #56] @ (80057c8 <prvAddCurrentTaskToDelayedList+0xa0>)
8005790: 681a ldr r2, [r3, #0]
8005792: 4b0a ldr r3, [pc, #40] @ (80057bc <prvAddCurrentTaskToDelayedList+0x94>)
8005794: 681b ldr r3, [r3, #0]
8005796: 3304 adds r3, #4
8005798: 4619 mov r1, r3
800579a: 4610 mov r0, r2
800579c: f7fe fb6b bl 8003e76 <vListInsert>
if( xTimeToWake < xNextTaskUnblockTime )
80057a0: 4b0a ldr r3, [pc, #40] @ (80057cc <prvAddCurrentTaskToDelayedList+0xa4>)
80057a2: 681b ldr r3, [r3, #0]
80057a4: 68ba ldr r2, [r7, #8]
80057a6: 429a cmp r2, r3
80057a8: d202 bcs.n 80057b0 <prvAddCurrentTaskToDelayedList+0x88>
xNextTaskUnblockTime = xTimeToWake;
80057aa: 4a08 ldr r2, [pc, #32] @ (80057cc <prvAddCurrentTaskToDelayedList+0xa4>)
80057ac: 68bb ldr r3, [r7, #8]
80057ae: 6013 str r3, [r2, #0]
}
80057b0: bf00 nop
80057b2: 3710 adds r7, #16
80057b4: 46bd mov sp, r7
80057b6: bd80 pop {r7, pc}
80057b8: 20001340 .word 0x20001340
80057bc: 20000e68 .word 0x20000e68
80057c0: 20001328 .word 0x20001328
80057c4: 200012f8 .word 0x200012f8
80057c8: 200012f4 .word 0x200012f4
80057cc: 2000135c .word 0x2000135c
080057d0 <xTimerCreateTimerTask>:
TimerCallbackFunction_t pxCallbackFunction,
Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/
BaseType_t xTimerCreateTimerTask( void )
{
80057d0: b580 push {r7, lr}
80057d2: b08a sub sp, #40 @ 0x28
80057d4: af04 add r7, sp, #16
BaseType_t xReturn = pdFAIL;
80057d6: 2300 movs r3, #0
80057d8: 617b str r3, [r7, #20]
/* This function is called when the scheduler is started if
configUSE_TIMERS is set to 1. Check that the infrastructure used by the
timer service task has been created/initialised. If timers have already
been created then the initialisation will already have been performed. */
prvCheckForValidListAndQueue();
80057da: f000 fb21 bl 8005e20 <prvCheckForValidListAndQueue>
if( xTimerQueue != NULL )
80057de: 4b1e ldr r3, [pc, #120] @ (8005858 <xTimerCreateTimerTask+0x88>)
80057e0: 681b ldr r3, [r3, #0]
80057e2: 2b00 cmp r3, #0
80057e4: d021 beq.n 800582a <xTimerCreateTimerTask+0x5a>
{
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
{
StaticTask_t *pxTimerTaskTCBBuffer = NULL;
80057e6: 2300 movs r3, #0
80057e8: 60fb str r3, [r7, #12]
StackType_t *pxTimerTaskStackBuffer = NULL;
80057ea: 2300 movs r3, #0
80057ec: 60bb str r3, [r7, #8]
uint32_t ulTimerTaskStackSize;
vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
80057ee: 1d3a adds r2, r7, #4
80057f0: f107 0108 add.w r1, r7, #8
80057f4: f107 030c add.w r3, r7, #12
80057f8: 4618 mov r0, r3
80057fa: f7fe fad1 bl 8003da0 <vApplicationGetTimerTaskMemory>
xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
80057fe: 6879 ldr r1, [r7, #4]
8005800: 68bb ldr r3, [r7, #8]
8005802: 68fa ldr r2, [r7, #12]
8005804: 9202 str r2, [sp, #8]
8005806: 9301 str r3, [sp, #4]
8005808: 2302 movs r3, #2
800580a: 9300 str r3, [sp, #0]
800580c: 2300 movs r3, #0
800580e: 460a mov r2, r1
8005810: 4912 ldr r1, [pc, #72] @ (800585c <xTimerCreateTimerTask+0x8c>)
8005812: 4813 ldr r0, [pc, #76] @ (8005860 <xTimerCreateTimerTask+0x90>)
8005814: f7ff f8ac bl 8004970 <xTaskCreateStatic>
8005818: 4603 mov r3, r0
800581a: 4a12 ldr r2, [pc, #72] @ (8005864 <xTimerCreateTimerTask+0x94>)
800581c: 6013 str r3, [r2, #0]
NULL,
( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
pxTimerTaskStackBuffer,
pxTimerTaskTCBBuffer );
if( xTimerTaskHandle != NULL )
800581e: 4b11 ldr r3, [pc, #68] @ (8005864 <xTimerCreateTimerTask+0x94>)
8005820: 681b ldr r3, [r3, #0]
8005822: 2b00 cmp r3, #0
8005824: d001 beq.n 800582a <xTimerCreateTimerTask+0x5a>
{
xReturn = pdPASS;
8005826: 2301 movs r3, #1
8005828: 617b str r3, [r7, #20]
else
{
mtCOVERAGE_TEST_MARKER();
}
configASSERT( xReturn );
800582a: 697b ldr r3, [r7, #20]
800582c: 2b00 cmp r3, #0
800582e: d10d bne.n 800584c <xTimerCreateTimerTask+0x7c>
__asm volatile
8005830: f04f 0350 mov.w r3, #80 @ 0x50
8005834: b672 cpsid i
8005836: f383 8811 msr BASEPRI, r3
800583a: f3bf 8f6f isb sy
800583e: f3bf 8f4f dsb sy
8005842: b662 cpsie i
8005844: 613b str r3, [r7, #16]
}
8005846: bf00 nop
8005848: bf00 nop
800584a: e7fd b.n 8005848 <xTimerCreateTimerTask+0x78>
return xReturn;
800584c: 697b ldr r3, [r7, #20]
}
800584e: 4618 mov r0, r3
8005850: 3718 adds r7, #24
8005852: 46bd mov sp, r7
8005854: bd80 pop {r7, pc}
8005856: bf00 nop
8005858: 20001398 .word 0x20001398
800585c: 080075d0 .word 0x080075d0
8005860: 080059a9 .word 0x080059a9
8005864: 2000139c .word 0x2000139c
08005868 <xTimerGenericCommand>:
}
}
/*-----------------------------------------------------------*/
BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
{
8005868: b580 push {r7, lr}
800586a: b08a sub sp, #40 @ 0x28
800586c: af00 add r7, sp, #0
800586e: 60f8 str r0, [r7, #12]
8005870: 60b9 str r1, [r7, #8]
8005872: 607a str r2, [r7, #4]
8005874: 603b str r3, [r7, #0]
BaseType_t xReturn = pdFAIL;
8005876: 2300 movs r3, #0
8005878: 627b str r3, [r7, #36] @ 0x24
DaemonTaskMessage_t xMessage;
configASSERT( xTimer );
800587a: 68fb ldr r3, [r7, #12]
800587c: 2b00 cmp r3, #0
800587e: d10d bne.n 800589c <xTimerGenericCommand+0x34>
__asm volatile
8005880: f04f 0350 mov.w r3, #80 @ 0x50
8005884: b672 cpsid i
8005886: f383 8811 msr BASEPRI, r3
800588a: f3bf 8f6f isb sy
800588e: f3bf 8f4f dsb sy
8005892: b662 cpsie i
8005894: 623b str r3, [r7, #32]
}
8005896: bf00 nop
8005898: bf00 nop
800589a: e7fd b.n 8005898 <xTimerGenericCommand+0x30>
/* Send a message to the timer service task to perform a particular action
on a particular timer definition. */
if( xTimerQueue != NULL )
800589c: 4b19 ldr r3, [pc, #100] @ (8005904 <xTimerGenericCommand+0x9c>)
800589e: 681b ldr r3, [r3, #0]
80058a0: 2b00 cmp r3, #0
80058a2: d02a beq.n 80058fa <xTimerGenericCommand+0x92>
{
/* Send a command to the timer service task to start the xTimer timer. */
xMessage.xMessageID = xCommandID;
80058a4: 68bb ldr r3, [r7, #8]
80058a6: 613b str r3, [r7, #16]
xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
80058a8: 687b ldr r3, [r7, #4]
80058aa: 617b str r3, [r7, #20]
xMessage.u.xTimerParameters.pxTimer = xTimer;
80058ac: 68fb ldr r3, [r7, #12]
80058ae: 61bb str r3, [r7, #24]
if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
80058b0: 68bb ldr r3, [r7, #8]
80058b2: 2b05 cmp r3, #5
80058b4: dc18 bgt.n 80058e8 <xTimerGenericCommand+0x80>
{
if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
80058b6: f7ff fea5 bl 8005604 <xTaskGetSchedulerState>
80058ba: 4603 mov r3, r0
80058bc: 2b02 cmp r3, #2
80058be: d109 bne.n 80058d4 <xTimerGenericCommand+0x6c>
{
xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
80058c0: 4b10 ldr r3, [pc, #64] @ (8005904 <xTimerGenericCommand+0x9c>)
80058c2: 6818 ldr r0, [r3, #0]
80058c4: f107 0110 add.w r1, r7, #16
80058c8: 2300 movs r3, #0
80058ca: 6b3a ldr r2, [r7, #48] @ 0x30
80058cc: f7fe fc4c bl 8004168 <xQueueGenericSend>
80058d0: 6278 str r0, [r7, #36] @ 0x24
80058d2: e012 b.n 80058fa <xTimerGenericCommand+0x92>
}
else
{
xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
80058d4: 4b0b ldr r3, [pc, #44] @ (8005904 <xTimerGenericCommand+0x9c>)
80058d6: 6818 ldr r0, [r3, #0]
80058d8: f107 0110 add.w r1, r7, #16
80058dc: 2300 movs r3, #0
80058de: 2200 movs r2, #0
80058e0: f7fe fc42 bl 8004168 <xQueueGenericSend>
80058e4: 6278 str r0, [r7, #36] @ 0x24
80058e6: e008 b.n 80058fa <xTimerGenericCommand+0x92>
}
}
else
{
xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
80058e8: 4b06 ldr r3, [pc, #24] @ (8005904 <xTimerGenericCommand+0x9c>)
80058ea: 6818 ldr r0, [r3, #0]
80058ec: f107 0110 add.w r1, r7, #16
80058f0: 2300 movs r3, #0
80058f2: 683a ldr r2, [r7, #0]
80058f4: f7fe fd42 bl 800437c <xQueueGenericSendFromISR>
80058f8: 6278 str r0, [r7, #36] @ 0x24
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
80058fa: 6a7b ldr r3, [r7, #36] @ 0x24
}
80058fc: 4618 mov r0, r3
80058fe: 3728 adds r7, #40 @ 0x28
8005900: 46bd mov sp, r7
8005902: bd80 pop {r7, pc}
8005904: 20001398 .word 0x20001398
08005908 <prvProcessExpiredTimer>:
return pxTimer->pcTimerName;
}
/*-----------------------------------------------------------*/
static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
{
8005908: b580 push {r7, lr}
800590a: b088 sub sp, #32
800590c: af02 add r7, sp, #8
800590e: 6078 str r0, [r7, #4]
8005910: 6039 str r1, [r7, #0]
BaseType_t xResult;
Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8005912: 4b24 ldr r3, [pc, #144] @ (80059a4 <prvProcessExpiredTimer+0x9c>)
8005914: 681b ldr r3, [r3, #0]
8005916: 68db ldr r3, [r3, #12]
8005918: 68db ldr r3, [r3, #12]
800591a: 617b str r3, [r7, #20]
/* Remove the timer from the list of active timers. A check has already
been performed to ensure the list is not empty. */
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
800591c: 697b ldr r3, [r7, #20]
800591e: 3304 adds r3, #4
8005920: 4618 mov r0, r3
8005922: f7fe fae1 bl 8003ee8 <uxListRemove>
traceTIMER_EXPIRED( pxTimer );
/* If the timer is an auto reload timer then calculate the next
expiry time and re-insert the timer in the list of active timers. */
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
8005926: 697b ldr r3, [r7, #20]
8005928: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
800592c: f003 0304 and.w r3, r3, #4
8005930: 2b00 cmp r3, #0
8005932: d025 beq.n 8005980 <prvProcessExpiredTimer+0x78>
{
/* The timer is inserted into a list using a time relative to anything
other than the current time. It will therefore be inserted into the
correct list relative to the time this task thinks it is now. */
if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
8005934: 697b ldr r3, [r7, #20]
8005936: 699a ldr r2, [r3, #24]
8005938: 687b ldr r3, [r7, #4]
800593a: 18d1 adds r1, r2, r3
800593c: 687b ldr r3, [r7, #4]
800593e: 683a ldr r2, [r7, #0]
8005940: 6978 ldr r0, [r7, #20]
8005942: f000 f8d7 bl 8005af4 <prvInsertTimerInActiveList>
8005946: 4603 mov r3, r0
8005948: 2b00 cmp r3, #0
800594a: d022 beq.n 8005992 <prvProcessExpiredTimer+0x8a>
{
/* The timer expired before it was added to the active timer
list. Reload it now. */
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
800594c: 2300 movs r3, #0
800594e: 9300 str r3, [sp, #0]
8005950: 2300 movs r3, #0
8005952: 687a ldr r2, [r7, #4]
8005954: 2100 movs r1, #0
8005956: 6978 ldr r0, [r7, #20]
8005958: f7ff ff86 bl 8005868 <xTimerGenericCommand>
800595c: 6138 str r0, [r7, #16]
configASSERT( xResult );
800595e: 693b ldr r3, [r7, #16]
8005960: 2b00 cmp r3, #0
8005962: d116 bne.n 8005992 <prvProcessExpiredTimer+0x8a>
__asm volatile
8005964: f04f 0350 mov.w r3, #80 @ 0x50
8005968: b672 cpsid i
800596a: f383 8811 msr BASEPRI, r3
800596e: f3bf 8f6f isb sy
8005972: f3bf 8f4f dsb sy
8005976: b662 cpsie i
8005978: 60fb str r3, [r7, #12]
}
800597a: bf00 nop
800597c: bf00 nop
800597e: e7fd b.n 800597c <prvProcessExpiredTimer+0x74>
mtCOVERAGE_TEST_MARKER();
}
}
else
{
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
8005980: 697b ldr r3, [r7, #20]
8005982: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8005986: f023 0301 bic.w r3, r3, #1
800598a: b2da uxtb r2, r3
800598c: 697b ldr r3, [r7, #20]
800598e: f883 2028 strb.w r2, [r3, #40] @ 0x28
mtCOVERAGE_TEST_MARKER();
}
/* Call the timer callback. */
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
8005992: 697b ldr r3, [r7, #20]
8005994: 6a1b ldr r3, [r3, #32]
8005996: 6978 ldr r0, [r7, #20]
8005998: 4798 blx r3
}
800599a: bf00 nop
800599c: 3718 adds r7, #24
800599e: 46bd mov sp, r7
80059a0: bd80 pop {r7, pc}
80059a2: bf00 nop
80059a4: 20001390 .word 0x20001390
080059a8 <prvTimerTask>:
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( prvTimerTask, pvParameters )
{
80059a8: b580 push {r7, lr}
80059aa: b084 sub sp, #16
80059ac: af00 add r7, sp, #0
80059ae: 6078 str r0, [r7, #4]
for( ;; )
{
/* Query the timers list to see if it contains any timers, and if so,
obtain the time at which the next timer will expire. */
xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
80059b0: f107 0308 add.w r3, r7, #8
80059b4: 4618 mov r0, r3
80059b6: f000 f859 bl 8005a6c <prvGetNextExpireTime>
80059ba: 60f8 str r0, [r7, #12]
/* If a timer has expired, process it. Otherwise, block this task
until either a timer does expire, or a command is received. */
prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
80059bc: 68bb ldr r3, [r7, #8]
80059be: 4619 mov r1, r3
80059c0: 68f8 ldr r0, [r7, #12]
80059c2: f000 f805 bl 80059d0 <prvProcessTimerOrBlockTask>
/* Empty the command queue. */
prvProcessReceivedCommands();
80059c6: f000 f8d7 bl 8005b78 <prvProcessReceivedCommands>
xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
80059ca: bf00 nop
80059cc: e7f0 b.n 80059b0 <prvTimerTask+0x8>
...
080059d0 <prvProcessTimerOrBlockTask>:
}
}
/*-----------------------------------------------------------*/
static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
{
80059d0: b580 push {r7, lr}
80059d2: b084 sub sp, #16
80059d4: af00 add r7, sp, #0
80059d6: 6078 str r0, [r7, #4]
80059d8: 6039 str r1, [r7, #0]
TickType_t xTimeNow;
BaseType_t xTimerListsWereSwitched;
vTaskSuspendAll();
80059da: f7ff fa1b bl 8004e14 <vTaskSuspendAll>
/* Obtain the time now to make an assessment as to whether the timer
has expired or not. If obtaining the time causes the lists to switch
then don't process this timer as any timers that remained in the list
when the lists were switched will have been processed within the
prvSampleTimeNow() function. */
xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
80059de: f107 0308 add.w r3, r7, #8
80059e2: 4618 mov r0, r3
80059e4: f000 f866 bl 8005ab4 <prvSampleTimeNow>
80059e8: 60f8 str r0, [r7, #12]
if( xTimerListsWereSwitched == pdFALSE )
80059ea: 68bb ldr r3, [r7, #8]
80059ec: 2b00 cmp r3, #0
80059ee: d130 bne.n 8005a52 <prvProcessTimerOrBlockTask+0x82>
{
/* The tick count has not overflowed, has the timer expired? */
if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
80059f0: 683b ldr r3, [r7, #0]
80059f2: 2b00 cmp r3, #0
80059f4: d10a bne.n 8005a0c <prvProcessTimerOrBlockTask+0x3c>
80059f6: 687a ldr r2, [r7, #4]
80059f8: 68fb ldr r3, [r7, #12]
80059fa: 429a cmp r2, r3
80059fc: d806 bhi.n 8005a0c <prvProcessTimerOrBlockTask+0x3c>
{
( void ) xTaskResumeAll();
80059fe: f7ff fa17 bl 8004e30 <xTaskResumeAll>
prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
8005a02: 68f9 ldr r1, [r7, #12]
8005a04: 6878 ldr r0, [r7, #4]
8005a06: f7ff ff7f bl 8005908 <prvProcessExpiredTimer>
else
{
( void ) xTaskResumeAll();
}
}
}
8005a0a: e024 b.n 8005a56 <prvProcessTimerOrBlockTask+0x86>
if( xListWasEmpty != pdFALSE )
8005a0c: 683b ldr r3, [r7, #0]
8005a0e: 2b00 cmp r3, #0
8005a10: d008 beq.n 8005a24 <prvProcessTimerOrBlockTask+0x54>
xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
8005a12: 4b13 ldr r3, [pc, #76] @ (8005a60 <prvProcessTimerOrBlockTask+0x90>)
8005a14: 681b ldr r3, [r3, #0]
8005a16: 681b ldr r3, [r3, #0]
8005a18: 2b00 cmp r3, #0
8005a1a: d101 bne.n 8005a20 <prvProcessTimerOrBlockTask+0x50>
8005a1c: 2301 movs r3, #1
8005a1e: e000 b.n 8005a22 <prvProcessTimerOrBlockTask+0x52>
8005a20: 2300 movs r3, #0
8005a22: 603b str r3, [r7, #0]
vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
8005a24: 4b0f ldr r3, [pc, #60] @ (8005a64 <prvProcessTimerOrBlockTask+0x94>)
8005a26: 6818 ldr r0, [r3, #0]
8005a28: 687a ldr r2, [r7, #4]
8005a2a: 68fb ldr r3, [r7, #12]
8005a2c: 1ad3 subs r3, r2, r3
8005a2e: 683a ldr r2, [r7, #0]
8005a30: 4619 mov r1, r3
8005a32: f7fe ff69 bl 8004908 <vQueueWaitForMessageRestricted>
if( xTaskResumeAll() == pdFALSE )
8005a36: f7ff f9fb bl 8004e30 <xTaskResumeAll>
8005a3a: 4603 mov r3, r0
8005a3c: 2b00 cmp r3, #0
8005a3e: d10a bne.n 8005a56 <prvProcessTimerOrBlockTask+0x86>
portYIELD_WITHIN_API();
8005a40: 4b09 ldr r3, [pc, #36] @ (8005a68 <prvProcessTimerOrBlockTask+0x98>)
8005a42: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8005a46: 601a str r2, [r3, #0]
8005a48: f3bf 8f4f dsb sy
8005a4c: f3bf 8f6f isb sy
}
8005a50: e001 b.n 8005a56 <prvProcessTimerOrBlockTask+0x86>
( void ) xTaskResumeAll();
8005a52: f7ff f9ed bl 8004e30 <xTaskResumeAll>
}
8005a56: bf00 nop
8005a58: 3710 adds r7, #16
8005a5a: 46bd mov sp, r7
8005a5c: bd80 pop {r7, pc}
8005a5e: bf00 nop
8005a60: 20001394 .word 0x20001394
8005a64: 20001398 .word 0x20001398
8005a68: e000ed04 .word 0xe000ed04
08005a6c <prvGetNextExpireTime>:
/*-----------------------------------------------------------*/
static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
{
8005a6c: b480 push {r7}
8005a6e: b085 sub sp, #20
8005a70: af00 add r7, sp, #0
8005a72: 6078 str r0, [r7, #4]
the timer with the nearest expiry time will expire. If there are no
active timers then just set the next expire time to 0. That will cause
this task to unblock when the tick count overflows, at which point the
timer lists will be switched and the next expiry time can be
re-assessed. */
*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
8005a74: 4b0e ldr r3, [pc, #56] @ (8005ab0 <prvGetNextExpireTime+0x44>)
8005a76: 681b ldr r3, [r3, #0]
8005a78: 681b ldr r3, [r3, #0]
8005a7a: 2b00 cmp r3, #0
8005a7c: d101 bne.n 8005a82 <prvGetNextExpireTime+0x16>
8005a7e: 2201 movs r2, #1
8005a80: e000 b.n 8005a84 <prvGetNextExpireTime+0x18>
8005a82: 2200 movs r2, #0
8005a84: 687b ldr r3, [r7, #4]
8005a86: 601a str r2, [r3, #0]
if( *pxListWasEmpty == pdFALSE )
8005a88: 687b ldr r3, [r7, #4]
8005a8a: 681b ldr r3, [r3, #0]
8005a8c: 2b00 cmp r3, #0
8005a8e: d105 bne.n 8005a9c <prvGetNextExpireTime+0x30>
{
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
8005a90: 4b07 ldr r3, [pc, #28] @ (8005ab0 <prvGetNextExpireTime+0x44>)
8005a92: 681b ldr r3, [r3, #0]
8005a94: 68db ldr r3, [r3, #12]
8005a96: 681b ldr r3, [r3, #0]
8005a98: 60fb str r3, [r7, #12]
8005a9a: e001 b.n 8005aa0 <prvGetNextExpireTime+0x34>
}
else
{
/* Ensure the task unblocks when the tick count rolls over. */
xNextExpireTime = ( TickType_t ) 0U;
8005a9c: 2300 movs r3, #0
8005a9e: 60fb str r3, [r7, #12]
}
return xNextExpireTime;
8005aa0: 68fb ldr r3, [r7, #12]
}
8005aa2: 4618 mov r0, r3
8005aa4: 3714 adds r7, #20
8005aa6: 46bd mov sp, r7
8005aa8: f85d 7b04 ldr.w r7, [sp], #4
8005aac: 4770 bx lr
8005aae: bf00 nop
8005ab0: 20001390 .word 0x20001390
08005ab4 <prvSampleTimeNow>:
/*-----------------------------------------------------------*/
static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
{
8005ab4: b580 push {r7, lr}
8005ab6: b084 sub sp, #16
8005ab8: af00 add r7, sp, #0
8005aba: 6078 str r0, [r7, #4]
TickType_t xTimeNow;
PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
xTimeNow = xTaskGetTickCount();
8005abc: f7ff fa58 bl 8004f70 <xTaskGetTickCount>
8005ac0: 60f8 str r0, [r7, #12]
if( xTimeNow < xLastTime )
8005ac2: 4b0b ldr r3, [pc, #44] @ (8005af0 <prvSampleTimeNow+0x3c>)
8005ac4: 681b ldr r3, [r3, #0]
8005ac6: 68fa ldr r2, [r7, #12]
8005ac8: 429a cmp r2, r3
8005aca: d205 bcs.n 8005ad8 <prvSampleTimeNow+0x24>
{
prvSwitchTimerLists();
8005acc: f000 f940 bl 8005d50 <prvSwitchTimerLists>
*pxTimerListsWereSwitched = pdTRUE;
8005ad0: 687b ldr r3, [r7, #4]
8005ad2: 2201 movs r2, #1
8005ad4: 601a str r2, [r3, #0]
8005ad6: e002 b.n 8005ade <prvSampleTimeNow+0x2a>
}
else
{
*pxTimerListsWereSwitched = pdFALSE;
8005ad8: 687b ldr r3, [r7, #4]
8005ada: 2200 movs r2, #0
8005adc: 601a str r2, [r3, #0]
}
xLastTime = xTimeNow;
8005ade: 4a04 ldr r2, [pc, #16] @ (8005af0 <prvSampleTimeNow+0x3c>)
8005ae0: 68fb ldr r3, [r7, #12]
8005ae2: 6013 str r3, [r2, #0]
return xTimeNow;
8005ae4: 68fb ldr r3, [r7, #12]
}
8005ae6: 4618 mov r0, r3
8005ae8: 3710 adds r7, #16
8005aea: 46bd mov sp, r7
8005aec: bd80 pop {r7, pc}
8005aee: bf00 nop
8005af0: 200013a0 .word 0x200013a0
08005af4 <prvInsertTimerInActiveList>:
/*-----------------------------------------------------------*/
static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
{
8005af4: b580 push {r7, lr}
8005af6: b086 sub sp, #24
8005af8: af00 add r7, sp, #0
8005afa: 60f8 str r0, [r7, #12]
8005afc: 60b9 str r1, [r7, #8]
8005afe: 607a str r2, [r7, #4]
8005b00: 603b str r3, [r7, #0]
BaseType_t xProcessTimerNow = pdFALSE;
8005b02: 2300 movs r3, #0
8005b04: 617b str r3, [r7, #20]
listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
8005b06: 68fb ldr r3, [r7, #12]
8005b08: 68ba ldr r2, [r7, #8]
8005b0a: 605a str r2, [r3, #4]
listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
8005b0c: 68fb ldr r3, [r7, #12]
8005b0e: 68fa ldr r2, [r7, #12]
8005b10: 611a str r2, [r3, #16]
if( xNextExpiryTime <= xTimeNow )
8005b12: 68ba ldr r2, [r7, #8]
8005b14: 687b ldr r3, [r7, #4]
8005b16: 429a cmp r2, r3
8005b18: d812 bhi.n 8005b40 <prvInsertTimerInActiveList+0x4c>
{
/* Has the expiry time elapsed between the command to start/reset a
timer was issued, and the time the command was processed? */
if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8005b1a: 687a ldr r2, [r7, #4]
8005b1c: 683b ldr r3, [r7, #0]
8005b1e: 1ad2 subs r2, r2, r3
8005b20: 68fb ldr r3, [r7, #12]
8005b22: 699b ldr r3, [r3, #24]
8005b24: 429a cmp r2, r3
8005b26: d302 bcc.n 8005b2e <prvInsertTimerInActiveList+0x3a>
{
/* The time between a command being issued and the command being
processed actually exceeds the timers period. */
xProcessTimerNow = pdTRUE;
8005b28: 2301 movs r3, #1
8005b2a: 617b str r3, [r7, #20]
8005b2c: e01b b.n 8005b66 <prvInsertTimerInActiveList+0x72>
}
else
{
vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
8005b2e: 4b10 ldr r3, [pc, #64] @ (8005b70 <prvInsertTimerInActiveList+0x7c>)
8005b30: 681a ldr r2, [r3, #0]
8005b32: 68fb ldr r3, [r7, #12]
8005b34: 3304 adds r3, #4
8005b36: 4619 mov r1, r3
8005b38: 4610 mov r0, r2
8005b3a: f7fe f99c bl 8003e76 <vListInsert>
8005b3e: e012 b.n 8005b66 <prvInsertTimerInActiveList+0x72>
}
}
else
{
if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
8005b40: 687a ldr r2, [r7, #4]
8005b42: 683b ldr r3, [r7, #0]
8005b44: 429a cmp r2, r3
8005b46: d206 bcs.n 8005b56 <prvInsertTimerInActiveList+0x62>
8005b48: 68ba ldr r2, [r7, #8]
8005b4a: 683b ldr r3, [r7, #0]
8005b4c: 429a cmp r2, r3
8005b4e: d302 bcc.n 8005b56 <prvInsertTimerInActiveList+0x62>
{
/* If, since the command was issued, the tick count has overflowed
but the expiry time has not, then the timer must have already passed
its expiry time and should be processed immediately. */
xProcessTimerNow = pdTRUE;
8005b50: 2301 movs r3, #1
8005b52: 617b str r3, [r7, #20]
8005b54: e007 b.n 8005b66 <prvInsertTimerInActiveList+0x72>
}
else
{
vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
8005b56: 4b07 ldr r3, [pc, #28] @ (8005b74 <prvInsertTimerInActiveList+0x80>)
8005b58: 681a ldr r2, [r3, #0]
8005b5a: 68fb ldr r3, [r7, #12]
8005b5c: 3304 adds r3, #4
8005b5e: 4619 mov r1, r3
8005b60: 4610 mov r0, r2
8005b62: f7fe f988 bl 8003e76 <vListInsert>
}
}
return xProcessTimerNow;
8005b66: 697b ldr r3, [r7, #20]
}
8005b68: 4618 mov r0, r3
8005b6a: 3718 adds r7, #24
8005b6c: 46bd mov sp, r7
8005b6e: bd80 pop {r7, pc}
8005b70: 20001394 .word 0x20001394
8005b74: 20001390 .word 0x20001390
08005b78 <prvProcessReceivedCommands>:
/*-----------------------------------------------------------*/
static void prvProcessReceivedCommands( void )
{
8005b78: b580 push {r7, lr}
8005b7a: b08e sub sp, #56 @ 0x38
8005b7c: af02 add r7, sp, #8
DaemonTaskMessage_t xMessage;
Timer_t *pxTimer;
BaseType_t xTimerListsWereSwitched, xResult;
TickType_t xTimeNow;
while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
8005b7e: e0d4 b.n 8005d2a <prvProcessReceivedCommands+0x1b2>
{
#if ( INCLUDE_xTimerPendFunctionCall == 1 )
{
/* Negative commands are pended function calls rather than timer
commands. */
if( xMessage.xMessageID < ( BaseType_t ) 0 )
8005b80: 687b ldr r3, [r7, #4]
8005b82: 2b00 cmp r3, #0
8005b84: da1b bge.n 8005bbe <prvProcessReceivedCommands+0x46>
{
const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
8005b86: 1d3b adds r3, r7, #4
8005b88: 3304 adds r3, #4
8005b8a: 62fb str r3, [r7, #44] @ 0x2c
/* The timer uses the xCallbackParameters member to request a
callback be executed. Check the callback is not NULL. */
configASSERT( pxCallback );
8005b8c: 6afb ldr r3, [r7, #44] @ 0x2c
8005b8e: 2b00 cmp r3, #0
8005b90: d10d bne.n 8005bae <prvProcessReceivedCommands+0x36>
__asm volatile
8005b92: f04f 0350 mov.w r3, #80 @ 0x50
8005b96: b672 cpsid i
8005b98: f383 8811 msr BASEPRI, r3
8005b9c: f3bf 8f6f isb sy
8005ba0: f3bf 8f4f dsb sy
8005ba4: b662 cpsie i
8005ba6: 61fb str r3, [r7, #28]
}
8005ba8: bf00 nop
8005baa: bf00 nop
8005bac: e7fd b.n 8005baa <prvProcessReceivedCommands+0x32>
/* Call the function. */
pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
8005bae: 6afb ldr r3, [r7, #44] @ 0x2c
8005bb0: 681b ldr r3, [r3, #0]
8005bb2: 6afa ldr r2, [r7, #44] @ 0x2c
8005bb4: 6850 ldr r0, [r2, #4]
8005bb6: 6afa ldr r2, [r7, #44] @ 0x2c
8005bb8: 6892 ldr r2, [r2, #8]
8005bba: 4611 mov r1, r2
8005bbc: 4798 blx r3
}
#endif /* INCLUDE_xTimerPendFunctionCall */
/* Commands that are positive are timer commands rather than pended
function calls. */
if( xMessage.xMessageID >= ( BaseType_t ) 0 )
8005bbe: 687b ldr r3, [r7, #4]
8005bc0: 2b00 cmp r3, #0
8005bc2: f2c0 80b2 blt.w 8005d2a <prvProcessReceivedCommands+0x1b2>
{
/* The messages uses the xTimerParameters member to work on a
software timer. */
pxTimer = xMessage.u.xTimerParameters.pxTimer;
8005bc6: 68fb ldr r3, [r7, #12]
8005bc8: 62bb str r3, [r7, #40] @ 0x28
if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
8005bca: 6abb ldr r3, [r7, #40] @ 0x28
8005bcc: 695b ldr r3, [r3, #20]
8005bce: 2b00 cmp r3, #0
8005bd0: d004 beq.n 8005bdc <prvProcessReceivedCommands+0x64>
{
/* The timer is in a list, remove it. */
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
8005bd2: 6abb ldr r3, [r7, #40] @ 0x28
8005bd4: 3304 adds r3, #4
8005bd6: 4618 mov r0, r3
8005bd8: f7fe f986 bl 8003ee8 <uxListRemove>
it must be present in the function call. prvSampleTimeNow() must be
called after the message is received from xTimerQueue so there is no
possibility of a higher priority task adding a message to the message
queue with a time that is ahead of the timer daemon task (because it
pre-empted the timer daemon task after the xTimeNow value was set). */
xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
8005bdc: 463b mov r3, r7
8005bde: 4618 mov r0, r3
8005be0: f7ff ff68 bl 8005ab4 <prvSampleTimeNow>
8005be4: 6278 str r0, [r7, #36] @ 0x24
switch( xMessage.xMessageID )
8005be6: 687b ldr r3, [r7, #4]
8005be8: 2b09 cmp r3, #9
8005bea: f200 809b bhi.w 8005d24 <prvProcessReceivedCommands+0x1ac>
8005bee: a201 add r2, pc, #4 @ (adr r2, 8005bf4 <prvProcessReceivedCommands+0x7c>)
8005bf0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8005bf4: 08005c1d .word 0x08005c1d
8005bf8: 08005c1d .word 0x08005c1d
8005bfc: 08005c1d .word 0x08005c1d
8005c00: 08005c97 .word 0x08005c97
8005c04: 08005cab .word 0x08005cab
8005c08: 08005cfb .word 0x08005cfb
8005c0c: 08005c1d .word 0x08005c1d
8005c10: 08005c1d .word 0x08005c1d
8005c14: 08005c97 .word 0x08005c97
8005c18: 08005cab .word 0x08005cab
case tmrCOMMAND_START_FROM_ISR :
case tmrCOMMAND_RESET :
case tmrCOMMAND_RESET_FROM_ISR :
case tmrCOMMAND_START_DONT_TRACE :
/* Start or restart a timer. */
pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
8005c1c: 6abb ldr r3, [r7, #40] @ 0x28
8005c1e: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8005c22: f043 0301 orr.w r3, r3, #1
8005c26: b2da uxtb r2, r3
8005c28: 6abb ldr r3, [r7, #40] @ 0x28
8005c2a: f883 2028 strb.w r2, [r3, #40] @ 0x28
if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
8005c2e: 68ba ldr r2, [r7, #8]
8005c30: 6abb ldr r3, [r7, #40] @ 0x28
8005c32: 699b ldr r3, [r3, #24]
8005c34: 18d1 adds r1, r2, r3
8005c36: 68bb ldr r3, [r7, #8]
8005c38: 6a7a ldr r2, [r7, #36] @ 0x24
8005c3a: 6ab8 ldr r0, [r7, #40] @ 0x28
8005c3c: f7ff ff5a bl 8005af4 <prvInsertTimerInActiveList>
8005c40: 4603 mov r3, r0
8005c42: 2b00 cmp r3, #0
8005c44: d070 beq.n 8005d28 <prvProcessReceivedCommands+0x1b0>
{
/* The timer expired before it was added to the active
timer list. Process it now. */
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
8005c46: 6abb ldr r3, [r7, #40] @ 0x28
8005c48: 6a1b ldr r3, [r3, #32]
8005c4a: 6ab8 ldr r0, [r7, #40] @ 0x28
8005c4c: 4798 blx r3
traceTIMER_EXPIRED( pxTimer );
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
8005c4e: 6abb ldr r3, [r7, #40] @ 0x28
8005c50: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8005c54: f003 0304 and.w r3, r3, #4
8005c58: 2b00 cmp r3, #0
8005c5a: d065 beq.n 8005d28 <prvProcessReceivedCommands+0x1b0>
{
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
8005c5c: 68ba ldr r2, [r7, #8]
8005c5e: 6abb ldr r3, [r7, #40] @ 0x28
8005c60: 699b ldr r3, [r3, #24]
8005c62: 441a add r2, r3
8005c64: 2300 movs r3, #0
8005c66: 9300 str r3, [sp, #0]
8005c68: 2300 movs r3, #0
8005c6a: 2100 movs r1, #0
8005c6c: 6ab8 ldr r0, [r7, #40] @ 0x28
8005c6e: f7ff fdfb bl 8005868 <xTimerGenericCommand>
8005c72: 6238 str r0, [r7, #32]
configASSERT( xResult );
8005c74: 6a3b ldr r3, [r7, #32]
8005c76: 2b00 cmp r3, #0
8005c78: d156 bne.n 8005d28 <prvProcessReceivedCommands+0x1b0>
__asm volatile
8005c7a: f04f 0350 mov.w r3, #80 @ 0x50
8005c7e: b672 cpsid i
8005c80: f383 8811 msr BASEPRI, r3
8005c84: f3bf 8f6f isb sy
8005c88: f3bf 8f4f dsb sy
8005c8c: b662 cpsie i
8005c8e: 61bb str r3, [r7, #24]
}
8005c90: bf00 nop
8005c92: bf00 nop
8005c94: e7fd b.n 8005c92 <prvProcessReceivedCommands+0x11a>
break;
case tmrCOMMAND_STOP :
case tmrCOMMAND_STOP_FROM_ISR :
/* The timer has already been removed from the active list. */
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
8005c96: 6abb ldr r3, [r7, #40] @ 0x28
8005c98: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8005c9c: f023 0301 bic.w r3, r3, #1
8005ca0: b2da uxtb r2, r3
8005ca2: 6abb ldr r3, [r7, #40] @ 0x28
8005ca4: f883 2028 strb.w r2, [r3, #40] @ 0x28
break;
8005ca8: e03f b.n 8005d2a <prvProcessReceivedCommands+0x1b2>
case tmrCOMMAND_CHANGE_PERIOD :
case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
8005caa: 6abb ldr r3, [r7, #40] @ 0x28
8005cac: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8005cb0: f043 0301 orr.w r3, r3, #1
8005cb4: b2da uxtb r2, r3
8005cb6: 6abb ldr r3, [r7, #40] @ 0x28
8005cb8: f883 2028 strb.w r2, [r3, #40] @ 0x28
pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
8005cbc: 68ba ldr r2, [r7, #8]
8005cbe: 6abb ldr r3, [r7, #40] @ 0x28
8005cc0: 619a str r2, [r3, #24]
configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
8005cc2: 6abb ldr r3, [r7, #40] @ 0x28
8005cc4: 699b ldr r3, [r3, #24]
8005cc6: 2b00 cmp r3, #0
8005cc8: d10d bne.n 8005ce6 <prvProcessReceivedCommands+0x16e>
__asm volatile
8005cca: f04f 0350 mov.w r3, #80 @ 0x50
8005cce: b672 cpsid i
8005cd0: f383 8811 msr BASEPRI, r3
8005cd4: f3bf 8f6f isb sy
8005cd8: f3bf 8f4f dsb sy
8005cdc: b662 cpsie i
8005cde: 617b str r3, [r7, #20]
}
8005ce0: bf00 nop
8005ce2: bf00 nop
8005ce4: e7fd b.n 8005ce2 <prvProcessReceivedCommands+0x16a>
be longer or shorter than the old one. The command time is
therefore set to the current time, and as the period cannot
be zero the next expiry time can only be in the future,
meaning (unlike for the xTimerStart() case above) there is
no fail case that needs to be handled here. */
( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
8005ce6: 6abb ldr r3, [r7, #40] @ 0x28
8005ce8: 699a ldr r2, [r3, #24]
8005cea: 6a7b ldr r3, [r7, #36] @ 0x24
8005cec: 18d1 adds r1, r2, r3
8005cee: 6a7b ldr r3, [r7, #36] @ 0x24
8005cf0: 6a7a ldr r2, [r7, #36] @ 0x24
8005cf2: 6ab8 ldr r0, [r7, #40] @ 0x28
8005cf4: f7ff fefe bl 8005af4 <prvInsertTimerInActiveList>
break;
8005cf8: e017 b.n 8005d2a <prvProcessReceivedCommands+0x1b2>
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
{
/* The timer has already been removed from the active list,
just free up the memory if the memory was dynamically
allocated. */
if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
8005cfa: 6abb ldr r3, [r7, #40] @ 0x28
8005cfc: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8005d00: f003 0302 and.w r3, r3, #2
8005d04: 2b00 cmp r3, #0
8005d06: d103 bne.n 8005d10 <prvProcessReceivedCommands+0x198>
{
vPortFree( pxTimer );
8005d08: 6ab8 ldr r0, [r7, #40] @ 0x28
8005d0a: f000 fbd3 bl 80064b4 <vPortFree>
no need to free the memory - just mark the timer as
"not active". */
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
break;
8005d0e: e00c b.n 8005d2a <prvProcessReceivedCommands+0x1b2>
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
8005d10: 6abb ldr r3, [r7, #40] @ 0x28
8005d12: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8005d16: f023 0301 bic.w r3, r3, #1
8005d1a: b2da uxtb r2, r3
8005d1c: 6abb ldr r3, [r7, #40] @ 0x28
8005d1e: f883 2028 strb.w r2, [r3, #40] @ 0x28
break;
8005d22: e002 b.n 8005d2a <prvProcessReceivedCommands+0x1b2>
default :
/* Don't expect to get here. */
break;
8005d24: bf00 nop
8005d26: e000 b.n 8005d2a <prvProcessReceivedCommands+0x1b2>
break;
8005d28: bf00 nop
while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
8005d2a: 4b08 ldr r3, [pc, #32] @ (8005d4c <prvProcessReceivedCommands+0x1d4>)
8005d2c: 681b ldr r3, [r3, #0]
8005d2e: 1d39 adds r1, r7, #4
8005d30: 2200 movs r2, #0
8005d32: 4618 mov r0, r3
8005d34: f7fe fbc6 bl 80044c4 <xQueueReceive>
8005d38: 4603 mov r3, r0
8005d3a: 2b00 cmp r3, #0
8005d3c: f47f af20 bne.w 8005b80 <prvProcessReceivedCommands+0x8>
}
}
}
}
8005d40: bf00 nop
8005d42: bf00 nop
8005d44: 3730 adds r7, #48 @ 0x30
8005d46: 46bd mov sp, r7
8005d48: bd80 pop {r7, pc}
8005d4a: bf00 nop
8005d4c: 20001398 .word 0x20001398
08005d50 <prvSwitchTimerLists>:
/*-----------------------------------------------------------*/
static void prvSwitchTimerLists( void )
{
8005d50: b580 push {r7, lr}
8005d52: b088 sub sp, #32
8005d54: af02 add r7, sp, #8
/* The tick count has overflowed. The timer lists must be switched.
If there are any timers still referenced from the current timer list
then they must have expired and should be processed before the lists
are switched. */
while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
8005d56: e04b b.n 8005df0 <prvSwitchTimerLists+0xa0>
{
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
8005d58: 4b2f ldr r3, [pc, #188] @ (8005e18 <prvSwitchTimerLists+0xc8>)
8005d5a: 681b ldr r3, [r3, #0]
8005d5c: 68db ldr r3, [r3, #12]
8005d5e: 681b ldr r3, [r3, #0]
8005d60: 613b str r3, [r7, #16]
/* Remove the timer from the list. */
pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8005d62: 4b2d ldr r3, [pc, #180] @ (8005e18 <prvSwitchTimerLists+0xc8>)
8005d64: 681b ldr r3, [r3, #0]
8005d66: 68db ldr r3, [r3, #12]
8005d68: 68db ldr r3, [r3, #12]
8005d6a: 60fb str r3, [r7, #12]
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
8005d6c: 68fb ldr r3, [r7, #12]
8005d6e: 3304 adds r3, #4
8005d70: 4618 mov r0, r3
8005d72: f7fe f8b9 bl 8003ee8 <uxListRemove>
traceTIMER_EXPIRED( pxTimer );
/* Execute its callback, then send a command to restart the timer if
it is an auto-reload timer. It cannot be restarted here as the lists
have not yet been switched. */
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
8005d76: 68fb ldr r3, [r7, #12]
8005d78: 6a1b ldr r3, [r3, #32]
8005d7a: 68f8 ldr r0, [r7, #12]
8005d7c: 4798 blx r3
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
8005d7e: 68fb ldr r3, [r7, #12]
8005d80: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8005d84: f003 0304 and.w r3, r3, #4
8005d88: 2b00 cmp r3, #0
8005d8a: d031 beq.n 8005df0 <prvSwitchTimerLists+0xa0>
the timer going into the same timer list then it has already expired
and the timer should be re-inserted into the current list so it is
processed again within this loop. Otherwise a command should be sent
to restart the timer to ensure it is only inserted into a list after
the lists have been swapped. */
xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
8005d8c: 68fb ldr r3, [r7, #12]
8005d8e: 699b ldr r3, [r3, #24]
8005d90: 693a ldr r2, [r7, #16]
8005d92: 4413 add r3, r2
8005d94: 60bb str r3, [r7, #8]
if( xReloadTime > xNextExpireTime )
8005d96: 68ba ldr r2, [r7, #8]
8005d98: 693b ldr r3, [r7, #16]
8005d9a: 429a cmp r2, r3
8005d9c: d90e bls.n 8005dbc <prvSwitchTimerLists+0x6c>
{
listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
8005d9e: 68fb ldr r3, [r7, #12]
8005da0: 68ba ldr r2, [r7, #8]
8005da2: 605a str r2, [r3, #4]
listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
8005da4: 68fb ldr r3, [r7, #12]
8005da6: 68fa ldr r2, [r7, #12]
8005da8: 611a str r2, [r3, #16]
vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
8005daa: 4b1b ldr r3, [pc, #108] @ (8005e18 <prvSwitchTimerLists+0xc8>)
8005dac: 681a ldr r2, [r3, #0]
8005dae: 68fb ldr r3, [r7, #12]
8005db0: 3304 adds r3, #4
8005db2: 4619 mov r1, r3
8005db4: 4610 mov r0, r2
8005db6: f7fe f85e bl 8003e76 <vListInsert>
8005dba: e019 b.n 8005df0 <prvSwitchTimerLists+0xa0>
}
else
{
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
8005dbc: 2300 movs r3, #0
8005dbe: 9300 str r3, [sp, #0]
8005dc0: 2300 movs r3, #0
8005dc2: 693a ldr r2, [r7, #16]
8005dc4: 2100 movs r1, #0
8005dc6: 68f8 ldr r0, [r7, #12]
8005dc8: f7ff fd4e bl 8005868 <xTimerGenericCommand>
8005dcc: 6078 str r0, [r7, #4]
configASSERT( xResult );
8005dce: 687b ldr r3, [r7, #4]
8005dd0: 2b00 cmp r3, #0
8005dd2: d10d bne.n 8005df0 <prvSwitchTimerLists+0xa0>
__asm volatile
8005dd4: f04f 0350 mov.w r3, #80 @ 0x50
8005dd8: b672 cpsid i
8005dda: f383 8811 msr BASEPRI, r3
8005dde: f3bf 8f6f isb sy
8005de2: f3bf 8f4f dsb sy
8005de6: b662 cpsie i
8005de8: 603b str r3, [r7, #0]
}
8005dea: bf00 nop
8005dec: bf00 nop
8005dee: e7fd b.n 8005dec <prvSwitchTimerLists+0x9c>
while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
8005df0: 4b09 ldr r3, [pc, #36] @ (8005e18 <prvSwitchTimerLists+0xc8>)
8005df2: 681b ldr r3, [r3, #0]
8005df4: 681b ldr r3, [r3, #0]
8005df6: 2b00 cmp r3, #0
8005df8: d1ae bne.n 8005d58 <prvSwitchTimerLists+0x8>
{
mtCOVERAGE_TEST_MARKER();
}
}
pxTemp = pxCurrentTimerList;
8005dfa: 4b07 ldr r3, [pc, #28] @ (8005e18 <prvSwitchTimerLists+0xc8>)
8005dfc: 681b ldr r3, [r3, #0]
8005dfe: 617b str r3, [r7, #20]
pxCurrentTimerList = pxOverflowTimerList;
8005e00: 4b06 ldr r3, [pc, #24] @ (8005e1c <prvSwitchTimerLists+0xcc>)
8005e02: 681b ldr r3, [r3, #0]
8005e04: 4a04 ldr r2, [pc, #16] @ (8005e18 <prvSwitchTimerLists+0xc8>)
8005e06: 6013 str r3, [r2, #0]
pxOverflowTimerList = pxTemp;
8005e08: 4a04 ldr r2, [pc, #16] @ (8005e1c <prvSwitchTimerLists+0xcc>)
8005e0a: 697b ldr r3, [r7, #20]
8005e0c: 6013 str r3, [r2, #0]
}
8005e0e: bf00 nop
8005e10: 3718 adds r7, #24
8005e12: 46bd mov sp, r7
8005e14: bd80 pop {r7, pc}
8005e16: bf00 nop
8005e18: 20001390 .word 0x20001390
8005e1c: 20001394 .word 0x20001394
08005e20 <prvCheckForValidListAndQueue>:
/*-----------------------------------------------------------*/
static void prvCheckForValidListAndQueue( void )
{
8005e20: b580 push {r7, lr}
8005e22: b082 sub sp, #8
8005e24: af02 add r7, sp, #8
/* Check that the list from which active timers are referenced, and the
queue used to communicate with the timer service, have been
initialised. */
taskENTER_CRITICAL();
8005e26: f000 f949 bl 80060bc <vPortEnterCritical>
{
if( xTimerQueue == NULL )
8005e2a: 4b15 ldr r3, [pc, #84] @ (8005e80 <prvCheckForValidListAndQueue+0x60>)
8005e2c: 681b ldr r3, [r3, #0]
8005e2e: 2b00 cmp r3, #0
8005e30: d120 bne.n 8005e74 <prvCheckForValidListAndQueue+0x54>
{
vListInitialise( &xActiveTimerList1 );
8005e32: 4814 ldr r0, [pc, #80] @ (8005e84 <prvCheckForValidListAndQueue+0x64>)
8005e34: f7fd ffce bl 8003dd4 <vListInitialise>
vListInitialise( &xActiveTimerList2 );
8005e38: 4813 ldr r0, [pc, #76] @ (8005e88 <prvCheckForValidListAndQueue+0x68>)
8005e3a: f7fd ffcb bl 8003dd4 <vListInitialise>
pxCurrentTimerList = &xActiveTimerList1;
8005e3e: 4b13 ldr r3, [pc, #76] @ (8005e8c <prvCheckForValidListAndQueue+0x6c>)
8005e40: 4a10 ldr r2, [pc, #64] @ (8005e84 <prvCheckForValidListAndQueue+0x64>)
8005e42: 601a str r2, [r3, #0]
pxOverflowTimerList = &xActiveTimerList2;
8005e44: 4b12 ldr r3, [pc, #72] @ (8005e90 <prvCheckForValidListAndQueue+0x70>)
8005e46: 4a10 ldr r2, [pc, #64] @ (8005e88 <prvCheckForValidListAndQueue+0x68>)
8005e48: 601a str r2, [r3, #0]
/* The timer queue is allocated statically in case
configSUPPORT_DYNAMIC_ALLOCATION is 0. */
static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
8005e4a: 2300 movs r3, #0
8005e4c: 9300 str r3, [sp, #0]
8005e4e: 4b11 ldr r3, [pc, #68] @ (8005e94 <prvCheckForValidListAndQueue+0x74>)
8005e50: 4a11 ldr r2, [pc, #68] @ (8005e98 <prvCheckForValidListAndQueue+0x78>)
8005e52: 2110 movs r1, #16
8005e54: 200a movs r0, #10
8005e56: f7fe f8dd bl 8004014 <xQueueGenericCreateStatic>
8005e5a: 4603 mov r3, r0
8005e5c: 4a08 ldr r2, [pc, #32] @ (8005e80 <prvCheckForValidListAndQueue+0x60>)
8005e5e: 6013 str r3, [r2, #0]
}
#endif
#if ( configQUEUE_REGISTRY_SIZE > 0 )
{
if( xTimerQueue != NULL )
8005e60: 4b07 ldr r3, [pc, #28] @ (8005e80 <prvCheckForValidListAndQueue+0x60>)
8005e62: 681b ldr r3, [r3, #0]
8005e64: 2b00 cmp r3, #0
8005e66: d005 beq.n 8005e74 <prvCheckForValidListAndQueue+0x54>
{
vQueueAddToRegistry( xTimerQueue, "TmrQ" );
8005e68: 4b05 ldr r3, [pc, #20] @ (8005e80 <prvCheckForValidListAndQueue+0x60>)
8005e6a: 681b ldr r3, [r3, #0]
8005e6c: 490b ldr r1, [pc, #44] @ (8005e9c <prvCheckForValidListAndQueue+0x7c>)
8005e6e: 4618 mov r0, r3
8005e70: f7fe fd20 bl 80048b4 <vQueueAddToRegistry>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
8005e74: f000 f958 bl 8006128 <vPortExitCritical>
}
8005e78: bf00 nop
8005e7a: 46bd mov sp, r7
8005e7c: bd80 pop {r7, pc}
8005e7e: bf00 nop
8005e80: 20001398 .word 0x20001398
8005e84: 20001368 .word 0x20001368
8005e88: 2000137c .word 0x2000137c
8005e8c: 20001390 .word 0x20001390
8005e90: 20001394 .word 0x20001394
8005e94: 20001444 .word 0x20001444
8005e98: 200013a4 .word 0x200013a4
8005e9c: 080075d8 .word 0x080075d8
08005ea0 <pxPortInitialiseStack>:
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
8005ea0: b480 push {r7}
8005ea2: b085 sub sp, #20
8005ea4: af00 add r7, sp, #0
8005ea6: 60f8 str r0, [r7, #12]
8005ea8: 60b9 str r1, [r7, #8]
8005eaa: 607a str r2, [r7, #4]
/* Simulate the stack frame as it would be created by a context switch
interrupt. */
/* Offset added to account for the way the MCU uses the stack on entry/exit
of interrupts, and to ensure alignment. */
pxTopOfStack--;
8005eac: 68fb ldr r3, [r7, #12]
8005eae: 3b04 subs r3, #4
8005eb0: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
8005eb2: 68fb ldr r3, [r7, #12]
8005eb4: f04f 7280 mov.w r2, #16777216 @ 0x1000000
8005eb8: 601a str r2, [r3, #0]
pxTopOfStack--;
8005eba: 68fb ldr r3, [r7, #12]
8005ebc: 3b04 subs r3, #4
8005ebe: 60fb str r3, [r7, #12]
*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
8005ec0: 68bb ldr r3, [r7, #8]
8005ec2: f023 0201 bic.w r2, r3, #1
8005ec6: 68fb ldr r3, [r7, #12]
8005ec8: 601a str r2, [r3, #0]
pxTopOfStack--;
8005eca: 68fb ldr r3, [r7, #12]
8005ecc: 3b04 subs r3, #4
8005ece: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
8005ed0: 4a0c ldr r2, [pc, #48] @ (8005f04 <pxPortInitialiseStack+0x64>)
8005ed2: 68fb ldr r3, [r7, #12]
8005ed4: 601a str r2, [r3, #0]
/* Save code space by skipping register initialisation. */
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
8005ed6: 68fb ldr r3, [r7, #12]
8005ed8: 3b14 subs r3, #20
8005eda: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
8005edc: 687a ldr r2, [r7, #4]
8005ede: 68fb ldr r3, [r7, #12]
8005ee0: 601a str r2, [r3, #0]
/* A save method is being used that requires each task to maintain its
own exec return value. */
pxTopOfStack--;
8005ee2: 68fb ldr r3, [r7, #12]
8005ee4: 3b04 subs r3, #4
8005ee6: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_EXC_RETURN;
8005ee8: 68fb ldr r3, [r7, #12]
8005eea: f06f 0202 mvn.w r2, #2
8005eee: 601a str r2, [r3, #0]
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
8005ef0: 68fb ldr r3, [r7, #12]
8005ef2: 3b20 subs r3, #32
8005ef4: 60fb str r3, [r7, #12]
return pxTopOfStack;
8005ef6: 68fb ldr r3, [r7, #12]
}
8005ef8: 4618 mov r0, r3
8005efa: 3714 adds r7, #20
8005efc: 46bd mov sp, r7
8005efe: f85d 7b04 ldr.w r7, [sp], #4
8005f02: 4770 bx lr
8005f04: 08005f09 .word 0x08005f09
08005f08 <prvTaskExitError>:
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
8005f08: b480 push {r7}
8005f0a: b085 sub sp, #20
8005f0c: af00 add r7, sp, #0
volatile uint32_t ulDummy = 0;
8005f0e: 2300 movs r3, #0
8005f10: 607b str r3, [r7, #4]
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
configASSERT( uxCriticalNesting == ~0UL );
8005f12: 4b15 ldr r3, [pc, #84] @ (8005f68 <prvTaskExitError+0x60>)
8005f14: 681b ldr r3, [r3, #0]
8005f16: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8005f1a: d00d beq.n 8005f38 <prvTaskExitError+0x30>
__asm volatile
8005f1c: f04f 0350 mov.w r3, #80 @ 0x50
8005f20: b672 cpsid i
8005f22: f383 8811 msr BASEPRI, r3
8005f26: f3bf 8f6f isb sy
8005f2a: f3bf 8f4f dsb sy
8005f2e: b662 cpsie i
8005f30: 60fb str r3, [r7, #12]
}
8005f32: bf00 nop
8005f34: bf00 nop
8005f36: e7fd b.n 8005f34 <prvTaskExitError+0x2c>
__asm volatile
8005f38: f04f 0350 mov.w r3, #80 @ 0x50
8005f3c: b672 cpsid i
8005f3e: f383 8811 msr BASEPRI, r3
8005f42: f3bf 8f6f isb sy
8005f46: f3bf 8f4f dsb sy
8005f4a: b662 cpsie i
8005f4c: 60bb str r3, [r7, #8]
}
8005f4e: bf00 nop
portDISABLE_INTERRUPTS();
while( ulDummy == 0 )
8005f50: bf00 nop
8005f52: 687b ldr r3, [r7, #4]
8005f54: 2b00 cmp r3, #0
8005f56: d0fc beq.n 8005f52 <prvTaskExitError+0x4a>
about code appearing after this function is called - making ulDummy
volatile makes the compiler think the function could return and
therefore not output an 'unreachable code' warning for code that appears
after it. */
}
}
8005f58: bf00 nop
8005f5a: bf00 nop
8005f5c: 3714 adds r7, #20
8005f5e: 46bd mov sp, r7
8005f60: f85d 7b04 ldr.w r7, [sp], #4
8005f64: 4770 bx lr
8005f66: bf00 nop
8005f68: 2000000c .word 0x2000000c
8005f6c: 00000000 .word 0x00000000
08005f70 <SVC_Handler>:
/*-----------------------------------------------------------*/
void vPortSVCHandler( void )
{
__asm volatile (
8005f70: 4b07 ldr r3, [pc, #28] @ (8005f90 <pxCurrentTCBConst2>)
8005f72: 6819 ldr r1, [r3, #0]
8005f74: 6808 ldr r0, [r1, #0]
8005f76: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8005f7a: f380 8809 msr PSP, r0
8005f7e: f3bf 8f6f isb sy
8005f82: f04f 0000 mov.w r0, #0
8005f86: f380 8811 msr BASEPRI, r0
8005f8a: 4770 bx lr
8005f8c: f3af 8000 nop.w
08005f90 <pxCurrentTCBConst2>:
8005f90: 20000e68 .word 0x20000e68
" bx r14 \n"
" \n"
" .align 4 \n"
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
}
8005f94: bf00 nop
8005f96: bf00 nop
08005f98 <prvPortStartFirstTask>:
{
/* Start the first task. This also clears the bit that indicates the FPU is
in use in case the FPU was used before the scheduler was started - which
would otherwise result in the unnecessary leaving of space in the SVC stack
for lazy saving of FPU registers. */
__asm volatile(
8005f98: 4808 ldr r0, [pc, #32] @ (8005fbc <prvPortStartFirstTask+0x24>)
8005f9a: 6800 ldr r0, [r0, #0]
8005f9c: 6800 ldr r0, [r0, #0]
8005f9e: f380 8808 msr MSP, r0
8005fa2: f04f 0000 mov.w r0, #0
8005fa6: f380 8814 msr CONTROL, r0
8005faa: b662 cpsie i
8005fac: b661 cpsie f
8005fae: f3bf 8f4f dsb sy
8005fb2: f3bf 8f6f isb sy
8005fb6: df00 svc 0
8005fb8: bf00 nop
" dsb \n"
" isb \n"
" svc 0 \n" /* System call to start first task. */
" nop \n"
);
}
8005fba: bf00 nop
8005fbc: e000ed08 .word 0xe000ed08
08005fc0 <xPortStartScheduler>:
/*
* See header file for description.
*/
BaseType_t xPortStartScheduler( void )
{
8005fc0: b580 push {r7, lr}
8005fc2: b084 sub sp, #16
8005fc4: af00 add r7, sp, #0
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
#if( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
8005fc6: 4b37 ldr r3, [pc, #220] @ (80060a4 <xPortStartScheduler+0xe4>)
8005fc8: 60fb str r3, [r7, #12]
functions can be called. ISR safe functions are those that end in
"FromISR". FreeRTOS maintains separate thread and ISR API functions to
ensure interrupt entry is as fast and simple as possible.
Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
8005fca: 68fb ldr r3, [r7, #12]
8005fcc: 781b ldrb r3, [r3, #0]
8005fce: b2db uxtb r3, r3
8005fd0: 607b str r3, [r7, #4]
/* Determine the number of priority bits available. First write to all
possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
8005fd2: 68fb ldr r3, [r7, #12]
8005fd4: 22ff movs r2, #255 @ 0xff
8005fd6: 701a strb r2, [r3, #0]
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
8005fd8: 68fb ldr r3, [r7, #12]
8005fda: 781b ldrb r3, [r3, #0]
8005fdc: b2db uxtb r3, r3
8005fde: 70fb strb r3, [r7, #3]
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
8005fe0: 78fb ldrb r3, [r7, #3]
8005fe2: b2db uxtb r3, r3
8005fe4: f003 0350 and.w r3, r3, #80 @ 0x50
8005fe8: b2da uxtb r2, r3
8005fea: 4b2f ldr r3, [pc, #188] @ (80060a8 <xPortStartScheduler+0xe8>)
8005fec: 701a strb r2, [r3, #0]
/* Calculate the maximum acceptable priority group value for the number
of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
8005fee: 4b2f ldr r3, [pc, #188] @ (80060ac <xPortStartScheduler+0xec>)
8005ff0: 2207 movs r2, #7
8005ff2: 601a str r2, [r3, #0]
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
8005ff4: e009 b.n 800600a <xPortStartScheduler+0x4a>
{
ulMaxPRIGROUPValue--;
8005ff6: 4b2d ldr r3, [pc, #180] @ (80060ac <xPortStartScheduler+0xec>)
8005ff8: 681b ldr r3, [r3, #0]
8005ffa: 3b01 subs r3, #1
8005ffc: 4a2b ldr r2, [pc, #172] @ (80060ac <xPortStartScheduler+0xec>)
8005ffe: 6013 str r3, [r2, #0]
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
8006000: 78fb ldrb r3, [r7, #3]
8006002: b2db uxtb r3, r3
8006004: 005b lsls r3, r3, #1
8006006: b2db uxtb r3, r3
8006008: 70fb strb r3, [r7, #3]
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
800600a: 78fb ldrb r3, [r7, #3]
800600c: b2db uxtb r3, r3
800600e: f003 0380 and.w r3, r3, #128 @ 0x80
8006012: 2b80 cmp r3, #128 @ 0x80
8006014: d0ef beq.n 8005ff6 <xPortStartScheduler+0x36>
#ifdef configPRIO_BITS
{
/* Check the FreeRTOS configuration that defines the number of
priority bits matches the number of priority bits actually queried
from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
8006016: 4b25 ldr r3, [pc, #148] @ (80060ac <xPortStartScheduler+0xec>)
8006018: 681b ldr r3, [r3, #0]
800601a: f1c3 0307 rsb r3, r3, #7
800601e: 2b04 cmp r3, #4
8006020: d00d beq.n 800603e <xPortStartScheduler+0x7e>
__asm volatile
8006022: f04f 0350 mov.w r3, #80 @ 0x50
8006026: b672 cpsid i
8006028: f383 8811 msr BASEPRI, r3
800602c: f3bf 8f6f isb sy
8006030: f3bf 8f4f dsb sy
8006034: b662 cpsie i
8006036: 60bb str r3, [r7, #8]
}
8006038: bf00 nop
800603a: bf00 nop
800603c: e7fd b.n 800603a <xPortStartScheduler+0x7a>
}
#endif
/* Shift the priority group value back to its position within the AIRCR
register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
800603e: 4b1b ldr r3, [pc, #108] @ (80060ac <xPortStartScheduler+0xec>)
8006040: 681b ldr r3, [r3, #0]
8006042: 021b lsls r3, r3, #8
8006044: 4a19 ldr r2, [pc, #100] @ (80060ac <xPortStartScheduler+0xec>)
8006046: 6013 str r3, [r2, #0]
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
8006048: 4b18 ldr r3, [pc, #96] @ (80060ac <xPortStartScheduler+0xec>)
800604a: 681b ldr r3, [r3, #0]
800604c: f403 63e0 and.w r3, r3, #1792 @ 0x700
8006050: 4a16 ldr r2, [pc, #88] @ (80060ac <xPortStartScheduler+0xec>)
8006052: 6013 str r3, [r2, #0]
/* Restore the clobbered interrupt priority register to its original
value. */
*pucFirstUserPriorityRegister = ulOriginalPriority;
8006054: 687b ldr r3, [r7, #4]
8006056: b2da uxtb r2, r3
8006058: 68fb ldr r3, [r7, #12]
800605a: 701a strb r2, [r3, #0]
}
#endif /* conifgASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
800605c: 4b14 ldr r3, [pc, #80] @ (80060b0 <xPortStartScheduler+0xf0>)
800605e: 681b ldr r3, [r3, #0]
8006060: 4a13 ldr r2, [pc, #76] @ (80060b0 <xPortStartScheduler+0xf0>)
8006062: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
8006066: 6013 str r3, [r2, #0]
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
8006068: 4b11 ldr r3, [pc, #68] @ (80060b0 <xPortStartScheduler+0xf0>)
800606a: 681b ldr r3, [r3, #0]
800606c: 4a10 ldr r2, [pc, #64] @ (80060b0 <xPortStartScheduler+0xf0>)
800606e: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000
8006072: 6013 str r3, [r2, #0]
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
vPortSetupTimerInterrupt();
8006074: f000 f8dc bl 8006230 <vPortSetupTimerInterrupt>
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
8006078: 4b0e ldr r3, [pc, #56] @ (80060b4 <xPortStartScheduler+0xf4>)
800607a: 2200 movs r2, #0
800607c: 601a str r2, [r3, #0]
/* Ensure the VFP is enabled - it should be anyway. */
vPortEnableVFP();
800607e: f000 f8fb bl 8006278 <vPortEnableVFP>
/* Lazy save always. */
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
8006082: 4b0d ldr r3, [pc, #52] @ (80060b8 <xPortStartScheduler+0xf8>)
8006084: 681b ldr r3, [r3, #0]
8006086: 4a0c ldr r2, [pc, #48] @ (80060b8 <xPortStartScheduler+0xf8>)
8006088: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000
800608c: 6013 str r3, [r2, #0]
/* Start the first task. */
prvPortStartFirstTask();
800608e: f7ff ff83 bl 8005f98 <prvPortStartFirstTask>
exit error function to prevent compiler warnings about a static function
not being called in the case that the application writer overrides this
functionality by defining configTASK_RETURN_ADDRESS. Call
vTaskSwitchContext() so link time optimisation does not remove the
symbol. */
vTaskSwitchContext();
8006092: f7ff f839 bl 8005108 <vTaskSwitchContext>
prvTaskExitError();
8006096: f7ff ff37 bl 8005f08 <prvTaskExitError>
/* Should not get here! */
return 0;
800609a: 2300 movs r3, #0
}
800609c: 4618 mov r0, r3
800609e: 3710 adds r7, #16
80060a0: 46bd mov sp, r7
80060a2: bd80 pop {r7, pc}
80060a4: e000e400 .word 0xe000e400
80060a8: 20001494 .word 0x20001494
80060ac: 20001498 .word 0x20001498
80060b0: e000ed20 .word 0xe000ed20
80060b4: 2000000c .word 0x2000000c
80060b8: e000ef34 .word 0xe000ef34
080060bc <vPortEnterCritical>:
configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
80060bc: b480 push {r7}
80060be: b083 sub sp, #12
80060c0: af00 add r7, sp, #0
__asm volatile
80060c2: f04f 0350 mov.w r3, #80 @ 0x50
80060c6: b672 cpsid i
80060c8: f383 8811 msr BASEPRI, r3
80060cc: f3bf 8f6f isb sy
80060d0: f3bf 8f4f dsb sy
80060d4: b662 cpsie i
80060d6: 607b str r3, [r7, #4]
}
80060d8: bf00 nop
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
80060da: 4b11 ldr r3, [pc, #68] @ (8006120 <vPortEnterCritical+0x64>)
80060dc: 681b ldr r3, [r3, #0]
80060de: 3301 adds r3, #1
80060e0: 4a0f ldr r2, [pc, #60] @ (8006120 <vPortEnterCritical+0x64>)
80060e2: 6013 str r3, [r2, #0]
/* This is not the interrupt safe version of the enter critical function so
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
if( uxCriticalNesting == 1 )
80060e4: 4b0e ldr r3, [pc, #56] @ (8006120 <vPortEnterCritical+0x64>)
80060e6: 681b ldr r3, [r3, #0]
80060e8: 2b01 cmp r3, #1
80060ea: d112 bne.n 8006112 <vPortEnterCritical+0x56>
{
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
80060ec: 4b0d ldr r3, [pc, #52] @ (8006124 <vPortEnterCritical+0x68>)
80060ee: 681b ldr r3, [r3, #0]
80060f0: b2db uxtb r3, r3
80060f2: 2b00 cmp r3, #0
80060f4: d00d beq.n 8006112 <vPortEnterCritical+0x56>
__asm volatile
80060f6: f04f 0350 mov.w r3, #80 @ 0x50
80060fa: b672 cpsid i
80060fc: f383 8811 msr BASEPRI, r3
8006100: f3bf 8f6f isb sy
8006104: f3bf 8f4f dsb sy
8006108: b662 cpsie i
800610a: 603b str r3, [r7, #0]
}
800610c: bf00 nop
800610e: bf00 nop
8006110: e7fd b.n 800610e <vPortEnterCritical+0x52>
}
}
8006112: bf00 nop
8006114: 370c adds r7, #12
8006116: 46bd mov sp, r7
8006118: f85d 7b04 ldr.w r7, [sp], #4
800611c: 4770 bx lr
800611e: bf00 nop
8006120: 2000000c .word 0x2000000c
8006124: e000ed04 .word 0xe000ed04
08006128 <vPortExitCritical>:
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
8006128: b480 push {r7}
800612a: b083 sub sp, #12
800612c: af00 add r7, sp, #0
configASSERT( uxCriticalNesting );
800612e: 4b13 ldr r3, [pc, #76] @ (800617c <vPortExitCritical+0x54>)
8006130: 681b ldr r3, [r3, #0]
8006132: 2b00 cmp r3, #0
8006134: d10d bne.n 8006152 <vPortExitCritical+0x2a>
__asm volatile
8006136: f04f 0350 mov.w r3, #80 @ 0x50
800613a: b672 cpsid i
800613c: f383 8811 msr BASEPRI, r3
8006140: f3bf 8f6f isb sy
8006144: f3bf 8f4f dsb sy
8006148: b662 cpsie i
800614a: 607b str r3, [r7, #4]
}
800614c: bf00 nop
800614e: bf00 nop
8006150: e7fd b.n 800614e <vPortExitCritical+0x26>
uxCriticalNesting--;
8006152: 4b0a ldr r3, [pc, #40] @ (800617c <vPortExitCritical+0x54>)
8006154: 681b ldr r3, [r3, #0]
8006156: 3b01 subs r3, #1
8006158: 4a08 ldr r2, [pc, #32] @ (800617c <vPortExitCritical+0x54>)
800615a: 6013 str r3, [r2, #0]
if( uxCriticalNesting == 0 )
800615c: 4b07 ldr r3, [pc, #28] @ (800617c <vPortExitCritical+0x54>)
800615e: 681b ldr r3, [r3, #0]
8006160: 2b00 cmp r3, #0
8006162: d105 bne.n 8006170 <vPortExitCritical+0x48>
8006164: 2300 movs r3, #0
8006166: 603b str r3, [r7, #0]
__asm volatile
8006168: 683b ldr r3, [r7, #0]
800616a: f383 8811 msr BASEPRI, r3
}
800616e: bf00 nop
{
portENABLE_INTERRUPTS();
}
}
8006170: bf00 nop
8006172: 370c adds r7, #12
8006174: 46bd mov sp, r7
8006176: f85d 7b04 ldr.w r7, [sp], #4
800617a: 4770 bx lr
800617c: 2000000c .word 0x2000000c
08006180 <PendSV_Handler>:
void xPortPendSVHandler( void )
{
/* This is a naked function. */
__asm volatile
8006180: f3ef 8009 mrs r0, PSP
8006184: f3bf 8f6f isb sy
8006188: 4b15 ldr r3, [pc, #84] @ (80061e0 <pxCurrentTCBConst>)
800618a: 681a ldr r2, [r3, #0]
800618c: f01e 0f10 tst.w lr, #16
8006190: bf08 it eq
8006192: ed20 8a10 vstmdbeq r0!, {s16-s31}
8006196: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800619a: 6010 str r0, [r2, #0]
800619c: e92d 0009 stmdb sp!, {r0, r3}
80061a0: f04f 0050 mov.w r0, #80 @ 0x50
80061a4: b672 cpsid i
80061a6: f380 8811 msr BASEPRI, r0
80061aa: f3bf 8f4f dsb sy
80061ae: f3bf 8f6f isb sy
80061b2: b662 cpsie i
80061b4: f7fe ffa8 bl 8005108 <vTaskSwitchContext>
80061b8: f04f 0000 mov.w r0, #0
80061bc: f380 8811 msr BASEPRI, r0
80061c0: bc09 pop {r0, r3}
80061c2: 6819 ldr r1, [r3, #0]
80061c4: 6808 ldr r0, [r1, #0]
80061c6: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
80061ca: f01e 0f10 tst.w lr, #16
80061ce: bf08 it eq
80061d0: ecb0 8a10 vldmiaeq r0!, {s16-s31}
80061d4: f380 8809 msr PSP, r0
80061d8: f3bf 8f6f isb sy
80061dc: 4770 bx lr
80061de: bf00 nop
080061e0 <pxCurrentTCBConst>:
80061e0: 20000e68 .word 0x20000e68
" \n"
" .align 4 \n"
"pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
);
}
80061e4: bf00 nop
80061e6: bf00 nop
080061e8 <SysTick_Handler>:
/*-----------------------------------------------------------*/
void xPortSysTickHandler( void )
{
80061e8: b580 push {r7, lr}
80061ea: b082 sub sp, #8
80061ec: af00 add r7, sp, #0
__asm volatile
80061ee: f04f 0350 mov.w r3, #80 @ 0x50
80061f2: b672 cpsid i
80061f4: f383 8811 msr BASEPRI, r3
80061f8: f3bf 8f6f isb sy
80061fc: f3bf 8f4f dsb sy
8006200: b662 cpsie i
8006202: 607b str r3, [r7, #4]
}
8006204: bf00 nop
save and then restore the interrupt mask value as its value is already
known. */
portDISABLE_INTERRUPTS();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
8006206: f7fe fec3 bl 8004f90 <xTaskIncrementTick>
800620a: 4603 mov r3, r0
800620c: 2b00 cmp r3, #0
800620e: d003 beq.n 8006218 <SysTick_Handler+0x30>
{
/* A context switch is required. Context switching is performed in
the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
8006210: 4b06 ldr r3, [pc, #24] @ (800622c <SysTick_Handler+0x44>)
8006212: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8006216: 601a str r2, [r3, #0]
8006218: 2300 movs r3, #0
800621a: 603b str r3, [r7, #0]
__asm volatile
800621c: 683b ldr r3, [r7, #0]
800621e: f383 8811 msr BASEPRI, r3
}
8006222: bf00 nop
}
}
portENABLE_INTERRUPTS();
}
8006224: bf00 nop
8006226: 3708 adds r7, #8
8006228: 46bd mov sp, r7
800622a: bd80 pop {r7, pc}
800622c: e000ed04 .word 0xe000ed04
08006230 <vPortSetupTimerInterrupt>:
/*
* Setup the systick timer to generate the tick interrupts at the required
* frequency.
*/
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
8006230: b480 push {r7}
8006232: af00 add r7, sp, #0
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
8006234: 4b0b ldr r3, [pc, #44] @ (8006264 <vPortSetupTimerInterrupt+0x34>)
8006236: 2200 movs r2, #0
8006238: 601a str r2, [r3, #0]
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
800623a: 4b0b ldr r3, [pc, #44] @ (8006268 <vPortSetupTimerInterrupt+0x38>)
800623c: 2200 movs r2, #0
800623e: 601a str r2, [r3, #0]
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
8006240: 4b0a ldr r3, [pc, #40] @ (800626c <vPortSetupTimerInterrupt+0x3c>)
8006242: 681b ldr r3, [r3, #0]
8006244: 4a0a ldr r2, [pc, #40] @ (8006270 <vPortSetupTimerInterrupt+0x40>)
8006246: fba2 2303 umull r2, r3, r2, r3
800624a: 099b lsrs r3, r3, #6
800624c: 4a09 ldr r2, [pc, #36] @ (8006274 <vPortSetupTimerInterrupt+0x44>)
800624e: 3b01 subs r3, #1
8006250: 6013 str r3, [r2, #0]
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
8006252: 4b04 ldr r3, [pc, #16] @ (8006264 <vPortSetupTimerInterrupt+0x34>)
8006254: 2207 movs r2, #7
8006256: 601a str r2, [r3, #0]
}
8006258: bf00 nop
800625a: 46bd mov sp, r7
800625c: f85d 7b04 ldr.w r7, [sp], #4
8006260: 4770 bx lr
8006262: bf00 nop
8006264: e000e010 .word 0xe000e010
8006268: e000e018 .word 0xe000e018
800626c: 20000000 .word 0x20000000
8006270: 10624dd3 .word 0x10624dd3
8006274: e000e014 .word 0xe000e014
08006278 <vPortEnableVFP>:
/*-----------------------------------------------------------*/
/* This is a naked function. */
static void vPortEnableVFP( void )
{
__asm volatile
8006278: f8df 000c ldr.w r0, [pc, #12] @ 8006288 <vPortEnableVFP+0x10>
800627c: 6801 ldr r1, [r0, #0]
800627e: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
8006282: 6001 str r1, [r0, #0]
8006284: 4770 bx lr
" \n"
" orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
" str r1, [r0] \n"
" bx r14 "
);
}
8006286: bf00 nop
8006288: e000ed88 .word 0xe000ed88
0800628c <vPortValidateInterruptPriority>:
/*-----------------------------------------------------------*/
#if( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void )
{
800628c: b480 push {r7}
800628e: b085 sub sp, #20
8006290: af00 add r7, sp, #0
uint32_t ulCurrentInterrupt;
uint8_t ucCurrentPriority;
/* Obtain the number of the currently executing interrupt. */
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
8006292: f3ef 8305 mrs r3, IPSR
8006296: 60fb str r3, [r7, #12]
/* Is the interrupt number a user defined interrupt? */
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
8006298: 68fb ldr r3, [r7, #12]
800629a: 2b0f cmp r3, #15
800629c: d917 bls.n 80062ce <vPortValidateInterruptPriority+0x42>
{
/* Look up the interrupt's priority. */
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
800629e: 4a1a ldr r2, [pc, #104] @ (8006308 <vPortValidateInterruptPriority+0x7c>)
80062a0: 68fb ldr r3, [r7, #12]
80062a2: 4413 add r3, r2
80062a4: 781b ldrb r3, [r3, #0]
80062a6: 72fb strb r3, [r7, #11]
interrupt entry is as fast and simple as possible.
The following links provide detailed information:
http://www.freertos.org/RTOS-Cortex-M3-M4.html
http://www.freertos.org/FAQHelp.html */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
80062a8: 4b18 ldr r3, [pc, #96] @ (800630c <vPortValidateInterruptPriority+0x80>)
80062aa: 781b ldrb r3, [r3, #0]
80062ac: 7afa ldrb r2, [r7, #11]
80062ae: 429a cmp r2, r3
80062b0: d20d bcs.n 80062ce <vPortValidateInterruptPriority+0x42>
__asm volatile
80062b2: f04f 0350 mov.w r3, #80 @ 0x50
80062b6: b672 cpsid i
80062b8: f383 8811 msr BASEPRI, r3
80062bc: f3bf 8f6f isb sy
80062c0: f3bf 8f4f dsb sy
80062c4: b662 cpsie i
80062c6: 607b str r3, [r7, #4]
}
80062c8: bf00 nop
80062ca: bf00 nop
80062cc: e7fd b.n 80062ca <vPortValidateInterruptPriority+0x3e>
configuration then the correct setting can be achieved on all Cortex-M
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
scheduler. Note however that some vendor specific peripheral libraries
assume a non-zero priority group setting, in which cases using a value
of zero will result in unpredictable behaviour. */
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
80062ce: 4b10 ldr r3, [pc, #64] @ (8006310 <vPortValidateInterruptPriority+0x84>)
80062d0: 681b ldr r3, [r3, #0]
80062d2: f403 62e0 and.w r2, r3, #1792 @ 0x700
80062d6: 4b0f ldr r3, [pc, #60] @ (8006314 <vPortValidateInterruptPriority+0x88>)
80062d8: 681b ldr r3, [r3, #0]
80062da: 429a cmp r2, r3
80062dc: d90d bls.n 80062fa <vPortValidateInterruptPriority+0x6e>
__asm volatile
80062de: f04f 0350 mov.w r3, #80 @ 0x50
80062e2: b672 cpsid i
80062e4: f383 8811 msr BASEPRI, r3
80062e8: f3bf 8f6f isb sy
80062ec: f3bf 8f4f dsb sy
80062f0: b662 cpsie i
80062f2: 603b str r3, [r7, #0]
}
80062f4: bf00 nop
80062f6: bf00 nop
80062f8: e7fd b.n 80062f6 <vPortValidateInterruptPriority+0x6a>
}
80062fa: bf00 nop
80062fc: 3714 adds r7, #20
80062fe: 46bd mov sp, r7
8006300: f85d 7b04 ldr.w r7, [sp], #4
8006304: 4770 bx lr
8006306: bf00 nop
8006308: e000e3f0 .word 0xe000e3f0
800630c: 20001494 .word 0x20001494
8006310: e000ed0c .word 0xe000ed0c
8006314: 20001498 .word 0x20001498
08006318 <pvPortMalloc>:
static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
void *pvPortMalloc( size_t xWantedSize )
{
8006318: b580 push {r7, lr}
800631a: b08a sub sp, #40 @ 0x28
800631c: af00 add r7, sp, #0
800631e: 6078 str r0, [r7, #4]
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
void *pvReturn = NULL;
8006320: 2300 movs r3, #0
8006322: 61fb str r3, [r7, #28]
vTaskSuspendAll();
8006324: f7fe fd76 bl 8004e14 <vTaskSuspendAll>
{
/* If this is the first call to malloc then the heap will require
initialisation to setup the list of free blocks. */
if( pxEnd == NULL )
8006328: 4b5d ldr r3, [pc, #372] @ (80064a0 <pvPortMalloc+0x188>)
800632a: 681b ldr r3, [r3, #0]
800632c: 2b00 cmp r3, #0
800632e: d101 bne.n 8006334 <pvPortMalloc+0x1c>
{
prvHeapInit();
8006330: f000 f920 bl 8006574 <prvHeapInit>
/* Check the requested block size is not so large that the top bit is
set. The top bit of the block size member of the BlockLink_t structure
is used to determine who owns the block - the application or the
kernel, so it must be free. */
if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
8006334: 4b5b ldr r3, [pc, #364] @ (80064a4 <pvPortMalloc+0x18c>)
8006336: 681a ldr r2, [r3, #0]
8006338: 687b ldr r3, [r7, #4]
800633a: 4013 ands r3, r2
800633c: 2b00 cmp r3, #0
800633e: f040 8094 bne.w 800646a <pvPortMalloc+0x152>
{
/* The wanted size is increased so it can contain a BlockLink_t
structure in addition to the requested amount of bytes. */
if( xWantedSize > 0 )
8006342: 687b ldr r3, [r7, #4]
8006344: 2b00 cmp r3, #0
8006346: d020 beq.n 800638a <pvPortMalloc+0x72>
{
xWantedSize += xHeapStructSize;
8006348: 2208 movs r2, #8
800634a: 687b ldr r3, [r7, #4]
800634c: 4413 add r3, r2
800634e: 607b str r3, [r7, #4]
/* Ensure that blocks are always aligned to the required number
of bytes. */
if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
8006350: 687b ldr r3, [r7, #4]
8006352: f003 0307 and.w r3, r3, #7
8006356: 2b00 cmp r3, #0
8006358: d017 beq.n 800638a <pvPortMalloc+0x72>
{
/* Byte alignment required. */
xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
800635a: 687b ldr r3, [r7, #4]
800635c: f023 0307 bic.w r3, r3, #7
8006360: 3308 adds r3, #8
8006362: 607b str r3, [r7, #4]
configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
8006364: 687b ldr r3, [r7, #4]
8006366: f003 0307 and.w r3, r3, #7
800636a: 2b00 cmp r3, #0
800636c: d00d beq.n 800638a <pvPortMalloc+0x72>
__asm volatile
800636e: f04f 0350 mov.w r3, #80 @ 0x50
8006372: b672 cpsid i
8006374: f383 8811 msr BASEPRI, r3
8006378: f3bf 8f6f isb sy
800637c: f3bf 8f4f dsb sy
8006380: b662 cpsie i
8006382: 617b str r3, [r7, #20]
}
8006384: bf00 nop
8006386: bf00 nop
8006388: e7fd b.n 8006386 <pvPortMalloc+0x6e>
else
{
mtCOVERAGE_TEST_MARKER();
}
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
800638a: 687b ldr r3, [r7, #4]
800638c: 2b00 cmp r3, #0
800638e: d06c beq.n 800646a <pvPortMalloc+0x152>
8006390: 4b45 ldr r3, [pc, #276] @ (80064a8 <pvPortMalloc+0x190>)
8006392: 681b ldr r3, [r3, #0]
8006394: 687a ldr r2, [r7, #4]
8006396: 429a cmp r2, r3
8006398: d867 bhi.n 800646a <pvPortMalloc+0x152>
{
/* Traverse the list from the start (lowest address) block until
one of adequate size is found. */
pxPreviousBlock = &xStart;
800639a: 4b44 ldr r3, [pc, #272] @ (80064ac <pvPortMalloc+0x194>)
800639c: 623b str r3, [r7, #32]
pxBlock = xStart.pxNextFreeBlock;
800639e: 4b43 ldr r3, [pc, #268] @ (80064ac <pvPortMalloc+0x194>)
80063a0: 681b ldr r3, [r3, #0]
80063a2: 627b str r3, [r7, #36] @ 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
80063a4: e004 b.n 80063b0 <pvPortMalloc+0x98>
{
pxPreviousBlock = pxBlock;
80063a6: 6a7b ldr r3, [r7, #36] @ 0x24
80063a8: 623b str r3, [r7, #32]
pxBlock = pxBlock->pxNextFreeBlock;
80063aa: 6a7b ldr r3, [r7, #36] @ 0x24
80063ac: 681b ldr r3, [r3, #0]
80063ae: 627b str r3, [r7, #36] @ 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
80063b0: 6a7b ldr r3, [r7, #36] @ 0x24
80063b2: 685b ldr r3, [r3, #4]
80063b4: 687a ldr r2, [r7, #4]
80063b6: 429a cmp r2, r3
80063b8: d903 bls.n 80063c2 <pvPortMalloc+0xaa>
80063ba: 6a7b ldr r3, [r7, #36] @ 0x24
80063bc: 681b ldr r3, [r3, #0]
80063be: 2b00 cmp r3, #0
80063c0: d1f1 bne.n 80063a6 <pvPortMalloc+0x8e>
}
/* If the end marker was reached then a block of adequate size
was not found. */
if( pxBlock != pxEnd )
80063c2: 4b37 ldr r3, [pc, #220] @ (80064a0 <pvPortMalloc+0x188>)
80063c4: 681b ldr r3, [r3, #0]
80063c6: 6a7a ldr r2, [r7, #36] @ 0x24
80063c8: 429a cmp r2, r3
80063ca: d04e beq.n 800646a <pvPortMalloc+0x152>
{
/* Return the memory space pointed to - jumping over the
BlockLink_t structure at its start. */
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
80063cc: 6a3b ldr r3, [r7, #32]
80063ce: 681b ldr r3, [r3, #0]
80063d0: 2208 movs r2, #8
80063d2: 4413 add r3, r2
80063d4: 61fb str r3, [r7, #28]
/* This block is being returned for use so must be taken out
of the list of free blocks. */
pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
80063d6: 6a7b ldr r3, [r7, #36] @ 0x24
80063d8: 681a ldr r2, [r3, #0]
80063da: 6a3b ldr r3, [r7, #32]
80063dc: 601a str r2, [r3, #0]
/* If the block is larger than required it can be split into
two. */
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
80063de: 6a7b ldr r3, [r7, #36] @ 0x24
80063e0: 685a ldr r2, [r3, #4]
80063e2: 687b ldr r3, [r7, #4]
80063e4: 1ad2 subs r2, r2, r3
80063e6: 2308 movs r3, #8
80063e8: 005b lsls r3, r3, #1
80063ea: 429a cmp r2, r3
80063ec: d922 bls.n 8006434 <pvPortMalloc+0x11c>
{
/* This block is to be split into two. Create a new
block following the number of bytes requested. The void
cast is used to prevent byte alignment warnings from the
compiler. */
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
80063ee: 6a7a ldr r2, [r7, #36] @ 0x24
80063f0: 687b ldr r3, [r7, #4]
80063f2: 4413 add r3, r2
80063f4: 61bb str r3, [r7, #24]
configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
80063f6: 69bb ldr r3, [r7, #24]
80063f8: f003 0307 and.w r3, r3, #7
80063fc: 2b00 cmp r3, #0
80063fe: d00d beq.n 800641c <pvPortMalloc+0x104>
__asm volatile
8006400: f04f 0350 mov.w r3, #80 @ 0x50
8006404: b672 cpsid i
8006406: f383 8811 msr BASEPRI, r3
800640a: f3bf 8f6f isb sy
800640e: f3bf 8f4f dsb sy
8006412: b662 cpsie i
8006414: 613b str r3, [r7, #16]
}
8006416: bf00 nop
8006418: bf00 nop
800641a: e7fd b.n 8006418 <pvPortMalloc+0x100>
/* Calculate the sizes of two blocks split from the
single block. */
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
800641c: 6a7b ldr r3, [r7, #36] @ 0x24
800641e: 685a ldr r2, [r3, #4]
8006420: 687b ldr r3, [r7, #4]
8006422: 1ad2 subs r2, r2, r3
8006424: 69bb ldr r3, [r7, #24]
8006426: 605a str r2, [r3, #4]
pxBlock->xBlockSize = xWantedSize;
8006428: 6a7b ldr r3, [r7, #36] @ 0x24
800642a: 687a ldr r2, [r7, #4]
800642c: 605a str r2, [r3, #4]
/* Insert the new block into the list of free blocks. */
prvInsertBlockIntoFreeList( pxNewBlockLink );
800642e: 69b8 ldr r0, [r7, #24]
8006430: f000 f902 bl 8006638 <prvInsertBlockIntoFreeList>
else
{
mtCOVERAGE_TEST_MARKER();
}
xFreeBytesRemaining -= pxBlock->xBlockSize;
8006434: 4b1c ldr r3, [pc, #112] @ (80064a8 <pvPortMalloc+0x190>)
8006436: 681a ldr r2, [r3, #0]
8006438: 6a7b ldr r3, [r7, #36] @ 0x24
800643a: 685b ldr r3, [r3, #4]
800643c: 1ad3 subs r3, r2, r3
800643e: 4a1a ldr r2, [pc, #104] @ (80064a8 <pvPortMalloc+0x190>)
8006440: 6013 str r3, [r2, #0]
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
8006442: 4b19 ldr r3, [pc, #100] @ (80064a8 <pvPortMalloc+0x190>)
8006444: 681a ldr r2, [r3, #0]
8006446: 4b1a ldr r3, [pc, #104] @ (80064b0 <pvPortMalloc+0x198>)
8006448: 681b ldr r3, [r3, #0]
800644a: 429a cmp r2, r3
800644c: d203 bcs.n 8006456 <pvPortMalloc+0x13e>
{
xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
800644e: 4b16 ldr r3, [pc, #88] @ (80064a8 <pvPortMalloc+0x190>)
8006450: 681b ldr r3, [r3, #0]
8006452: 4a17 ldr r2, [pc, #92] @ (80064b0 <pvPortMalloc+0x198>)
8006454: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
/* The block is being returned - it is allocated and owned
by the application and has no "next" block. */
pxBlock->xBlockSize |= xBlockAllocatedBit;
8006456: 6a7b ldr r3, [r7, #36] @ 0x24
8006458: 685a ldr r2, [r3, #4]
800645a: 4b12 ldr r3, [pc, #72] @ (80064a4 <pvPortMalloc+0x18c>)
800645c: 681b ldr r3, [r3, #0]
800645e: 431a orrs r2, r3
8006460: 6a7b ldr r3, [r7, #36] @ 0x24
8006462: 605a str r2, [r3, #4]
pxBlock->pxNextFreeBlock = NULL;
8006464: 6a7b ldr r3, [r7, #36] @ 0x24
8006466: 2200 movs r2, #0
8006468: 601a str r2, [r3, #0]
mtCOVERAGE_TEST_MARKER();
}
traceMALLOC( pvReturn, xWantedSize );
}
( void ) xTaskResumeAll();
800646a: f7fe fce1 bl 8004e30 <xTaskResumeAll>
mtCOVERAGE_TEST_MARKER();
}
}
#endif
configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
800646e: 69fb ldr r3, [r7, #28]
8006470: f003 0307 and.w r3, r3, #7
8006474: 2b00 cmp r3, #0
8006476: d00d beq.n 8006494 <pvPortMalloc+0x17c>
__asm volatile
8006478: f04f 0350 mov.w r3, #80 @ 0x50
800647c: b672 cpsid i
800647e: f383 8811 msr BASEPRI, r3
8006482: f3bf 8f6f isb sy
8006486: f3bf 8f4f dsb sy
800648a: b662 cpsie i
800648c: 60fb str r3, [r7, #12]
}
800648e: bf00 nop
8006490: bf00 nop
8006492: e7fd b.n 8006490 <pvPortMalloc+0x178>
return pvReturn;
8006494: 69fb ldr r3, [r7, #28]
}
8006496: 4618 mov r0, r3
8006498: 3728 adds r7, #40 @ 0x28
800649a: 46bd mov sp, r7
800649c: bd80 pop {r7, pc}
800649e: bf00 nop
80064a0: 200050a4 .word 0x200050a4
80064a4: 200050b0 .word 0x200050b0
80064a8: 200050a8 .word 0x200050a8
80064ac: 2000509c .word 0x2000509c
80064b0: 200050ac .word 0x200050ac
080064b4 <vPortFree>:
/*-----------------------------------------------------------*/
void vPortFree( void *pv )
{
80064b4: b580 push {r7, lr}
80064b6: b086 sub sp, #24
80064b8: af00 add r7, sp, #0
80064ba: 6078 str r0, [r7, #4]
uint8_t *puc = ( uint8_t * ) pv;
80064bc: 687b ldr r3, [r7, #4]
80064be: 617b str r3, [r7, #20]
BlockLink_t *pxLink;
if( pv != NULL )
80064c0: 687b ldr r3, [r7, #4]
80064c2: 2b00 cmp r3, #0
80064c4: d04e beq.n 8006564 <vPortFree+0xb0>
{
/* The memory being freed will have an BlockLink_t structure immediately
before it. */
puc -= xHeapStructSize;
80064c6: 2308 movs r3, #8
80064c8: 425b negs r3, r3
80064ca: 697a ldr r2, [r7, #20]
80064cc: 4413 add r3, r2
80064ce: 617b str r3, [r7, #20]
/* This casting is to keep the compiler from issuing warnings. */
pxLink = ( void * ) puc;
80064d0: 697b ldr r3, [r7, #20]
80064d2: 613b str r3, [r7, #16]
/* Check the block is actually allocated. */
configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
80064d4: 693b ldr r3, [r7, #16]
80064d6: 685a ldr r2, [r3, #4]
80064d8: 4b24 ldr r3, [pc, #144] @ (800656c <vPortFree+0xb8>)
80064da: 681b ldr r3, [r3, #0]
80064dc: 4013 ands r3, r2
80064de: 2b00 cmp r3, #0
80064e0: d10d bne.n 80064fe <vPortFree+0x4a>
__asm volatile
80064e2: f04f 0350 mov.w r3, #80 @ 0x50
80064e6: b672 cpsid i
80064e8: f383 8811 msr BASEPRI, r3
80064ec: f3bf 8f6f isb sy
80064f0: f3bf 8f4f dsb sy
80064f4: b662 cpsie i
80064f6: 60fb str r3, [r7, #12]
}
80064f8: bf00 nop
80064fa: bf00 nop
80064fc: e7fd b.n 80064fa <vPortFree+0x46>
configASSERT( pxLink->pxNextFreeBlock == NULL );
80064fe: 693b ldr r3, [r7, #16]
8006500: 681b ldr r3, [r3, #0]
8006502: 2b00 cmp r3, #0
8006504: d00d beq.n 8006522 <vPortFree+0x6e>
__asm volatile
8006506: f04f 0350 mov.w r3, #80 @ 0x50
800650a: b672 cpsid i
800650c: f383 8811 msr BASEPRI, r3
8006510: f3bf 8f6f isb sy
8006514: f3bf 8f4f dsb sy
8006518: b662 cpsie i
800651a: 60bb str r3, [r7, #8]
}
800651c: bf00 nop
800651e: bf00 nop
8006520: e7fd b.n 800651e <vPortFree+0x6a>
if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
8006522: 693b ldr r3, [r7, #16]
8006524: 685a ldr r2, [r3, #4]
8006526: 4b11 ldr r3, [pc, #68] @ (800656c <vPortFree+0xb8>)
8006528: 681b ldr r3, [r3, #0]
800652a: 4013 ands r3, r2
800652c: 2b00 cmp r3, #0
800652e: d019 beq.n 8006564 <vPortFree+0xb0>
{
if( pxLink->pxNextFreeBlock == NULL )
8006530: 693b ldr r3, [r7, #16]
8006532: 681b ldr r3, [r3, #0]
8006534: 2b00 cmp r3, #0
8006536: d115 bne.n 8006564 <vPortFree+0xb0>
{
/* The block is being returned to the heap - it is no longer
allocated. */
pxLink->xBlockSize &= ~xBlockAllocatedBit;
8006538: 693b ldr r3, [r7, #16]
800653a: 685a ldr r2, [r3, #4]
800653c: 4b0b ldr r3, [pc, #44] @ (800656c <vPortFree+0xb8>)
800653e: 681b ldr r3, [r3, #0]
8006540: 43db mvns r3, r3
8006542: 401a ands r2, r3
8006544: 693b ldr r3, [r7, #16]
8006546: 605a str r2, [r3, #4]
vTaskSuspendAll();
8006548: f7fe fc64 bl 8004e14 <vTaskSuspendAll>
{
/* Add this block to the list of free blocks. */
xFreeBytesRemaining += pxLink->xBlockSize;
800654c: 693b ldr r3, [r7, #16]
800654e: 685a ldr r2, [r3, #4]
8006550: 4b07 ldr r3, [pc, #28] @ (8006570 <vPortFree+0xbc>)
8006552: 681b ldr r3, [r3, #0]
8006554: 4413 add r3, r2
8006556: 4a06 ldr r2, [pc, #24] @ (8006570 <vPortFree+0xbc>)
8006558: 6013 str r3, [r2, #0]
traceFREE( pv, pxLink->xBlockSize );
prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
800655a: 6938 ldr r0, [r7, #16]
800655c: f000 f86c bl 8006638 <prvInsertBlockIntoFreeList>
}
( void ) xTaskResumeAll();
8006560: f7fe fc66 bl 8004e30 <xTaskResumeAll>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
}
8006564: bf00 nop
8006566: 3718 adds r7, #24
8006568: 46bd mov sp, r7
800656a: bd80 pop {r7, pc}
800656c: 200050b0 .word 0x200050b0
8006570: 200050a8 .word 0x200050a8
08006574 <prvHeapInit>:
/* This just exists to keep the linker quiet. */
}
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
{
8006574: b480 push {r7}
8006576: b085 sub sp, #20
8006578: af00 add r7, sp, #0
BlockLink_t *pxFirstFreeBlock;
uint8_t *pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
800657a: f44f 5370 mov.w r3, #15360 @ 0x3c00
800657e: 60bb str r3, [r7, #8]
/* Ensure the heap starts on a correctly aligned boundary. */
uxAddress = ( size_t ) ucHeap;
8006580: 4b27 ldr r3, [pc, #156] @ (8006620 <prvHeapInit+0xac>)
8006582: 60fb str r3, [r7, #12]
if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
8006584: 68fb ldr r3, [r7, #12]
8006586: f003 0307 and.w r3, r3, #7
800658a: 2b00 cmp r3, #0
800658c: d00c beq.n 80065a8 <prvHeapInit+0x34>
{
uxAddress += ( portBYTE_ALIGNMENT - 1 );
800658e: 68fb ldr r3, [r7, #12]
8006590: 3307 adds r3, #7
8006592: 60fb str r3, [r7, #12]
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
8006594: 68fb ldr r3, [r7, #12]
8006596: f023 0307 bic.w r3, r3, #7
800659a: 60fb str r3, [r7, #12]
xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
800659c: 68ba ldr r2, [r7, #8]
800659e: 68fb ldr r3, [r7, #12]
80065a0: 1ad3 subs r3, r2, r3
80065a2: 4a1f ldr r2, [pc, #124] @ (8006620 <prvHeapInit+0xac>)
80065a4: 4413 add r3, r2
80065a6: 60bb str r3, [r7, #8]
}
pucAlignedHeap = ( uint8_t * ) uxAddress;
80065a8: 68fb ldr r3, [r7, #12]
80065aa: 607b str r3, [r7, #4]
/* xStart is used to hold a pointer to the first item in the list of free
blocks. The void cast is used to prevent compiler warnings. */
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
80065ac: 4a1d ldr r2, [pc, #116] @ (8006624 <prvHeapInit+0xb0>)
80065ae: 687b ldr r3, [r7, #4]
80065b0: 6013 str r3, [r2, #0]
xStart.xBlockSize = ( size_t ) 0;
80065b2: 4b1c ldr r3, [pc, #112] @ (8006624 <prvHeapInit+0xb0>)
80065b4: 2200 movs r2, #0
80065b6: 605a str r2, [r3, #4]
/* pxEnd is used to mark the end of the list of free blocks and is inserted
at the end of the heap space. */
uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
80065b8: 687b ldr r3, [r7, #4]
80065ba: 68ba ldr r2, [r7, #8]
80065bc: 4413 add r3, r2
80065be: 60fb str r3, [r7, #12]
uxAddress -= xHeapStructSize;
80065c0: 2208 movs r2, #8
80065c2: 68fb ldr r3, [r7, #12]
80065c4: 1a9b subs r3, r3, r2
80065c6: 60fb str r3, [r7, #12]
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
80065c8: 68fb ldr r3, [r7, #12]
80065ca: f023 0307 bic.w r3, r3, #7
80065ce: 60fb str r3, [r7, #12]
pxEnd = ( void * ) uxAddress;
80065d0: 68fb ldr r3, [r7, #12]
80065d2: 4a15 ldr r2, [pc, #84] @ (8006628 <prvHeapInit+0xb4>)
80065d4: 6013 str r3, [r2, #0]
pxEnd->xBlockSize = 0;
80065d6: 4b14 ldr r3, [pc, #80] @ (8006628 <prvHeapInit+0xb4>)
80065d8: 681b ldr r3, [r3, #0]
80065da: 2200 movs r2, #0
80065dc: 605a str r2, [r3, #4]
pxEnd->pxNextFreeBlock = NULL;
80065de: 4b12 ldr r3, [pc, #72] @ (8006628 <prvHeapInit+0xb4>)
80065e0: 681b ldr r3, [r3, #0]
80065e2: 2200 movs r2, #0
80065e4: 601a str r2, [r3, #0]
/* To start with there is a single free block that is sized to take up the
entire heap space, minus the space taken by pxEnd. */
pxFirstFreeBlock = ( void * ) pucAlignedHeap;
80065e6: 687b ldr r3, [r7, #4]
80065e8: 603b str r3, [r7, #0]
pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
80065ea: 683b ldr r3, [r7, #0]
80065ec: 68fa ldr r2, [r7, #12]
80065ee: 1ad2 subs r2, r2, r3
80065f0: 683b ldr r3, [r7, #0]
80065f2: 605a str r2, [r3, #4]
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
80065f4: 4b0c ldr r3, [pc, #48] @ (8006628 <prvHeapInit+0xb4>)
80065f6: 681a ldr r2, [r3, #0]
80065f8: 683b ldr r3, [r7, #0]
80065fa: 601a str r2, [r3, #0]
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
80065fc: 683b ldr r3, [r7, #0]
80065fe: 685b ldr r3, [r3, #4]
8006600: 4a0a ldr r2, [pc, #40] @ (800662c <prvHeapInit+0xb8>)
8006602: 6013 str r3, [r2, #0]
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
8006604: 683b ldr r3, [r7, #0]
8006606: 685b ldr r3, [r3, #4]
8006608: 4a09 ldr r2, [pc, #36] @ (8006630 <prvHeapInit+0xbc>)
800660a: 6013 str r3, [r2, #0]
/* Work out the position of the top bit in a size_t variable. */
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
800660c: 4b09 ldr r3, [pc, #36] @ (8006634 <prvHeapInit+0xc0>)
800660e: f04f 4200 mov.w r2, #2147483648 @ 0x80000000
8006612: 601a str r2, [r3, #0]
}
8006614: bf00 nop
8006616: 3714 adds r7, #20
8006618: 46bd mov sp, r7
800661a: f85d 7b04 ldr.w r7, [sp], #4
800661e: 4770 bx lr
8006620: 2000149c .word 0x2000149c
8006624: 2000509c .word 0x2000509c
8006628: 200050a4 .word 0x200050a4
800662c: 200050ac .word 0x200050ac
8006630: 200050a8 .word 0x200050a8
8006634: 200050b0 .word 0x200050b0
08006638 <prvInsertBlockIntoFreeList>:
/*-----------------------------------------------------------*/
static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
{
8006638: b480 push {r7}
800663a: b085 sub sp, #20
800663c: af00 add r7, sp, #0
800663e: 6078 str r0, [r7, #4]
BlockLink_t *pxIterator;
uint8_t *puc;
/* Iterate through the list until a block is found that has a higher address
than the block being inserted. */
for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
8006640: 4b28 ldr r3, [pc, #160] @ (80066e4 <prvInsertBlockIntoFreeList+0xac>)
8006642: 60fb str r3, [r7, #12]
8006644: e002 b.n 800664c <prvInsertBlockIntoFreeList+0x14>
8006646: 68fb ldr r3, [r7, #12]
8006648: 681b ldr r3, [r3, #0]
800664a: 60fb str r3, [r7, #12]
800664c: 68fb ldr r3, [r7, #12]
800664e: 681b ldr r3, [r3, #0]
8006650: 687a ldr r2, [r7, #4]
8006652: 429a cmp r2, r3
8006654: d8f7 bhi.n 8006646 <prvInsertBlockIntoFreeList+0xe>
/* Nothing to do here, just iterate to the right position. */
}
/* Do the block being inserted, and the block it is being inserted after
make a contiguous block of memory? */
puc = ( uint8_t * ) pxIterator;
8006656: 68fb ldr r3, [r7, #12]
8006658: 60bb str r3, [r7, #8]
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
800665a: 68fb ldr r3, [r7, #12]
800665c: 685b ldr r3, [r3, #4]
800665e: 68ba ldr r2, [r7, #8]
8006660: 4413 add r3, r2
8006662: 687a ldr r2, [r7, #4]
8006664: 429a cmp r2, r3
8006666: d108 bne.n 800667a <prvInsertBlockIntoFreeList+0x42>
{
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
8006668: 68fb ldr r3, [r7, #12]
800666a: 685a ldr r2, [r3, #4]
800666c: 687b ldr r3, [r7, #4]
800666e: 685b ldr r3, [r3, #4]
8006670: 441a add r2, r3
8006672: 68fb ldr r3, [r7, #12]
8006674: 605a str r2, [r3, #4]
pxBlockToInsert = pxIterator;
8006676: 68fb ldr r3, [r7, #12]
8006678: 607b str r3, [r7, #4]
mtCOVERAGE_TEST_MARKER();
}
/* Do the block being inserted, and the block it is being inserted before
make a contiguous block of memory? */
puc = ( uint8_t * ) pxBlockToInsert;
800667a: 687b ldr r3, [r7, #4]
800667c: 60bb str r3, [r7, #8]
if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
800667e: 687b ldr r3, [r7, #4]
8006680: 685b ldr r3, [r3, #4]
8006682: 68ba ldr r2, [r7, #8]
8006684: 441a add r2, r3
8006686: 68fb ldr r3, [r7, #12]
8006688: 681b ldr r3, [r3, #0]
800668a: 429a cmp r2, r3
800668c: d118 bne.n 80066c0 <prvInsertBlockIntoFreeList+0x88>
{
if( pxIterator->pxNextFreeBlock != pxEnd )
800668e: 68fb ldr r3, [r7, #12]
8006690: 681a ldr r2, [r3, #0]
8006692: 4b15 ldr r3, [pc, #84] @ (80066e8 <prvInsertBlockIntoFreeList+0xb0>)
8006694: 681b ldr r3, [r3, #0]
8006696: 429a cmp r2, r3
8006698: d00d beq.n 80066b6 <prvInsertBlockIntoFreeList+0x7e>
{
/* Form one big block from the two blocks. */
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
800669a: 687b ldr r3, [r7, #4]
800669c: 685a ldr r2, [r3, #4]
800669e: 68fb ldr r3, [r7, #12]
80066a0: 681b ldr r3, [r3, #0]
80066a2: 685b ldr r3, [r3, #4]
80066a4: 441a add r2, r3
80066a6: 687b ldr r3, [r7, #4]
80066a8: 605a str r2, [r3, #4]
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
80066aa: 68fb ldr r3, [r7, #12]
80066ac: 681b ldr r3, [r3, #0]
80066ae: 681a ldr r2, [r3, #0]
80066b0: 687b ldr r3, [r7, #4]
80066b2: 601a str r2, [r3, #0]
80066b4: e008 b.n 80066c8 <prvInsertBlockIntoFreeList+0x90>
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxEnd;
80066b6: 4b0c ldr r3, [pc, #48] @ (80066e8 <prvInsertBlockIntoFreeList+0xb0>)
80066b8: 681a ldr r2, [r3, #0]
80066ba: 687b ldr r3, [r7, #4]
80066bc: 601a str r2, [r3, #0]
80066be: e003 b.n 80066c8 <prvInsertBlockIntoFreeList+0x90>
}
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
80066c0: 68fb ldr r3, [r7, #12]
80066c2: 681a ldr r2, [r3, #0]
80066c4: 687b ldr r3, [r7, #4]
80066c6: 601a str r2, [r3, #0]
/* If the block being inserted plugged a gab, so was merged with the block
before and the block after, then it's pxNextFreeBlock pointer will have
already been set, and should not be set here as that would make it point
to itself. */
if( pxIterator != pxBlockToInsert )
80066c8: 68fa ldr r2, [r7, #12]
80066ca: 687b ldr r3, [r7, #4]
80066cc: 429a cmp r2, r3
80066ce: d002 beq.n 80066d6 <prvInsertBlockIntoFreeList+0x9e>
{
pxIterator->pxNextFreeBlock = pxBlockToInsert;
80066d0: 68fb ldr r3, [r7, #12]
80066d2: 687a ldr r2, [r7, #4]
80066d4: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
80066d6: bf00 nop
80066d8: 3714 adds r7, #20
80066da: 46bd mov sp, r7
80066dc: f85d 7b04 ldr.w r7, [sp], #4
80066e0: 4770 bx lr
80066e2: bf00 nop
80066e4: 2000509c .word 0x2000509c
80066e8: 200050a4 .word 0x200050a4
080066ec <std>:
80066ec: 2300 movs r3, #0
80066ee: b510 push {r4, lr}
80066f0: 4604 mov r4, r0
80066f2: e9c0 3300 strd r3, r3, [r0]
80066f6: e9c0 3304 strd r3, r3, [r0, #16]
80066fa: 6083 str r3, [r0, #8]
80066fc: 8181 strh r1, [r0, #12]
80066fe: 6643 str r3, [r0, #100] @ 0x64
8006700: 81c2 strh r2, [r0, #14]
8006702: 6183 str r3, [r0, #24]
8006704: 4619 mov r1, r3
8006706: 2208 movs r2, #8
8006708: 305c adds r0, #92 @ 0x5c
800670a: f000 f906 bl 800691a <memset>
800670e: 4b0d ldr r3, [pc, #52] @ (8006744 <std+0x58>)
8006710: 6263 str r3, [r4, #36] @ 0x24
8006712: 4b0d ldr r3, [pc, #52] @ (8006748 <std+0x5c>)
8006714: 62a3 str r3, [r4, #40] @ 0x28
8006716: 4b0d ldr r3, [pc, #52] @ (800674c <std+0x60>)
8006718: 62e3 str r3, [r4, #44] @ 0x2c
800671a: 4b0d ldr r3, [pc, #52] @ (8006750 <std+0x64>)
800671c: 6323 str r3, [r4, #48] @ 0x30
800671e: 4b0d ldr r3, [pc, #52] @ (8006754 <std+0x68>)
8006720: 6224 str r4, [r4, #32]
8006722: 429c cmp r4, r3
8006724: d006 beq.n 8006734 <std+0x48>
8006726: f103 0268 add.w r2, r3, #104 @ 0x68
800672a: 4294 cmp r4, r2
800672c: d002 beq.n 8006734 <std+0x48>
800672e: 33d0 adds r3, #208 @ 0xd0
8006730: 429c cmp r4, r3
8006732: d105 bne.n 8006740 <std+0x54>
8006734: f104 0058 add.w r0, r4, #88 @ 0x58
8006738: e8bd 4010 ldmia.w sp!, {r4, lr}
800673c: f000 b966 b.w 8006a0c <__retarget_lock_init_recursive>
8006740: bd10 pop {r4, pc}
8006742: bf00 nop
8006744: 08006895 .word 0x08006895
8006748: 080068b7 .word 0x080068b7
800674c: 080068ef .word 0x080068ef
8006750: 08006913 .word 0x08006913
8006754: 200050b4 .word 0x200050b4
08006758 <stdio_exit_handler>:
8006758: 4a02 ldr r2, [pc, #8] @ (8006764 <stdio_exit_handler+0xc>)
800675a: 4903 ldr r1, [pc, #12] @ (8006768 <stdio_exit_handler+0x10>)
800675c: 4803 ldr r0, [pc, #12] @ (800676c <stdio_exit_handler+0x14>)
800675e: f000 b869 b.w 8006834 <_fwalk_sglue>
8006762: bf00 nop
8006764: 20000010 .word 0x20000010
8006768: 080072c5 .word 0x080072c5
800676c: 20000020 .word 0x20000020
08006770 <cleanup_stdio>:
8006770: 6841 ldr r1, [r0, #4]
8006772: 4b0c ldr r3, [pc, #48] @ (80067a4 <cleanup_stdio+0x34>)
8006774: 4299 cmp r1, r3
8006776: b510 push {r4, lr}
8006778: 4604 mov r4, r0
800677a: d001 beq.n 8006780 <cleanup_stdio+0x10>
800677c: f000 fda2 bl 80072c4 <_fflush_r>
8006780: 68a1 ldr r1, [r4, #8]
8006782: 4b09 ldr r3, [pc, #36] @ (80067a8 <cleanup_stdio+0x38>)
8006784: 4299 cmp r1, r3
8006786: d002 beq.n 800678e <cleanup_stdio+0x1e>
8006788: 4620 mov r0, r4
800678a: f000 fd9b bl 80072c4 <_fflush_r>
800678e: 68e1 ldr r1, [r4, #12]
8006790: 4b06 ldr r3, [pc, #24] @ (80067ac <cleanup_stdio+0x3c>)
8006792: 4299 cmp r1, r3
8006794: d004 beq.n 80067a0 <cleanup_stdio+0x30>
8006796: 4620 mov r0, r4
8006798: e8bd 4010 ldmia.w sp!, {r4, lr}
800679c: f000 bd92 b.w 80072c4 <_fflush_r>
80067a0: bd10 pop {r4, pc}
80067a2: bf00 nop
80067a4: 200050b4 .word 0x200050b4
80067a8: 2000511c .word 0x2000511c
80067ac: 20005184 .word 0x20005184
080067b0 <global_stdio_init.part.0>:
80067b0: b510 push {r4, lr}
80067b2: 4b0b ldr r3, [pc, #44] @ (80067e0 <global_stdio_init.part.0+0x30>)
80067b4: 4c0b ldr r4, [pc, #44] @ (80067e4 <global_stdio_init.part.0+0x34>)
80067b6: 4a0c ldr r2, [pc, #48] @ (80067e8 <global_stdio_init.part.0+0x38>)
80067b8: 601a str r2, [r3, #0]
80067ba: 4620 mov r0, r4
80067bc: 2200 movs r2, #0
80067be: 2104 movs r1, #4
80067c0: f7ff ff94 bl 80066ec <std>
80067c4: f104 0068 add.w r0, r4, #104 @ 0x68
80067c8: 2201 movs r2, #1
80067ca: 2109 movs r1, #9
80067cc: f7ff ff8e bl 80066ec <std>
80067d0: f104 00d0 add.w r0, r4, #208 @ 0xd0
80067d4: 2202 movs r2, #2
80067d6: e8bd 4010 ldmia.w sp!, {r4, lr}
80067da: 2112 movs r1, #18
80067dc: f7ff bf86 b.w 80066ec <std>
80067e0: 200051ec .word 0x200051ec
80067e4: 200050b4 .word 0x200050b4
80067e8: 08006759 .word 0x08006759
080067ec <__sfp_lock_acquire>:
80067ec: 4801 ldr r0, [pc, #4] @ (80067f4 <__sfp_lock_acquire+0x8>)
80067ee: f000 b90e b.w 8006a0e <__retarget_lock_acquire_recursive>
80067f2: bf00 nop
80067f4: 200051f5 .word 0x200051f5
080067f8 <__sfp_lock_release>:
80067f8: 4801 ldr r0, [pc, #4] @ (8006800 <__sfp_lock_release+0x8>)
80067fa: f000 b909 b.w 8006a10 <__retarget_lock_release_recursive>
80067fe: bf00 nop
8006800: 200051f5 .word 0x200051f5
08006804 <__sinit>:
8006804: b510 push {r4, lr}
8006806: 4604 mov r4, r0
8006808: f7ff fff0 bl 80067ec <__sfp_lock_acquire>
800680c: 6a23 ldr r3, [r4, #32]
800680e: b11b cbz r3, 8006818 <__sinit+0x14>
8006810: e8bd 4010 ldmia.w sp!, {r4, lr}
8006814: f7ff bff0 b.w 80067f8 <__sfp_lock_release>
8006818: 4b04 ldr r3, [pc, #16] @ (800682c <__sinit+0x28>)
800681a: 6223 str r3, [r4, #32]
800681c: 4b04 ldr r3, [pc, #16] @ (8006830 <__sinit+0x2c>)
800681e: 681b ldr r3, [r3, #0]
8006820: 2b00 cmp r3, #0
8006822: d1f5 bne.n 8006810 <__sinit+0xc>
8006824: f7ff ffc4 bl 80067b0 <global_stdio_init.part.0>
8006828: e7f2 b.n 8006810 <__sinit+0xc>
800682a: bf00 nop
800682c: 08006771 .word 0x08006771
8006830: 200051ec .word 0x200051ec
08006834 <_fwalk_sglue>:
8006834: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
8006838: 4607 mov r7, r0
800683a: 4688 mov r8, r1
800683c: 4614 mov r4, r2
800683e: 2600 movs r6, #0
8006840: e9d4 9501 ldrd r9, r5, [r4, #4]
8006844: f1b9 0901 subs.w r9, r9, #1
8006848: d505 bpl.n 8006856 <_fwalk_sglue+0x22>
800684a: 6824 ldr r4, [r4, #0]
800684c: 2c00 cmp r4, #0
800684e: d1f7 bne.n 8006840 <_fwalk_sglue+0xc>
8006850: 4630 mov r0, r6
8006852: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
8006856: 89ab ldrh r3, [r5, #12]
8006858: 2b01 cmp r3, #1
800685a: d907 bls.n 800686c <_fwalk_sglue+0x38>
800685c: f9b5 300e ldrsh.w r3, [r5, #14]
8006860: 3301 adds r3, #1
8006862: d003 beq.n 800686c <_fwalk_sglue+0x38>
8006864: 4629 mov r1, r5
8006866: 4638 mov r0, r7
8006868: 47c0 blx r8
800686a: 4306 orrs r6, r0
800686c: 3568 adds r5, #104 @ 0x68
800686e: e7e9 b.n 8006844 <_fwalk_sglue+0x10>
08006870 <iprintf>:
8006870: b40f push {r0, r1, r2, r3}
8006872: b507 push {r0, r1, r2, lr}
8006874: 4906 ldr r1, [pc, #24] @ (8006890 <iprintf+0x20>)
8006876: ab04 add r3, sp, #16
8006878: 6808 ldr r0, [r1, #0]
800687a: f853 2b04 ldr.w r2, [r3], #4
800687e: 6881 ldr r1, [r0, #8]
8006880: 9301 str r3, [sp, #4]
8006882: f000 f9f7 bl 8006c74 <_vfiprintf_r>
8006886: b003 add sp, #12
8006888: f85d eb04 ldr.w lr, [sp], #4
800688c: b004 add sp, #16
800688e: 4770 bx lr
8006890: 2000001c .word 0x2000001c
08006894 <__sread>:
8006894: b510 push {r4, lr}
8006896: 460c mov r4, r1
8006898: f9b1 100e ldrsh.w r1, [r1, #14]
800689c: f000 f868 bl 8006970 <_read_r>
80068a0: 2800 cmp r0, #0
80068a2: bfab itete ge
80068a4: 6d63 ldrge r3, [r4, #84] @ 0x54
80068a6: 89a3 ldrhlt r3, [r4, #12]
80068a8: 181b addge r3, r3, r0
80068aa: f423 5380 biclt.w r3, r3, #4096 @ 0x1000
80068ae: bfac ite ge
80068b0: 6563 strge r3, [r4, #84] @ 0x54
80068b2: 81a3 strhlt r3, [r4, #12]
80068b4: bd10 pop {r4, pc}
080068b6 <__swrite>:
80068b6: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
80068ba: 461f mov r7, r3
80068bc: 898b ldrh r3, [r1, #12]
80068be: 05db lsls r3, r3, #23
80068c0: 4605 mov r5, r0
80068c2: 460c mov r4, r1
80068c4: 4616 mov r6, r2
80068c6: d505 bpl.n 80068d4 <__swrite+0x1e>
80068c8: f9b1 100e ldrsh.w r1, [r1, #14]
80068cc: 2302 movs r3, #2
80068ce: 2200 movs r2, #0
80068d0: f000 f83c bl 800694c <_lseek_r>
80068d4: 89a3 ldrh r3, [r4, #12]
80068d6: f9b4 100e ldrsh.w r1, [r4, #14]
80068da: f423 5380 bic.w r3, r3, #4096 @ 0x1000
80068de: 81a3 strh r3, [r4, #12]
80068e0: 4632 mov r2, r6
80068e2: 463b mov r3, r7
80068e4: 4628 mov r0, r5
80068e6: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
80068ea: f000 b853 b.w 8006994 <_write_r>
080068ee <__sseek>:
80068ee: b510 push {r4, lr}
80068f0: 460c mov r4, r1
80068f2: f9b1 100e ldrsh.w r1, [r1, #14]
80068f6: f000 f829 bl 800694c <_lseek_r>
80068fa: 1c43 adds r3, r0, #1
80068fc: 89a3 ldrh r3, [r4, #12]
80068fe: bf15 itete ne
8006900: 6560 strne r0, [r4, #84] @ 0x54
8006902: f423 5380 biceq.w r3, r3, #4096 @ 0x1000
8006906: f443 5380 orrne.w r3, r3, #4096 @ 0x1000
800690a: 81a3 strheq r3, [r4, #12]
800690c: bf18 it ne
800690e: 81a3 strhne r3, [r4, #12]
8006910: bd10 pop {r4, pc}
08006912 <__sclose>:
8006912: f9b1 100e ldrsh.w r1, [r1, #14]
8006916: f000 b809 b.w 800692c <_close_r>
0800691a <memset>:
800691a: 4402 add r2, r0
800691c: 4603 mov r3, r0
800691e: 4293 cmp r3, r2
8006920: d100 bne.n 8006924 <memset+0xa>
8006922: 4770 bx lr
8006924: f803 1b01 strb.w r1, [r3], #1
8006928: e7f9 b.n 800691e <memset+0x4>
...
0800692c <_close_r>:
800692c: b538 push {r3, r4, r5, lr}
800692e: 4d06 ldr r5, [pc, #24] @ (8006948 <_close_r+0x1c>)
8006930: 2300 movs r3, #0
8006932: 4604 mov r4, r0
8006934: 4608 mov r0, r1
8006936: 602b str r3, [r5, #0]
8006938: f7fa fcfb bl 8001332 <_close>
800693c: 1c43 adds r3, r0, #1
800693e: d102 bne.n 8006946 <_close_r+0x1a>
8006940: 682b ldr r3, [r5, #0]
8006942: b103 cbz r3, 8006946 <_close_r+0x1a>
8006944: 6023 str r3, [r4, #0]
8006946: bd38 pop {r3, r4, r5, pc}
8006948: 200051f0 .word 0x200051f0
0800694c <_lseek_r>:
800694c: b538 push {r3, r4, r5, lr}
800694e: 4d07 ldr r5, [pc, #28] @ (800696c <_lseek_r+0x20>)
8006950: 4604 mov r4, r0
8006952: 4608 mov r0, r1
8006954: 4611 mov r1, r2
8006956: 2200 movs r2, #0
8006958: 602a str r2, [r5, #0]
800695a: 461a mov r2, r3
800695c: f7fa fd10 bl 8001380 <_lseek>
8006960: 1c43 adds r3, r0, #1
8006962: d102 bne.n 800696a <_lseek_r+0x1e>
8006964: 682b ldr r3, [r5, #0]
8006966: b103 cbz r3, 800696a <_lseek_r+0x1e>
8006968: 6023 str r3, [r4, #0]
800696a: bd38 pop {r3, r4, r5, pc}
800696c: 200051f0 .word 0x200051f0
08006970 <_read_r>:
8006970: b538 push {r3, r4, r5, lr}
8006972: 4d07 ldr r5, [pc, #28] @ (8006990 <_read_r+0x20>)
8006974: 4604 mov r4, r0
8006976: 4608 mov r0, r1
8006978: 4611 mov r1, r2
800697a: 2200 movs r2, #0
800697c: 602a str r2, [r5, #0]
800697e: 461a mov r2, r3
8006980: f7fa fcba bl 80012f8 <_read>
8006984: 1c43 adds r3, r0, #1
8006986: d102 bne.n 800698e <_read_r+0x1e>
8006988: 682b ldr r3, [r5, #0]
800698a: b103 cbz r3, 800698e <_read_r+0x1e>
800698c: 6023 str r3, [r4, #0]
800698e: bd38 pop {r3, r4, r5, pc}
8006990: 200051f0 .word 0x200051f0
08006994 <_write_r>:
8006994: b538 push {r3, r4, r5, lr}
8006996: 4d07 ldr r5, [pc, #28] @ (80069b4 <_write_r+0x20>)
8006998: 4604 mov r4, r0
800699a: 4608 mov r0, r1
800699c: 4611 mov r1, r2
800699e: 2200 movs r2, #0
80069a0: 602a str r2, [r5, #0]
80069a2: 461a mov r2, r3
80069a4: f7f9 fe22 bl 80005ec <_write>
80069a8: 1c43 adds r3, r0, #1
80069aa: d102 bne.n 80069b2 <_write_r+0x1e>
80069ac: 682b ldr r3, [r5, #0]
80069ae: b103 cbz r3, 80069b2 <_write_r+0x1e>
80069b0: 6023 str r3, [r4, #0]
80069b2: bd38 pop {r3, r4, r5, pc}
80069b4: 200051f0 .word 0x200051f0
080069b8 <__errno>:
80069b8: 4b01 ldr r3, [pc, #4] @ (80069c0 <__errno+0x8>)
80069ba: 6818 ldr r0, [r3, #0]
80069bc: 4770 bx lr
80069be: bf00 nop
80069c0: 2000001c .word 0x2000001c
080069c4 <__libc_init_array>:
80069c4: b570 push {r4, r5, r6, lr}
80069c6: 4d0d ldr r5, [pc, #52] @ (80069fc <__libc_init_array+0x38>)
80069c8: 4c0d ldr r4, [pc, #52] @ (8006a00 <__libc_init_array+0x3c>)
80069ca: 1b64 subs r4, r4, r5
80069cc: 10a4 asrs r4, r4, #2
80069ce: 2600 movs r6, #0
80069d0: 42a6 cmp r6, r4
80069d2: d109 bne.n 80069e8 <__libc_init_array+0x24>
80069d4: 4d0b ldr r5, [pc, #44] @ (8006a04 <__libc_init_array+0x40>)
80069d6: 4c0c ldr r4, [pc, #48] @ (8006a08 <__libc_init_array+0x44>)
80069d8: f000 fdc4 bl 8007564 <_init>
80069dc: 1b64 subs r4, r4, r5
80069de: 10a4 asrs r4, r4, #2
80069e0: 2600 movs r6, #0
80069e2: 42a6 cmp r6, r4
80069e4: d105 bne.n 80069f2 <__libc_init_array+0x2e>
80069e6: bd70 pop {r4, r5, r6, pc}
80069e8: f855 3b04 ldr.w r3, [r5], #4
80069ec: 4798 blx r3
80069ee: 3601 adds r6, #1
80069f0: e7ee b.n 80069d0 <__libc_init_array+0xc>
80069f2: f855 3b04 ldr.w r3, [r5], #4
80069f6: 4798 blx r3
80069f8: 3601 adds r6, #1
80069fa: e7f2 b.n 80069e2 <__libc_init_array+0x1e>
80069fc: 08007658 .word 0x08007658
8006a00: 08007658 .word 0x08007658
8006a04: 08007658 .word 0x08007658
8006a08: 0800765c .word 0x0800765c
08006a0c <__retarget_lock_init_recursive>:
8006a0c: 4770 bx lr
08006a0e <__retarget_lock_acquire_recursive>:
8006a0e: 4770 bx lr
08006a10 <__retarget_lock_release_recursive>:
8006a10: 4770 bx lr
08006a12 <memcpy>:
8006a12: 440a add r2, r1
8006a14: 4291 cmp r1, r2
8006a16: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff
8006a1a: d100 bne.n 8006a1e <memcpy+0xc>
8006a1c: 4770 bx lr
8006a1e: b510 push {r4, lr}
8006a20: f811 4b01 ldrb.w r4, [r1], #1
8006a24: f803 4f01 strb.w r4, [r3, #1]!
8006a28: 4291 cmp r1, r2
8006a2a: d1f9 bne.n 8006a20 <memcpy+0xe>
8006a2c: bd10 pop {r4, pc}
...
08006a30 <_free_r>:
8006a30: b538 push {r3, r4, r5, lr}
8006a32: 4605 mov r5, r0
8006a34: 2900 cmp r1, #0
8006a36: d041 beq.n 8006abc <_free_r+0x8c>
8006a38: f851 3c04 ldr.w r3, [r1, #-4]
8006a3c: 1f0c subs r4, r1, #4
8006a3e: 2b00 cmp r3, #0
8006a40: bfb8 it lt
8006a42: 18e4 addlt r4, r4, r3
8006a44: f000 f8e0 bl 8006c08 <__malloc_lock>
8006a48: 4a1d ldr r2, [pc, #116] @ (8006ac0 <_free_r+0x90>)
8006a4a: 6813 ldr r3, [r2, #0]
8006a4c: b933 cbnz r3, 8006a5c <_free_r+0x2c>
8006a4e: 6063 str r3, [r4, #4]
8006a50: 6014 str r4, [r2, #0]
8006a52: 4628 mov r0, r5
8006a54: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
8006a58: f000 b8dc b.w 8006c14 <__malloc_unlock>
8006a5c: 42a3 cmp r3, r4
8006a5e: d908 bls.n 8006a72 <_free_r+0x42>
8006a60: 6820 ldr r0, [r4, #0]
8006a62: 1821 adds r1, r4, r0
8006a64: 428b cmp r3, r1
8006a66: bf01 itttt eq
8006a68: 6819 ldreq r1, [r3, #0]
8006a6a: 685b ldreq r3, [r3, #4]
8006a6c: 1809 addeq r1, r1, r0
8006a6e: 6021 streq r1, [r4, #0]
8006a70: e7ed b.n 8006a4e <_free_r+0x1e>
8006a72: 461a mov r2, r3
8006a74: 685b ldr r3, [r3, #4]
8006a76: b10b cbz r3, 8006a7c <_free_r+0x4c>
8006a78: 42a3 cmp r3, r4
8006a7a: d9fa bls.n 8006a72 <_free_r+0x42>
8006a7c: 6811 ldr r1, [r2, #0]
8006a7e: 1850 adds r0, r2, r1
8006a80: 42a0 cmp r0, r4
8006a82: d10b bne.n 8006a9c <_free_r+0x6c>
8006a84: 6820 ldr r0, [r4, #0]
8006a86: 4401 add r1, r0
8006a88: 1850 adds r0, r2, r1
8006a8a: 4283 cmp r3, r0
8006a8c: 6011 str r1, [r2, #0]
8006a8e: d1e0 bne.n 8006a52 <_free_r+0x22>
8006a90: 6818 ldr r0, [r3, #0]
8006a92: 685b ldr r3, [r3, #4]
8006a94: 6053 str r3, [r2, #4]
8006a96: 4408 add r0, r1
8006a98: 6010 str r0, [r2, #0]
8006a9a: e7da b.n 8006a52 <_free_r+0x22>
8006a9c: d902 bls.n 8006aa4 <_free_r+0x74>
8006a9e: 230c movs r3, #12
8006aa0: 602b str r3, [r5, #0]
8006aa2: e7d6 b.n 8006a52 <_free_r+0x22>
8006aa4: 6820 ldr r0, [r4, #0]
8006aa6: 1821 adds r1, r4, r0
8006aa8: 428b cmp r3, r1
8006aaa: bf04 itt eq
8006aac: 6819 ldreq r1, [r3, #0]
8006aae: 685b ldreq r3, [r3, #4]
8006ab0: 6063 str r3, [r4, #4]
8006ab2: bf04 itt eq
8006ab4: 1809 addeq r1, r1, r0
8006ab6: 6021 streq r1, [r4, #0]
8006ab8: 6054 str r4, [r2, #4]
8006aba: e7ca b.n 8006a52 <_free_r+0x22>
8006abc: bd38 pop {r3, r4, r5, pc}
8006abe: bf00 nop
8006ac0: 200051fc .word 0x200051fc
08006ac4 <sbrk_aligned>:
8006ac4: b570 push {r4, r5, r6, lr}
8006ac6: 4e0f ldr r6, [pc, #60] @ (8006b04 <sbrk_aligned+0x40>)
8006ac8: 460c mov r4, r1
8006aca: 6831 ldr r1, [r6, #0]
8006acc: 4605 mov r5, r0
8006ace: b911 cbnz r1, 8006ad6 <sbrk_aligned+0x12>
8006ad0: f000 fcb4 bl 800743c <_sbrk_r>
8006ad4: 6030 str r0, [r6, #0]
8006ad6: 4621 mov r1, r4
8006ad8: 4628 mov r0, r5
8006ada: f000 fcaf bl 800743c <_sbrk_r>
8006ade: 1c43 adds r3, r0, #1
8006ae0: d103 bne.n 8006aea <sbrk_aligned+0x26>
8006ae2: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff
8006ae6: 4620 mov r0, r4
8006ae8: bd70 pop {r4, r5, r6, pc}
8006aea: 1cc4 adds r4, r0, #3
8006aec: f024 0403 bic.w r4, r4, #3
8006af0: 42a0 cmp r0, r4
8006af2: d0f8 beq.n 8006ae6 <sbrk_aligned+0x22>
8006af4: 1a21 subs r1, r4, r0
8006af6: 4628 mov r0, r5
8006af8: f000 fca0 bl 800743c <_sbrk_r>
8006afc: 3001 adds r0, #1
8006afe: d1f2 bne.n 8006ae6 <sbrk_aligned+0x22>
8006b00: e7ef b.n 8006ae2 <sbrk_aligned+0x1e>
8006b02: bf00 nop
8006b04: 200051f8 .word 0x200051f8
08006b08 <_malloc_r>:
8006b08: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
8006b0c: 1ccd adds r5, r1, #3
8006b0e: f025 0503 bic.w r5, r5, #3
8006b12: 3508 adds r5, #8
8006b14: 2d0c cmp r5, #12
8006b16: bf38 it cc
8006b18: 250c movcc r5, #12
8006b1a: 2d00 cmp r5, #0
8006b1c: 4606 mov r6, r0
8006b1e: db01 blt.n 8006b24 <_malloc_r+0x1c>
8006b20: 42a9 cmp r1, r5
8006b22: d904 bls.n 8006b2e <_malloc_r+0x26>
8006b24: 230c movs r3, #12
8006b26: 6033 str r3, [r6, #0]
8006b28: 2000 movs r0, #0
8006b2a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
8006b2e: f8df 80d4 ldr.w r8, [pc, #212] @ 8006c04 <_malloc_r+0xfc>
8006b32: f000 f869 bl 8006c08 <__malloc_lock>
8006b36: f8d8 3000 ldr.w r3, [r8]
8006b3a: 461c mov r4, r3
8006b3c: bb44 cbnz r4, 8006b90 <_malloc_r+0x88>
8006b3e: 4629 mov r1, r5
8006b40: 4630 mov r0, r6
8006b42: f7ff ffbf bl 8006ac4 <sbrk_aligned>
8006b46: 1c43 adds r3, r0, #1
8006b48: 4604 mov r4, r0
8006b4a: d158 bne.n 8006bfe <_malloc_r+0xf6>
8006b4c: f8d8 4000 ldr.w r4, [r8]
8006b50: 4627 mov r7, r4
8006b52: 2f00 cmp r7, #0
8006b54: d143 bne.n 8006bde <_malloc_r+0xd6>
8006b56: 2c00 cmp r4, #0
8006b58: d04b beq.n 8006bf2 <_malloc_r+0xea>
8006b5a: 6823 ldr r3, [r4, #0]
8006b5c: 4639 mov r1, r7
8006b5e: 4630 mov r0, r6
8006b60: eb04 0903 add.w r9, r4, r3
8006b64: f000 fc6a bl 800743c <_sbrk_r>
8006b68: 4581 cmp r9, r0
8006b6a: d142 bne.n 8006bf2 <_malloc_r+0xea>
8006b6c: 6821 ldr r1, [r4, #0]
8006b6e: 1a6d subs r5, r5, r1
8006b70: 4629 mov r1, r5
8006b72: 4630 mov r0, r6
8006b74: f7ff ffa6 bl 8006ac4 <sbrk_aligned>
8006b78: 3001 adds r0, #1
8006b7a: d03a beq.n 8006bf2 <_malloc_r+0xea>
8006b7c: 6823 ldr r3, [r4, #0]
8006b7e: 442b add r3, r5
8006b80: 6023 str r3, [r4, #0]
8006b82: f8d8 3000 ldr.w r3, [r8]
8006b86: 685a ldr r2, [r3, #4]
8006b88: bb62 cbnz r2, 8006be4 <_malloc_r+0xdc>
8006b8a: f8c8 7000 str.w r7, [r8]
8006b8e: e00f b.n 8006bb0 <_malloc_r+0xa8>
8006b90: 6822 ldr r2, [r4, #0]
8006b92: 1b52 subs r2, r2, r5
8006b94: d420 bmi.n 8006bd8 <_malloc_r+0xd0>
8006b96: 2a0b cmp r2, #11
8006b98: d917 bls.n 8006bca <_malloc_r+0xc2>
8006b9a: 1961 adds r1, r4, r5
8006b9c: 42a3 cmp r3, r4
8006b9e: 6025 str r5, [r4, #0]
8006ba0: bf18 it ne
8006ba2: 6059 strne r1, [r3, #4]
8006ba4: 6863 ldr r3, [r4, #4]
8006ba6: bf08 it eq
8006ba8: f8c8 1000 streq.w r1, [r8]
8006bac: 5162 str r2, [r4, r5]
8006bae: 604b str r3, [r1, #4]
8006bb0: 4630 mov r0, r6
8006bb2: f000 f82f bl 8006c14 <__malloc_unlock>
8006bb6: f104 000b add.w r0, r4, #11
8006bba: 1d23 adds r3, r4, #4
8006bbc: f020 0007 bic.w r0, r0, #7
8006bc0: 1ac2 subs r2, r0, r3
8006bc2: bf1c itt ne
8006bc4: 1a1b subne r3, r3, r0
8006bc6: 50a3 strne r3, [r4, r2]
8006bc8: e7af b.n 8006b2a <_malloc_r+0x22>
8006bca: 6862 ldr r2, [r4, #4]
8006bcc: 42a3 cmp r3, r4
8006bce: bf0c ite eq
8006bd0: f8c8 2000 streq.w r2, [r8]
8006bd4: 605a strne r2, [r3, #4]
8006bd6: e7eb b.n 8006bb0 <_malloc_r+0xa8>
8006bd8: 4623 mov r3, r4
8006bda: 6864 ldr r4, [r4, #4]
8006bdc: e7ae b.n 8006b3c <_malloc_r+0x34>
8006bde: 463c mov r4, r7
8006be0: 687f ldr r7, [r7, #4]
8006be2: e7b6 b.n 8006b52 <_malloc_r+0x4a>
8006be4: 461a mov r2, r3
8006be6: 685b ldr r3, [r3, #4]
8006be8: 42a3 cmp r3, r4
8006bea: d1fb bne.n 8006be4 <_malloc_r+0xdc>
8006bec: 2300 movs r3, #0
8006bee: 6053 str r3, [r2, #4]
8006bf0: e7de b.n 8006bb0 <_malloc_r+0xa8>
8006bf2: 230c movs r3, #12
8006bf4: 6033 str r3, [r6, #0]
8006bf6: 4630 mov r0, r6
8006bf8: f000 f80c bl 8006c14 <__malloc_unlock>
8006bfc: e794 b.n 8006b28 <_malloc_r+0x20>
8006bfe: 6005 str r5, [r0, #0]
8006c00: e7d6 b.n 8006bb0 <_malloc_r+0xa8>
8006c02: bf00 nop
8006c04: 200051fc .word 0x200051fc
08006c08 <__malloc_lock>:
8006c08: 4801 ldr r0, [pc, #4] @ (8006c10 <__malloc_lock+0x8>)
8006c0a: f7ff bf00 b.w 8006a0e <__retarget_lock_acquire_recursive>
8006c0e: bf00 nop
8006c10: 200051f4 .word 0x200051f4
08006c14 <__malloc_unlock>:
8006c14: 4801 ldr r0, [pc, #4] @ (8006c1c <__malloc_unlock+0x8>)
8006c16: f7ff befb b.w 8006a10 <__retarget_lock_release_recursive>
8006c1a: bf00 nop
8006c1c: 200051f4 .word 0x200051f4
08006c20 <__sfputc_r>:
8006c20: 6893 ldr r3, [r2, #8]
8006c22: 3b01 subs r3, #1
8006c24: 2b00 cmp r3, #0
8006c26: b410 push {r4}
8006c28: 6093 str r3, [r2, #8]
8006c2a: da08 bge.n 8006c3e <__sfputc_r+0x1e>
8006c2c: 6994 ldr r4, [r2, #24]
8006c2e: 42a3 cmp r3, r4
8006c30: db01 blt.n 8006c36 <__sfputc_r+0x16>
8006c32: 290a cmp r1, #10
8006c34: d103 bne.n 8006c3e <__sfputc_r+0x1e>
8006c36: f85d 4b04 ldr.w r4, [sp], #4
8006c3a: f000 bb6b b.w 8007314 <__swbuf_r>
8006c3e: 6813 ldr r3, [r2, #0]
8006c40: 1c58 adds r0, r3, #1
8006c42: 6010 str r0, [r2, #0]
8006c44: 7019 strb r1, [r3, #0]
8006c46: 4608 mov r0, r1
8006c48: f85d 4b04 ldr.w r4, [sp], #4
8006c4c: 4770 bx lr
08006c4e <__sfputs_r>:
8006c4e: b5f8 push {r3, r4, r5, r6, r7, lr}
8006c50: 4606 mov r6, r0
8006c52: 460f mov r7, r1
8006c54: 4614 mov r4, r2
8006c56: 18d5 adds r5, r2, r3
8006c58: 42ac cmp r4, r5
8006c5a: d101 bne.n 8006c60 <__sfputs_r+0x12>
8006c5c: 2000 movs r0, #0
8006c5e: e007 b.n 8006c70 <__sfputs_r+0x22>
8006c60: f814 1b01 ldrb.w r1, [r4], #1
8006c64: 463a mov r2, r7
8006c66: 4630 mov r0, r6
8006c68: f7ff ffda bl 8006c20 <__sfputc_r>
8006c6c: 1c43 adds r3, r0, #1
8006c6e: d1f3 bne.n 8006c58 <__sfputs_r+0xa>
8006c70: bdf8 pop {r3, r4, r5, r6, r7, pc}
...
08006c74 <_vfiprintf_r>:
8006c74: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8006c78: 460d mov r5, r1
8006c7a: b09d sub sp, #116 @ 0x74
8006c7c: 4614 mov r4, r2
8006c7e: 4698 mov r8, r3
8006c80: 4606 mov r6, r0
8006c82: b118 cbz r0, 8006c8c <_vfiprintf_r+0x18>
8006c84: 6a03 ldr r3, [r0, #32]
8006c86: b90b cbnz r3, 8006c8c <_vfiprintf_r+0x18>
8006c88: f7ff fdbc bl 8006804 <__sinit>
8006c8c: 6e6b ldr r3, [r5, #100] @ 0x64
8006c8e: 07d9 lsls r1, r3, #31
8006c90: d405 bmi.n 8006c9e <_vfiprintf_r+0x2a>
8006c92: 89ab ldrh r3, [r5, #12]
8006c94: 059a lsls r2, r3, #22
8006c96: d402 bmi.n 8006c9e <_vfiprintf_r+0x2a>
8006c98: 6da8 ldr r0, [r5, #88] @ 0x58
8006c9a: f7ff feb8 bl 8006a0e <__retarget_lock_acquire_recursive>
8006c9e: 89ab ldrh r3, [r5, #12]
8006ca0: 071b lsls r3, r3, #28
8006ca2: d501 bpl.n 8006ca8 <_vfiprintf_r+0x34>
8006ca4: 692b ldr r3, [r5, #16]
8006ca6: b99b cbnz r3, 8006cd0 <_vfiprintf_r+0x5c>
8006ca8: 4629 mov r1, r5
8006caa: 4630 mov r0, r6
8006cac: f000 fb70 bl 8007390 <__swsetup_r>
8006cb0: b170 cbz r0, 8006cd0 <_vfiprintf_r+0x5c>
8006cb2: 6e6b ldr r3, [r5, #100] @ 0x64
8006cb4: 07dc lsls r4, r3, #31
8006cb6: d504 bpl.n 8006cc2 <_vfiprintf_r+0x4e>
8006cb8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8006cbc: b01d add sp, #116 @ 0x74
8006cbe: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8006cc2: 89ab ldrh r3, [r5, #12]
8006cc4: 0598 lsls r0, r3, #22
8006cc6: d4f7 bmi.n 8006cb8 <_vfiprintf_r+0x44>
8006cc8: 6da8 ldr r0, [r5, #88] @ 0x58
8006cca: f7ff fea1 bl 8006a10 <__retarget_lock_release_recursive>
8006cce: e7f3 b.n 8006cb8 <_vfiprintf_r+0x44>
8006cd0: 2300 movs r3, #0
8006cd2: 9309 str r3, [sp, #36] @ 0x24
8006cd4: 2320 movs r3, #32
8006cd6: f88d 3029 strb.w r3, [sp, #41] @ 0x29
8006cda: f8cd 800c str.w r8, [sp, #12]
8006cde: 2330 movs r3, #48 @ 0x30
8006ce0: f8df 81ac ldr.w r8, [pc, #428] @ 8006e90 <_vfiprintf_r+0x21c>
8006ce4: f88d 302a strb.w r3, [sp, #42] @ 0x2a
8006ce8: f04f 0901 mov.w r9, #1
8006cec: 4623 mov r3, r4
8006cee: 469a mov sl, r3
8006cf0: f813 2b01 ldrb.w r2, [r3], #1
8006cf4: b10a cbz r2, 8006cfa <_vfiprintf_r+0x86>
8006cf6: 2a25 cmp r2, #37 @ 0x25
8006cf8: d1f9 bne.n 8006cee <_vfiprintf_r+0x7a>
8006cfa: ebba 0b04 subs.w fp, sl, r4
8006cfe: d00b beq.n 8006d18 <_vfiprintf_r+0xa4>
8006d00: 465b mov r3, fp
8006d02: 4622 mov r2, r4
8006d04: 4629 mov r1, r5
8006d06: 4630 mov r0, r6
8006d08: f7ff ffa1 bl 8006c4e <__sfputs_r>
8006d0c: 3001 adds r0, #1
8006d0e: f000 80a7 beq.w 8006e60 <_vfiprintf_r+0x1ec>
8006d12: 9a09 ldr r2, [sp, #36] @ 0x24
8006d14: 445a add r2, fp
8006d16: 9209 str r2, [sp, #36] @ 0x24
8006d18: f89a 3000 ldrb.w r3, [sl]
8006d1c: 2b00 cmp r3, #0
8006d1e: f000 809f beq.w 8006e60 <_vfiprintf_r+0x1ec>
8006d22: 2300 movs r3, #0
8006d24: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8006d28: e9cd 2305 strd r2, r3, [sp, #20]
8006d2c: f10a 0a01 add.w sl, sl, #1
8006d30: 9304 str r3, [sp, #16]
8006d32: 9307 str r3, [sp, #28]
8006d34: f88d 3053 strb.w r3, [sp, #83] @ 0x53
8006d38: 931a str r3, [sp, #104] @ 0x68
8006d3a: 4654 mov r4, sl
8006d3c: 2205 movs r2, #5
8006d3e: f814 1b01 ldrb.w r1, [r4], #1
8006d42: 4853 ldr r0, [pc, #332] @ (8006e90 <_vfiprintf_r+0x21c>)
8006d44: f7f9 fa6c bl 8000220 <memchr>
8006d48: 9a04 ldr r2, [sp, #16]
8006d4a: b9d8 cbnz r0, 8006d84 <_vfiprintf_r+0x110>
8006d4c: 06d1 lsls r1, r2, #27
8006d4e: bf44 itt mi
8006d50: 2320 movmi r3, #32
8006d52: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
8006d56: 0713 lsls r3, r2, #28
8006d58: bf44 itt mi
8006d5a: 232b movmi r3, #43 @ 0x2b
8006d5c: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
8006d60: f89a 3000 ldrb.w r3, [sl]
8006d64: 2b2a cmp r3, #42 @ 0x2a
8006d66: d015 beq.n 8006d94 <_vfiprintf_r+0x120>
8006d68: 9a07 ldr r2, [sp, #28]
8006d6a: 4654 mov r4, sl
8006d6c: 2000 movs r0, #0
8006d6e: f04f 0c0a mov.w ip, #10
8006d72: 4621 mov r1, r4
8006d74: f811 3b01 ldrb.w r3, [r1], #1
8006d78: 3b30 subs r3, #48 @ 0x30
8006d7a: 2b09 cmp r3, #9
8006d7c: d94b bls.n 8006e16 <_vfiprintf_r+0x1a2>
8006d7e: b1b0 cbz r0, 8006dae <_vfiprintf_r+0x13a>
8006d80: 9207 str r2, [sp, #28]
8006d82: e014 b.n 8006dae <_vfiprintf_r+0x13a>
8006d84: eba0 0308 sub.w r3, r0, r8
8006d88: fa09 f303 lsl.w r3, r9, r3
8006d8c: 4313 orrs r3, r2
8006d8e: 9304 str r3, [sp, #16]
8006d90: 46a2 mov sl, r4
8006d92: e7d2 b.n 8006d3a <_vfiprintf_r+0xc6>
8006d94: 9b03 ldr r3, [sp, #12]
8006d96: 1d19 adds r1, r3, #4
8006d98: 681b ldr r3, [r3, #0]
8006d9a: 9103 str r1, [sp, #12]
8006d9c: 2b00 cmp r3, #0
8006d9e: bfbb ittet lt
8006da0: 425b neglt r3, r3
8006da2: f042 0202 orrlt.w r2, r2, #2
8006da6: 9307 strge r3, [sp, #28]
8006da8: 9307 strlt r3, [sp, #28]
8006daa: bfb8 it lt
8006dac: 9204 strlt r2, [sp, #16]
8006dae: 7823 ldrb r3, [r4, #0]
8006db0: 2b2e cmp r3, #46 @ 0x2e
8006db2: d10a bne.n 8006dca <_vfiprintf_r+0x156>
8006db4: 7863 ldrb r3, [r4, #1]
8006db6: 2b2a cmp r3, #42 @ 0x2a
8006db8: d132 bne.n 8006e20 <_vfiprintf_r+0x1ac>
8006dba: 9b03 ldr r3, [sp, #12]
8006dbc: 1d1a adds r2, r3, #4
8006dbe: 681b ldr r3, [r3, #0]
8006dc0: 9203 str r2, [sp, #12]
8006dc2: ea43 73e3 orr.w r3, r3, r3, asr #31
8006dc6: 3402 adds r4, #2
8006dc8: 9305 str r3, [sp, #20]
8006dca: f8df a0d4 ldr.w sl, [pc, #212] @ 8006ea0 <_vfiprintf_r+0x22c>
8006dce: 7821 ldrb r1, [r4, #0]
8006dd0: 2203 movs r2, #3
8006dd2: 4650 mov r0, sl
8006dd4: f7f9 fa24 bl 8000220 <memchr>
8006dd8: b138 cbz r0, 8006dea <_vfiprintf_r+0x176>
8006dda: 9b04 ldr r3, [sp, #16]
8006ddc: eba0 000a sub.w r0, r0, sl
8006de0: 2240 movs r2, #64 @ 0x40
8006de2: 4082 lsls r2, r0
8006de4: 4313 orrs r3, r2
8006de6: 3401 adds r4, #1
8006de8: 9304 str r3, [sp, #16]
8006dea: f814 1b01 ldrb.w r1, [r4], #1
8006dee: 4829 ldr r0, [pc, #164] @ (8006e94 <_vfiprintf_r+0x220>)
8006df0: f88d 1028 strb.w r1, [sp, #40] @ 0x28
8006df4: 2206 movs r2, #6
8006df6: f7f9 fa13 bl 8000220 <memchr>
8006dfa: 2800 cmp r0, #0
8006dfc: d03f beq.n 8006e7e <_vfiprintf_r+0x20a>
8006dfe: 4b26 ldr r3, [pc, #152] @ (8006e98 <_vfiprintf_r+0x224>)
8006e00: bb1b cbnz r3, 8006e4a <_vfiprintf_r+0x1d6>
8006e02: 9b03 ldr r3, [sp, #12]
8006e04: 3307 adds r3, #7
8006e06: f023 0307 bic.w r3, r3, #7
8006e0a: 3308 adds r3, #8
8006e0c: 9303 str r3, [sp, #12]
8006e0e: 9b09 ldr r3, [sp, #36] @ 0x24
8006e10: 443b add r3, r7
8006e12: 9309 str r3, [sp, #36] @ 0x24
8006e14: e76a b.n 8006cec <_vfiprintf_r+0x78>
8006e16: fb0c 3202 mla r2, ip, r2, r3
8006e1a: 460c mov r4, r1
8006e1c: 2001 movs r0, #1
8006e1e: e7a8 b.n 8006d72 <_vfiprintf_r+0xfe>
8006e20: 2300 movs r3, #0
8006e22: 3401 adds r4, #1
8006e24: 9305 str r3, [sp, #20]
8006e26: 4619 mov r1, r3
8006e28: f04f 0c0a mov.w ip, #10
8006e2c: 4620 mov r0, r4
8006e2e: f810 2b01 ldrb.w r2, [r0], #1
8006e32: 3a30 subs r2, #48 @ 0x30
8006e34: 2a09 cmp r2, #9
8006e36: d903 bls.n 8006e40 <_vfiprintf_r+0x1cc>
8006e38: 2b00 cmp r3, #0
8006e3a: d0c6 beq.n 8006dca <_vfiprintf_r+0x156>
8006e3c: 9105 str r1, [sp, #20]
8006e3e: e7c4 b.n 8006dca <_vfiprintf_r+0x156>
8006e40: fb0c 2101 mla r1, ip, r1, r2
8006e44: 4604 mov r4, r0
8006e46: 2301 movs r3, #1
8006e48: e7f0 b.n 8006e2c <_vfiprintf_r+0x1b8>
8006e4a: ab03 add r3, sp, #12
8006e4c: 9300 str r3, [sp, #0]
8006e4e: 462a mov r2, r5
8006e50: 4b12 ldr r3, [pc, #72] @ (8006e9c <_vfiprintf_r+0x228>)
8006e52: a904 add r1, sp, #16
8006e54: 4630 mov r0, r6
8006e56: f3af 8000 nop.w
8006e5a: 4607 mov r7, r0
8006e5c: 1c78 adds r0, r7, #1
8006e5e: d1d6 bne.n 8006e0e <_vfiprintf_r+0x19a>
8006e60: 6e6b ldr r3, [r5, #100] @ 0x64
8006e62: 07d9 lsls r1, r3, #31
8006e64: d405 bmi.n 8006e72 <_vfiprintf_r+0x1fe>
8006e66: 89ab ldrh r3, [r5, #12]
8006e68: 059a lsls r2, r3, #22
8006e6a: d402 bmi.n 8006e72 <_vfiprintf_r+0x1fe>
8006e6c: 6da8 ldr r0, [r5, #88] @ 0x58
8006e6e: f7ff fdcf bl 8006a10 <__retarget_lock_release_recursive>
8006e72: 89ab ldrh r3, [r5, #12]
8006e74: 065b lsls r3, r3, #25
8006e76: f53f af1f bmi.w 8006cb8 <_vfiprintf_r+0x44>
8006e7a: 9809 ldr r0, [sp, #36] @ 0x24
8006e7c: e71e b.n 8006cbc <_vfiprintf_r+0x48>
8006e7e: ab03 add r3, sp, #12
8006e80: 9300 str r3, [sp, #0]
8006e82: 462a mov r2, r5
8006e84: 4b05 ldr r3, [pc, #20] @ (8006e9c <_vfiprintf_r+0x228>)
8006e86: a904 add r1, sp, #16
8006e88: 4630 mov r0, r6
8006e8a: f000 f879 bl 8006f80 <_printf_i>
8006e8e: e7e4 b.n 8006e5a <_vfiprintf_r+0x1e6>
8006e90: 0800761c .word 0x0800761c
8006e94: 08007626 .word 0x08007626
8006e98: 00000000 .word 0x00000000
8006e9c: 08006c4f .word 0x08006c4f
8006ea0: 08007622 .word 0x08007622
08006ea4 <_printf_common>:
8006ea4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8006ea8: 4616 mov r6, r2
8006eaa: 4698 mov r8, r3
8006eac: 688a ldr r2, [r1, #8]
8006eae: 690b ldr r3, [r1, #16]
8006eb0: f8dd 9020 ldr.w r9, [sp, #32]
8006eb4: 4293 cmp r3, r2
8006eb6: bfb8 it lt
8006eb8: 4613 movlt r3, r2
8006eba: 6033 str r3, [r6, #0]
8006ebc: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
8006ec0: 4607 mov r7, r0
8006ec2: 460c mov r4, r1
8006ec4: b10a cbz r2, 8006eca <_printf_common+0x26>
8006ec6: 3301 adds r3, #1
8006ec8: 6033 str r3, [r6, #0]
8006eca: 6823 ldr r3, [r4, #0]
8006ecc: 0699 lsls r1, r3, #26
8006ece: bf42 ittt mi
8006ed0: 6833 ldrmi r3, [r6, #0]
8006ed2: 3302 addmi r3, #2
8006ed4: 6033 strmi r3, [r6, #0]
8006ed6: 6825 ldr r5, [r4, #0]
8006ed8: f015 0506 ands.w r5, r5, #6
8006edc: d106 bne.n 8006eec <_printf_common+0x48>
8006ede: f104 0a19 add.w sl, r4, #25
8006ee2: 68e3 ldr r3, [r4, #12]
8006ee4: 6832 ldr r2, [r6, #0]
8006ee6: 1a9b subs r3, r3, r2
8006ee8: 42ab cmp r3, r5
8006eea: dc26 bgt.n 8006f3a <_printf_common+0x96>
8006eec: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
8006ef0: 6822 ldr r2, [r4, #0]
8006ef2: 3b00 subs r3, #0
8006ef4: bf18 it ne
8006ef6: 2301 movne r3, #1
8006ef8: 0692 lsls r2, r2, #26
8006efa: d42b bmi.n 8006f54 <_printf_common+0xb0>
8006efc: f104 0243 add.w r2, r4, #67 @ 0x43
8006f00: 4641 mov r1, r8
8006f02: 4638 mov r0, r7
8006f04: 47c8 blx r9
8006f06: 3001 adds r0, #1
8006f08: d01e beq.n 8006f48 <_printf_common+0xa4>
8006f0a: 6823 ldr r3, [r4, #0]
8006f0c: 6922 ldr r2, [r4, #16]
8006f0e: f003 0306 and.w r3, r3, #6
8006f12: 2b04 cmp r3, #4
8006f14: bf02 ittt eq
8006f16: 68e5 ldreq r5, [r4, #12]
8006f18: 6833 ldreq r3, [r6, #0]
8006f1a: 1aed subeq r5, r5, r3
8006f1c: 68a3 ldr r3, [r4, #8]
8006f1e: bf0c ite eq
8006f20: ea25 75e5 biceq.w r5, r5, r5, asr #31
8006f24: 2500 movne r5, #0
8006f26: 4293 cmp r3, r2
8006f28: bfc4 itt gt
8006f2a: 1a9b subgt r3, r3, r2
8006f2c: 18ed addgt r5, r5, r3
8006f2e: 2600 movs r6, #0
8006f30: 341a adds r4, #26
8006f32: 42b5 cmp r5, r6
8006f34: d11a bne.n 8006f6c <_printf_common+0xc8>
8006f36: 2000 movs r0, #0
8006f38: e008 b.n 8006f4c <_printf_common+0xa8>
8006f3a: 2301 movs r3, #1
8006f3c: 4652 mov r2, sl
8006f3e: 4641 mov r1, r8
8006f40: 4638 mov r0, r7
8006f42: 47c8 blx r9
8006f44: 3001 adds r0, #1
8006f46: d103 bne.n 8006f50 <_printf_common+0xac>
8006f48: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8006f4c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8006f50: 3501 adds r5, #1
8006f52: e7c6 b.n 8006ee2 <_printf_common+0x3e>
8006f54: 18e1 adds r1, r4, r3
8006f56: 1c5a adds r2, r3, #1
8006f58: 2030 movs r0, #48 @ 0x30
8006f5a: f881 0043 strb.w r0, [r1, #67] @ 0x43
8006f5e: 4422 add r2, r4
8006f60: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
8006f64: f882 1043 strb.w r1, [r2, #67] @ 0x43
8006f68: 3302 adds r3, #2
8006f6a: e7c7 b.n 8006efc <_printf_common+0x58>
8006f6c: 2301 movs r3, #1
8006f6e: 4622 mov r2, r4
8006f70: 4641 mov r1, r8
8006f72: 4638 mov r0, r7
8006f74: 47c8 blx r9
8006f76: 3001 adds r0, #1
8006f78: d0e6 beq.n 8006f48 <_printf_common+0xa4>
8006f7a: 3601 adds r6, #1
8006f7c: e7d9 b.n 8006f32 <_printf_common+0x8e>
...
08006f80 <_printf_i>:
8006f80: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
8006f84: 7e0f ldrb r7, [r1, #24]
8006f86: 9e0c ldr r6, [sp, #48] @ 0x30
8006f88: 2f78 cmp r7, #120 @ 0x78
8006f8a: 4691 mov r9, r2
8006f8c: 4680 mov r8, r0
8006f8e: 460c mov r4, r1
8006f90: 469a mov sl, r3
8006f92: f101 0243 add.w r2, r1, #67 @ 0x43
8006f96: d807 bhi.n 8006fa8 <_printf_i+0x28>
8006f98: 2f62 cmp r7, #98 @ 0x62
8006f9a: d80a bhi.n 8006fb2 <_printf_i+0x32>
8006f9c: 2f00 cmp r7, #0
8006f9e: f000 80d1 beq.w 8007144 <_printf_i+0x1c4>
8006fa2: 2f58 cmp r7, #88 @ 0x58
8006fa4: f000 80b8 beq.w 8007118 <_printf_i+0x198>
8006fa8: f104 0642 add.w r6, r4, #66 @ 0x42
8006fac: f884 7042 strb.w r7, [r4, #66] @ 0x42
8006fb0: e03a b.n 8007028 <_printf_i+0xa8>
8006fb2: f1a7 0363 sub.w r3, r7, #99 @ 0x63
8006fb6: 2b15 cmp r3, #21
8006fb8: d8f6 bhi.n 8006fa8 <_printf_i+0x28>
8006fba: a101 add r1, pc, #4 @ (adr r1, 8006fc0 <_printf_i+0x40>)
8006fbc: f851 f023 ldr.w pc, [r1, r3, lsl #2]
8006fc0: 08007019 .word 0x08007019
8006fc4: 0800702d .word 0x0800702d
8006fc8: 08006fa9 .word 0x08006fa9
8006fcc: 08006fa9 .word 0x08006fa9
8006fd0: 08006fa9 .word 0x08006fa9
8006fd4: 08006fa9 .word 0x08006fa9
8006fd8: 0800702d .word 0x0800702d
8006fdc: 08006fa9 .word 0x08006fa9
8006fe0: 08006fa9 .word 0x08006fa9
8006fe4: 08006fa9 .word 0x08006fa9
8006fe8: 08006fa9 .word 0x08006fa9
8006fec: 0800712b .word 0x0800712b
8006ff0: 08007057 .word 0x08007057
8006ff4: 080070e5 .word 0x080070e5
8006ff8: 08006fa9 .word 0x08006fa9
8006ffc: 08006fa9 .word 0x08006fa9
8007000: 0800714d .word 0x0800714d
8007004: 08006fa9 .word 0x08006fa9
8007008: 08007057 .word 0x08007057
800700c: 08006fa9 .word 0x08006fa9
8007010: 08006fa9 .word 0x08006fa9
8007014: 080070ed .word 0x080070ed
8007018: 6833 ldr r3, [r6, #0]
800701a: 1d1a adds r2, r3, #4
800701c: 681b ldr r3, [r3, #0]
800701e: 6032 str r2, [r6, #0]
8007020: f104 0642 add.w r6, r4, #66 @ 0x42
8007024: f884 3042 strb.w r3, [r4, #66] @ 0x42
8007028: 2301 movs r3, #1
800702a: e09c b.n 8007166 <_printf_i+0x1e6>
800702c: 6833 ldr r3, [r6, #0]
800702e: 6820 ldr r0, [r4, #0]
8007030: 1d19 adds r1, r3, #4
8007032: 6031 str r1, [r6, #0]
8007034: 0606 lsls r6, r0, #24
8007036: d501 bpl.n 800703c <_printf_i+0xbc>
8007038: 681d ldr r5, [r3, #0]
800703a: e003 b.n 8007044 <_printf_i+0xc4>
800703c: 0645 lsls r5, r0, #25
800703e: d5fb bpl.n 8007038 <_printf_i+0xb8>
8007040: f9b3 5000 ldrsh.w r5, [r3]
8007044: 2d00 cmp r5, #0
8007046: da03 bge.n 8007050 <_printf_i+0xd0>
8007048: 232d movs r3, #45 @ 0x2d
800704a: 426d negs r5, r5
800704c: f884 3043 strb.w r3, [r4, #67] @ 0x43
8007050: 4858 ldr r0, [pc, #352] @ (80071b4 <_printf_i+0x234>)
8007052: 230a movs r3, #10
8007054: e011 b.n 800707a <_printf_i+0xfa>
8007056: 6821 ldr r1, [r4, #0]
8007058: 6833 ldr r3, [r6, #0]
800705a: 0608 lsls r0, r1, #24
800705c: f853 5b04 ldr.w r5, [r3], #4
8007060: d402 bmi.n 8007068 <_printf_i+0xe8>
8007062: 0649 lsls r1, r1, #25
8007064: bf48 it mi
8007066: b2ad uxthmi r5, r5
8007068: 2f6f cmp r7, #111 @ 0x6f
800706a: 4852 ldr r0, [pc, #328] @ (80071b4 <_printf_i+0x234>)
800706c: 6033 str r3, [r6, #0]
800706e: bf14 ite ne
8007070: 230a movne r3, #10
8007072: 2308 moveq r3, #8
8007074: 2100 movs r1, #0
8007076: f884 1043 strb.w r1, [r4, #67] @ 0x43
800707a: 6866 ldr r6, [r4, #4]
800707c: 60a6 str r6, [r4, #8]
800707e: 2e00 cmp r6, #0
8007080: db05 blt.n 800708e <_printf_i+0x10e>
8007082: 6821 ldr r1, [r4, #0]
8007084: 432e orrs r6, r5
8007086: f021 0104 bic.w r1, r1, #4
800708a: 6021 str r1, [r4, #0]
800708c: d04b beq.n 8007126 <_printf_i+0x1a6>
800708e: 4616 mov r6, r2
8007090: fbb5 f1f3 udiv r1, r5, r3
8007094: fb03 5711 mls r7, r3, r1, r5
8007098: 5dc7 ldrb r7, [r0, r7]
800709a: f806 7d01 strb.w r7, [r6, #-1]!
800709e: 462f mov r7, r5
80070a0: 42bb cmp r3, r7
80070a2: 460d mov r5, r1
80070a4: d9f4 bls.n 8007090 <_printf_i+0x110>
80070a6: 2b08 cmp r3, #8
80070a8: d10b bne.n 80070c2 <_printf_i+0x142>
80070aa: 6823 ldr r3, [r4, #0]
80070ac: 07df lsls r7, r3, #31
80070ae: d508 bpl.n 80070c2 <_printf_i+0x142>
80070b0: 6923 ldr r3, [r4, #16]
80070b2: 6861 ldr r1, [r4, #4]
80070b4: 4299 cmp r1, r3
80070b6: bfde ittt le
80070b8: 2330 movle r3, #48 @ 0x30
80070ba: f806 3c01 strble.w r3, [r6, #-1]
80070be: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff
80070c2: 1b92 subs r2, r2, r6
80070c4: 6122 str r2, [r4, #16]
80070c6: f8cd a000 str.w sl, [sp]
80070ca: 464b mov r3, r9
80070cc: aa03 add r2, sp, #12
80070ce: 4621 mov r1, r4
80070d0: 4640 mov r0, r8
80070d2: f7ff fee7 bl 8006ea4 <_printf_common>
80070d6: 3001 adds r0, #1
80070d8: d14a bne.n 8007170 <_printf_i+0x1f0>
80070da: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
80070de: b004 add sp, #16
80070e0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80070e4: 6823 ldr r3, [r4, #0]
80070e6: f043 0320 orr.w r3, r3, #32
80070ea: 6023 str r3, [r4, #0]
80070ec: 4832 ldr r0, [pc, #200] @ (80071b8 <_printf_i+0x238>)
80070ee: 2778 movs r7, #120 @ 0x78
80070f0: f884 7045 strb.w r7, [r4, #69] @ 0x45
80070f4: 6823 ldr r3, [r4, #0]
80070f6: 6831 ldr r1, [r6, #0]
80070f8: 061f lsls r7, r3, #24
80070fa: f851 5b04 ldr.w r5, [r1], #4
80070fe: d402 bmi.n 8007106 <_printf_i+0x186>
8007100: 065f lsls r7, r3, #25
8007102: bf48 it mi
8007104: b2ad uxthmi r5, r5
8007106: 6031 str r1, [r6, #0]
8007108: 07d9 lsls r1, r3, #31
800710a: bf44 itt mi
800710c: f043 0320 orrmi.w r3, r3, #32
8007110: 6023 strmi r3, [r4, #0]
8007112: b11d cbz r5, 800711c <_printf_i+0x19c>
8007114: 2310 movs r3, #16
8007116: e7ad b.n 8007074 <_printf_i+0xf4>
8007118: 4826 ldr r0, [pc, #152] @ (80071b4 <_printf_i+0x234>)
800711a: e7e9 b.n 80070f0 <_printf_i+0x170>
800711c: 6823 ldr r3, [r4, #0]
800711e: f023 0320 bic.w r3, r3, #32
8007122: 6023 str r3, [r4, #0]
8007124: e7f6 b.n 8007114 <_printf_i+0x194>
8007126: 4616 mov r6, r2
8007128: e7bd b.n 80070a6 <_printf_i+0x126>
800712a: 6833 ldr r3, [r6, #0]
800712c: 6825 ldr r5, [r4, #0]
800712e: 6961 ldr r1, [r4, #20]
8007130: 1d18 adds r0, r3, #4
8007132: 6030 str r0, [r6, #0]
8007134: 062e lsls r6, r5, #24
8007136: 681b ldr r3, [r3, #0]
8007138: d501 bpl.n 800713e <_printf_i+0x1be>
800713a: 6019 str r1, [r3, #0]
800713c: e002 b.n 8007144 <_printf_i+0x1c4>
800713e: 0668 lsls r0, r5, #25
8007140: d5fb bpl.n 800713a <_printf_i+0x1ba>
8007142: 8019 strh r1, [r3, #0]
8007144: 2300 movs r3, #0
8007146: 6123 str r3, [r4, #16]
8007148: 4616 mov r6, r2
800714a: e7bc b.n 80070c6 <_printf_i+0x146>
800714c: 6833 ldr r3, [r6, #0]
800714e: 1d1a adds r2, r3, #4
8007150: 6032 str r2, [r6, #0]
8007152: 681e ldr r6, [r3, #0]
8007154: 6862 ldr r2, [r4, #4]
8007156: 2100 movs r1, #0
8007158: 4630 mov r0, r6
800715a: f7f9 f861 bl 8000220 <memchr>
800715e: b108 cbz r0, 8007164 <_printf_i+0x1e4>
8007160: 1b80 subs r0, r0, r6
8007162: 6060 str r0, [r4, #4]
8007164: 6863 ldr r3, [r4, #4]
8007166: 6123 str r3, [r4, #16]
8007168: 2300 movs r3, #0
800716a: f884 3043 strb.w r3, [r4, #67] @ 0x43
800716e: e7aa b.n 80070c6 <_printf_i+0x146>
8007170: 6923 ldr r3, [r4, #16]
8007172: 4632 mov r2, r6
8007174: 4649 mov r1, r9
8007176: 4640 mov r0, r8
8007178: 47d0 blx sl
800717a: 3001 adds r0, #1
800717c: d0ad beq.n 80070da <_printf_i+0x15a>
800717e: 6823 ldr r3, [r4, #0]
8007180: 079b lsls r3, r3, #30
8007182: d413 bmi.n 80071ac <_printf_i+0x22c>
8007184: 68e0 ldr r0, [r4, #12]
8007186: 9b03 ldr r3, [sp, #12]
8007188: 4298 cmp r0, r3
800718a: bfb8 it lt
800718c: 4618 movlt r0, r3
800718e: e7a6 b.n 80070de <_printf_i+0x15e>
8007190: 2301 movs r3, #1
8007192: 4632 mov r2, r6
8007194: 4649 mov r1, r9
8007196: 4640 mov r0, r8
8007198: 47d0 blx sl
800719a: 3001 adds r0, #1
800719c: d09d beq.n 80070da <_printf_i+0x15a>
800719e: 3501 adds r5, #1
80071a0: 68e3 ldr r3, [r4, #12]
80071a2: 9903 ldr r1, [sp, #12]
80071a4: 1a5b subs r3, r3, r1
80071a6: 42ab cmp r3, r5
80071a8: dcf2 bgt.n 8007190 <_printf_i+0x210>
80071aa: e7eb b.n 8007184 <_printf_i+0x204>
80071ac: 2500 movs r5, #0
80071ae: f104 0619 add.w r6, r4, #25
80071b2: e7f5 b.n 80071a0 <_printf_i+0x220>
80071b4: 0800762d .word 0x0800762d
80071b8: 0800763e .word 0x0800763e
080071bc <__sflush_r>:
80071bc: f9b1 200c ldrsh.w r2, [r1, #12]
80071c0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
80071c4: 0716 lsls r6, r2, #28
80071c6: 4605 mov r5, r0
80071c8: 460c mov r4, r1
80071ca: d454 bmi.n 8007276 <__sflush_r+0xba>
80071cc: 684b ldr r3, [r1, #4]
80071ce: 2b00 cmp r3, #0
80071d0: dc02 bgt.n 80071d8 <__sflush_r+0x1c>
80071d2: 6c0b ldr r3, [r1, #64] @ 0x40
80071d4: 2b00 cmp r3, #0
80071d6: dd48 ble.n 800726a <__sflush_r+0xae>
80071d8: 6ae6 ldr r6, [r4, #44] @ 0x2c
80071da: 2e00 cmp r6, #0
80071dc: d045 beq.n 800726a <__sflush_r+0xae>
80071de: 2300 movs r3, #0
80071e0: f412 5280 ands.w r2, r2, #4096 @ 0x1000
80071e4: 682f ldr r7, [r5, #0]
80071e6: 6a21 ldr r1, [r4, #32]
80071e8: 602b str r3, [r5, #0]
80071ea: d030 beq.n 800724e <__sflush_r+0x92>
80071ec: 6d62 ldr r2, [r4, #84] @ 0x54
80071ee: 89a3 ldrh r3, [r4, #12]
80071f0: 0759 lsls r1, r3, #29
80071f2: d505 bpl.n 8007200 <__sflush_r+0x44>
80071f4: 6863 ldr r3, [r4, #4]
80071f6: 1ad2 subs r2, r2, r3
80071f8: 6b63 ldr r3, [r4, #52] @ 0x34
80071fa: b10b cbz r3, 8007200 <__sflush_r+0x44>
80071fc: 6c23 ldr r3, [r4, #64] @ 0x40
80071fe: 1ad2 subs r2, r2, r3
8007200: 2300 movs r3, #0
8007202: 6ae6 ldr r6, [r4, #44] @ 0x2c
8007204: 6a21 ldr r1, [r4, #32]
8007206: 4628 mov r0, r5
8007208: 47b0 blx r6
800720a: 1c43 adds r3, r0, #1
800720c: 89a3 ldrh r3, [r4, #12]
800720e: d106 bne.n 800721e <__sflush_r+0x62>
8007210: 6829 ldr r1, [r5, #0]
8007212: 291d cmp r1, #29
8007214: d82b bhi.n 800726e <__sflush_r+0xb2>
8007216: 4a2a ldr r2, [pc, #168] @ (80072c0 <__sflush_r+0x104>)
8007218: 40ca lsrs r2, r1
800721a: 07d6 lsls r6, r2, #31
800721c: d527 bpl.n 800726e <__sflush_r+0xb2>
800721e: 2200 movs r2, #0
8007220: 6062 str r2, [r4, #4]
8007222: 04d9 lsls r1, r3, #19
8007224: 6922 ldr r2, [r4, #16]
8007226: 6022 str r2, [r4, #0]
8007228: d504 bpl.n 8007234 <__sflush_r+0x78>
800722a: 1c42 adds r2, r0, #1
800722c: d101 bne.n 8007232 <__sflush_r+0x76>
800722e: 682b ldr r3, [r5, #0]
8007230: b903 cbnz r3, 8007234 <__sflush_r+0x78>
8007232: 6560 str r0, [r4, #84] @ 0x54
8007234: 6b61 ldr r1, [r4, #52] @ 0x34
8007236: 602f str r7, [r5, #0]
8007238: b1b9 cbz r1, 800726a <__sflush_r+0xae>
800723a: f104 0344 add.w r3, r4, #68 @ 0x44
800723e: 4299 cmp r1, r3
8007240: d002 beq.n 8007248 <__sflush_r+0x8c>
8007242: 4628 mov r0, r5
8007244: f7ff fbf4 bl 8006a30 <_free_r>
8007248: 2300 movs r3, #0
800724a: 6363 str r3, [r4, #52] @ 0x34
800724c: e00d b.n 800726a <__sflush_r+0xae>
800724e: 2301 movs r3, #1
8007250: 4628 mov r0, r5
8007252: 47b0 blx r6
8007254: 4602 mov r2, r0
8007256: 1c50 adds r0, r2, #1
8007258: d1c9 bne.n 80071ee <__sflush_r+0x32>
800725a: 682b ldr r3, [r5, #0]
800725c: 2b00 cmp r3, #0
800725e: d0c6 beq.n 80071ee <__sflush_r+0x32>
8007260: 2b1d cmp r3, #29
8007262: d001 beq.n 8007268 <__sflush_r+0xac>
8007264: 2b16 cmp r3, #22
8007266: d11e bne.n 80072a6 <__sflush_r+0xea>
8007268: 602f str r7, [r5, #0]
800726a: 2000 movs r0, #0
800726c: e022 b.n 80072b4 <__sflush_r+0xf8>
800726e: f043 0340 orr.w r3, r3, #64 @ 0x40
8007272: b21b sxth r3, r3
8007274: e01b b.n 80072ae <__sflush_r+0xf2>
8007276: 690f ldr r7, [r1, #16]
8007278: 2f00 cmp r7, #0
800727a: d0f6 beq.n 800726a <__sflush_r+0xae>
800727c: 0793 lsls r3, r2, #30
800727e: 680e ldr r6, [r1, #0]
8007280: bf08 it eq
8007282: 694b ldreq r3, [r1, #20]
8007284: 600f str r7, [r1, #0]
8007286: bf18 it ne
8007288: 2300 movne r3, #0
800728a: eba6 0807 sub.w r8, r6, r7
800728e: 608b str r3, [r1, #8]
8007290: f1b8 0f00 cmp.w r8, #0
8007294: dde9 ble.n 800726a <__sflush_r+0xae>
8007296: 6a21 ldr r1, [r4, #32]
8007298: 6aa6 ldr r6, [r4, #40] @ 0x28
800729a: 4643 mov r3, r8
800729c: 463a mov r2, r7
800729e: 4628 mov r0, r5
80072a0: 47b0 blx r6
80072a2: 2800 cmp r0, #0
80072a4: dc08 bgt.n 80072b8 <__sflush_r+0xfc>
80072a6: f9b4 300c ldrsh.w r3, [r4, #12]
80072aa: f043 0340 orr.w r3, r3, #64 @ 0x40
80072ae: 81a3 strh r3, [r4, #12]
80072b0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
80072b4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
80072b8: 4407 add r7, r0
80072ba: eba8 0800 sub.w r8, r8, r0
80072be: e7e7 b.n 8007290 <__sflush_r+0xd4>
80072c0: 20400001 .word 0x20400001
080072c4 <_fflush_r>:
80072c4: b538 push {r3, r4, r5, lr}
80072c6: 690b ldr r3, [r1, #16]
80072c8: 4605 mov r5, r0
80072ca: 460c mov r4, r1
80072cc: b913 cbnz r3, 80072d4 <_fflush_r+0x10>
80072ce: 2500 movs r5, #0
80072d0: 4628 mov r0, r5
80072d2: bd38 pop {r3, r4, r5, pc}
80072d4: b118 cbz r0, 80072de <_fflush_r+0x1a>
80072d6: 6a03 ldr r3, [r0, #32]
80072d8: b90b cbnz r3, 80072de <_fflush_r+0x1a>
80072da: f7ff fa93 bl 8006804 <__sinit>
80072de: f9b4 300c ldrsh.w r3, [r4, #12]
80072e2: 2b00 cmp r3, #0
80072e4: d0f3 beq.n 80072ce <_fflush_r+0xa>
80072e6: 6e62 ldr r2, [r4, #100] @ 0x64
80072e8: 07d0 lsls r0, r2, #31
80072ea: d404 bmi.n 80072f6 <_fflush_r+0x32>
80072ec: 0599 lsls r1, r3, #22
80072ee: d402 bmi.n 80072f6 <_fflush_r+0x32>
80072f0: 6da0 ldr r0, [r4, #88] @ 0x58
80072f2: f7ff fb8c bl 8006a0e <__retarget_lock_acquire_recursive>
80072f6: 4628 mov r0, r5
80072f8: 4621 mov r1, r4
80072fa: f7ff ff5f bl 80071bc <__sflush_r>
80072fe: 6e63 ldr r3, [r4, #100] @ 0x64
8007300: 07da lsls r2, r3, #31
8007302: 4605 mov r5, r0
8007304: d4e4 bmi.n 80072d0 <_fflush_r+0xc>
8007306: 89a3 ldrh r3, [r4, #12]
8007308: 059b lsls r3, r3, #22
800730a: d4e1 bmi.n 80072d0 <_fflush_r+0xc>
800730c: 6da0 ldr r0, [r4, #88] @ 0x58
800730e: f7ff fb7f bl 8006a10 <__retarget_lock_release_recursive>
8007312: e7dd b.n 80072d0 <_fflush_r+0xc>
08007314 <__swbuf_r>:
8007314: b5f8 push {r3, r4, r5, r6, r7, lr}
8007316: 460e mov r6, r1
8007318: 4614 mov r4, r2
800731a: 4605 mov r5, r0
800731c: b118 cbz r0, 8007326 <__swbuf_r+0x12>
800731e: 6a03 ldr r3, [r0, #32]
8007320: b90b cbnz r3, 8007326 <__swbuf_r+0x12>
8007322: f7ff fa6f bl 8006804 <__sinit>
8007326: 69a3 ldr r3, [r4, #24]
8007328: 60a3 str r3, [r4, #8]
800732a: 89a3 ldrh r3, [r4, #12]
800732c: 071a lsls r2, r3, #28
800732e: d501 bpl.n 8007334 <__swbuf_r+0x20>
8007330: 6923 ldr r3, [r4, #16]
8007332: b943 cbnz r3, 8007346 <__swbuf_r+0x32>
8007334: 4621 mov r1, r4
8007336: 4628 mov r0, r5
8007338: f000 f82a bl 8007390 <__swsetup_r>
800733c: b118 cbz r0, 8007346 <__swbuf_r+0x32>
800733e: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff
8007342: 4638 mov r0, r7
8007344: bdf8 pop {r3, r4, r5, r6, r7, pc}
8007346: 6823 ldr r3, [r4, #0]
8007348: 6922 ldr r2, [r4, #16]
800734a: 1a98 subs r0, r3, r2
800734c: 6963 ldr r3, [r4, #20]
800734e: b2f6 uxtb r6, r6
8007350: 4283 cmp r3, r0
8007352: 4637 mov r7, r6
8007354: dc05 bgt.n 8007362 <__swbuf_r+0x4e>
8007356: 4621 mov r1, r4
8007358: 4628 mov r0, r5
800735a: f7ff ffb3 bl 80072c4 <_fflush_r>
800735e: 2800 cmp r0, #0
8007360: d1ed bne.n 800733e <__swbuf_r+0x2a>
8007362: 68a3 ldr r3, [r4, #8]
8007364: 3b01 subs r3, #1
8007366: 60a3 str r3, [r4, #8]
8007368: 6823 ldr r3, [r4, #0]
800736a: 1c5a adds r2, r3, #1
800736c: 6022 str r2, [r4, #0]
800736e: 701e strb r6, [r3, #0]
8007370: 6962 ldr r2, [r4, #20]
8007372: 1c43 adds r3, r0, #1
8007374: 429a cmp r2, r3
8007376: d004 beq.n 8007382 <__swbuf_r+0x6e>
8007378: 89a3 ldrh r3, [r4, #12]
800737a: 07db lsls r3, r3, #31
800737c: d5e1 bpl.n 8007342 <__swbuf_r+0x2e>
800737e: 2e0a cmp r6, #10
8007380: d1df bne.n 8007342 <__swbuf_r+0x2e>
8007382: 4621 mov r1, r4
8007384: 4628 mov r0, r5
8007386: f7ff ff9d bl 80072c4 <_fflush_r>
800738a: 2800 cmp r0, #0
800738c: d0d9 beq.n 8007342 <__swbuf_r+0x2e>
800738e: e7d6 b.n 800733e <__swbuf_r+0x2a>
08007390 <__swsetup_r>:
8007390: b538 push {r3, r4, r5, lr}
8007392: 4b29 ldr r3, [pc, #164] @ (8007438 <__swsetup_r+0xa8>)
8007394: 4605 mov r5, r0
8007396: 6818 ldr r0, [r3, #0]
8007398: 460c mov r4, r1
800739a: b118 cbz r0, 80073a4 <__swsetup_r+0x14>
800739c: 6a03 ldr r3, [r0, #32]
800739e: b90b cbnz r3, 80073a4 <__swsetup_r+0x14>
80073a0: f7ff fa30 bl 8006804 <__sinit>
80073a4: f9b4 300c ldrsh.w r3, [r4, #12]
80073a8: 0719 lsls r1, r3, #28
80073aa: d422 bmi.n 80073f2 <__swsetup_r+0x62>
80073ac: 06da lsls r2, r3, #27
80073ae: d407 bmi.n 80073c0 <__swsetup_r+0x30>
80073b0: 2209 movs r2, #9
80073b2: 602a str r2, [r5, #0]
80073b4: f043 0340 orr.w r3, r3, #64 @ 0x40
80073b8: 81a3 strh r3, [r4, #12]
80073ba: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
80073be: e033 b.n 8007428 <__swsetup_r+0x98>
80073c0: 0758 lsls r0, r3, #29
80073c2: d512 bpl.n 80073ea <__swsetup_r+0x5a>
80073c4: 6b61 ldr r1, [r4, #52] @ 0x34
80073c6: b141 cbz r1, 80073da <__swsetup_r+0x4a>
80073c8: f104 0344 add.w r3, r4, #68 @ 0x44
80073cc: 4299 cmp r1, r3
80073ce: d002 beq.n 80073d6 <__swsetup_r+0x46>
80073d0: 4628 mov r0, r5
80073d2: f7ff fb2d bl 8006a30 <_free_r>
80073d6: 2300 movs r3, #0
80073d8: 6363 str r3, [r4, #52] @ 0x34
80073da: 89a3 ldrh r3, [r4, #12]
80073dc: f023 0324 bic.w r3, r3, #36 @ 0x24
80073e0: 81a3 strh r3, [r4, #12]
80073e2: 2300 movs r3, #0
80073e4: 6063 str r3, [r4, #4]
80073e6: 6923 ldr r3, [r4, #16]
80073e8: 6023 str r3, [r4, #0]
80073ea: 89a3 ldrh r3, [r4, #12]
80073ec: f043 0308 orr.w r3, r3, #8
80073f0: 81a3 strh r3, [r4, #12]
80073f2: 6923 ldr r3, [r4, #16]
80073f4: b94b cbnz r3, 800740a <__swsetup_r+0x7a>
80073f6: 89a3 ldrh r3, [r4, #12]
80073f8: f403 7320 and.w r3, r3, #640 @ 0x280
80073fc: f5b3 7f00 cmp.w r3, #512 @ 0x200
8007400: d003 beq.n 800740a <__swsetup_r+0x7a>
8007402: 4621 mov r1, r4
8007404: 4628 mov r0, r5
8007406: f000 f84f bl 80074a8 <__smakebuf_r>
800740a: f9b4 300c ldrsh.w r3, [r4, #12]
800740e: f013 0201 ands.w r2, r3, #1
8007412: d00a beq.n 800742a <__swsetup_r+0x9a>
8007414: 2200 movs r2, #0
8007416: 60a2 str r2, [r4, #8]
8007418: 6962 ldr r2, [r4, #20]
800741a: 4252 negs r2, r2
800741c: 61a2 str r2, [r4, #24]
800741e: 6922 ldr r2, [r4, #16]
8007420: b942 cbnz r2, 8007434 <__swsetup_r+0xa4>
8007422: f013 0080 ands.w r0, r3, #128 @ 0x80
8007426: d1c5 bne.n 80073b4 <__swsetup_r+0x24>
8007428: bd38 pop {r3, r4, r5, pc}
800742a: 0799 lsls r1, r3, #30
800742c: bf58 it pl
800742e: 6962 ldrpl r2, [r4, #20]
8007430: 60a2 str r2, [r4, #8]
8007432: e7f4 b.n 800741e <__swsetup_r+0x8e>
8007434: 2000 movs r0, #0
8007436: e7f7 b.n 8007428 <__swsetup_r+0x98>
8007438: 2000001c .word 0x2000001c
0800743c <_sbrk_r>:
800743c: b538 push {r3, r4, r5, lr}
800743e: 4d06 ldr r5, [pc, #24] @ (8007458 <_sbrk_r+0x1c>)
8007440: 2300 movs r3, #0
8007442: 4604 mov r4, r0
8007444: 4608 mov r0, r1
8007446: 602b str r3, [r5, #0]
8007448: f7f9 ffa8 bl 800139c <_sbrk>
800744c: 1c43 adds r3, r0, #1
800744e: d102 bne.n 8007456 <_sbrk_r+0x1a>
8007450: 682b ldr r3, [r5, #0]
8007452: b103 cbz r3, 8007456 <_sbrk_r+0x1a>
8007454: 6023 str r3, [r4, #0]
8007456: bd38 pop {r3, r4, r5, pc}
8007458: 200051f0 .word 0x200051f0
0800745c <__swhatbuf_r>:
800745c: b570 push {r4, r5, r6, lr}
800745e: 460c mov r4, r1
8007460: f9b1 100e ldrsh.w r1, [r1, #14]
8007464: 2900 cmp r1, #0
8007466: b096 sub sp, #88 @ 0x58
8007468: 4615 mov r5, r2
800746a: 461e mov r6, r3
800746c: da0d bge.n 800748a <__swhatbuf_r+0x2e>
800746e: 89a3 ldrh r3, [r4, #12]
8007470: f013 0f80 tst.w r3, #128 @ 0x80
8007474: f04f 0100 mov.w r1, #0
8007478: bf14 ite ne
800747a: 2340 movne r3, #64 @ 0x40
800747c: f44f 6380 moveq.w r3, #1024 @ 0x400
8007480: 2000 movs r0, #0
8007482: 6031 str r1, [r6, #0]
8007484: 602b str r3, [r5, #0]
8007486: b016 add sp, #88 @ 0x58
8007488: bd70 pop {r4, r5, r6, pc}
800748a: 466a mov r2, sp
800748c: f000 f848 bl 8007520 <_fstat_r>
8007490: 2800 cmp r0, #0
8007492: dbec blt.n 800746e <__swhatbuf_r+0x12>
8007494: 9901 ldr r1, [sp, #4]
8007496: f401 4170 and.w r1, r1, #61440 @ 0xf000
800749a: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000
800749e: 4259 negs r1, r3
80074a0: 4159 adcs r1, r3
80074a2: f44f 6380 mov.w r3, #1024 @ 0x400
80074a6: e7eb b.n 8007480 <__swhatbuf_r+0x24>
080074a8 <__smakebuf_r>:
80074a8: 898b ldrh r3, [r1, #12]
80074aa: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
80074ac: 079d lsls r5, r3, #30
80074ae: 4606 mov r6, r0
80074b0: 460c mov r4, r1
80074b2: d507 bpl.n 80074c4 <__smakebuf_r+0x1c>
80074b4: f104 0347 add.w r3, r4, #71 @ 0x47
80074b8: 6023 str r3, [r4, #0]
80074ba: 6123 str r3, [r4, #16]
80074bc: 2301 movs r3, #1
80074be: 6163 str r3, [r4, #20]
80074c0: b003 add sp, #12
80074c2: bdf0 pop {r4, r5, r6, r7, pc}
80074c4: ab01 add r3, sp, #4
80074c6: 466a mov r2, sp
80074c8: f7ff ffc8 bl 800745c <__swhatbuf_r>
80074cc: 9f00 ldr r7, [sp, #0]
80074ce: 4605 mov r5, r0
80074d0: 4639 mov r1, r7
80074d2: 4630 mov r0, r6
80074d4: f7ff fb18 bl 8006b08 <_malloc_r>
80074d8: b948 cbnz r0, 80074ee <__smakebuf_r+0x46>
80074da: f9b4 300c ldrsh.w r3, [r4, #12]
80074de: 059a lsls r2, r3, #22
80074e0: d4ee bmi.n 80074c0 <__smakebuf_r+0x18>
80074e2: f023 0303 bic.w r3, r3, #3
80074e6: f043 0302 orr.w r3, r3, #2
80074ea: 81a3 strh r3, [r4, #12]
80074ec: e7e2 b.n 80074b4 <__smakebuf_r+0xc>
80074ee: 89a3 ldrh r3, [r4, #12]
80074f0: 6020 str r0, [r4, #0]
80074f2: f043 0380 orr.w r3, r3, #128 @ 0x80
80074f6: 81a3 strh r3, [r4, #12]
80074f8: 9b01 ldr r3, [sp, #4]
80074fa: e9c4 0704 strd r0, r7, [r4, #16]
80074fe: b15b cbz r3, 8007518 <__smakebuf_r+0x70>
8007500: f9b4 100e ldrsh.w r1, [r4, #14]
8007504: 4630 mov r0, r6
8007506: f000 f81d bl 8007544 <_isatty_r>
800750a: b128 cbz r0, 8007518 <__smakebuf_r+0x70>
800750c: 89a3 ldrh r3, [r4, #12]
800750e: f023 0303 bic.w r3, r3, #3
8007512: f043 0301 orr.w r3, r3, #1
8007516: 81a3 strh r3, [r4, #12]
8007518: 89a3 ldrh r3, [r4, #12]
800751a: 431d orrs r5, r3
800751c: 81a5 strh r5, [r4, #12]
800751e: e7cf b.n 80074c0 <__smakebuf_r+0x18>
08007520 <_fstat_r>:
8007520: b538 push {r3, r4, r5, lr}
8007522: 4d07 ldr r5, [pc, #28] @ (8007540 <_fstat_r+0x20>)
8007524: 2300 movs r3, #0
8007526: 4604 mov r4, r0
8007528: 4608 mov r0, r1
800752a: 4611 mov r1, r2
800752c: 602b str r3, [r5, #0]
800752e: f7f9 ff0c bl 800134a <_fstat>
8007532: 1c43 adds r3, r0, #1
8007534: d102 bne.n 800753c <_fstat_r+0x1c>
8007536: 682b ldr r3, [r5, #0]
8007538: b103 cbz r3, 800753c <_fstat_r+0x1c>
800753a: 6023 str r3, [r4, #0]
800753c: bd38 pop {r3, r4, r5, pc}
800753e: bf00 nop
8007540: 200051f0 .word 0x200051f0
08007544 <_isatty_r>:
8007544: b538 push {r3, r4, r5, lr}
8007546: 4d06 ldr r5, [pc, #24] @ (8007560 <_isatty_r+0x1c>)
8007548: 2300 movs r3, #0
800754a: 4604 mov r4, r0
800754c: 4608 mov r0, r1
800754e: 602b str r3, [r5, #0]
8007550: f7f9 ff0b bl 800136a <_isatty>
8007554: 1c43 adds r3, r0, #1
8007556: d102 bne.n 800755e <_isatty_r+0x1a>
8007558: 682b ldr r3, [r5, #0]
800755a: b103 cbz r3, 800755e <_isatty_r+0x1a>
800755c: 6023 str r3, [r4, #0]
800755e: bd38 pop {r3, r4, r5, pc}
8007560: 200051f0 .word 0x200051f0
08007564 <_init>:
8007564: b5f8 push {r3, r4, r5, r6, r7, lr}
8007566: bf00 nop
8007568: bcf8 pop {r3, r4, r5, r6, r7}
800756a: bc08 pop {r3}
800756c: 469e mov lr, r3
800756e: 4770 bx lr
08007570 <_fini>:
8007570: b5f8 push {r3, r4, r5, r6, r7, lr}
8007572: bf00 nop
8007574: bcf8 pop {r3, r4, r5, r6, r7}
8007576: bc08 pop {r3}
8007578: 469e mov lr, r3
800757a: 4770 bx lr
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