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HAW-LA_s7-prakt-mikrocontro.../Versuch3/Debug/Versuch3.list
jonny 33672839e9 Add V3 implementation (not tested)
2025-11-17 18:07:46 +01:00

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Versuch3.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001e0 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00008654 080001e0 080001e0 000011e0 2**4
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000240 08008834 08008834 00009834 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08008a74 08008a74 0000a06c 2**0
CONTENTS, READONLY
4 .ARM 00000008 08008a74 08008a74 00009a74 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08008a7c 08008a7c 0000a06c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08008a7c 08008a7c 00009a7c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08008a80 08008a80 00009a80 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000006c 20000000 08008a84 0000a000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00008dcc 2000006c 08008af0 0000a06c 2**2
ALLOC
10 ._user_heap_stack 00000600 20008e38 08008af0 0000ae38 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0000a06c 2**0
CONTENTS, READONLY
12 .debug_info 0001f375 00000000 00000000 0000a09c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000044f3 00000000 00000000 00029411 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00001ad0 00000000 00000000 0002d908 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 000014d4 00000000 00000000 0002f3d8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00027db1 00000000 00000000 000308ac 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0001e3d6 00000000 00000000 0005865d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000ef3be 00000000 00000000 00076a33 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 00165df1 2**0
CONTENTS, READONLY
20 .debug_frame 000078ac 00000000 00000000 00165e34 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 0000007e 00000000 00000000 0016d6e0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001e0 <__do_global_dtors_aux>:
80001e0: b510 push {r4, lr}
80001e2: 4c05 ldr r4, [pc, #20] @ (80001f8 <__do_global_dtors_aux+0x18>)
80001e4: 7823 ldrb r3, [r4, #0]
80001e6: b933 cbnz r3, 80001f6 <__do_global_dtors_aux+0x16>
80001e8: 4b04 ldr r3, [pc, #16] @ (80001fc <__do_global_dtors_aux+0x1c>)
80001ea: b113 cbz r3, 80001f2 <__do_global_dtors_aux+0x12>
80001ec: 4804 ldr r0, [pc, #16] @ (8000200 <__do_global_dtors_aux+0x20>)
80001ee: f3af 8000 nop.w
80001f2: 2301 movs r3, #1
80001f4: 7023 strb r3, [r4, #0]
80001f6: bd10 pop {r4, pc}
80001f8: 2000006c .word 0x2000006c
80001fc: 00000000 .word 0x00000000
8000200: 0800881c .word 0x0800881c
08000204 <frame_dummy>:
8000204: b508 push {r3, lr}
8000206: 4b03 ldr r3, [pc, #12] @ (8000214 <frame_dummy+0x10>)
8000208: b11b cbz r3, 8000212 <frame_dummy+0xe>
800020a: 4903 ldr r1, [pc, #12] @ (8000218 <frame_dummy+0x14>)
800020c: 4803 ldr r0, [pc, #12] @ (800021c <frame_dummy+0x18>)
800020e: f3af 8000 nop.w
8000212: bd08 pop {r3, pc}
8000214: 00000000 .word 0x00000000
8000218: 20000070 .word 0x20000070
800021c: 0800881c .word 0x0800881c
08000220 <memchr>:
8000220: f001 01ff and.w r1, r1, #255 @ 0xff
8000224: 2a10 cmp r2, #16
8000226: db2b blt.n 8000280 <memchr+0x60>
8000228: f010 0f07 tst.w r0, #7
800022c: d008 beq.n 8000240 <memchr+0x20>
800022e: f810 3b01 ldrb.w r3, [r0], #1
8000232: 3a01 subs r2, #1
8000234: 428b cmp r3, r1
8000236: d02d beq.n 8000294 <memchr+0x74>
8000238: f010 0f07 tst.w r0, #7
800023c: b342 cbz r2, 8000290 <memchr+0x70>
800023e: d1f6 bne.n 800022e <memchr+0xe>
8000240: b4f0 push {r4, r5, r6, r7}
8000242: ea41 2101 orr.w r1, r1, r1, lsl #8
8000246: ea41 4101 orr.w r1, r1, r1, lsl #16
800024a: f022 0407 bic.w r4, r2, #7
800024e: f07f 0700 mvns.w r7, #0
8000252: 2300 movs r3, #0
8000254: e8f0 5602 ldrd r5, r6, [r0], #8
8000258: 3c08 subs r4, #8
800025a: ea85 0501 eor.w r5, r5, r1
800025e: ea86 0601 eor.w r6, r6, r1
8000262: fa85 f547 uadd8 r5, r5, r7
8000266: faa3 f587 sel r5, r3, r7
800026a: fa86 f647 uadd8 r6, r6, r7
800026e: faa5 f687 sel r6, r5, r7
8000272: b98e cbnz r6, 8000298 <memchr+0x78>
8000274: d1ee bne.n 8000254 <memchr+0x34>
8000276: bcf0 pop {r4, r5, r6, r7}
8000278: f001 01ff and.w r1, r1, #255 @ 0xff
800027c: f002 0207 and.w r2, r2, #7
8000280: b132 cbz r2, 8000290 <memchr+0x70>
8000282: f810 3b01 ldrb.w r3, [r0], #1
8000286: 3a01 subs r2, #1
8000288: ea83 0301 eor.w r3, r3, r1
800028c: b113 cbz r3, 8000294 <memchr+0x74>
800028e: d1f8 bne.n 8000282 <memchr+0x62>
8000290: 2000 movs r0, #0
8000292: 4770 bx lr
8000294: 3801 subs r0, #1
8000296: 4770 bx lr
8000298: 2d00 cmp r5, #0
800029a: bf06 itte eq
800029c: 4635 moveq r5, r6
800029e: 3803 subeq r0, #3
80002a0: 3807 subne r0, #7
80002a2: f015 0f01 tst.w r5, #1
80002a6: d107 bne.n 80002b8 <memchr+0x98>
80002a8: 3001 adds r0, #1
80002aa: f415 7f80 tst.w r5, #256 @ 0x100
80002ae: bf02 ittt eq
80002b0: 3001 addeq r0, #1
80002b2: f415 3fc0 tsteq.w r5, #98304 @ 0x18000
80002b6: 3001 addeq r0, #1
80002b8: bcf0 pop {r4, r5, r6, r7}
80002ba: 3801 subs r0, #1
80002bc: 4770 bx lr
80002be: bf00 nop
080002c0 <__aeabi_uldivmod>:
80002c0: b953 cbnz r3, 80002d8 <__aeabi_uldivmod+0x18>
80002c2: b94a cbnz r2, 80002d8 <__aeabi_uldivmod+0x18>
80002c4: 2900 cmp r1, #0
80002c6: bf08 it eq
80002c8: 2800 cmpeq r0, #0
80002ca: bf1c itt ne
80002cc: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
80002d0: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
80002d4: f000 b988 b.w 80005e8 <__aeabi_idiv0>
80002d8: f1ad 0c08 sub.w ip, sp, #8
80002dc: e96d ce04 strd ip, lr, [sp, #-16]!
80002e0: f000 f806 bl 80002f0 <__udivmoddi4>
80002e4: f8dd e004 ldr.w lr, [sp, #4]
80002e8: e9dd 2302 ldrd r2, r3, [sp, #8]
80002ec: b004 add sp, #16
80002ee: 4770 bx lr
080002f0 <__udivmoddi4>:
80002f0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80002f4: 9d08 ldr r5, [sp, #32]
80002f6: 468e mov lr, r1
80002f8: 4604 mov r4, r0
80002fa: 4688 mov r8, r1
80002fc: 2b00 cmp r3, #0
80002fe: d14a bne.n 8000396 <__udivmoddi4+0xa6>
8000300: 428a cmp r2, r1
8000302: 4617 mov r7, r2
8000304: d962 bls.n 80003cc <__udivmoddi4+0xdc>
8000306: fab2 f682 clz r6, r2
800030a: b14e cbz r6, 8000320 <__udivmoddi4+0x30>
800030c: f1c6 0320 rsb r3, r6, #32
8000310: fa01 f806 lsl.w r8, r1, r6
8000314: fa20 f303 lsr.w r3, r0, r3
8000318: 40b7 lsls r7, r6
800031a: ea43 0808 orr.w r8, r3, r8
800031e: 40b4 lsls r4, r6
8000320: ea4f 4e17 mov.w lr, r7, lsr #16
8000324: fa1f fc87 uxth.w ip, r7
8000328: fbb8 f1fe udiv r1, r8, lr
800032c: 0c23 lsrs r3, r4, #16
800032e: fb0e 8811 mls r8, lr, r1, r8
8000332: ea43 4308 orr.w r3, r3, r8, lsl #16
8000336: fb01 f20c mul.w r2, r1, ip
800033a: 429a cmp r2, r3
800033c: d909 bls.n 8000352 <__udivmoddi4+0x62>
800033e: 18fb adds r3, r7, r3
8000340: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
8000344: f080 80ea bcs.w 800051c <__udivmoddi4+0x22c>
8000348: 429a cmp r2, r3
800034a: f240 80e7 bls.w 800051c <__udivmoddi4+0x22c>
800034e: 3902 subs r1, #2
8000350: 443b add r3, r7
8000352: 1a9a subs r2, r3, r2
8000354: b2a3 uxth r3, r4
8000356: fbb2 f0fe udiv r0, r2, lr
800035a: fb0e 2210 mls r2, lr, r0, r2
800035e: ea43 4302 orr.w r3, r3, r2, lsl #16
8000362: fb00 fc0c mul.w ip, r0, ip
8000366: 459c cmp ip, r3
8000368: d909 bls.n 800037e <__udivmoddi4+0x8e>
800036a: 18fb adds r3, r7, r3
800036c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
8000370: f080 80d6 bcs.w 8000520 <__udivmoddi4+0x230>
8000374: 459c cmp ip, r3
8000376: f240 80d3 bls.w 8000520 <__udivmoddi4+0x230>
800037a: 443b add r3, r7
800037c: 3802 subs r0, #2
800037e: ea40 4001 orr.w r0, r0, r1, lsl #16
8000382: eba3 030c sub.w r3, r3, ip
8000386: 2100 movs r1, #0
8000388: b11d cbz r5, 8000392 <__udivmoddi4+0xa2>
800038a: 40f3 lsrs r3, r6
800038c: 2200 movs r2, #0
800038e: e9c5 3200 strd r3, r2, [r5]
8000392: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000396: 428b cmp r3, r1
8000398: d905 bls.n 80003a6 <__udivmoddi4+0xb6>
800039a: b10d cbz r5, 80003a0 <__udivmoddi4+0xb0>
800039c: e9c5 0100 strd r0, r1, [r5]
80003a0: 2100 movs r1, #0
80003a2: 4608 mov r0, r1
80003a4: e7f5 b.n 8000392 <__udivmoddi4+0xa2>
80003a6: fab3 f183 clz r1, r3
80003aa: 2900 cmp r1, #0
80003ac: d146 bne.n 800043c <__udivmoddi4+0x14c>
80003ae: 4573 cmp r3, lr
80003b0: d302 bcc.n 80003b8 <__udivmoddi4+0xc8>
80003b2: 4282 cmp r2, r0
80003b4: f200 8105 bhi.w 80005c2 <__udivmoddi4+0x2d2>
80003b8: 1a84 subs r4, r0, r2
80003ba: eb6e 0203 sbc.w r2, lr, r3
80003be: 2001 movs r0, #1
80003c0: 4690 mov r8, r2
80003c2: 2d00 cmp r5, #0
80003c4: d0e5 beq.n 8000392 <__udivmoddi4+0xa2>
80003c6: e9c5 4800 strd r4, r8, [r5]
80003ca: e7e2 b.n 8000392 <__udivmoddi4+0xa2>
80003cc: 2a00 cmp r2, #0
80003ce: f000 8090 beq.w 80004f2 <__udivmoddi4+0x202>
80003d2: fab2 f682 clz r6, r2
80003d6: 2e00 cmp r6, #0
80003d8: f040 80a4 bne.w 8000524 <__udivmoddi4+0x234>
80003dc: 1a8a subs r2, r1, r2
80003de: 0c03 lsrs r3, r0, #16
80003e0: ea4f 4e17 mov.w lr, r7, lsr #16
80003e4: b280 uxth r0, r0
80003e6: b2bc uxth r4, r7
80003e8: 2101 movs r1, #1
80003ea: fbb2 fcfe udiv ip, r2, lr
80003ee: fb0e 221c mls r2, lr, ip, r2
80003f2: ea43 4302 orr.w r3, r3, r2, lsl #16
80003f6: fb04 f20c mul.w r2, r4, ip
80003fa: 429a cmp r2, r3
80003fc: d907 bls.n 800040e <__udivmoddi4+0x11e>
80003fe: 18fb adds r3, r7, r3
8000400: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
8000404: d202 bcs.n 800040c <__udivmoddi4+0x11c>
8000406: 429a cmp r2, r3
8000408: f200 80e0 bhi.w 80005cc <__udivmoddi4+0x2dc>
800040c: 46c4 mov ip, r8
800040e: 1a9b subs r3, r3, r2
8000410: fbb3 f2fe udiv r2, r3, lr
8000414: fb0e 3312 mls r3, lr, r2, r3
8000418: ea40 4303 orr.w r3, r0, r3, lsl #16
800041c: fb02 f404 mul.w r4, r2, r4
8000420: 429c cmp r4, r3
8000422: d907 bls.n 8000434 <__udivmoddi4+0x144>
8000424: 18fb adds r3, r7, r3
8000426: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
800042a: d202 bcs.n 8000432 <__udivmoddi4+0x142>
800042c: 429c cmp r4, r3
800042e: f200 80ca bhi.w 80005c6 <__udivmoddi4+0x2d6>
8000432: 4602 mov r2, r0
8000434: 1b1b subs r3, r3, r4
8000436: ea42 400c orr.w r0, r2, ip, lsl #16
800043a: e7a5 b.n 8000388 <__udivmoddi4+0x98>
800043c: f1c1 0620 rsb r6, r1, #32
8000440: 408b lsls r3, r1
8000442: fa22 f706 lsr.w r7, r2, r6
8000446: 431f orrs r7, r3
8000448: fa0e f401 lsl.w r4, lr, r1
800044c: fa20 f306 lsr.w r3, r0, r6
8000450: fa2e fe06 lsr.w lr, lr, r6
8000454: ea4f 4917 mov.w r9, r7, lsr #16
8000458: 4323 orrs r3, r4
800045a: fa00 f801 lsl.w r8, r0, r1
800045e: fa1f fc87 uxth.w ip, r7
8000462: fbbe f0f9 udiv r0, lr, r9
8000466: 0c1c lsrs r4, r3, #16
8000468: fb09 ee10 mls lr, r9, r0, lr
800046c: ea44 440e orr.w r4, r4, lr, lsl #16
8000470: fb00 fe0c mul.w lr, r0, ip
8000474: 45a6 cmp lr, r4
8000476: fa02 f201 lsl.w r2, r2, r1
800047a: d909 bls.n 8000490 <__udivmoddi4+0x1a0>
800047c: 193c adds r4, r7, r4
800047e: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
8000482: f080 809c bcs.w 80005be <__udivmoddi4+0x2ce>
8000486: 45a6 cmp lr, r4
8000488: f240 8099 bls.w 80005be <__udivmoddi4+0x2ce>
800048c: 3802 subs r0, #2
800048e: 443c add r4, r7
8000490: eba4 040e sub.w r4, r4, lr
8000494: fa1f fe83 uxth.w lr, r3
8000498: fbb4 f3f9 udiv r3, r4, r9
800049c: fb09 4413 mls r4, r9, r3, r4
80004a0: ea4e 4404 orr.w r4, lr, r4, lsl #16
80004a4: fb03 fc0c mul.w ip, r3, ip
80004a8: 45a4 cmp ip, r4
80004aa: d908 bls.n 80004be <__udivmoddi4+0x1ce>
80004ac: 193c adds r4, r7, r4
80004ae: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
80004b2: f080 8082 bcs.w 80005ba <__udivmoddi4+0x2ca>
80004b6: 45a4 cmp ip, r4
80004b8: d97f bls.n 80005ba <__udivmoddi4+0x2ca>
80004ba: 3b02 subs r3, #2
80004bc: 443c add r4, r7
80004be: ea43 4000 orr.w r0, r3, r0, lsl #16
80004c2: eba4 040c sub.w r4, r4, ip
80004c6: fba0 ec02 umull lr, ip, r0, r2
80004ca: 4564 cmp r4, ip
80004cc: 4673 mov r3, lr
80004ce: 46e1 mov r9, ip
80004d0: d362 bcc.n 8000598 <__udivmoddi4+0x2a8>
80004d2: d05f beq.n 8000594 <__udivmoddi4+0x2a4>
80004d4: b15d cbz r5, 80004ee <__udivmoddi4+0x1fe>
80004d6: ebb8 0203 subs.w r2, r8, r3
80004da: eb64 0409 sbc.w r4, r4, r9
80004de: fa04 f606 lsl.w r6, r4, r6
80004e2: fa22 f301 lsr.w r3, r2, r1
80004e6: 431e orrs r6, r3
80004e8: 40cc lsrs r4, r1
80004ea: e9c5 6400 strd r6, r4, [r5]
80004ee: 2100 movs r1, #0
80004f0: e74f b.n 8000392 <__udivmoddi4+0xa2>
80004f2: fbb1 fcf2 udiv ip, r1, r2
80004f6: 0c01 lsrs r1, r0, #16
80004f8: ea41 410e orr.w r1, r1, lr, lsl #16
80004fc: b280 uxth r0, r0
80004fe: ea40 4201 orr.w r2, r0, r1, lsl #16
8000502: 463b mov r3, r7
8000504: 4638 mov r0, r7
8000506: 463c mov r4, r7
8000508: 46b8 mov r8, r7
800050a: 46be mov lr, r7
800050c: 2620 movs r6, #32
800050e: fbb1 f1f7 udiv r1, r1, r7
8000512: eba2 0208 sub.w r2, r2, r8
8000516: ea41 410c orr.w r1, r1, ip, lsl #16
800051a: e766 b.n 80003ea <__udivmoddi4+0xfa>
800051c: 4601 mov r1, r0
800051e: e718 b.n 8000352 <__udivmoddi4+0x62>
8000520: 4610 mov r0, r2
8000522: e72c b.n 800037e <__udivmoddi4+0x8e>
8000524: f1c6 0220 rsb r2, r6, #32
8000528: fa2e f302 lsr.w r3, lr, r2
800052c: 40b7 lsls r7, r6
800052e: 40b1 lsls r1, r6
8000530: fa20 f202 lsr.w r2, r0, r2
8000534: ea4f 4e17 mov.w lr, r7, lsr #16
8000538: 430a orrs r2, r1
800053a: fbb3 f8fe udiv r8, r3, lr
800053e: b2bc uxth r4, r7
8000540: fb0e 3318 mls r3, lr, r8, r3
8000544: 0c11 lsrs r1, r2, #16
8000546: ea41 4103 orr.w r1, r1, r3, lsl #16
800054a: fb08 f904 mul.w r9, r8, r4
800054e: 40b0 lsls r0, r6
8000550: 4589 cmp r9, r1
8000552: ea4f 4310 mov.w r3, r0, lsr #16
8000556: b280 uxth r0, r0
8000558: d93e bls.n 80005d8 <__udivmoddi4+0x2e8>
800055a: 1879 adds r1, r7, r1
800055c: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
8000560: d201 bcs.n 8000566 <__udivmoddi4+0x276>
8000562: 4589 cmp r9, r1
8000564: d81f bhi.n 80005a6 <__udivmoddi4+0x2b6>
8000566: eba1 0109 sub.w r1, r1, r9
800056a: fbb1 f9fe udiv r9, r1, lr
800056e: fb09 f804 mul.w r8, r9, r4
8000572: fb0e 1119 mls r1, lr, r9, r1
8000576: b292 uxth r2, r2
8000578: ea42 4201 orr.w r2, r2, r1, lsl #16
800057c: 4542 cmp r2, r8
800057e: d229 bcs.n 80005d4 <__udivmoddi4+0x2e4>
8000580: 18ba adds r2, r7, r2
8000582: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
8000586: d2c4 bcs.n 8000512 <__udivmoddi4+0x222>
8000588: 4542 cmp r2, r8
800058a: d2c2 bcs.n 8000512 <__udivmoddi4+0x222>
800058c: f1a9 0102 sub.w r1, r9, #2
8000590: 443a add r2, r7
8000592: e7be b.n 8000512 <__udivmoddi4+0x222>
8000594: 45f0 cmp r8, lr
8000596: d29d bcs.n 80004d4 <__udivmoddi4+0x1e4>
8000598: ebbe 0302 subs.w r3, lr, r2
800059c: eb6c 0c07 sbc.w ip, ip, r7
80005a0: 3801 subs r0, #1
80005a2: 46e1 mov r9, ip
80005a4: e796 b.n 80004d4 <__udivmoddi4+0x1e4>
80005a6: eba7 0909 sub.w r9, r7, r9
80005aa: 4449 add r1, r9
80005ac: f1a8 0c02 sub.w ip, r8, #2
80005b0: fbb1 f9fe udiv r9, r1, lr
80005b4: fb09 f804 mul.w r8, r9, r4
80005b8: e7db b.n 8000572 <__udivmoddi4+0x282>
80005ba: 4673 mov r3, lr
80005bc: e77f b.n 80004be <__udivmoddi4+0x1ce>
80005be: 4650 mov r0, sl
80005c0: e766 b.n 8000490 <__udivmoddi4+0x1a0>
80005c2: 4608 mov r0, r1
80005c4: e6fd b.n 80003c2 <__udivmoddi4+0xd2>
80005c6: 443b add r3, r7
80005c8: 3a02 subs r2, #2
80005ca: e733 b.n 8000434 <__udivmoddi4+0x144>
80005cc: f1ac 0c02 sub.w ip, ip, #2
80005d0: 443b add r3, r7
80005d2: e71c b.n 800040e <__udivmoddi4+0x11e>
80005d4: 4649 mov r1, r9
80005d6: e79c b.n 8000512 <__udivmoddi4+0x222>
80005d8: eba1 0109 sub.w r1, r1, r9
80005dc: 46c4 mov ip, r8
80005de: fbb1 f9fe udiv r9, r1, lr
80005e2: fb09 f804 mul.w r8, r9, r4
80005e6: e7c4 b.n 8000572 <__udivmoddi4+0x282>
080005e8 <__aeabi_idiv0>:
80005e8: 4770 bx lr
80005ea: bf00 nop
080005ec <Display_WriteCommand>:
} LCD_CONTROLLER_TypeDef;
#define FMC_BANK2_BASE ((uint32_t)(0x60000000 | 0x04000000))
#define FMC_BANK2 ((LCD_CONTROLLER_TypeDef *) FMC_BANK2_BASE)
void Display_WriteCommand( uint8_t Reg) {
80005ec: b480 push {r7}
80005ee: b083 sub sp, #12
80005f0: af00 add r7, sp, #0
80005f2: 4603 mov r3, r0
80005f4: 71fb strb r3, [r7, #7]
FMC_BANK2->REG = Reg;
80005f6: f04f 43c8 mov.w r3, #1677721600 @ 0x64000000
80005fa: 79fa ldrb r2, [r7, #7]
80005fc: b292 uxth r2, r2
80005fe: 801a strh r2, [r3, #0]
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__STATIC_FORCEINLINE void __DSB(void)
{
__ASM volatile ("dsb 0xF":::"memory");
8000600: f3bf 8f4f dsb sy
}
8000604: bf00 nop
__DSB();
}
8000606: bf00 nop
8000608: 370c adds r7, #12
800060a: 46bd mov sp, r7
800060c: f85d 7b04 ldr.w r7, [sp], #4
8000610: 4770 bx lr
08000612 <Display_WriteData>:
void Display_WriteData( uint16_t Value ) {
8000612: b480 push {r7}
8000614: b083 sub sp, #12
8000616: af00 add r7, sp, #0
8000618: 4603 mov r3, r0
800061a: 80fb strh r3, [r7, #6]
FMC_BANK2->RAM = Value;
800061c: f04f 42c8 mov.w r2, #1677721600 @ 0x64000000
8000620: 88fb ldrh r3, [r7, #6]
8000622: 8053 strh r3, [r2, #2]
__ASM volatile ("dsb 0xF":::"memory");
8000624: f3bf 8f4f dsb sy
}
8000628: bf00 nop
__DSB();
}
800062a: bf00 nop
800062c: 370c adds r7, #12
800062e: 46bd mov sp, r7
8000630: f85d 7b04 ldr.w r7, [sp], #4
8000634: 4770 bx lr
08000636 <Display_ReadData>:
static uint16_t Display_ReadData(void) {
8000636: b480 push {r7}
8000638: af00 add r7, sp, #0
return FMC_BANK2->RAM;
800063a: f04f 43c8 mov.w r3, #1677721600 @ 0x64000000
800063e: 885b ldrh r3, [r3, #2]
8000640: b29b uxth r3, r3
}
8000642: 4618 mov r0, r3
8000644: 46bd mov sp, r7
8000646: f85d 7b04 ldr.w r7, [sp], #4
800064a: 4770 bx lr
0800064c <Display_ReadReg>:
uint8_t Display_ReadReg(uint8_t Command) {
800064c: b580 push {r7, lr}
800064e: b082 sub sp, #8
8000650: af00 add r7, sp, #0
8000652: 4603 mov r3, r0
8000654: 71fb strb r3, [r7, #7]
Display_WriteCommand(Command);
8000656: 79fb ldrb r3, [r7, #7]
8000658: 4618 mov r0, r3
800065a: f7ff ffc7 bl 80005ec <Display_WriteCommand>
Display_ReadData();
800065e: f7ff ffea bl 8000636 <Display_ReadData>
return (Display_ReadData());
8000662: f7ff ffe8 bl 8000636 <Display_ReadData>
8000666: 4603 mov r3, r0
8000668: b2db uxtb r3, r3
}
800066a: 4618 mov r0, r3
800066c: 3708 adds r7, #8
800066e: 46bd mov sp, r7
8000670: bd80 pop {r7, pc}
08000672 <Display_WriteCommandList>:
0x11, 0, // Sleep out
0x35, 1, 0x00, // Tearing Effect
0xff
};
static void Display_WriteCommandList(const uint8_t *addr) {
8000672: b580 push {r7, lr}
8000674: b084 sub sp, #16
8000676: af00 add r7, sp, #0
8000678: 6078 str r0, [r7, #4]
uint8_t NumArgs;
uint16_t Delay;
while(*addr != 0xff) {
800067a: e033 b.n 80006e4 <Display_WriteCommandList+0x72>
//printf("Cmd %x, ", *addr);
Display_WriteCommand(*addr++); // Command
800067c: 687b ldr r3, [r7, #4]
800067e: 1c5a adds r2, r3, #1
8000680: 607a str r2, [r7, #4]
8000682: 781b ldrb r3, [r3, #0]
8000684: 4618 mov r0, r3
8000686: f7ff ffb1 bl 80005ec <Display_WriteCommand>
NumArgs = *addr++; // Number of arguments
800068a: 687b ldr r3, [r7, #4]
800068c: 1c5a adds r2, r3, #1
800068e: 607a str r2, [r7, #4]
8000690: 781b ldrb r3, [r3, #0]
8000692: 73fb strb r3, [r7, #15]
Delay = NumArgs & 0x80; // Bit 7: Delay flag
8000694: 7bfb ldrb r3, [r7, #15]
8000696: b29b uxth r3, r3
8000698: f003 0380 and.w r3, r3, #128 @ 0x80
800069c: 81bb strh r3, [r7, #12]
NumArgs &= ~0x80;
800069e: 7bfb ldrb r3, [r7, #15]
80006a0: f003 037f and.w r3, r3, #127 @ 0x7f
80006a4: 73fb strb r3, [r7, #15]
//printf("Num: %d: ", NumArgs);
while(NumArgs--) {
80006a6: e006 b.n 80006b6 <Display_WriteCommandList+0x44>
//printf("%x ", *addr );
Display_WriteData(*addr++);
80006a8: 687b ldr r3, [r7, #4]
80006aa: 1c5a adds r2, r3, #1
80006ac: 607a str r2, [r7, #4]
80006ae: 781b ldrb r3, [r3, #0]
80006b0: 4618 mov r0, r3
80006b2: f7ff ffae bl 8000612 <Display_WriteData>
while(NumArgs--) {
80006b6: 7bfb ldrb r3, [r7, #15]
80006b8: 1e5a subs r2, r3, #1
80006ba: 73fa strb r2, [r7, #15]
80006bc: 2b00 cmp r3, #0
80006be: d1f3 bne.n 80006a8 <Display_WriteCommandList+0x36>
}
//printf("\n");
// Delay after command
if(Delay) { // If delay flag set
80006c0: 89bb ldrh r3, [r7, #12]
80006c2: 2b00 cmp r3, #0
80006c4: d00e beq.n 80006e4 <Display_WriteCommandList+0x72>
Delay = *addr++; // Delay time
80006c6: 687b ldr r3, [r7, #4]
80006c8: 1c5a adds r2, r3, #1
80006ca: 607a str r2, [r7, #4]
80006cc: 781b ldrb r3, [r3, #0]
80006ce: 81bb strh r3, [r7, #12]
if( Delay == 255) {
80006d0: 89bb ldrh r3, [r7, #12]
80006d2: 2bff cmp r3, #255 @ 0xff
80006d4: d102 bne.n 80006dc <Display_WriteCommandList+0x6a>
Delay = 500;
80006d6: f44f 73fa mov.w r3, #500 @ 0x1f4
80006da: 81bb strh r3, [r7, #12]
}
//printf("Delay: %d\n", Delay );
HAL_Delay(Delay);
80006dc: 89bb ldrh r3, [r7, #12]
80006de: 4618 mov r0, r3
80006e0: f001 fce0 bl 80020a4 <HAL_Delay>
while(*addr != 0xff) {
80006e4: 687b ldr r3, [r7, #4]
80006e6: 781b ldrb r3, [r3, #0]
80006e8: 2bff cmp r3, #255 @ 0xff
80006ea: d1c7 bne.n 800067c <Display_WriteCommandList+0xa>
}
}
}
80006ec: bf00 nop
80006ee: bf00 nop
80006f0: 3710 adds r7, #16
80006f2: 46bd mov sp, r7
80006f4: bd80 pop {r7, pc}
...
080006f8 <Display_InitFmc>:
static void Display_InitFmc( void ) {
80006f8: b580 push {r7, lr}
80006fa: b088 sub sp, #32
80006fc: af00 add r7, sp, #0
FMC_NORSRAM_TimingTypeDef sram_timing={0};
80006fe: 1d3b adds r3, r7, #4
8000700: 2200 movs r2, #0
8000702: 601a str r2, [r3, #0]
8000704: 605a str r2, [r3, #4]
8000706: 609a str r2, [r3, #8]
8000708: 60da str r2, [r3, #12]
800070a: 611a str r2, [r3, #16]
800070c: 615a str r2, [r3, #20]
800070e: 619a str r2, [r3, #24]
// PSRAM device configuration
// Timing configuration derived from system clock (up to 216Mhz) for 108Mhz as PSRAM clock frequency
sram_timing.AddressSetupTime = 9;
8000710: 2309 movs r3, #9
8000712: 607b str r3, [r7, #4]
sram_timing.AddressHoldTime = 2;
8000714: 2302 movs r3, #2
8000716: 60bb str r3, [r7, #8]
sram_timing.DataSetupTime = 6;
8000718: 2306 movs r3, #6
800071a: 60fb str r3, [r7, #12]
sram_timing.BusTurnAroundDuration = 1;
800071c: 2301 movs r3, #1
800071e: 613b str r3, [r7, #16]
sram_timing.CLKDivision = 2;
8000720: 2302 movs r3, #2
8000722: 617b str r3, [r7, #20]
sram_timing.DataLatency = 2;
8000724: 2302 movs r3, #2
8000726: 61bb str r3, [r7, #24]
sram_timing.AccessMode = FMC_ACCESS_MODE_A;
8000728: 2300 movs r3, #0
800072a: 61fb str r3, [r7, #28]
// Initialize the FMC controller for LCD (FMC_NORSRAM_BANK2)
HAL_SRAM_Init(&hsram2, &sram_timing, &sram_timing);
800072c: 1d3a adds r2, r7, #4
800072e: 1d3b adds r3, r7, #4
8000730: 4619 mov r1, r3
8000732: 4803 ldr r0, [pc, #12] @ (8000740 <Display_InitFmc+0x48>)
8000734: f003 f93e bl 80039b4 <HAL_SRAM_Init>
}
8000738: bf00 nop
800073a: 3720 adds r7, #32
800073c: 46bd mov sp, r7
800073e: bd80 pop {r7, pc}
8000740: 20000610 .word 0x20000610
08000744 <Display_SetOrientation>:
static void Display_SetOrientation(uint32_t orientation) {
8000744: b580 push {r7, lr}
8000746: b084 sub sp, #16
8000748: af00 add r7, sp, #0
800074a: 6078 str r0, [r7, #4]
uint8_t NormalDisplayParam;
if( orientation == LCD_ORIENTATION_LANDSCAPE ) {
800074c: 687b ldr r3, [r7, #4]
800074e: 2b01 cmp r3, #1
8000750: d102 bne.n 8000758 <Display_SetOrientation+0x14>
NormalDisplayParam = 0x00;
8000752: 2300 movs r3, #0
8000754: 73fb strb r3, [r7, #15]
8000756: e025 b.n 80007a4 <Display_SetOrientation+0x60>
} else if( orientation == LCD_ORIENTATION_LANDSCAPE_ROT180 ) {
8000758: 687b ldr r3, [r7, #4]
800075a: 2b02 cmp r3, #2
800075c: d120 bne.n 80007a0 <Display_SetOrientation+0x5c>
// Vertical Scrolling Definition
Display_WriteCommand(0x33);
800075e: 2033 movs r0, #51 @ 0x33
8000760: f7ff ff44 bl 80005ec <Display_WriteCommand>
// TFA describes the Top Fixed Area
Display_WriteData(0x00);
8000764: 2000 movs r0, #0
8000766: f7ff ff54 bl 8000612 <Display_WriteData>
Display_WriteData(0x00);
800076a: 2000 movs r0, #0
800076c: f7ff ff51 bl 8000612 <Display_WriteData>
// VSA describes the height of the Vertical Scrolling Area
Display_WriteData(0x01);
8000770: 2001 movs r0, #1
8000772: f7ff ff4e bl 8000612 <Display_WriteData>
Display_WriteData(0xf0);
8000776: 20f0 movs r0, #240 @ 0xf0
8000778: f7ff ff4b bl 8000612 <Display_WriteData>
// BFA describes the Bottom Fixed Area
Display_WriteData(0x00);
800077c: 2000 movs r0, #0
800077e: f7ff ff48 bl 8000612 <Display_WriteData>
Display_WriteData(0x00);
8000782: 2000 movs r0, #0
8000784: f7ff ff45 bl 8000612 <Display_WriteData>
// Vertical Scroll Start Address of RAM:
// GRAM row nbr (320) - Display row nbr (240) = 80 = 0x50
Display_WriteCommand(0x37);
8000788: 2037 movs r0, #55 @ 0x37
800078a: f7ff ff2f bl 80005ec <Display_WriteCommand>
Display_WriteData(0x00);
800078e: 2000 movs r0, #0
8000790: f7ff ff3f bl 8000612 <Display_WriteData>
Display_WriteData(0x50);
8000794: 2050 movs r0, #80 @ 0x50
8000796: f7ff ff3c bl 8000612 <Display_WriteData>
NormalDisplayParam = 0xC0;
800079a: 23c0 movs r3, #192 @ 0xc0
800079c: 73fb strb r3, [r7, #15]
800079e: e001 b.n 80007a4 <Display_SetOrientation+0x60>
} else {
NormalDisplayParam = 0x60;
80007a0: 2360 movs r3, #96 @ 0x60
80007a2: 73fb strb r3, [r7, #15]
}
Display_WriteCommand(0x36);
80007a4: 2036 movs r0, #54 @ 0x36
80007a6: f7ff ff21 bl 80005ec <Display_WriteCommand>
Display_WriteData(NormalDisplayParam);
80007aa: 7bfb ldrb r3, [r7, #15]
80007ac: b29b uxth r3, r3
80007ae: 4618 mov r0, r3
80007b0: f7ff ff2f bl 8000612 <Display_WriteData>
}
80007b4: bf00 nop
80007b6: 3710 adds r7, #16
80007b8: 46bd mov sp, r7
80007ba: bd80 pop {r7, pc}
080007bc <Display_SetWindow_>:
Display_WriteData( y+1 );
Display_WriteCommand( 0x2c );
}
static void Display_SetWindow_( uint16_t x, uint16_t y, uint16_t Width, uint16_t Height ) {
80007bc: b590 push {r4, r7, lr}
80007be: b083 sub sp, #12
80007c0: af00 add r7, sp, #0
80007c2: 4604 mov r4, r0
80007c4: 4608 mov r0, r1
80007c6: 4611 mov r1, r2
80007c8: 461a mov r2, r3
80007ca: 4623 mov r3, r4
80007cc: 80fb strh r3, [r7, #6]
80007ce: 4603 mov r3, r0
80007d0: 80bb strh r3, [r7, #4]
80007d2: 460b mov r3, r1
80007d4: 807b strh r3, [r7, #2]
80007d6: 4613 mov r3, r2
80007d8: 803b strh r3, [r7, #0]
DISPLAY_LIMIT( x, 0, DISPLAY_WIDTH-1 );
80007da: 88fb ldrh r3, [r7, #6]
80007dc: 2bef cmp r3, #239 @ 0xef
80007de: d901 bls.n 80007e4 <Display_SetWindow_+0x28>
80007e0: 23ef movs r3, #239 @ 0xef
80007e2: 80fb strh r3, [r7, #6]
DISPLAY_LIMIT( y, 0, DISPLAY_HEIGHT-1 );
80007e4: 88bb ldrh r3, [r7, #4]
80007e6: 2bef cmp r3, #239 @ 0xef
80007e8: d901 bls.n 80007ee <Display_SetWindow_+0x32>
80007ea: 23ef movs r3, #239 @ 0xef
80007ec: 80bb strh r3, [r7, #4]
Display_WriteCommand( 0x2a );
80007ee: 202a movs r0, #42 @ 0x2a
80007f0: f7ff fefc bl 80005ec <Display_WriteCommand>
Display_WriteData( 0 );
80007f4: 2000 movs r0, #0
80007f6: f7ff ff0c bl 8000612 <Display_WriteData>
Display_WriteData( x );
80007fa: 88fb ldrh r3, [r7, #6]
80007fc: 4618 mov r0, r3
80007fe: f7ff ff08 bl 8000612 <Display_WriteData>
Display_WriteData( 0 );
8000802: 2000 movs r0, #0
8000804: f7ff ff05 bl 8000612 <Display_WriteData>
Display_WriteData( x+Width );
8000808: 88fa ldrh r2, [r7, #6]
800080a: 887b ldrh r3, [r7, #2]
800080c: 4413 add r3, r2
800080e: b29b uxth r3, r3
8000810: 4618 mov r0, r3
8000812: f7ff fefe bl 8000612 <Display_WriteData>
Display_WriteCommand( 0x2b );
8000816: 202b movs r0, #43 @ 0x2b
8000818: f7ff fee8 bl 80005ec <Display_WriteCommand>
Display_WriteData( 0 );
800081c: 2000 movs r0, #0
800081e: f7ff fef8 bl 8000612 <Display_WriteData>
Display_WriteData( y );
8000822: 88bb ldrh r3, [r7, #4]
8000824: 4618 mov r0, r3
8000826: f7ff fef4 bl 8000612 <Display_WriteData>
Display_WriteData( 0 );
800082a: 2000 movs r0, #0
800082c: f7ff fef1 bl 8000612 <Display_WriteData>
Display_WriteData( y+Height );
8000830: 88ba ldrh r2, [r7, #4]
8000832: 883b ldrh r3, [r7, #0]
8000834: 4413 add r3, r2
8000836: b29b uxth r3, r3
8000838: 4618 mov r0, r3
800083a: f7ff feea bl 8000612 <Display_WriteData>
Display_WriteCommand( 0x2c );
800083e: 202c movs r0, #44 @ 0x2c
8000840: f7ff fed4 bl 80005ec <Display_WriteCommand>
}
8000844: bf00 nop
8000846: 370c adds r7, #12
8000848: 46bd mov sp, r7
800084a: bd90 pop {r4, r7, pc}
0800084c <Display_DrawHLine_>:
static void Display_DrawHLine_( uint16_t x, uint16_t y, uint16_t Length, uint16_t Color ) {
800084c: b590 push {r4, r7, lr}
800084e: b085 sub sp, #20
8000850: af00 add r7, sp, #0
8000852: 4604 mov r4, r0
8000854: 4608 mov r0, r1
8000856: 4611 mov r1, r2
8000858: 461a mov r2, r3
800085a: 4623 mov r3, r4
800085c: 80fb strh r3, [r7, #6]
800085e: 4603 mov r3, r0
8000860: 80bb strh r3, [r7, #4]
8000862: 460b mov r3, r1
8000864: 807b strh r3, [r7, #2]
8000866: 4613 mov r3, r2
8000868: 803b strh r3, [r7, #0]
uint16_t counter = 0;
800086a: 2300 movs r3, #0
800086c: 81fb strh r3, [r7, #14]
Display_SetWindow_( x, y, DISPLAY_WIDTH-1, 0 );
800086e: 88b9 ldrh r1, [r7, #4]
8000870: 88f8 ldrh r0, [r7, #6]
8000872: 2300 movs r3, #0
8000874: 22ef movs r2, #239 @ 0xef
8000876: f7ff ffa1 bl 80007bc <Display_SetWindow_>
for(counter = 0; counter < Length; counter++) {
800087a: 2300 movs r3, #0
800087c: 81fb strh r3, [r7, #14]
800087e: e006 b.n 800088e <Display_DrawHLine_+0x42>
Display_WriteData( Color );
8000880: 883b ldrh r3, [r7, #0]
8000882: 4618 mov r0, r3
8000884: f7ff fec5 bl 8000612 <Display_WriteData>
for(counter = 0; counter < Length; counter++) {
8000888: 89fb ldrh r3, [r7, #14]
800088a: 3301 adds r3, #1
800088c: 81fb strh r3, [r7, #14]
800088e: 89fa ldrh r2, [r7, #14]
8000890: 887b ldrh r3, [r7, #2]
8000892: 429a cmp r2, r3
8000894: d3f4 bcc.n 8000880 <Display_DrawHLine_+0x34>
}
}
8000896: bf00 nop
8000898: bf00 nop
800089a: 3714 adds r7, #20
800089c: 46bd mov sp, r7
800089e: bd90 pop {r4, r7, pc}
080008a0 <Display_GetHeight>:
for(counter = 0; counter < Length; counter++) {
Display_WriteData( Color );
}
}
uint16_t Display_GetHeight( void ) {
80008a0: b480 push {r7}
80008a2: af00 add r7, sp, #0
return DISPLAY_HEIGHT;
80008a4: 23f0 movs r3, #240 @ 0xf0
}
80008a6: 4618 mov r0, r3
80008a8: 46bd mov sp, r7
80008aa: f85d 7b04 ldr.w r7, [sp], #4
80008ae: 4770 bx lr
080008b0 <Display_GetWidth>:
uint16_t Display_GetWidth( void ) {
80008b0: b480 push {r7}
80008b2: af00 add r7, sp, #0
return DISPLAY_WIDTH;
80008b4: 23f0 movs r3, #240 @ 0xf0
}
80008b6: 4618 mov r0, r3
80008b8: 46bd mov sp, r7
80008ba: f85d 7b04 ldr.w r7, [sp], #4
80008be: 4770 bx lr
080008c0 <Display_Clear_>:
x += xinc2; // Change the x as appropriate
y += yinc2; // Change the y as appropriate
}
}
static void Display_Clear_( uint16_t Color ) {
80008c0: b580 push {r7, lr}
80008c2: b084 sub sp, #16
80008c4: af00 add r7, sp, #0
80008c6: 4603 mov r3, r0
80008c8: 80fb strh r3, [r7, #6]
uint16_t y = 0;
80008ca: 2300 movs r3, #0
80008cc: 81fb strh r3, [r7, #14]
uint16_t Height = 0;
80008ce: 2300 movs r3, #0
80008d0: 81bb strh r3, [r7, #12]
uint16_t Width = Display_GetWidth();
80008d2: f7ff ffed bl 80008b0 <Display_GetWidth>
80008d6: 4603 mov r3, r0
80008d8: 817b strh r3, [r7, #10]
Height = Display_GetHeight();
80008da: f7ff ffe1 bl 80008a0 <Display_GetHeight>
80008de: 4603 mov r3, r0
80008e0: 81bb strh r3, [r7, #12]
for( y = 0; y < Height ; y ++ ) {
80008e2: 2300 movs r3, #0
80008e4: 81fb strh r3, [r7, #14]
80008e6: e008 b.n 80008fa <Display_Clear_+0x3a>
Display_DrawHLine_( 0, y, Width, Color );
80008e8: 88fb ldrh r3, [r7, #6]
80008ea: 897a ldrh r2, [r7, #10]
80008ec: 89f9 ldrh r1, [r7, #14]
80008ee: 2000 movs r0, #0
80008f0: f7ff ffac bl 800084c <Display_DrawHLine_>
for( y = 0; y < Height ; y ++ ) {
80008f4: 89fb ldrh r3, [r7, #14]
80008f6: 3301 adds r3, #1
80008f8: 81fb strh r3, [r7, #14]
80008fa: 89fa ldrh r2, [r7, #14]
80008fc: 89bb ldrh r3, [r7, #12]
80008fe: 429a cmp r2, r3
8000900: d3f2 bcc.n 80008e8 <Display_Clear_+0x28>
}
}
8000902: bf00 nop
8000904: bf00 nop
8000906: 3710 adds r7, #16
8000908: 46bd mov sp, r7
800090a: bd80 pop {r7, pc}
0800090c <Display_Init>:
Points[i].x += 100;
}
Display_FillPolygon( Points, 4, LCD_COLOR_LIGHTBLUE );
}
void Display_Init( void ) {
800090c: b580 push {r7, lr}
800090e: b082 sub sp, #8
8000910: af00 add r7, sp, #0
// Backlight control signal assertion:
HAL_GPIO_WritePin(GPIOH, GPIO_PIN_11, GPIO_PIN_SET);
8000912: 2201 movs r2, #1
8000914: f44f 6100 mov.w r1, #2048 @ 0x800
8000918: 481c ldr r0, [pc, #112] @ (800098c <Display_Init+0x80>)
800091a: f001 fe7d bl 8002618 <HAL_GPIO_WritePin>
// Apply hardware reset according to procedure indicated in FRD154BP2901 documentation:
HAL_GPIO_WritePin(LCD_RST_GPIO_Port, LCD_RST_Pin, GPIO_PIN_RESET);
800091e: 2200 movs r2, #0
8000920: 2180 movs r1, #128 @ 0x80
8000922: 481a ldr r0, [pc, #104] @ (800098c <Display_Init+0x80>)
8000924: f001 fe78 bl 8002618 <HAL_GPIO_WritePin>
HAL_Delay(5);
8000928: 2005 movs r0, #5
800092a: f001 fbbb bl 80020a4 <HAL_Delay>
HAL_GPIO_WritePin(LCD_RST_GPIO_Port, LCD_RST_Pin, GPIO_PIN_SET);
800092e: 2201 movs r2, #1
8000930: 2180 movs r1, #128 @ 0x80
8000932: 4816 ldr r0, [pc, #88] @ (800098c <Display_Init+0x80>)
8000934: f001 fe70 bl 8002618 <HAL_GPIO_WritePin>
HAL_Delay(10);
8000938: 200a movs r0, #10
800093a: f001 fbb3 bl 80020a4 <HAL_Delay>
HAL_GPIO_WritePin(LCD_RST_GPIO_Port, LCD_RST_Pin, GPIO_PIN_RESET);
800093e: 2200 movs r2, #0
8000940: 2180 movs r1, #128 @ 0x80
8000942: 4812 ldr r0, [pc, #72] @ (800098c <Display_Init+0x80>)
8000944: f001 fe68 bl 8002618 <HAL_GPIO_WritePin>
HAL_Delay(20);
8000948: 2014 movs r0, #20
800094a: f001 fbab bl 80020a4 <HAL_Delay>
HAL_GPIO_WritePin(LCD_RST_GPIO_Port, LCD_RST_Pin, GPIO_PIN_SET);
800094e: 2201 movs r2, #1
8000950: 2180 movs r1, #128 @ 0x80
8000952: 480e ldr r0, [pc, #56] @ (800098c <Display_Init+0x80>)
8000954: f001 fe60 bl 8002618 <HAL_GPIO_WritePin>
HAL_Delay(10);
8000958: 200a movs r0, #10
800095a: f001 fba3 bl 80020a4 <HAL_Delay>
Display_InitFmc();
800095e: f7ff fecb bl 80006f8 <Display_InitFmc>
uint8_t DisplayId = Display_ReadReg(0x04);
8000962: 2004 movs r0, #4
8000964: f7ff fe72 bl 800064c <Display_ReadReg>
8000968: 4603 mov r3, r0
800096a: 71fb strb r3, [r7, #7]
if( DisplayId == 0x85 ) {
800096c: 79fb ldrb r3, [r7, #7]
800096e: 2b85 cmp r3, #133 @ 0x85
8000970: d108 bne.n 8000984 <Display_Init+0x78>
Display_WriteCommandList( InitCmd );
8000972: 4807 ldr r0, [pc, #28] @ (8000990 <Display_Init+0x84>)
8000974: f7ff fe7d bl 8000672 <Display_WriteCommandList>
Display_SetOrientation( LCD_ORIENTATION_LANDSCAPE_ROT180 );
8000978: 2002 movs r0, #2
800097a: f7ff fee3 bl 8000744 <Display_SetOrientation>
Display_Clear_( LCD_COLOR_BLACK ); // Use variant without select/deselect to ignore OS and Mutex here!
800097e: 2000 movs r0, #0
8000980: f7ff ff9e bl 80008c0 <Display_Clear_>
}
/* ToDo: Create Mutex */
}
8000984: bf00 nop
8000986: 3708 adds r7, #8
8000988: 46bd mov sp, r7
800098a: bd80 pop {r7, pc}
800098c: 40021c00 .word 0x40021c00
8000990: 080089c4 .word 0x080089c4
08000994 <configureTimerForRunTimeStats>:
unsigned long getRunTimeCounterValue(void);
/* USER CODE BEGIN 1 */
/* Functions needed when configGENERATE_RUN_TIME_STATS is on */
#include "usage.h"
void configureTimerForRunTimeStats(void) { }
8000994: b480 push {r7}
8000996: af00 add r7, sp, #0
8000998: bf00 nop
800099a: 46bd mov sp, r7
800099c: f85d 7b04 ldr.w r7, [sp], #4
80009a0: 4770 bx lr
080009a2 <getRunTimeCounterValue>:
unsigned long getRunTimeCounterValue(void)
{
80009a2: b580 push {r7, lr}
80009a4: af00 add r7, sp, #0
return Usage_GetTicks();
80009a6: f001 f99b bl 8001ce0 <Usage_GetTicks>
80009aa: 4603 mov r3, r0
}
80009ac: 4618 mov r0, r3
80009ae: bd80 pop {r7, pc}
080009b0 <vApplicationGetIdleTaskMemory>:
/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */
static StaticTask_t xIdleTaskTCBBuffer;
static StackType_t xIdleStack[configMINIMAL_STACK_SIZE];
void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
{
80009b0: b480 push {r7}
80009b2: b085 sub sp, #20
80009b4: af00 add r7, sp, #0
80009b6: 60f8 str r0, [r7, #12]
80009b8: 60b9 str r1, [r7, #8]
80009ba: 607a str r2, [r7, #4]
*ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer;
80009bc: 68fb ldr r3, [r7, #12]
80009be: 4a07 ldr r2, [pc, #28] @ (80009dc <vApplicationGetIdleTaskMemory+0x2c>)
80009c0: 601a str r2, [r3, #0]
*ppxIdleTaskStackBuffer = &xIdleStack[0];
80009c2: 68bb ldr r3, [r7, #8]
80009c4: 4a06 ldr r2, [pc, #24] @ (80009e0 <vApplicationGetIdleTaskMemory+0x30>)
80009c6: 601a str r2, [r3, #0]
*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
80009c8: 687b ldr r3, [r7, #4]
80009ca: f44f 7280 mov.w r2, #256 @ 0x100
80009ce: 601a str r2, [r3, #0]
/* place for user code */
}
80009d0: bf00 nop
80009d2: 3714 adds r7, #20
80009d4: 46bd mov sp, r7
80009d6: f85d 7b04 ldr.w r7, [sp], #4
80009da: 4770 bx lr
80009dc: 20000088 .word 0x20000088
80009e0: 20000134 .word 0x20000134
080009e4 <_write>:
int _write( int file, char *ptr, int len );
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
int _write( int file, char *ptr, int len ){
80009e4: b580 push {r7, lr}
80009e6: b084 sub sp, #16
80009e8: af00 add r7, sp, #0
80009ea: 60f8 str r0, [r7, #12]
80009ec: 60b9 str r1, [r7, #8]
80009ee: 607a str r2, [r7, #4]
HAL_UART_Transmit(&huart6, (uint8_t*)ptr, len, 1000);
80009f0: 687b ldr r3, [r7, #4]
80009f2: b29a uxth r2, r3
80009f4: f44f 737a mov.w r3, #1000 @ 0x3e8
80009f8: 68b9 ldr r1, [r7, #8]
80009fa: 4804 ldr r0, [pc, #16] @ (8000a0c <_write+0x28>)
80009fc: f003 fb3e bl 800407c <HAL_UART_Transmit>
return len;
8000a00: 687b ldr r3, [r7, #4]
}
8000a02: 4618 mov r0, r3
8000a04: 3710 adds r7, #16
8000a06: 46bd mov sp, r7
8000a08: bd80 pop {r7, pc}
8000a0a: bf00 nop
8000a0c: 20000588 .word 0x20000588
08000a10 <Task1_blinkGreenLed>:
//==========================
//==== Task definitions ====
//==========================
void Task1_blinkGreenLed(void *){
8000a10: b580 push {r7, lr}
8000a12: b082 sub sp, #8
8000a14: af00 add r7, sp, #0
8000a16: 6078 str r0, [r7, #4]
while(1){
HAL_GPIO_TogglePin(LED_GREEN_GPIO_PORT, LED_GREEN_GPIO_PIN);
8000a18: 2102 movs r1, #2
8000a1a: 4804 ldr r0, [pc, #16] @ (8000a2c <Task1_blinkGreenLed+0x1c>)
8000a1c: f001 fe15 bl 800264a <HAL_GPIO_TogglePin>
vTaskDelay(pdMS_TO_TICKS(200));
8000a20: 20c8 movs r0, #200 @ 0xc8
8000a22: f005 f925 bl 8005c70 <vTaskDelay>
HAL_GPIO_TogglePin(LED_GREEN_GPIO_PORT, LED_GREEN_GPIO_PIN);
8000a26: bf00 nop
8000a28: e7f6 b.n 8000a18 <Task1_blinkGreenLed+0x8>
8000a2a: bf00 nop
8000a2c: 40020400 .word 0x40020400
08000a30 <Task2_blinkBlueLed>:
//HAL_Delay(200);
}
}
void Task2_blinkBlueLed(void *){
8000a30: b580 push {r7, lr}
8000a32: b082 sub sp, #8
8000a34: af00 add r7, sp, #0
8000a36: 6078 str r0, [r7, #4]
while(1){
HAL_GPIO_TogglePin(LED_BLUE_GPIO_PORT, LED_BLUE_GPIO_PIN);
8000a38: 2120 movs r1, #32
8000a3a: 4804 ldr r0, [pc, #16] @ (8000a4c <Task2_blinkBlueLed+0x1c>)
8000a3c: f001 fe05 bl 800264a <HAL_GPIO_TogglePin>
vTaskDelay(pdMS_TO_TICKS(1500));
8000a40: f240 50dc movw r0, #1500 @ 0x5dc
8000a44: f005 f914 bl 8005c70 <vTaskDelay>
HAL_GPIO_TogglePin(LED_BLUE_GPIO_PORT, LED_BLUE_GPIO_PIN);
8000a48: bf00 nop
8000a4a: e7f5 b.n 8000a38 <Task2_blinkBlueLed+0x8>
8000a4c: 40020000 .word 0x40020000
08000a50 <Task3_4_blinkRedLed>:
}
}
SemaphoreHandle_t Mutex_redLed = NULL;
void Task3_4_blinkRedLed(void * param_uint32_blinkDelay){
8000a50: b580 push {r7, lr}
8000a52: b084 sub sp, #16
8000a54: af00 add r7, sp, #0
8000a56: 6078 str r0, [r7, #4]
uint32_t blinkDelayMs = (uint32_t)param_uint32_blinkDelay;
8000a58: 687b ldr r3, [r7, #4]
8000a5a: 60bb str r3, [r7, #8]
while(1){
xSemaphoreTake(Mutex_redLed, portMAX_DELAY);
8000a5c: 4b1e ldr r3, [pc, #120] @ (8000ad8 <Task3_4_blinkRedLed+0x88>)
8000a5e: 681b ldr r3, [r3, #0]
8000a60: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
8000a64: 4618 mov r0, r3
8000a66: f004 fcfd bl 8005464 <xQueueSemaphoreTake>
for (int i=0; i<2; i++){
8000a6a: 2300 movs r3, #0
8000a6c: 60fb str r3, [r7, #12]
8000a6e: e024 b.n 8000aba <Task3_4_blinkRedLed+0x6a>
HAL_GPIO_WritePin(LED_RED_GPIO_PORT, LED_RED_GPIO_PIN, GPIO_PIN_SET);
8000a70: 2201 movs r2, #1
8000a72: 2180 movs r1, #128 @ 0x80
8000a74: 4819 ldr r0, [pc, #100] @ (8000adc <Task3_4_blinkRedLed+0x8c>)
8000a76: f001 fdcf bl 8002618 <HAL_GPIO_WritePin>
vTaskDelay(pdMS_TO_TICKS(blinkDelayMs));
8000a7a: 68bb ldr r3, [r7, #8]
8000a7c: f44f 727a mov.w r2, #1000 @ 0x3e8
8000a80: fb02 f303 mul.w r3, r2, r3
8000a84: 4a16 ldr r2, [pc, #88] @ (8000ae0 <Task3_4_blinkRedLed+0x90>)
8000a86: fba2 2303 umull r2, r3, r2, r3
8000a8a: 099b lsrs r3, r3, #6
8000a8c: 4618 mov r0, r3
8000a8e: f005 f8ef bl 8005c70 <vTaskDelay>
HAL_GPIO_WritePin(LED_RED_GPIO_PORT, LED_RED_GPIO_PIN, GPIO_PIN_RESET);
8000a92: 2200 movs r2, #0
8000a94: 2180 movs r1, #128 @ 0x80
8000a96: 4811 ldr r0, [pc, #68] @ (8000adc <Task3_4_blinkRedLed+0x8c>)
8000a98: f001 fdbe bl 8002618 <HAL_GPIO_WritePin>
vTaskDelay(pdMS_TO_TICKS(blinkDelayMs));
8000a9c: 68bb ldr r3, [r7, #8]
8000a9e: f44f 727a mov.w r2, #1000 @ 0x3e8
8000aa2: fb02 f303 mul.w r3, r2, r3
8000aa6: 4a0e ldr r2, [pc, #56] @ (8000ae0 <Task3_4_blinkRedLed+0x90>)
8000aa8: fba2 2303 umull r2, r3, r2, r3
8000aac: 099b lsrs r3, r3, #6
8000aae: 4618 mov r0, r3
8000ab0: f005 f8de bl 8005c70 <vTaskDelay>
for (int i=0; i<2; i++){
8000ab4: 68fb ldr r3, [r7, #12]
8000ab6: 3301 adds r3, #1
8000ab8: 60fb str r3, [r7, #12]
8000aba: 68fb ldr r3, [r7, #12]
8000abc: 2b01 cmp r3, #1
8000abe: ddd7 ble.n 8000a70 <Task3_4_blinkRedLed+0x20>
}
xSemaphoreGive(Mutex_redLed);
8000ac0: 4b05 ldr r3, [pc, #20] @ (8000ad8 <Task3_4_blinkRedLed+0x88>)
8000ac2: 6818 ldr r0, [r3, #0]
8000ac4: 2300 movs r3, #0
8000ac6: 2200 movs r2, #0
8000ac8: 2100 movs r1, #0
8000aca: f004 fad9 bl 8005080 <xQueueGenericSend>
vTaskDelay(pdMS_TO_TICKS(75));
8000ace: 204b movs r0, #75 @ 0x4b
8000ad0: f005 f8ce bl 8005c70 <vTaskDelay>
xSemaphoreTake(Mutex_redLed, portMAX_DELAY);
8000ad4: e7c2 b.n 8000a5c <Task3_4_blinkRedLed+0xc>
8000ad6: bf00 nop
8000ad8: 20000660 .word 0x20000660
8000adc: 40020000 .word 0x40020000
8000ae0: 10624dd3 .word 0x10624dd3
08000ae4 <Task5_readButton>:
}
SemaphoreHandle_t Semphr_buttonPressEvent = NULL;
QueueHandle_t Queue_buttonEvents;
void Task5_readButton(void *){
8000ae4: b580 push {r7, lr}
8000ae6: b084 sub sp, #16
8000ae8: af00 add r7, sp, #0
8000aea: 6078 str r0, [r7, #4]
bool buttonIsPressed, buttonIsPressedLast = false;
8000aec: 2300 movs r3, #0
8000aee: 73bb strb r3, [r7, #14]
while(1){
buttonIsPressedLast = buttonIsPressed;
8000af0: 7bfb ldrb r3, [r7, #15]
8000af2: 73bb strb r3, [r7, #14]
buttonIsPressed = HAL_GPIO_ReadPin(BUTTON_GPIO_PORT, BUTTON_GPIO_PIN) == GPIO_PIN_SET;
8000af4: 2101 movs r1, #1
8000af6: 481e ldr r0, [pc, #120] @ (8000b70 <Task5_readButton+0x8c>)
8000af8: f001 fd76 bl 80025e8 <HAL_GPIO_ReadPin>
8000afc: 4603 mov r3, r0
8000afe: 2b01 cmp r3, #1
8000b00: bf0c ite eq
8000b02: 2301 moveq r3, #1
8000b04: 2300 movne r3, #0
8000b06: 73fb strb r3, [r7, #15]
if (buttonIsPressed && !buttonIsPressedLast) { //rising edge, pressed event
8000b08: 7bfb ldrb r3, [r7, #15]
8000b0a: 2b00 cmp r3, #0
8000b0c: d018 beq.n 8000b40 <Task5_readButton+0x5c>
8000b0e: 7bbb ldrb r3, [r7, #14]
8000b10: f083 0301 eor.w r3, r3, #1
8000b14: b2db uxtb r3, r3
8000b16: 2b00 cmp r3, #0
8000b18: d012 beq.n 8000b40 <Task5_readButton+0x5c>
// free semaphore (notifies Task6)
xSemaphoreGive(Semphr_buttonPressEvent);
8000b1a: 4b16 ldr r3, [pc, #88] @ (8000b74 <Task5_readButton+0x90>)
8000b1c: 6818 ldr r0, [r3, #0]
8000b1e: 2300 movs r3, #0
8000b20: 2200 movs r2, #0
8000b22: 2100 movs r1, #0
8000b24: f004 faac bl 8005080 <xQueueGenericSend>
// send event to queue (used in Task7)
bool queueElement = true;
8000b28: 2301 movs r3, #1
8000b2a: 737b strb r3, [r7, #13]
xQueueSendToBack(Queue_buttonEvents, &queueElement, pdMS_TO_TICKS(1000));
8000b2c: 4b12 ldr r3, [pc, #72] @ (8000b78 <Task5_readButton+0x94>)
8000b2e: 6818 ldr r0, [r3, #0]
8000b30: f107 010d add.w r1, r7, #13
8000b34: 2300 movs r3, #0
8000b36: f44f 727a mov.w r2, #1000 @ 0x3e8
8000b3a: f004 faa1 bl 8005080 <xQueueGenericSend>
if (buttonIsPressed && !buttonIsPressedLast) { //rising edge, pressed event
8000b3e: e013 b.n 8000b68 <Task5_readButton+0x84>
}
else if (!buttonIsPressed && buttonIsPressedLast){ //falling edge, released event
8000b40: 7bfb ldrb r3, [r7, #15]
8000b42: f083 0301 eor.w r3, r3, #1
8000b46: b2db uxtb r3, r3
8000b48: 2b00 cmp r3, #0
8000b4a: d00d beq.n 8000b68 <Task5_readButton+0x84>
8000b4c: 7bbb ldrb r3, [r7, #14]
8000b4e: 2b00 cmp r3, #0
8000b50: d00a beq.n 8000b68 <Task5_readButton+0x84>
// send event to queue (used in Task7)
bool queueElement = false;
8000b52: 2300 movs r3, #0
8000b54: 733b strb r3, [r7, #12]
xQueueSendToBack(Queue_buttonEvents, &queueElement, pdMS_TO_TICKS(1000));
8000b56: 4b08 ldr r3, [pc, #32] @ (8000b78 <Task5_readButton+0x94>)
8000b58: 6818 ldr r0, [r3, #0]
8000b5a: f107 010c add.w r1, r7, #12
8000b5e: 2300 movs r3, #0
8000b60: f44f 727a mov.w r2, #1000 @ 0x3e8
8000b64: f004 fa8c bl 8005080 <xQueueGenericSend>
}
vTaskDelay(pdMS_TO_TICKS(25));
8000b68: 2019 movs r0, #25
8000b6a: f005 f881 bl 8005c70 <vTaskDelay>
buttonIsPressedLast = buttonIsPressed;
8000b6e: e7bf b.n 8000af0 <Task5_readButton+0xc>
8000b70: 40020000 .word 0x40020000
8000b74: 20000664 .word 0x20000664
8000b78: 20000668 .word 0x20000668
08000b7c <Task6_countButtonPresses>:
}
}
void Task6_countButtonPresses(void *){
8000b7c: b580 push {r7, lr}
8000b7e: b084 sub sp, #16
8000b80: af00 add r7, sp, #0
8000b82: 6078 str r0, [r7, #4]
uint16_t y = 0;
8000b84: 2300 movs r3, #0
8000b86: 81fb strh r3, [r7, #14]
while(1){
if (xSemaphoreTake(Semphr_buttonPressEvent, pdMS_TO_TICKS(1000))){
8000b88: 4b0c ldr r3, [pc, #48] @ (8000bbc <Task6_countButtonPresses+0x40>)
8000b8a: 681b ldr r3, [r3, #0]
8000b8c: f44f 717a mov.w r1, #1000 @ 0x3e8
8000b90: 4618 mov r0, r3
8000b92: f004 fc67 bl 8005464 <xQueueSemaphoreTake>
8000b96: 4603 mov r3, r0
8000b98: 2b00 cmp r3, #0
8000b9a: d00a beq.n 8000bb2 <Task6_countButtonPresses+0x36>
y++;
8000b9c: 89fb ldrh r3, [r7, #14]
8000b9e: 3301 adds r3, #1
8000ba0: 81fb strh r3, [r7, #14]
printf("Task6: received Semaphore, current count = %d", y);
8000ba2: 89fb ldrh r3, [r7, #14]
8000ba4: 4619 mov r1, r3
8000ba6: 4806 ldr r0, [pc, #24] @ (8000bc0 <Task6_countButtonPresses+0x44>)
8000ba8: f006 ff60 bl 8007a6c <iprintf>
vTaskDelay(pdMS_TO_TICKS(5));
8000bac: 2005 movs r0, #5
8000bae: f005 f85f bl 8005c70 <vTaskDelay>
}
printf("### Task 6 Loop ###");
8000bb2: 4804 ldr r0, [pc, #16] @ (8000bc4 <Task6_countButtonPresses+0x48>)
8000bb4: f006 ff5a bl 8007a6c <iprintf>
while(1){
8000bb8: e7e6 b.n 8000b88 <Task6_countButtonPresses+0xc>
8000bba: bf00 nop
8000bbc: 20000664 .word 0x20000664
8000bc0: 08008834 .word 0x08008834
8000bc4: 08008864 .word 0x08008864
08000bc8 <Task7_receiveQueueEvents>:
}
}
void Task7_receiveQueueEvents(void *){
8000bc8: b580 push {r7, lr}
8000bca: b084 sub sp, #16
8000bcc: af00 add r7, sp, #0
8000bce: 6078 str r0, [r7, #4]
bool receivedEvent;
while(1){
if (xQueueReceive(Queue_buttonEvents, &receivedEvent, portMAX_DELAY)){
8000bd0: 4b0c ldr r3, [pc, #48] @ (8000c04 <Task7_receiveQueueEvents+0x3c>)
8000bd2: 681b ldr r3, [r3, #0]
8000bd4: f107 010f add.w r1, r7, #15
8000bd8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8000bdc: 4618 mov r0, r3
8000bde: f004 fb59 bl 8005294 <xQueueReceive>
8000be2: 4603 mov r3, r0
8000be4: 2b00 cmp r3, #0
8000be6: d009 beq.n 8000bfc <Task7_receiveQueueEvents+0x34>
printf("Task 7: %s", receivedEvent ? "pressed" : "released");
8000be8: 7bfb ldrb r3, [r7, #15]
8000bea: 2b00 cmp r3, #0
8000bec: d001 beq.n 8000bf2 <Task7_receiveQueueEvents+0x2a>
8000bee: 4b06 ldr r3, [pc, #24] @ (8000c08 <Task7_receiveQueueEvents+0x40>)
8000bf0: e000 b.n 8000bf4 <Task7_receiveQueueEvents+0x2c>
8000bf2: 4b06 ldr r3, [pc, #24] @ (8000c0c <Task7_receiveQueueEvents+0x44>)
8000bf4: 4619 mov r1, r3
8000bf6: 4806 ldr r0, [pc, #24] @ (8000c10 <Task7_receiveQueueEvents+0x48>)
8000bf8: f006 ff38 bl 8007a6c <iprintf>
}
vTaskDelay(pdMS_TO_TICKS(10));
8000bfc: 200a movs r0, #10
8000bfe: f005 f837 bl 8005c70 <vTaskDelay>
if (xQueueReceive(Queue_buttonEvents, &receivedEvent, portMAX_DELAY)){
8000c02: e7e5 b.n 8000bd0 <Task7_receiveQueueEvents+0x8>
8000c04: 20000668 .word 0x20000668
8000c08: 08008878 .word 0x08008878
8000c0c: 08008880 .word 0x08008880
8000c10: 0800888c .word 0x0800888c
08000c14 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000c14: b5b0 push {r4, r5, r7, lr}
8000c16: b090 sub sp, #64 @ 0x40
8000c18: af02 add r7, sp, #8
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000c1a: f001 fa16 bl 800204a <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000c1e: f000 f8c5 bl 8000dac <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000c22: f000 fa05 bl 8001030 <MX_GPIO_Init>
MX_USART6_UART_Init();
8000c26: f000 f971 bl 8000f0c <MX_USART6_UART_Init>
MX_FMC_Init();
8000c2a: f000 f99f bl 8000f6c <MX_FMC_Init>
MX_I2C3_Init();
8000c2e: f000 f92d bl 8000e8c <MX_I2C3_Init>
/* USER CODE BEGIN 2 */
Usage_Init();
8000c32: f001 f9c7 bl 8001fc4 <Usage_Init>
Display_Init();
8000c36: f7ff fe69 bl 800090c <Display_Init>
// local variables
uint32_t timestamp_lastCounted = HAL_GetTick();
8000c3a: f001 fa27 bl 800208c <HAL_GetTick>
8000c3e: 6378 str r0, [r7, #52] @ 0x34
uint32_t timestamp_lastTouchRead = HAL_GetTick();
8000c40: f001 fa24 bl 800208c <HAL_GetTick>
8000c44: 6338 str r0, [r7, #48] @ 0x30
uint8_t i = 100;
8000c46: 2364 movs r3, #100 @ 0x64
8000c48: f887 302f strb.w r3, [r7, #47] @ 0x2f
uint8_t DataRx[4];
uint8_t Eventflag = TOUCH_EVENT_NOT_PRESSED, EventflagLast = TOUCH_EVENT_NOT_PRESSED;
8000c4c: 2304 movs r3, #4
8000c4e: f887 302e strb.w r3, [r7, #46] @ 0x2e
8000c52: 2304 movs r3, #4
8000c54: f887 302d strb.w r3, [r7, #45] @ 0x2d
/* USER CODE END 2 */
/* USER CODE BEGIN RTOS_MUTEX */
/* add mutexes, ... */
Mutex_redLed = xSemaphoreCreateMutex();
8000c58: 2001 movs r0, #1
8000c5a: f004 f9f9 bl 8005050 <xQueueCreateMutex>
8000c5e: 4603 mov r3, r0
8000c60: 4a40 ldr r2, [pc, #256] @ (8000d64 <main+0x150>)
8000c62: 6013 str r3, [r2, #0]
/* USER CODE END RTOS_MUTEX */
/* USER CODE BEGIN RTOS_SEMAPHORES */
/* add semaphores, ... */
Semphr_buttonPressEvent = xSemaphoreCreateBinary();
8000c64: 2203 movs r2, #3
8000c66: 2100 movs r1, #0
8000c68: 2001 movs r0, #1
8000c6a: f004 f971 bl 8004f50 <xQueueGenericCreate>
8000c6e: 4603 mov r3, r0
8000c70: 4a3d ldr r2, [pc, #244] @ (8000d68 <main+0x154>)
8000c72: 6013 str r3, [r2, #0]
/* start timers, add new ones, ... */
/* USER CODE END RTOS_TIMERS */
/* USER CODE BEGIN RTOS_QUEUES */
/* add queues, ... */
Queue_buttonEvents = xQueueCreate(10, sizeof(bool));
8000c74: 2200 movs r2, #0
8000c76: 2101 movs r1, #1
8000c78: 200a movs r0, #10
8000c7a: f004 f969 bl 8004f50 <xQueueGenericCreate>
8000c7e: 4603 mov r3, r0
8000c80: 4a3a ldr r2, [pc, #232] @ (8000d6c <main+0x158>)
8000c82: 6013 str r3, [r2, #0]
/* USER CODE END RTOS_QUEUES */
/* Create the thread(s) */
/* definition and creation of defaultTask */
osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 256);
8000c84: 4b3a ldr r3, [pc, #232] @ (8000d70 <main+0x15c>)
8000c86: f107 040c add.w r4, r7, #12
8000c8a: 461d mov r5, r3
8000c8c: cd0f ldmia r5!, {r0, r1, r2, r3}
8000c8e: c40f stmia r4!, {r0, r1, r2, r3}
8000c90: e895 0007 ldmia.w r5, {r0, r1, r2}
8000c94: e884 0007 stmia.w r4, {r0, r1, r2}
defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
8000c98: f107 030c add.w r3, r7, #12
8000c9c: 2100 movs r1, #0
8000c9e: 4618 mov r0, r3
8000ca0: f003 ffd5 bl 8004c4e <osThreadCreate>
8000ca4: 4603 mov r3, r0
8000ca6: 4a33 ldr r2, [pc, #204] @ (8000d74 <main+0x160>)
8000ca8: 6013 str r3, [r2, #0]
xTaskCreate(Task1_blinkGreenLed, "Task1_green-led", 256, NULL, 0, NULL);
8000caa: 2300 movs r3, #0
8000cac: 9301 str r3, [sp, #4]
8000cae: 2300 movs r3, #0
8000cb0: 9300 str r3, [sp, #0]
8000cb2: 2300 movs r3, #0
8000cb4: f44f 7280 mov.w r2, #256 @ 0x100
8000cb8: 492f ldr r1, [pc, #188] @ (8000d78 <main+0x164>)
8000cba: 4830 ldr r0, [pc, #192] @ (8000d7c <main+0x168>)
8000cbc: f004 fe78 bl 80059b0 <xTaskCreate>
xTaskCreate(Task2_blinkBlueLed, "Task2_blue-led", 256, NULL, 0, NULL);
8000cc0: 2300 movs r3, #0
8000cc2: 9301 str r3, [sp, #4]
8000cc4: 2300 movs r3, #0
8000cc6: 9300 str r3, [sp, #0]
8000cc8: 2300 movs r3, #0
8000cca: f44f 7280 mov.w r2, #256 @ 0x100
8000cce: 492c ldr r1, [pc, #176] @ (8000d80 <main+0x16c>)
8000cd0: 482c ldr r0, [pc, #176] @ (8000d84 <main+0x170>)
8000cd2: f004 fe6d bl 80059b0 <xTaskCreate>
uint32_t delay1 = 150;
8000cd6: 2396 movs r3, #150 @ 0x96
8000cd8: 60bb str r3, [r7, #8]
xTaskCreate(Task3_4_blinkRedLed, "Task3_red-led-150", 256, (void *)&delay1, 0, NULL);
8000cda: f107 0308 add.w r3, r7, #8
8000cde: 2200 movs r2, #0
8000ce0: 9201 str r2, [sp, #4]
8000ce2: 2200 movs r2, #0
8000ce4: 9200 str r2, [sp, #0]
8000ce6: f44f 7280 mov.w r2, #256 @ 0x100
8000cea: 4927 ldr r1, [pc, #156] @ (8000d88 <main+0x174>)
8000cec: 4827 ldr r0, [pc, #156] @ (8000d8c <main+0x178>)
8000cee: f004 fe5f bl 80059b0 <xTaskCreate>
uint32_t delay2 = 600;
8000cf2: f44f 7316 mov.w r3, #600 @ 0x258
8000cf6: 607b str r3, [r7, #4]
xTaskCreate(Task3_4_blinkRedLed, "Task4_red-led-600", 256, (void *)&delay2, 0, NULL);
8000cf8: 1d3b adds r3, r7, #4
8000cfa: 2200 movs r2, #0
8000cfc: 9201 str r2, [sp, #4]
8000cfe: 2200 movs r2, #0
8000d00: 9200 str r2, [sp, #0]
8000d02: f44f 7280 mov.w r2, #256 @ 0x100
8000d06: 4922 ldr r1, [pc, #136] @ (8000d90 <main+0x17c>)
8000d08: 4820 ldr r0, [pc, #128] @ (8000d8c <main+0x178>)
8000d0a: f004 fe51 bl 80059b0 <xTaskCreate>
xTaskCreate(Task5_readButton, "Task5_read-button", 256, NULL, 0, NULL);
8000d0e: 2300 movs r3, #0
8000d10: 9301 str r3, [sp, #4]
8000d12: 2300 movs r3, #0
8000d14: 9300 str r3, [sp, #0]
8000d16: 2300 movs r3, #0
8000d18: f44f 7280 mov.w r2, #256 @ 0x100
8000d1c: 491d ldr r1, [pc, #116] @ (8000d94 <main+0x180>)
8000d1e: 481e ldr r0, [pc, #120] @ (8000d98 <main+0x184>)
8000d20: f004 fe46 bl 80059b0 <xTaskCreate>
xTaskCreate(Task6_countButtonPresses, "Task6_countButtonPresses", 256, NULL, 0, NULL);
8000d24: 2300 movs r3, #0
8000d26: 9301 str r3, [sp, #4]
8000d28: 2300 movs r3, #0
8000d2a: 9300 str r3, [sp, #0]
8000d2c: 2300 movs r3, #0
8000d2e: f44f 7280 mov.w r2, #256 @ 0x100
8000d32: 491a ldr r1, [pc, #104] @ (8000d9c <main+0x188>)
8000d34: 481a ldr r0, [pc, #104] @ (8000da0 <main+0x18c>)
8000d36: f004 fe3b bl 80059b0 <xTaskCreate>
xTaskCreate(Task7_receiveQueueEvents, "Task7_receiveQueueEvents", 256, NULL, 0, NULL);
8000d3a: 2300 movs r3, #0
8000d3c: 9301 str r3, [sp, #4]
8000d3e: 2300 movs r3, #0
8000d40: 9300 str r3, [sp, #0]
8000d42: 2300 movs r3, #0
8000d44: f44f 7280 mov.w r2, #256 @ 0x100
8000d48: 4916 ldr r1, [pc, #88] @ (8000da4 <main+0x190>)
8000d4a: 4817 ldr r0, [pc, #92] @ (8000da8 <main+0x194>)
8000d4c: f004 fe30 bl 80059b0 <xTaskCreate>
/* USER CODE BEGIN RTOS_THREADS */
/* add threads, ... */
/* USER CODE END RTOS_THREADS */
/* Start scheduler */
osKernelStart();
8000d50: f003 ff76 bl 8004c40 <osKernelStart>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
// print processor statistics
Usage_PrintStats();
8000d54: f001 f81e bl 8001d94 <Usage_PrintStats>
vTaskDelay(pdMS_TO_TICKS(1000));
8000d58: f44f 707a mov.w r0, #1000 @ 0x3e8
8000d5c: f004 ff88 bl 8005c70 <vTaskDelay>
Usage_PrintStats();
8000d60: bf00 nop
8000d62: e7f7 b.n 8000d54 <main+0x140>
8000d64: 20000660 .word 0x20000660
8000d68: 20000664 .word 0x20000664
8000d6c: 20000668 .word 0x20000668
8000d70: 08008938 .word 0x08008938
8000d74: 2000065c .word 0x2000065c
8000d78: 08008898 .word 0x08008898
8000d7c: 08000a11 .word 0x08000a11
8000d80: 080088a8 .word 0x080088a8
8000d84: 08000a31 .word 0x08000a31
8000d88: 080088b8 .word 0x080088b8
8000d8c: 08000a51 .word 0x08000a51
8000d90: 080088cc .word 0x080088cc
8000d94: 080088e0 .word 0x080088e0
8000d98: 08000ae5 .word 0x08000ae5
8000d9c: 080088f4 .word 0x080088f4
8000da0: 08000b7d .word 0x08000b7d
8000da4: 08008910 .word 0x08008910
8000da8: 08000bc9 .word 0x08000bc9
08000dac <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000dac: b580 push {r7, lr}
8000dae: b094 sub sp, #80 @ 0x50
8000db0: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000db2: f107 0320 add.w r3, r7, #32
8000db6: 2230 movs r2, #48 @ 0x30
8000db8: 2100 movs r1, #0
8000dba: 4618 mov r0, r3
8000dbc: f006 feab bl 8007b16 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000dc0: f107 030c add.w r3, r7, #12
8000dc4: 2200 movs r2, #0
8000dc6: 601a str r2, [r3, #0]
8000dc8: 605a str r2, [r3, #4]
8000dca: 609a str r2, [r3, #8]
8000dcc: 60da str r2, [r3, #12]
8000dce: 611a str r2, [r3, #16]
/** Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess();
8000dd0: f001 fd8a bl 80028e8 <HAL_PWR_EnableBkUpAccess>
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
8000dd4: 4b2b ldr r3, [pc, #172] @ (8000e84 <SystemClock_Config+0xd8>)
8000dd6: 6c1b ldr r3, [r3, #64] @ 0x40
8000dd8: 4a2a ldr r2, [pc, #168] @ (8000e84 <SystemClock_Config+0xd8>)
8000dda: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000dde: 6413 str r3, [r2, #64] @ 0x40
8000de0: 4b28 ldr r3, [pc, #160] @ (8000e84 <SystemClock_Config+0xd8>)
8000de2: 6c1b ldr r3, [r3, #64] @ 0x40
8000de4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000de8: 60bb str r3, [r7, #8]
8000dea: 68bb ldr r3, [r7, #8]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8000dec: 4b26 ldr r3, [pc, #152] @ (8000e88 <SystemClock_Config+0xdc>)
8000dee: 681b ldr r3, [r3, #0]
8000df0: 4a25 ldr r2, [pc, #148] @ (8000e88 <SystemClock_Config+0xdc>)
8000df2: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8000df6: 6013 str r3, [r2, #0]
8000df8: 4b23 ldr r3, [pc, #140] @ (8000e88 <SystemClock_Config+0xdc>)
8000dfa: 681b ldr r3, [r3, #0]
8000dfc: f403 4340 and.w r3, r3, #49152 @ 0xc000
8000e00: 607b str r3, [r7, #4]
8000e02: 687b ldr r3, [r7, #4]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8000e04: 2301 movs r3, #1
8000e06: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
8000e08: f44f 3380 mov.w r3, #65536 @ 0x10000
8000e0c: 627b str r3, [r7, #36] @ 0x24
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000e0e: 2302 movs r3, #2
8000e10: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
8000e12: f44f 0380 mov.w r3, #4194304 @ 0x400000
8000e16: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.PLL.PLLM = 25;
8000e18: 2319 movs r3, #25
8000e1a: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.PLL.PLLN = 432;
8000e1c: f44f 73d8 mov.w r3, #432 @ 0x1b0
8000e20: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8000e22: 2302 movs r3, #2
8000e24: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLQ = 9;
8000e26: 2309 movs r3, #9
8000e28: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000e2a: f107 0320 add.w r3, r7, #32
8000e2e: 4618 mov r0, r3
8000e30: f001 fdba bl 80029a8 <HAL_RCC_OscConfig>
8000e34: 4603 mov r3, r0
8000e36: 2b00 cmp r3, #0
8000e38: d001 beq.n 8000e3e <SystemClock_Config+0x92>
{
Error_Handler();
8000e3a: f000 fc7d bl 8001738 <Error_Handler>
}
/** Activate the Over-Drive mode
*/
if (HAL_PWREx_EnableOverDrive() != HAL_OK)
8000e3e: f001 fd63 bl 8002908 <HAL_PWREx_EnableOverDrive>
8000e42: 4603 mov r3, r0
8000e44: 2b00 cmp r3, #0
8000e46: d001 beq.n 8000e4c <SystemClock_Config+0xa0>
{
Error_Handler();
8000e48: f000 fc76 bl 8001738 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000e4c: 230f movs r3, #15
8000e4e: 60fb str r3, [r7, #12]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000e50: 2302 movs r3, #2
8000e52: 613b str r3, [r7, #16]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000e54: 2300 movs r3, #0
8000e56: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
8000e58: f44f 53a0 mov.w r3, #5120 @ 0x1400
8000e5c: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
8000e5e: f44f 5380 mov.w r3, #4096 @ 0x1000
8000e62: 61fb str r3, [r7, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
8000e64: f107 030c add.w r3, r7, #12
8000e68: 2107 movs r1, #7
8000e6a: 4618 mov r0, r3
8000e6c: f002 f840 bl 8002ef0 <HAL_RCC_ClockConfig>
8000e70: 4603 mov r3, r0
8000e72: 2b00 cmp r3, #0
8000e74: d001 beq.n 8000e7a <SystemClock_Config+0xce>
{
Error_Handler();
8000e76: f000 fc5f bl 8001738 <Error_Handler>
}
}
8000e7a: bf00 nop
8000e7c: 3750 adds r7, #80 @ 0x50
8000e7e: 46bd mov sp, r7
8000e80: bd80 pop {r7, pc}
8000e82: bf00 nop
8000e84: 40023800 .word 0x40023800
8000e88: 40007000 .word 0x40007000
08000e8c <MX_I2C3_Init>:
* @brief I2C3 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C3_Init(void)
{
8000e8c: b580 push {r7, lr}
8000e8e: af00 add r7, sp, #0
/* USER CODE END I2C3_Init 0 */
/* USER CODE BEGIN I2C3_Init 1 */
/* USER CODE END I2C3_Init 1 */
hi2c3.Instance = I2C3;
8000e90: 4b1b ldr r3, [pc, #108] @ (8000f00 <MX_I2C3_Init+0x74>)
8000e92: 4a1c ldr r2, [pc, #112] @ (8000f04 <MX_I2C3_Init+0x78>)
8000e94: 601a str r2, [r3, #0]
hi2c3.Init.Timing = 0x6000030D;
8000e96: 4b1a ldr r3, [pc, #104] @ (8000f00 <MX_I2C3_Init+0x74>)
8000e98: 4a1b ldr r2, [pc, #108] @ (8000f08 <MX_I2C3_Init+0x7c>)
8000e9a: 605a str r2, [r3, #4]
hi2c3.Init.OwnAddress1 = 0;
8000e9c: 4b18 ldr r3, [pc, #96] @ (8000f00 <MX_I2C3_Init+0x74>)
8000e9e: 2200 movs r2, #0
8000ea0: 609a str r2, [r3, #8]
hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
8000ea2: 4b17 ldr r3, [pc, #92] @ (8000f00 <MX_I2C3_Init+0x74>)
8000ea4: 2201 movs r2, #1
8000ea6: 60da str r2, [r3, #12]
hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
8000ea8: 4b15 ldr r3, [pc, #84] @ (8000f00 <MX_I2C3_Init+0x74>)
8000eaa: 2200 movs r2, #0
8000eac: 611a str r2, [r3, #16]
hi2c3.Init.OwnAddress2 = 0;
8000eae: 4b14 ldr r3, [pc, #80] @ (8000f00 <MX_I2C3_Init+0x74>)
8000eb0: 2200 movs r2, #0
8000eb2: 615a str r2, [r3, #20]
hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
8000eb4: 4b12 ldr r3, [pc, #72] @ (8000f00 <MX_I2C3_Init+0x74>)
8000eb6: 2200 movs r2, #0
8000eb8: 619a str r2, [r3, #24]
hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8000eba: 4b11 ldr r3, [pc, #68] @ (8000f00 <MX_I2C3_Init+0x74>)
8000ebc: 2200 movs r2, #0
8000ebe: 61da str r2, [r3, #28]
hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
8000ec0: 4b0f ldr r3, [pc, #60] @ (8000f00 <MX_I2C3_Init+0x74>)
8000ec2: 2200 movs r2, #0
8000ec4: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c3) != HAL_OK)
8000ec6: 480e ldr r0, [pc, #56] @ (8000f00 <MX_I2C3_Init+0x74>)
8000ec8: f001 fbda bl 8002680 <HAL_I2C_Init>
8000ecc: 4603 mov r3, r0
8000ece: 2b00 cmp r3, #0
8000ed0: d001 beq.n 8000ed6 <MX_I2C3_Init+0x4a>
{
Error_Handler();
8000ed2: f000 fc31 bl 8001738 <Error_Handler>
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
8000ed6: 2100 movs r1, #0
8000ed8: 4809 ldr r0, [pc, #36] @ (8000f00 <MX_I2C3_Init+0x74>)
8000eda: f001 fc6d bl 80027b8 <HAL_I2CEx_ConfigAnalogFilter>
8000ede: 4603 mov r3, r0
8000ee0: 2b00 cmp r3, #0
8000ee2: d001 beq.n 8000ee8 <MX_I2C3_Init+0x5c>
{
Error_Handler();
8000ee4: f000 fc28 bl 8001738 <Error_Handler>
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK)
8000ee8: 2100 movs r1, #0
8000eea: 4805 ldr r0, [pc, #20] @ (8000f00 <MX_I2C3_Init+0x74>)
8000eec: f001 fcaf bl 800284e <HAL_I2CEx_ConfigDigitalFilter>
8000ef0: 4603 mov r3, r0
8000ef2: 2b00 cmp r3, #0
8000ef4: d001 beq.n 8000efa <MX_I2C3_Init+0x6e>
{
Error_Handler();
8000ef6: f000 fc1f bl 8001738 <Error_Handler>
}
/* USER CODE BEGIN I2C3_Init 2 */
/* USER CODE END I2C3_Init 2 */
}
8000efa: bf00 nop
8000efc: bd80 pop {r7, pc}
8000efe: bf00 nop
8000f00: 20000534 .word 0x20000534
8000f04: 40005c00 .word 0x40005c00
8000f08: 6000030d .word 0x6000030d
08000f0c <MX_USART6_UART_Init>:
* @brief USART6 Initialization Function
* @param None
* @retval None
*/
static void MX_USART6_UART_Init(void)
{
8000f0c: b580 push {r7, lr}
8000f0e: af00 add r7, sp, #0
/* USER CODE END USART6_Init 0 */
/* USER CODE BEGIN USART6_Init 1 */
/* USER CODE END USART6_Init 1 */
huart6.Instance = USART6;
8000f10: 4b14 ldr r3, [pc, #80] @ (8000f64 <MX_USART6_UART_Init+0x58>)
8000f12: 4a15 ldr r2, [pc, #84] @ (8000f68 <MX_USART6_UART_Init+0x5c>)
8000f14: 601a str r2, [r3, #0]
huart6.Init.BaudRate = 115200;
8000f16: 4b13 ldr r3, [pc, #76] @ (8000f64 <MX_USART6_UART_Init+0x58>)
8000f18: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8000f1c: 605a str r2, [r3, #4]
huart6.Init.WordLength = UART_WORDLENGTH_8B;
8000f1e: 4b11 ldr r3, [pc, #68] @ (8000f64 <MX_USART6_UART_Init+0x58>)
8000f20: 2200 movs r2, #0
8000f22: 609a str r2, [r3, #8]
huart6.Init.StopBits = UART_STOPBITS_1;
8000f24: 4b0f ldr r3, [pc, #60] @ (8000f64 <MX_USART6_UART_Init+0x58>)
8000f26: 2200 movs r2, #0
8000f28: 60da str r2, [r3, #12]
huart6.Init.Parity = UART_PARITY_NONE;
8000f2a: 4b0e ldr r3, [pc, #56] @ (8000f64 <MX_USART6_UART_Init+0x58>)
8000f2c: 2200 movs r2, #0
8000f2e: 611a str r2, [r3, #16]
huart6.Init.Mode = UART_MODE_TX_RX;
8000f30: 4b0c ldr r3, [pc, #48] @ (8000f64 <MX_USART6_UART_Init+0x58>)
8000f32: 220c movs r2, #12
8000f34: 615a str r2, [r3, #20]
huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000f36: 4b0b ldr r3, [pc, #44] @ (8000f64 <MX_USART6_UART_Init+0x58>)
8000f38: 2200 movs r2, #0
8000f3a: 619a str r2, [r3, #24]
huart6.Init.OverSampling = UART_OVERSAMPLING_16;
8000f3c: 4b09 ldr r3, [pc, #36] @ (8000f64 <MX_USART6_UART_Init+0x58>)
8000f3e: 2200 movs r2, #0
8000f40: 61da str r2, [r3, #28]
huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
8000f42: 4b08 ldr r3, [pc, #32] @ (8000f64 <MX_USART6_UART_Init+0x58>)
8000f44: 2200 movs r2, #0
8000f46: 621a str r2, [r3, #32]
huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8000f48: 4b06 ldr r3, [pc, #24] @ (8000f64 <MX_USART6_UART_Init+0x58>)
8000f4a: 2200 movs r2, #0
8000f4c: 625a str r2, [r3, #36] @ 0x24
if (HAL_UART_Init(&huart6) != HAL_OK)
8000f4e: 4805 ldr r0, [pc, #20] @ (8000f64 <MX_USART6_UART_Init+0x58>)
8000f50: f003 f846 bl 8003fe0 <HAL_UART_Init>
8000f54: 4603 mov r3, r0
8000f56: 2b00 cmp r3, #0
8000f58: d001 beq.n 8000f5e <MX_USART6_UART_Init+0x52>
{
Error_Handler();
8000f5a: f000 fbed bl 8001738 <Error_Handler>
}
/* USER CODE BEGIN USART6_Init 2 */
/* USER CODE END USART6_Init 2 */
}
8000f5e: bf00 nop
8000f60: bd80 pop {r7, pc}
8000f62: bf00 nop
8000f64: 20000588 .word 0x20000588
8000f68: 40011400 .word 0x40011400
08000f6c <MX_FMC_Init>:
/* FMC initialization function */
static void MX_FMC_Init(void)
{
8000f6c: b580 push {r7, lr}
8000f6e: b088 sub sp, #32
8000f70: af00 add r7, sp, #0
/* USER CODE BEGIN FMC_Init 0 */
/* USER CODE END FMC_Init 0 */
FMC_NORSRAM_TimingTypeDef Timing = {0};
8000f72: 1d3b adds r3, r7, #4
8000f74: 2200 movs r2, #0
8000f76: 601a str r2, [r3, #0]
8000f78: 605a str r2, [r3, #4]
8000f7a: 609a str r2, [r3, #8]
8000f7c: 60da str r2, [r3, #12]
8000f7e: 611a str r2, [r3, #16]
8000f80: 615a str r2, [r3, #20]
8000f82: 619a str r2, [r3, #24]
/* USER CODE END FMC_Init 1 */
/** Perform the SRAM2 memory initialization sequence
*/
hsram2.Instance = FMC_NORSRAM_DEVICE;
8000f84: 4b28 ldr r3, [pc, #160] @ (8001028 <MX_FMC_Init+0xbc>)
8000f86: f04f 4220 mov.w r2, #2684354560 @ 0xa0000000
8000f8a: 601a str r2, [r3, #0]
hsram2.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
8000f8c: 4b26 ldr r3, [pc, #152] @ (8001028 <MX_FMC_Init+0xbc>)
8000f8e: 4a27 ldr r2, [pc, #156] @ (800102c <MX_FMC_Init+0xc0>)
8000f90: 605a str r2, [r3, #4]
/* hsram2.Init */
hsram2.Init.NSBank = FMC_NORSRAM_BANK2;
8000f92: 4b25 ldr r3, [pc, #148] @ (8001028 <MX_FMC_Init+0xbc>)
8000f94: 2202 movs r2, #2
8000f96: 609a str r2, [r3, #8]
hsram2.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
8000f98: 4b23 ldr r3, [pc, #140] @ (8001028 <MX_FMC_Init+0xbc>)
8000f9a: 2200 movs r2, #0
8000f9c: 60da str r2, [r3, #12]
hsram2.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
8000f9e: 4b22 ldr r3, [pc, #136] @ (8001028 <MX_FMC_Init+0xbc>)
8000fa0: 2200 movs r2, #0
8000fa2: 611a str r2, [r3, #16]
hsram2.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
8000fa4: 4b20 ldr r3, [pc, #128] @ (8001028 <MX_FMC_Init+0xbc>)
8000fa6: 2210 movs r2, #16
8000fa8: 615a str r2, [r3, #20]
hsram2.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
8000faa: 4b1f ldr r3, [pc, #124] @ (8001028 <MX_FMC_Init+0xbc>)
8000fac: 2200 movs r2, #0
8000fae: 619a str r2, [r3, #24]
hsram2.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
8000fb0: 4b1d ldr r3, [pc, #116] @ (8001028 <MX_FMC_Init+0xbc>)
8000fb2: 2200 movs r2, #0
8000fb4: 61da str r2, [r3, #28]
hsram2.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
8000fb6: 4b1c ldr r3, [pc, #112] @ (8001028 <MX_FMC_Init+0xbc>)
8000fb8: 2200 movs r2, #0
8000fba: 621a str r2, [r3, #32]
hsram2.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
8000fbc: 4b1a ldr r3, [pc, #104] @ (8001028 <MX_FMC_Init+0xbc>)
8000fbe: f44f 5280 mov.w r2, #4096 @ 0x1000
8000fc2: 625a str r2, [r3, #36] @ 0x24
hsram2.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
8000fc4: 4b18 ldr r3, [pc, #96] @ (8001028 <MX_FMC_Init+0xbc>)
8000fc6: 2200 movs r2, #0
8000fc8: 629a str r2, [r3, #40] @ 0x28
hsram2.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
8000fca: 4b17 ldr r3, [pc, #92] @ (8001028 <MX_FMC_Init+0xbc>)
8000fcc: 2200 movs r2, #0
8000fce: 62da str r2, [r3, #44] @ 0x2c
hsram2.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
8000fd0: 4b15 ldr r3, [pc, #84] @ (8001028 <MX_FMC_Init+0xbc>)
8000fd2: 2200 movs r2, #0
8000fd4: 631a str r2, [r3, #48] @ 0x30
hsram2.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
8000fd6: 4b14 ldr r3, [pc, #80] @ (8001028 <MX_FMC_Init+0xbc>)
8000fd8: 2200 movs r2, #0
8000fda: 635a str r2, [r3, #52] @ 0x34
hsram2.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
8000fdc: 4b12 ldr r3, [pc, #72] @ (8001028 <MX_FMC_Init+0xbc>)
8000fde: 2200 movs r2, #0
8000fe0: 639a str r2, [r3, #56] @ 0x38
hsram2.Init.WriteFifo = FMC_WRITE_FIFO_ENABLE;
8000fe2: 4b11 ldr r3, [pc, #68] @ (8001028 <MX_FMC_Init+0xbc>)
8000fe4: 2200 movs r2, #0
8000fe6: 63da str r2, [r3, #60] @ 0x3c
hsram2.Init.PageSize = FMC_PAGE_SIZE_NONE;
8000fe8: 4b0f ldr r3, [pc, #60] @ (8001028 <MX_FMC_Init+0xbc>)
8000fea: 2200 movs r2, #0
8000fec: 641a str r2, [r3, #64] @ 0x40
/* Timing */
Timing.AddressSetupTime = 15;
8000fee: 230f movs r3, #15
8000ff0: 607b str r3, [r7, #4]
Timing.AddressHoldTime = 15;
8000ff2: 230f movs r3, #15
8000ff4: 60bb str r3, [r7, #8]
Timing.DataSetupTime = 255;
8000ff6: 23ff movs r3, #255 @ 0xff
8000ff8: 60fb str r3, [r7, #12]
Timing.BusTurnAroundDuration = 15;
8000ffa: 230f movs r3, #15
8000ffc: 613b str r3, [r7, #16]
Timing.CLKDivision = 16;
8000ffe: 2310 movs r3, #16
8001000: 617b str r3, [r7, #20]
Timing.DataLatency = 17;
8001002: 2311 movs r3, #17
8001004: 61bb str r3, [r7, #24]
Timing.AccessMode = FMC_ACCESS_MODE_A;
8001006: 2300 movs r3, #0
8001008: 61fb str r3, [r7, #28]
/* ExtTiming */
if (HAL_SRAM_Init(&hsram2, &Timing, NULL) != HAL_OK)
800100a: 1d3b adds r3, r7, #4
800100c: 2200 movs r2, #0
800100e: 4619 mov r1, r3
8001010: 4805 ldr r0, [pc, #20] @ (8001028 <MX_FMC_Init+0xbc>)
8001012: f002 fccf bl 80039b4 <HAL_SRAM_Init>
8001016: 4603 mov r3, r0
8001018: 2b00 cmp r3, #0
800101a: d001 beq.n 8001020 <MX_FMC_Init+0xb4>
{
Error_Handler( );
800101c: f000 fb8c bl 8001738 <Error_Handler>
}
/* USER CODE BEGIN FMC_Init 2 */
/* USER CODE END FMC_Init 2 */
}
8001020: bf00 nop
8001022: 3720 adds r7, #32
8001024: 46bd mov sp, r7
8001026: bd80 pop {r7, pc}
8001028: 20000610 .word 0x20000610
800102c: a0000104 .word 0xa0000104
08001030 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8001030: b580 push {r7, lr}
8001032: b08e sub sp, #56 @ 0x38
8001034: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001036: f107 0324 add.w r3, r7, #36 @ 0x24
800103a: 2200 movs r2, #0
800103c: 601a str r2, [r3, #0]
800103e: 605a str r2, [r3, #4]
8001040: 609a str r2, [r3, #8]
8001042: 60da str r2, [r3, #12]
8001044: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
8001046: 4bb3 ldr r3, [pc, #716] @ (8001314 <MX_GPIO_Init+0x2e4>)
8001048: 6b1b ldr r3, [r3, #48] @ 0x30
800104a: 4ab2 ldr r2, [pc, #712] @ (8001314 <MX_GPIO_Init+0x2e4>)
800104c: f043 0310 orr.w r3, r3, #16
8001050: 6313 str r3, [r2, #48] @ 0x30
8001052: 4bb0 ldr r3, [pc, #704] @ (8001314 <MX_GPIO_Init+0x2e4>)
8001054: 6b1b ldr r3, [r3, #48] @ 0x30
8001056: f003 0310 and.w r3, r3, #16
800105a: 623b str r3, [r7, #32]
800105c: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOB_CLK_ENABLE();
800105e: 4bad ldr r3, [pc, #692] @ (8001314 <MX_GPIO_Init+0x2e4>)
8001060: 6b1b ldr r3, [r3, #48] @ 0x30
8001062: 4aac ldr r2, [pc, #688] @ (8001314 <MX_GPIO_Init+0x2e4>)
8001064: f043 0302 orr.w r3, r3, #2
8001068: 6313 str r3, [r2, #48] @ 0x30
800106a: 4baa ldr r3, [pc, #680] @ (8001314 <MX_GPIO_Init+0x2e4>)
800106c: 6b1b ldr r3, [r3, #48] @ 0x30
800106e: f003 0302 and.w r3, r3, #2
8001072: 61fb str r3, [r7, #28]
8001074: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOG_CLK_ENABLE();
8001076: 4ba7 ldr r3, [pc, #668] @ (8001314 <MX_GPIO_Init+0x2e4>)
8001078: 6b1b ldr r3, [r3, #48] @ 0x30
800107a: 4aa6 ldr r2, [pc, #664] @ (8001314 <MX_GPIO_Init+0x2e4>)
800107c: f043 0340 orr.w r3, r3, #64 @ 0x40
8001080: 6313 str r3, [r2, #48] @ 0x30
8001082: 4ba4 ldr r3, [pc, #656] @ (8001314 <MX_GPIO_Init+0x2e4>)
8001084: 6b1b ldr r3, [r3, #48] @ 0x30
8001086: f003 0340 and.w r3, r3, #64 @ 0x40
800108a: 61bb str r3, [r7, #24]
800108c: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOD_CLK_ENABLE();
800108e: 4ba1 ldr r3, [pc, #644] @ (8001314 <MX_GPIO_Init+0x2e4>)
8001090: 6b1b ldr r3, [r3, #48] @ 0x30
8001092: 4aa0 ldr r2, [pc, #640] @ (8001314 <MX_GPIO_Init+0x2e4>)
8001094: f043 0308 orr.w r3, r3, #8
8001098: 6313 str r3, [r2, #48] @ 0x30
800109a: 4b9e ldr r3, [pc, #632] @ (8001314 <MX_GPIO_Init+0x2e4>)
800109c: 6b1b ldr r3, [r3, #48] @ 0x30
800109e: f003 0308 and.w r3, r3, #8
80010a2: 617b str r3, [r7, #20]
80010a4: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOC_CLK_ENABLE();
80010a6: 4b9b ldr r3, [pc, #620] @ (8001314 <MX_GPIO_Init+0x2e4>)
80010a8: 6b1b ldr r3, [r3, #48] @ 0x30
80010aa: 4a9a ldr r2, [pc, #616] @ (8001314 <MX_GPIO_Init+0x2e4>)
80010ac: f043 0304 orr.w r3, r3, #4
80010b0: 6313 str r3, [r2, #48] @ 0x30
80010b2: 4b98 ldr r3, [pc, #608] @ (8001314 <MX_GPIO_Init+0x2e4>)
80010b4: 6b1b ldr r3, [r3, #48] @ 0x30
80010b6: f003 0304 and.w r3, r3, #4
80010ba: 613b str r3, [r7, #16]
80010bc: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
80010be: 4b95 ldr r3, [pc, #596] @ (8001314 <MX_GPIO_Init+0x2e4>)
80010c0: 6b1b ldr r3, [r3, #48] @ 0x30
80010c2: 4a94 ldr r2, [pc, #592] @ (8001314 <MX_GPIO_Init+0x2e4>)
80010c4: f043 0301 orr.w r3, r3, #1
80010c8: 6313 str r3, [r2, #48] @ 0x30
80010ca: 4b92 ldr r3, [pc, #584] @ (8001314 <MX_GPIO_Init+0x2e4>)
80010cc: 6b1b ldr r3, [r3, #48] @ 0x30
80010ce: f003 0301 and.w r3, r3, #1
80010d2: 60fb str r3, [r7, #12]
80010d4: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOI_CLK_ENABLE();
80010d6: 4b8f ldr r3, [pc, #572] @ (8001314 <MX_GPIO_Init+0x2e4>)
80010d8: 6b1b ldr r3, [r3, #48] @ 0x30
80010da: 4a8e ldr r2, [pc, #568] @ (8001314 <MX_GPIO_Init+0x2e4>)
80010dc: f443 7380 orr.w r3, r3, #256 @ 0x100
80010e0: 6313 str r3, [r2, #48] @ 0x30
80010e2: 4b8c ldr r3, [pc, #560] @ (8001314 <MX_GPIO_Init+0x2e4>)
80010e4: 6b1b ldr r3, [r3, #48] @ 0x30
80010e6: f403 7380 and.w r3, r3, #256 @ 0x100
80010ea: 60bb str r3, [r7, #8]
80010ec: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOH_CLK_ENABLE();
80010ee: 4b89 ldr r3, [pc, #548] @ (8001314 <MX_GPIO_Init+0x2e4>)
80010f0: 6b1b ldr r3, [r3, #48] @ 0x30
80010f2: 4a88 ldr r2, [pc, #544] @ (8001314 <MX_GPIO_Init+0x2e4>)
80010f4: f043 0380 orr.w r3, r3, #128 @ 0x80
80010f8: 6313 str r3, [r2, #48] @ 0x30
80010fa: 4b86 ldr r3, [pc, #536] @ (8001314 <MX_GPIO_Init+0x2e4>)
80010fc: 6b1b ldr r3, [r3, #48] @ 0x30
80010fe: f003 0380 and.w r3, r3, #128 @ 0x80
8001102: 607b str r3, [r7, #4]
8001104: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOF_CLK_ENABLE();
8001106: 4b83 ldr r3, [pc, #524] @ (8001314 <MX_GPIO_Init+0x2e4>)
8001108: 6b1b ldr r3, [r3, #48] @ 0x30
800110a: 4a82 ldr r2, [pc, #520] @ (8001314 <MX_GPIO_Init+0x2e4>)
800110c: f043 0320 orr.w r3, r3, #32
8001110: 6313 str r3, [r2, #48] @ 0x30
8001112: 4b80 ldr r3, [pc, #512] @ (8001314 <MX_GPIO_Init+0x2e4>)
8001114: 6b1b ldr r3, [r3, #48] @ 0x30
8001116: f003 0320 and.w r3, r3, #32
800111a: 603b str r3, [r7, #0]
800111c: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, ARD_D7_GPIO_Pin|ARD_D8_GPIO_Pin, GPIO_PIN_RESET);
800111e: 2200 movs r2, #0
8001120: 2118 movs r1, #24
8001122: 487d ldr r0, [pc, #500] @ (8001318 <MX_GPIO_Init+0x2e8>)
8001124: f001 fa78 bl 8002618 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOG, WIFI_RST_Pin|WIFI_GPIO_0_Pin|PMOD_GPIO_0_Pin|USB_OTGFS_PPWR_EN_Pin, GPIO_PIN_RESET);
8001128: 2200 movs r2, #0
800112a: f44f 41e2 mov.w r1, #28928 @ 0x7100
800112e: 487b ldr r0, [pc, #492] @ (800131c <MX_GPIO_Init+0x2ec>)
8001130: f001 fa72 bl 8002618 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, WIFI_GPIO_2_Pin|WIFI_CH_PD_Pin, GPIO_PIN_RESET);
8001134: 2200 movs r2, #0
8001136: 2148 movs r1, #72 @ 0x48
8001138: 4879 ldr r0, [pc, #484] @ (8001320 <MX_GPIO_Init+0x2f0>)
800113a: f001 fa6d bl 8002618 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, STMOD_UART4_RXD_s_Pin|ARD_D2_GPIO_Pin, GPIO_PIN_RESET);
800113e: 2200 movs r2, #0
8001140: f44f 6102 mov.w r1, #2080 @ 0x820
8001144: 4877 ldr r0, [pc, #476] @ (8001324 <MX_GPIO_Init+0x2f4>)
8001146: f001 fa67 bl 8002618 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOI, PMOD_SPI2_MOSI_Pin|PMOD_SPI2_MISO_Pin|GPIO_PIN_10, GPIO_PIN_RESET);
800114a: 2200 movs r2, #0
800114c: f240 410c movw r1, #1036 @ 0x40c
8001150: 4875 ldr r0, [pc, #468] @ (8001328 <MX_GPIO_Init+0x2f8>)
8001152: f001 fa61 bl 8002618 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOH, PMOD_SEL_0_Pin|CTP_RST_Pin, GPIO_PIN_SET);
8001156: 2201 movs r2, #1
8001158: f44f 4102 mov.w r1, #33280 @ 0x8200
800115c: 4873 ldr r0, [pc, #460] @ (800132c <MX_GPIO_Init+0x2fc>)
800115e: f001 fa5b bl 8002618 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, USB_OTG_FS_ID_Pin|GPIO_PIN_5|SYS_LD_USER1_Pin, GPIO_PIN_RESET);
8001162: 2200 movs r2, #0
8001164: f44f 6194 mov.w r1, #1184 @ 0x4a0
8001168: 4871 ldr r0, [pc, #452] @ (8001330 <MX_GPIO_Init+0x300>)
800116a: f001 fa55 bl 8002618 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOH, PMOD_GPIO_1_Pin|ARD_D4_GPIO_Pin|USB_OTGHS_PPWR_EN_Pin|LCD_RST_Pin, GPIO_PIN_RESET);
800116e: 2200 movs r2, #0
8001170: f241 018c movw r1, #4236 @ 0x108c
8001174: 486d ldr r0, [pc, #436] @ (800132c <MX_GPIO_Init+0x2fc>)
8001176: f001 fa4f bl 8002618 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, USB_OTG_HS_ID_Pin|SYS_LD_USER2_Pin, GPIO_PIN_RESET);
800117a: 2200 movs r2, #0
800117c: f241 0102 movw r1, #4098 @ 0x1002
8001180: 486c ldr r0, [pc, #432] @ (8001334 <MX_GPIO_Init+0x304>)
8001182: f001 fa49 bl 8002618 <HAL_GPIO_WritePin>
/*Configure GPIO pins : ARD_D7_GPIO_Pin ARD_D8_GPIO_Pin */
GPIO_InitStruct.Pin = ARD_D7_GPIO_Pin|ARD_D8_GPIO_Pin;
8001186: 2318 movs r3, #24
8001188: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800118a: 2301 movs r3, #1
800118c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800118e: 2300 movs r3, #0
8001190: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001192: 2300 movs r3, #0
8001194: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8001196: f107 0324 add.w r3, r7, #36 @ 0x24
800119a: 4619 mov r1, r3
800119c: 485e ldr r0, [pc, #376] @ (8001318 <MX_GPIO_Init+0x2e8>)
800119e: f001 f887 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : QSPI_D2_Pin */
GPIO_InitStruct.Pin = QSPI_D2_Pin;
80011a2: 2304 movs r3, #4
80011a4: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80011a6: 2302 movs r3, #2
80011a8: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80011aa: 2300 movs r3, #0
80011ac: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80011ae: 2303 movs r3, #3
80011b0: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
80011b2: 2309 movs r3, #9
80011b4: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(QSPI_D2_GPIO_Port, &GPIO_InitStruct);
80011b6: f107 0324 add.w r3, r7, #36 @ 0x24
80011ba: 4619 mov r1, r3
80011bc: 4856 ldr r0, [pc, #344] @ (8001318 <MX_GPIO_Init+0x2e8>)
80011be: f001 f877 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : SAI2_I2C1_SCL_Pin SAI2_I2C1_SDA_Pin */
GPIO_InitStruct.Pin = SAI2_I2C1_SCL_Pin|SAI2_I2C1_SDA_Pin;
80011c2: f44f 7340 mov.w r3, #768 @ 0x300
80011c6: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
80011c8: 2312 movs r3, #18
80011ca: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80011cc: 2300 movs r3, #0
80011ce: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80011d0: 2303 movs r3, #3
80011d2: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
80011d4: 2304 movs r3, #4
80011d6: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80011d8: f107 0324 add.w r3, r7, #36 @ 0x24
80011dc: 4619 mov r1, r3
80011de: 4855 ldr r0, [pc, #340] @ (8001334 <MX_GPIO_Init+0x304>)
80011e0: f001 f866 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D11_TIM3_CH2_SPI1_MOSI_Pin ARD_D12_SPI1_MISO_Pin */
GPIO_InitStruct.Pin = ARD_D11_TIM3_CH2_SPI1_MOSI_Pin|ARD_D12_SPI1_MISO_Pin;
80011e4: 2330 movs r3, #48 @ 0x30
80011e6: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80011e8: 2302 movs r3, #2
80011ea: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80011ec: 2300 movs r3, #0
80011ee: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80011f0: 2303 movs r3, #3
80011f2: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
80011f4: 2305 movs r3, #5
80011f6: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80011f8: f107 0324 add.w r3, r7, #36 @ 0x24
80011fc: 4619 mov r1, r3
80011fe: 484d ldr r0, [pc, #308] @ (8001334 <MX_GPIO_Init+0x304>)
8001200: f001 f856 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : WIFI_RST_Pin WIFI_GPIO_0_Pin PMOD_GPIO_0_Pin USB_OTGFS_PPWR_EN_Pin */
GPIO_InitStruct.Pin = WIFI_RST_Pin|WIFI_GPIO_0_Pin|PMOD_GPIO_0_Pin|USB_OTGFS_PPWR_EN_Pin;
8001204: f44f 43e2 mov.w r3, #28928 @ 0x7100
8001208: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800120a: 2301 movs r3, #1
800120c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800120e: 2300 movs r3, #0
8001210: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001212: 2300 movs r3, #0
8001214: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8001216: f107 0324 add.w r3, r7, #36 @ 0x24
800121a: 4619 mov r1, r3
800121c: 483f ldr r0, [pc, #252] @ (800131c <MX_GPIO_Init+0x2ec>)
800121e: f001 f847 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : UART_TXD_WIFI_RX_Pin */
GPIO_InitStruct.Pin = UART_TXD_WIFI_RX_Pin;
8001222: f44f 5380 mov.w r3, #4096 @ 0x1000
8001226: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001228: 2302 movs r3, #2
800122a: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800122c: 2300 movs r3, #0
800122e: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001230: 2303 movs r3, #3
8001232: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
8001234: 2308 movs r3, #8
8001236: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(UART_TXD_WIFI_RX_GPIO_Port, &GPIO_InitStruct);
8001238: f107 0324 add.w r3, r7, #36 @ 0x24
800123c: 4619 mov r1, r3
800123e: 4839 ldr r0, [pc, #228] @ (8001324 <MX_GPIO_Init+0x2f4>)
8001240: f001 f836 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : STMOD_TIM2_CH1_2_ETR_Pin ARD_D10_TIM2_CH2_SPI1_NSS_Pin */
GPIO_InitStruct.Pin = STMOD_TIM2_CH1_2_ETR_Pin|ARD_D10_TIM2_CH2_SPI1_NSS_Pin;
8001244: f248 0302 movw r3, #32770 @ 0x8002
8001248: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800124a: 2302 movs r3, #2
800124c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800124e: 2300 movs r3, #0
8001250: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001252: 2300 movs r3, #0
8001254: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
8001256: 2301 movs r3, #1
8001258: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800125a: f107 0324 add.w r3, r7, #36 @ 0x24
800125e: 4619 mov r1, r3
8001260: 4833 ldr r0, [pc, #204] @ (8001330 <MX_GPIO_Init+0x300>)
8001262: f001 f825 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D3_TIM9_CH1_Pin ARD_D6_TIM9_CH2_Pin */
GPIO_InitStruct.Pin = ARD_D3_TIM9_CH1_Pin|ARD_D6_TIM9_CH2_Pin;
8001266: 2360 movs r3, #96 @ 0x60
8001268: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800126a: 2302 movs r3, #2
800126c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800126e: 2300 movs r3, #0
8001270: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001272: 2300 movs r3, #0
8001274: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF3_TIM9;
8001276: 2303 movs r3, #3
8001278: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
800127a: f107 0324 add.w r3, r7, #36 @ 0x24
800127e: 4619 mov r1, r3
8001280: 4825 ldr r0, [pc, #148] @ (8001318 <MX_GPIO_Init+0x2e8>)
8001282: f001 f815 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : QSPI_NCS_Pin */
GPIO_InitStruct.Pin = QSPI_NCS_Pin;
8001286: 2340 movs r3, #64 @ 0x40
8001288: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800128a: 2302 movs r3, #2
800128c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800128e: 2300 movs r3, #0
8001290: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001292: 2303 movs r3, #3
8001294: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
8001296: 230a movs r3, #10
8001298: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(QSPI_NCS_GPIO_Port, &GPIO_InitStruct);
800129a: f107 0324 add.w r3, r7, #36 @ 0x24
800129e: 4619 mov r1, r3
80012a0: 4824 ldr r0, [pc, #144] @ (8001334 <MX_GPIO_Init+0x304>)
80012a2: f001 f805 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : SAI2_INT_Pin */
GPIO_InitStruct.Pin = SAI2_INT_Pin;
80012a6: f44f 4300 mov.w r3, #32768 @ 0x8000
80012aa: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
80012ac: f44f 1388 mov.w r3, #1114112 @ 0x110000
80012b0: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80012b2: 2300 movs r3, #0
80012b4: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(SAI2_INT_GPIO_Port, &GPIO_InitStruct);
80012b6: f107 0324 add.w r3, r7, #36 @ 0x24
80012ba: 4619 mov r1, r3
80012bc: 4817 ldr r0, [pc, #92] @ (800131c <MX_GPIO_Init+0x2ec>)
80012be: f000 fff7 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : SAI2_SD_B_Pin */
GPIO_InitStruct.Pin = SAI2_SD_B_Pin;
80012c2: f44f 6380 mov.w r3, #1024 @ 0x400
80012c6: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80012c8: 2302 movs r3, #2
80012ca: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80012cc: 2300 movs r3, #0
80012ce: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80012d0: 2300 movs r3, #0
80012d2: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF10_SAI2;
80012d4: 230a movs r3, #10
80012d6: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(SAI2_SD_B_GPIO_Port, &GPIO_InitStruct);
80012d8: f107 0324 add.w r3, r7, #36 @ 0x24
80012dc: 4619 mov r1, r3
80012de: 480f ldr r0, [pc, #60] @ (800131c <MX_GPIO_Init+0x2ec>)
80012e0: f000 ffe6 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : WIFI_GPIO_2_Pin WIFI_CH_PD_Pin */
GPIO_InitStruct.Pin = WIFI_GPIO_2_Pin|WIFI_CH_PD_Pin;
80012e4: 2348 movs r3, #72 @ 0x48
80012e6: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80012e8: 2301 movs r3, #1
80012ea: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80012ec: 2300 movs r3, #0
80012ee: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80012f0: 2300 movs r3, #0
80012f2: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
80012f4: f107 0324 add.w r3, r7, #36 @ 0x24
80012f8: 4619 mov r1, r3
80012fa: 4809 ldr r0, [pc, #36] @ (8001320 <MX_GPIO_Init+0x2f0>)
80012fc: f000 ffd8 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : STMOD_UART4_RXD_s_Pin ARD_D2_GPIO_Pin */
GPIO_InitStruct.Pin = STMOD_UART4_RXD_s_Pin|ARD_D2_GPIO_Pin;
8001300: f44f 6302 mov.w r3, #2080 @ 0x820
8001304: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001306: 2301 movs r3, #1
8001308: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800130a: 2300 movs r3, #0
800130c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800130e: 2300 movs r3, #0
8001310: e012 b.n 8001338 <MX_GPIO_Init+0x308>
8001312: bf00 nop
8001314: 40023800 .word 0x40023800
8001318: 40021000 .word 0x40021000
800131c: 40021800 .word 0x40021800
8001320: 40020c00 .word 0x40020c00
8001324: 40020800 .word 0x40020800
8001328: 40022000 .word 0x40022000
800132c: 40021c00 .word 0x40021c00
8001330: 40020000 .word 0x40020000
8001334: 40020400 .word 0x40020400
8001338: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
800133a: f107 0324 add.w r3, r7, #36 @ 0x24
800133e: 4619 mov r1, r3
8001340: 48bc ldr r0, [pc, #752] @ (8001634 <MX_GPIO_Init+0x604>)
8001342: f000 ffb5 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : QSPI_D1_Pin QSPI_D0_Pin */
GPIO_InitStruct.Pin = QSPI_D1_Pin|QSPI_D0_Pin;
8001346: f44f 63c0 mov.w r3, #1536 @ 0x600
800134a: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800134c: 2302 movs r3, #2
800134e: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001350: 2300 movs r3, #0
8001352: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001354: 2303 movs r3, #3
8001356: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
8001358: 2309 movs r3, #9
800135a: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
800135c: f107 0324 add.w r3, r7, #36 @ 0x24
8001360: 4619 mov r1, r3
8001362: 48b4 ldr r0, [pc, #720] @ (8001634 <MX_GPIO_Init+0x604>)
8001364: f000 ffa4 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : PA12 PA11 */
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11;
8001368: f44f 53c0 mov.w r3, #6144 @ 0x1800
800136c: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800136e: 2302 movs r3, #2
8001370: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001372: 2300 movs r3, #0
8001374: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001376: 2303 movs r3, #3
8001378: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
800137a: 230a movs r3, #10
800137c: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800137e: f107 0324 add.w r3, r7, #36 @ 0x24
8001382: 4619 mov r1, r3
8001384: 48ac ldr r0, [pc, #688] @ (8001638 <MX_GPIO_Init+0x608>)
8001386: f000 ff93 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : SAI2_FS_A_Pin SAI2_SD_A_Pin SAI2_SCK_A_Pin SAI2_MCLK_A_Pin */
GPIO_InitStruct.Pin = SAI2_FS_A_Pin|SAI2_SD_A_Pin|SAI2_SCK_A_Pin|SAI2_MCLK_A_Pin;
800138a: 23f0 movs r3, #240 @ 0xf0
800138c: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800138e: 2302 movs r3, #2
8001390: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001392: 2300 movs r3, #0
8001394: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001396: 2300 movs r3, #0
8001398: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF10_SAI2;
800139a: 230a movs r3, #10
800139c: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
800139e: f107 0324 add.w r3, r7, #36 @ 0x24
80013a2: 4619 mov r1, r3
80013a4: 48a5 ldr r0, [pc, #660] @ (800163c <MX_GPIO_Init+0x60c>)
80013a6: f000 ff83 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_SPI2_MOSI_Pin PMOD_SPI2_MISO_Pin PI10 */
GPIO_InitStruct.Pin = PMOD_SPI2_MOSI_Pin|PMOD_SPI2_MISO_Pin|GPIO_PIN_10;
80013aa: f240 430c movw r3, #1036 @ 0x40c
80013ae: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80013b0: 2301 movs r3, #1
80013b2: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80013b4: 2300 movs r3, #0
80013b6: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80013b8: 2300 movs r3, #0
80013ba: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
80013bc: f107 0324 add.w r3, r7, #36 @ 0x24
80013c0: 4619 mov r1, r3
80013c2: 489e ldr r0, [pc, #632] @ (800163c <MX_GPIO_Init+0x60c>)
80013c4: f000 ff74 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : CTP_INT_Pin */
GPIO_InitStruct.Pin = CTP_INT_Pin;
80013c8: f44f 7300 mov.w r3, #512 @ 0x200
80013cc: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
80013ce: f44f 1388 mov.w r3, #1114112 @ 0x110000
80013d2: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80013d4: 2300 movs r3, #0
80013d6: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(CTP_INT_GPIO_Port, &GPIO_InitStruct);
80013d8: f107 0324 add.w r3, r7, #36 @ 0x24
80013dc: 4619 mov r1, r3
80013de: 4897 ldr r0, [pc, #604] @ (800163c <MX_GPIO_Init+0x60c>)
80013e0: f000 ff66 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : UART_RXD_WIFI_TX_Pin */
GPIO_InitStruct.Pin = UART_RXD_WIFI_TX_Pin;
80013e4: 2304 movs r3, #4
80013e6: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80013e8: 2302 movs r3, #2
80013ea: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80013ec: 2300 movs r3, #0
80013ee: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80013f0: 2303 movs r3, #3
80013f2: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
80013f4: 2308 movs r3, #8
80013f6: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(UART_RXD_WIFI_TX_GPIO_Port, &GPIO_InitStruct);
80013f8: f107 0324 add.w r3, r7, #36 @ 0x24
80013fc: 4619 mov r1, r3
80013fe: 4890 ldr r0, [pc, #576] @ (8001640 <MX_GPIO_Init+0x610>)
8001400: f000 ff56 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_SEL_0_Pin PMOD_GPIO_1_Pin ARD_D4_GPIO_Pin USB_OTGHS_PPWR_EN_Pin
CTP_RST_Pin LCD_RST_Pin */
GPIO_InitStruct.Pin = PMOD_SEL_0_Pin|PMOD_GPIO_1_Pin|ARD_D4_GPIO_Pin|USB_OTGHS_PPWR_EN_Pin
8001404: f249 238c movw r3, #37516 @ 0x928c
8001408: 627b str r3, [r7, #36] @ 0x24
|CTP_RST_Pin|LCD_RST_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800140a: 2301 movs r3, #1
800140c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800140e: 2300 movs r3, #0
8001410: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001412: 2300 movs r3, #0
8001414: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8001416: f107 0324 add.w r3, r7, #36 @ 0x24
800141a: 4619 mov r1, r3
800141c: 4889 ldr r0, [pc, #548] @ (8001644 <MX_GPIO_Init+0x614>)
800141e: f000 ff47 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_SPI2_SCK_Pin PMOD_SPI2_NSS_Pin */
GPIO_InitStruct.Pin = PMOD_SPI2_SCK_Pin|PMOD_SPI2_NSS_Pin;
8001422: 2303 movs r3, #3
8001424: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001426: 2302 movs r3, #2
8001428: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800142a: 2300 movs r3, #0
800142c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800142e: 2303 movs r3, #3
8001430: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8001432: 2305 movs r3, #5
8001434: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8001436: f107 0324 add.w r3, r7, #36 @ 0x24
800143a: 4619 mov r1, r3
800143c: 487f ldr r0, [pc, #508] @ (800163c <MX_GPIO_Init+0x60c>)
800143e: f000 ff37 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : USB_OTG_FS_ID_Pin PA5 SYS_LD_USER1_Pin */
GPIO_InitStruct.Pin = USB_OTG_FS_ID_Pin|GPIO_PIN_5|SYS_LD_USER1_Pin;
8001442: f44f 6394 mov.w r3, #1184 @ 0x4a0
8001446: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001448: 2301 movs r3, #1
800144a: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800144c: 2300 movs r3, #0
800144e: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001450: 2300 movs r3, #0
8001452: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001454: f107 0324 add.w r3, r7, #36 @ 0x24
8001458: 4619 mov r1, r3
800145a: 4877 ldr r0, [pc, #476] @ (8001638 <MX_GPIO_Init+0x608>)
800145c: f000 ff28 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : STMOD_UART4_TXD_Pin STMOD_UART4_RXD_Pin */
GPIO_InitStruct.Pin = STMOD_UART4_TXD_Pin|STMOD_UART4_RXD_Pin;
8001460: f44f 43c0 mov.w r3, #24576 @ 0x6000
8001464: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001466: 2302 movs r3, #2
8001468: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800146a: 2300 movs r3, #0
800146c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800146e: 2303 movs r3, #3
8001470: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
8001472: 2308 movs r3, #8
8001474: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8001476: f107 0324 add.w r3, r7, #36 @ 0x24
800147a: 4619 mov r1, r3
800147c: 4871 ldr r0, [pc, #452] @ (8001644 <MX_GPIO_Init+0x614>)
800147e: f000 ff17 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : PA9 */
GPIO_InitStruct.Pin = GPIO_PIN_9;
8001482: f44f 7300 mov.w r3, #512 @ 0x200
8001486: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001488: 2300 movs r3, #0
800148a: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800148c: 2300 movs r3, #0
800148e: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001490: f107 0324 add.w r3, r7, #36 @ 0x24
8001494: 4619 mov r1, r3
8001496: 4868 ldr r0, [pc, #416] @ (8001638 <MX_GPIO_Init+0x608>)
8001498: f000 ff0a bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : LCD_TE_INT_Pin */
GPIO_InitStruct.Pin = LCD_TE_INT_Pin;
800149c: f44f 7380 mov.w r3, #256 @ 0x100
80014a0: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
80014a2: f44f 1388 mov.w r3, #1114112 @ 0x110000
80014a6: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80014a8: 2300 movs r3, #0
80014aa: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(LCD_TE_INT_GPIO_Port, &GPIO_InitStruct);
80014ac: f107 0324 add.w r3, r7, #36 @ 0x24
80014b0: 4619 mov r1, r3
80014b2: 4860 ldr r0, [pc, #384] @ (8001634 <MX_GPIO_Init+0x604>)
80014b4: f000 fefc bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D15_STMOD_I2C2_SCL_Pin ARD_D14_STMOD_I2C2_SDA_Pin */
GPIO_InitStruct.Pin = ARD_D15_STMOD_I2C2_SCL_Pin|ARD_D14_STMOD_I2C2_SDA_Pin;
80014b8: 2330 movs r3, #48 @ 0x30
80014ba: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
80014bc: 2312 movs r3, #18
80014be: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80014c0: 2300 movs r3, #0
80014c2: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80014c4: 2303 movs r3, #3
80014c6: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
80014c8: 2304 movs r3, #4
80014ca: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
80014cc: f107 0324 add.w r3, r7, #36 @ 0x24
80014d0: 4619 mov r1, r3
80014d2: 485c ldr r0, [pc, #368] @ (8001644 <MX_GPIO_Init+0x614>)
80014d4: f000 feec bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_UART7_TXD_Pin PMOD_UART7_RXD_Pin PMOD_UART7_CTS_Pin PMOD_UART7_RTS_Pin */
GPIO_InitStruct.Pin = PMOD_UART7_TXD_Pin|PMOD_UART7_RXD_Pin|PMOD_UART7_CTS_Pin|PMOD_UART7_RTS_Pin;
80014d8: f44f 7370 mov.w r3, #960 @ 0x3c0
80014dc: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80014de: 2302 movs r3, #2
80014e0: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80014e2: 2300 movs r3, #0
80014e4: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80014e6: 2303 movs r3, #3
80014e8: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART7;
80014ea: 2308 movs r3, #8
80014ec: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
80014ee: f107 0324 add.w r3, r7, #36 @ 0x24
80014f2: 4619 mov r1, r3
80014f4: 4854 ldr r0, [pc, #336] @ (8001648 <MX_GPIO_Init+0x618>)
80014f6: f000 fedb bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_A3_ADC3_IN8_Pin */
GPIO_InitStruct.Pin = ARD_A3_ADC3_IN8_Pin;
80014fa: f44f 6380 mov.w r3, #1024 @ 0x400
80014fe: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001500: 2303 movs r3, #3
8001502: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001504: 2300 movs r3, #0
8001506: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(ARD_A3_ADC3_IN8_GPIO_Port, &GPIO_InitStruct);
8001508: f107 0324 add.w r3, r7, #36 @ 0x24
800150c: 4619 mov r1, r3
800150e: 484e ldr r0, [pc, #312] @ (8001648 <MX_GPIO_Init+0x618>)
8001510: f000 fece bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : LCD_BL_Pin */
GPIO_InitStruct.Pin = LCD_BL_Pin;
8001514: f44f 6300 mov.w r3, #2048 @ 0x800
8001518: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800151a: 2302 movs r3, #2
800151c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800151e: 2300 movs r3, #0
8001520: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001522: 2300 movs r3, #0
8001524: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF2_TIM5;
8001526: 2302 movs r3, #2
8001528: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(LCD_BL_GPIO_Port, &GPIO_InitStruct);
800152a: f107 0324 add.w r3, r7, #36 @ 0x24
800152e: 4619 mov r1, r3
8001530: 4844 ldr r0, [pc, #272] @ (8001644 <MX_GPIO_Init+0x614>)
8001532: f000 febd bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : USB_OTGHS_OVCR_INT_Pin */
GPIO_InitStruct.Pin = USB_OTGHS_OVCR_INT_Pin;
8001536: f44f 6380 mov.w r3, #1024 @ 0x400
800153a: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800153c: 2300 movs r3, #0
800153e: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001540: 2300 movs r3, #0
8001542: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(USB_OTGHS_OVCR_INT_GPIO_Port, &GPIO_InitStruct);
8001544: f107 0324 add.w r3, r7, #36 @ 0x24
8001548: 4619 mov r1, r3
800154a: 483e ldr r0, [pc, #248] @ (8001644 <MX_GPIO_Init+0x614>)
800154c: f000 feb0 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_A4_Pin ARD_A5_Pin ARD_A2_Pin */
GPIO_InitStruct.Pin = ARD_A4_Pin|ARD_A5_Pin|ARD_A2_Pin;
8001550: 2313 movs r3, #19
8001552: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001554: 2303 movs r3, #3
8001556: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001558: 2300 movs r3, #0
800155a: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
800155c: f107 0324 add.w r3, r7, #36 @ 0x24
8001560: 4619 mov r1, r3
8001562: 4834 ldr r0, [pc, #208] @ (8001634 <MX_GPIO_Init+0x604>)
8001564: f000 fea4 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : STMOD_SPI2_MISOs_Pin STMOD_SPI2_MOSIs_Pin */
GPIO_InitStruct.Pin = STMOD_SPI2_MISOs_Pin|STMOD_SPI2_MOSIs_Pin;
8001568: 230c movs r3, #12
800156a: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800156c: 2302 movs r3, #2
800156e: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001570: 2300 movs r3, #0
8001572: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001574: 2303 movs r3, #3
8001576: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8001578: 2305 movs r3, #5
800157a: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
800157c: f107 0324 add.w r3, r7, #36 @ 0x24
8001580: 4619 mov r1, r3
8001582: 482c ldr r0, [pc, #176] @ (8001634 <MX_GPIO_Init+0x604>)
8001584: f000 fe94 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : QSPI_CLK_Pin */
GPIO_InitStruct.Pin = QSPI_CLK_Pin;
8001588: 2304 movs r3, #4
800158a: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800158c: 2302 movs r3, #2
800158e: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001590: 2300 movs r3, #0
8001592: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001594: 2303 movs r3, #3
8001596: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
8001598: 2309 movs r3, #9
800159a: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(QSPI_CLK_GPIO_Port, &GPIO_InitStruct);
800159c: f107 0324 add.w r3, r7, #36 @ 0x24
80015a0: 4619 mov r1, r3
80015a2: 482a ldr r0, [pc, #168] @ (800164c <MX_GPIO_Init+0x61c>)
80015a4: f000 fe84 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_D9_TIM12_CH1_Pin */
GPIO_InitStruct.Pin = ARD_D9_TIM12_CH1_Pin;
80015a8: 2340 movs r3, #64 @ 0x40
80015aa: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80015ac: 2302 movs r3, #2
80015ae: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80015b0: 2300 movs r3, #0
80015b2: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80015b4: 2300 movs r3, #0
80015b6: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_TIM12;
80015b8: 2309 movs r3, #9
80015ba: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(ARD_D9_TIM12_CH1_GPIO_Port, &GPIO_InitStruct);
80015bc: f107 0324 add.w r3, r7, #36 @ 0x24
80015c0: 4619 mov r1, r3
80015c2: 4820 ldr r0, [pc, #128] @ (8001644 <MX_GPIO_Init+0x614>)
80015c4: f000 fe74 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : QSPI_D3_Pin */
GPIO_InitStruct.Pin = QSPI_D3_Pin;
80015c8: f44f 5300 mov.w r3, #8192 @ 0x2000
80015cc: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80015ce: 2302 movs r3, #2
80015d0: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80015d2: 2300 movs r3, #0
80015d4: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80015d6: 2303 movs r3, #3
80015d8: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
80015da: 2309 movs r3, #9
80015dc: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(QSPI_D3_GPIO_Port, &GPIO_InitStruct);
80015de: f107 0324 add.w r3, r7, #36 @ 0x24
80015e2: 4619 mov r1, r3
80015e4: 4816 ldr r0, [pc, #88] @ (8001640 <MX_GPIO_Init+0x610>)
80015e6: f000 fe63 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : PA0 */
GPIO_InitStruct.Pin = GPIO_PIN_0;
80015ea: 2301 movs r3, #1
80015ec: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80015ee: 2300 movs r3, #0
80015f0: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80015f2: 2300 movs r3, #0
80015f4: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80015f6: f107 0324 add.w r3, r7, #36 @ 0x24
80015fa: 4619 mov r1, r3
80015fc: 480e ldr r0, [pc, #56] @ (8001638 <MX_GPIO_Init+0x608>)
80015fe: f000 fe57 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_A1_Pin ARD_A0_Pin */
GPIO_InitStruct.Pin = ARD_A1_Pin|ARD_A0_Pin;
8001602: 2350 movs r3, #80 @ 0x50
8001604: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001606: 2303 movs r3, #3
8001608: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800160a: 2300 movs r3, #0
800160c: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800160e: f107 0324 add.w r3, r7, #36 @ 0x24
8001612: 4619 mov r1, r3
8001614: 4808 ldr r0, [pc, #32] @ (8001638 <MX_GPIO_Init+0x608>)
8001616: f000 fe4b bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D1_USART2_TX_Pin ARD_D0_USART2_RX_Pin */
GPIO_InitStruct.Pin = ARD_D1_USART2_TX_Pin|ARD_D0_USART2_RX_Pin;
800161a: 230c movs r3, #12
800161c: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800161e: 2302 movs r3, #2
8001620: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001622: 2300 movs r3, #0
8001624: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001626: 2303 movs r3, #3
8001628: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
800162a: 2307 movs r3, #7
800162c: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800162e: f107 0324 add.w r3, r7, #36 @ 0x24
8001632: e00d b.n 8001650 <MX_GPIO_Init+0x620>
8001634: 40020800 .word 0x40020800
8001638: 40020000 .word 0x40020000
800163c: 40022000 .word 0x40022000
8001640: 40020c00 .word 0x40020c00
8001644: 40021c00 .word 0x40021c00
8001648: 40021400 .word 0x40021400
800164c: 40020400 .word 0x40020400
8001650: 4619 mov r1, r3
8001652: 4829 ldr r0, [pc, #164] @ (80016f8 <MX_GPIO_Init+0x6c8>)
8001654: f000 fe2c bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : USB_OTG_HS_ID_Pin SYS_LD_USER2_Pin */
GPIO_InitStruct.Pin = USB_OTG_HS_ID_Pin|SYS_LD_USER2_Pin;
8001658: f241 0302 movw r3, #4098 @ 0x1002
800165c: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800165e: 2301 movs r3, #1
8001660: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001662: 2300 movs r3, #0
8001664: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001666: 2300 movs r3, #0
8001668: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800166a: f107 0324 add.w r3, r7, #36 @ 0x24
800166e: 4619 mov r1, r3
8001670: 4822 ldr r0, [pc, #136] @ (80016fc <MX_GPIO_Init+0x6cc>)
8001672: f000 fe1d bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : USB_OTG_HS_VBUS_Pin USB_OTGFS_OVCR_INT_Pin PMOD_INT_Pin */
GPIO_InitStruct.Pin = USB_OTG_HS_VBUS_Pin|USB_OTGFS_OVCR_INT_Pin|PMOD_INT_Pin;
8001676: f44f 5330 mov.w r3, #11264 @ 0x2c00
800167a: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
800167c: f44f 1388 mov.w r3, #1114112 @ 0x110000
8001680: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001682: 2300 movs r3, #0
8001684: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001686: f107 0324 add.w r3, r7, #36 @ 0x24
800168a: 4619 mov r1, r3
800168c: 481b ldr r0, [pc, #108] @ (80016fc <MX_GPIO_Init+0x6cc>)
800168e: f000 fe0f bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_D5_STMOD_TIM3_CH3_Pin */
GPIO_InitStruct.Pin = ARD_D5_STMOD_TIM3_CH3_Pin;
8001692: 2301 movs r3, #1
8001694: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001696: 2302 movs r3, #2
8001698: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800169a: 2300 movs r3, #0
800169c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800169e: 2300 movs r3, #0
80016a0: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
80016a2: 2302 movs r3, #2
80016a4: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(ARD_D5_STMOD_TIM3_CH3_GPIO_Port, &GPIO_InitStruct);
80016a6: f107 0324 add.w r3, r7, #36 @ 0x24
80016aa: 4619 mov r1, r3
80016ac: 4813 ldr r0, [pc, #76] @ (80016fc <MX_GPIO_Init+0x6cc>)
80016ae: f000 fdff bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pin : PMOD_RESET_Pin */
GPIO_InitStruct.Pin = PMOD_RESET_Pin;
80016b2: f44f 6300 mov.w r3, #2048 @ 0x800
80016b6: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80016b8: 2300 movs r3, #0
80016ba: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80016bc: 2300 movs r3, #0
80016be: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(PMOD_RESET_GPIO_Port, &GPIO_InitStruct);
80016c0: f107 0324 add.w r3, r7, #36 @ 0x24
80016c4: 4619 mov r1, r3
80016c6: 480e ldr r0, [pc, #56] @ (8001700 <MX_GPIO_Init+0x6d0>)
80016c8: f000 fdf2 bl 80022b0 <HAL_GPIO_Init>
/*Configure GPIO pins : PB14 PB15 */
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
80016cc: f44f 4340 mov.w r3, #49152 @ 0xc000
80016d0: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80016d2: 2302 movs r3, #2
80016d4: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80016d6: 2300 movs r3, #0
80016d8: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80016da: 2303 movs r3, #3
80016dc: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;
80016de: 230c movs r3, #12
80016e0: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80016e2: f107 0324 add.w r3, r7, #36 @ 0x24
80016e6: 4619 mov r1, r3
80016e8: 4804 ldr r0, [pc, #16] @ (80016fc <MX_GPIO_Init+0x6cc>)
80016ea: f000 fde1 bl 80022b0 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
80016ee: bf00 nop
80016f0: 3738 adds r7, #56 @ 0x38
80016f2: 46bd mov sp, r7
80016f4: bd80 pop {r7, pc}
80016f6: bf00 nop
80016f8: 40020000 .word 0x40020000
80016fc: 40020400 .word 0x40020400
8001700: 40021400 .word 0x40021400
08001704 <StartDefaultTask>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_StartDefaultTask */
void StartDefaultTask(void const * argument)
{
8001704: b580 push {r7, lr}
8001706: b082 sub sp, #8
8001708: af00 add r7, sp, #0
800170a: 6078 str r0, [r7, #4]
/* USER CODE BEGIN 5 */
/* Infinite loop */
for(;;)
{
osDelay(1);
800170c: 2001 movs r0, #1
800170e: f003 faea bl 8004ce6 <osDelay>
8001712: e7fb b.n 800170c <StartDefaultTask+0x8>
08001714 <HAL_TIM_PeriodElapsedCallback>:
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8001714: b580 push {r7, lr}
8001716: b082 sub sp, #8
8001718: af00 add r7, sp, #0
800171a: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM14)
800171c: 687b ldr r3, [r7, #4]
800171e: 681b ldr r3, [r3, #0]
8001720: 4a04 ldr r2, [pc, #16] @ (8001734 <HAL_TIM_PeriodElapsedCallback+0x20>)
8001722: 4293 cmp r3, r2
8001724: d101 bne.n 800172a <HAL_TIM_PeriodElapsedCallback+0x16>
{
HAL_IncTick();
8001726: f000 fc9d bl 8002064 <HAL_IncTick>
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
800172a: bf00 nop
800172c: 3708 adds r7, #8
800172e: 46bd mov sp, r7
8001730: bd80 pop {r7, pc}
8001732: bf00 nop
8001734: 40002000 .word 0x40002000
08001738 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8001738: b480 push {r7}
800173a: af00 add r7, sp, #0
__ASM volatile ("cpsid i" : : : "memory");
800173c: b672 cpsid i
}
800173e: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8001740: bf00 nop
8001742: e7fd b.n 8001740 <Error_Handler+0x8>
08001744 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8001744: b580 push {r7, lr}
8001746: b082 sub sp, #8
8001748: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_PWR_CLK_ENABLE();
800174a: 4b11 ldr r3, [pc, #68] @ (8001790 <HAL_MspInit+0x4c>)
800174c: 6c1b ldr r3, [r3, #64] @ 0x40
800174e: 4a10 ldr r2, [pc, #64] @ (8001790 <HAL_MspInit+0x4c>)
8001750: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001754: 6413 str r3, [r2, #64] @ 0x40
8001756: 4b0e ldr r3, [pc, #56] @ (8001790 <HAL_MspInit+0x4c>)
8001758: 6c1b ldr r3, [r3, #64] @ 0x40
800175a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800175e: 607b str r3, [r7, #4]
8001760: 687b ldr r3, [r7, #4]
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001762: 4b0b ldr r3, [pc, #44] @ (8001790 <HAL_MspInit+0x4c>)
8001764: 6c5b ldr r3, [r3, #68] @ 0x44
8001766: 4a0a ldr r2, [pc, #40] @ (8001790 <HAL_MspInit+0x4c>)
8001768: f443 4380 orr.w r3, r3, #16384 @ 0x4000
800176c: 6453 str r3, [r2, #68] @ 0x44
800176e: 4b08 ldr r3, [pc, #32] @ (8001790 <HAL_MspInit+0x4c>)
8001770: 6c5b ldr r3, [r3, #68] @ 0x44
8001772: f403 4380 and.w r3, r3, #16384 @ 0x4000
8001776: 603b str r3, [r7, #0]
8001778: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
800177a: 2200 movs r2, #0
800177c: 210f movs r1, #15
800177e: f06f 0001 mvn.w r0, #1
8001782: f000 fd6b bl 800225c <HAL_NVIC_SetPriority>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8001786: bf00 nop
8001788: 3708 adds r7, #8
800178a: 46bd mov sp, r7
800178c: bd80 pop {r7, pc}
800178e: bf00 nop
8001790: 40023800 .word 0x40023800
08001794 <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
8001794: b580 push {r7, lr}
8001796: b0aa sub sp, #168 @ 0xa8
8001798: af00 add r7, sp, #0
800179a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800179c: f107 0394 add.w r3, r7, #148 @ 0x94
80017a0: 2200 movs r2, #0
80017a2: 601a str r2, [r3, #0]
80017a4: 605a str r2, [r3, #4]
80017a6: 609a str r2, [r3, #8]
80017a8: 60da str r2, [r3, #12]
80017aa: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
80017ac: f107 0314 add.w r3, r7, #20
80017b0: 2280 movs r2, #128 @ 0x80
80017b2: 2100 movs r1, #0
80017b4: 4618 mov r0, r3
80017b6: f006 f9ae bl 8007b16 <memset>
if(hi2c->Instance==I2C3)
80017ba: 687b ldr r3, [r7, #4]
80017bc: 681b ldr r3, [r3, #0]
80017be: 4a33 ldr r2, [pc, #204] @ (800188c <HAL_I2C_MspInit+0xf8>)
80017c0: 4293 cmp r3, r2
80017c2: d15e bne.n 8001882 <HAL_I2C_MspInit+0xee>
/* USER CODE END I2C3_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C3;
80017c4: f44f 3380 mov.w r3, #65536 @ 0x10000
80017c8: 617b str r3, [r7, #20]
PeriphClkInitStruct.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1;
80017ca: 2300 movs r3, #0
80017cc: 67bb str r3, [r7, #120] @ 0x78
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
80017ce: f107 0314 add.w r3, r7, #20
80017d2: 4618 mov r0, r3
80017d4: f001 fda4 bl 8003320 <HAL_RCCEx_PeriphCLKConfig>
80017d8: 4603 mov r3, r0
80017da: 2b00 cmp r3, #0
80017dc: d001 beq.n 80017e2 <HAL_I2C_MspInit+0x4e>
{
Error_Handler();
80017de: f7ff ffab bl 8001738 <Error_Handler>
}
__HAL_RCC_GPIOA_CLK_ENABLE();
80017e2: 4b2b ldr r3, [pc, #172] @ (8001890 <HAL_I2C_MspInit+0xfc>)
80017e4: 6b1b ldr r3, [r3, #48] @ 0x30
80017e6: 4a2a ldr r2, [pc, #168] @ (8001890 <HAL_I2C_MspInit+0xfc>)
80017e8: f043 0301 orr.w r3, r3, #1
80017ec: 6313 str r3, [r2, #48] @ 0x30
80017ee: 4b28 ldr r3, [pc, #160] @ (8001890 <HAL_I2C_MspInit+0xfc>)
80017f0: 6b1b ldr r3, [r3, #48] @ 0x30
80017f2: f003 0301 and.w r3, r3, #1
80017f6: 613b str r3, [r7, #16]
80017f8: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOH_CLK_ENABLE();
80017fa: 4b25 ldr r3, [pc, #148] @ (8001890 <HAL_I2C_MspInit+0xfc>)
80017fc: 6b1b ldr r3, [r3, #48] @ 0x30
80017fe: 4a24 ldr r2, [pc, #144] @ (8001890 <HAL_I2C_MspInit+0xfc>)
8001800: f043 0380 orr.w r3, r3, #128 @ 0x80
8001804: 6313 str r3, [r2, #48] @ 0x30
8001806: 4b22 ldr r3, [pc, #136] @ (8001890 <HAL_I2C_MspInit+0xfc>)
8001808: 6b1b ldr r3, [r3, #48] @ 0x30
800180a: f003 0380 and.w r3, r3, #128 @ 0x80
800180e: 60fb str r3, [r7, #12]
8001810: 68fb ldr r3, [r7, #12]
/**I2C3 GPIO Configuration
PA8 ------> I2C3_SCL
PH8 ------> I2C3_SDA
*/
GPIO_InitStruct.Pin = CTP_SCL_Pin;
8001812: f44f 7380 mov.w r3, #256 @ 0x100
8001816: f8c7 3094 str.w r3, [r7, #148] @ 0x94
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
800181a: 2312 movs r3, #18
800181c: f8c7 3098 str.w r3, [r7, #152] @ 0x98
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001820: 2300 movs r3, #0
8001822: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001826: 2303 movs r3, #3
8001828: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
800182c: 2304 movs r3, #4
800182e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
HAL_GPIO_Init(CTP_SCL_GPIO_Port, &GPIO_InitStruct);
8001832: f107 0394 add.w r3, r7, #148 @ 0x94
8001836: 4619 mov r1, r3
8001838: 4816 ldr r0, [pc, #88] @ (8001894 <HAL_I2C_MspInit+0x100>)
800183a: f000 fd39 bl 80022b0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = CTP_SDA_Pin;
800183e: f44f 7380 mov.w r3, #256 @ 0x100
8001842: f8c7 3094 str.w r3, [r7, #148] @ 0x94
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8001846: 2312 movs r3, #18
8001848: f8c7 3098 str.w r3, [r7, #152] @ 0x98
GPIO_InitStruct.Pull = GPIO_NOPULL;
800184c: 2300 movs r3, #0
800184e: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001852: 2303 movs r3, #3
8001854: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
8001858: 2304 movs r3, #4
800185a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
HAL_GPIO_Init(CTP_SDA_GPIO_Port, &GPIO_InitStruct);
800185e: f107 0394 add.w r3, r7, #148 @ 0x94
8001862: 4619 mov r1, r3
8001864: 480c ldr r0, [pc, #48] @ (8001898 <HAL_I2C_MspInit+0x104>)
8001866: f000 fd23 bl 80022b0 <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_I2C3_CLK_ENABLE();
800186a: 4b09 ldr r3, [pc, #36] @ (8001890 <HAL_I2C_MspInit+0xfc>)
800186c: 6c1b ldr r3, [r3, #64] @ 0x40
800186e: 4a08 ldr r2, [pc, #32] @ (8001890 <HAL_I2C_MspInit+0xfc>)
8001870: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
8001874: 6413 str r3, [r2, #64] @ 0x40
8001876: 4b06 ldr r3, [pc, #24] @ (8001890 <HAL_I2C_MspInit+0xfc>)
8001878: 6c1b ldr r3, [r3, #64] @ 0x40
800187a: f403 0300 and.w r3, r3, #8388608 @ 0x800000
800187e: 60bb str r3, [r7, #8]
8001880: 68bb ldr r3, [r7, #8]
/* USER CODE END I2C3_MspInit 1 */
}
}
8001882: bf00 nop
8001884: 37a8 adds r7, #168 @ 0xa8
8001886: 46bd mov sp, r7
8001888: bd80 pop {r7, pc}
800188a: bf00 nop
800188c: 40005c00 .word 0x40005c00
8001890: 40023800 .word 0x40023800
8001894: 40020000 .word 0x40020000
8001898: 40021c00 .word 0x40021c00
0800189c <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
800189c: b580 push {r7, lr}
800189e: b0aa sub sp, #168 @ 0xa8
80018a0: af00 add r7, sp, #0
80018a2: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80018a4: f107 0394 add.w r3, r7, #148 @ 0x94
80018a8: 2200 movs r2, #0
80018aa: 601a str r2, [r3, #0]
80018ac: 605a str r2, [r3, #4]
80018ae: 609a str r2, [r3, #8]
80018b0: 60da str r2, [r3, #12]
80018b2: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
80018b4: f107 0314 add.w r3, r7, #20
80018b8: 2280 movs r2, #128 @ 0x80
80018ba: 2100 movs r1, #0
80018bc: 4618 mov r0, r3
80018be: f006 f92a bl 8007b16 <memset>
if(huart->Instance==USART6)
80018c2: 687b ldr r3, [r7, #4]
80018c4: 681b ldr r3, [r3, #0]
80018c6: 4a21 ldr r2, [pc, #132] @ (800194c <HAL_UART_MspInit+0xb0>)
80018c8: 4293 cmp r3, r2
80018ca: d13b bne.n 8001944 <HAL_UART_MspInit+0xa8>
/* USER CODE END USART6_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6;
80018cc: f44f 6300 mov.w r3, #2048 @ 0x800
80018d0: 617b str r3, [r7, #20]
PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
80018d2: 2300 movs r3, #0
80018d4: 667b str r3, [r7, #100] @ 0x64
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
80018d6: f107 0314 add.w r3, r7, #20
80018da: 4618 mov r0, r3
80018dc: f001 fd20 bl 8003320 <HAL_RCCEx_PeriphCLKConfig>
80018e0: 4603 mov r3, r0
80018e2: 2b00 cmp r3, #0
80018e4: d001 beq.n 80018ea <HAL_UART_MspInit+0x4e>
{
Error_Handler();
80018e6: f7ff ff27 bl 8001738 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_USART6_CLK_ENABLE();
80018ea: 4b19 ldr r3, [pc, #100] @ (8001950 <HAL_UART_MspInit+0xb4>)
80018ec: 6c5b ldr r3, [r3, #68] @ 0x44
80018ee: 4a18 ldr r2, [pc, #96] @ (8001950 <HAL_UART_MspInit+0xb4>)
80018f0: f043 0320 orr.w r3, r3, #32
80018f4: 6453 str r3, [r2, #68] @ 0x44
80018f6: 4b16 ldr r3, [pc, #88] @ (8001950 <HAL_UART_MspInit+0xb4>)
80018f8: 6c5b ldr r3, [r3, #68] @ 0x44
80018fa: f003 0320 and.w r3, r3, #32
80018fe: 613b str r3, [r7, #16]
8001900: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
8001902: 4b13 ldr r3, [pc, #76] @ (8001950 <HAL_UART_MspInit+0xb4>)
8001904: 6b1b ldr r3, [r3, #48] @ 0x30
8001906: 4a12 ldr r2, [pc, #72] @ (8001950 <HAL_UART_MspInit+0xb4>)
8001908: f043 0304 orr.w r3, r3, #4
800190c: 6313 str r3, [r2, #48] @ 0x30
800190e: 4b10 ldr r3, [pc, #64] @ (8001950 <HAL_UART_MspInit+0xb4>)
8001910: 6b1b ldr r3, [r3, #48] @ 0x30
8001912: f003 0304 and.w r3, r3, #4
8001916: 60fb str r3, [r7, #12]
8001918: 68fb ldr r3, [r7, #12]
/**USART6 GPIO Configuration
PC7 ------> USART6_RX
PC6 ------> USART6_TX
*/
GPIO_InitStruct.Pin = VCP_RX_Pin|VCP_TX_Pin;
800191a: 23c0 movs r3, #192 @ 0xc0
800191c: f8c7 3094 str.w r3, [r7, #148] @ 0x94
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001920: 2302 movs r3, #2
8001922: f8c7 3098 str.w r3, [r7, #152] @ 0x98
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001926: 2300 movs r3, #0
8001928: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800192c: 2303 movs r3, #3
800192e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
8001932: 2308 movs r3, #8
8001934: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001938: f107 0394 add.w r3, r7, #148 @ 0x94
800193c: 4619 mov r1, r3
800193e: 4805 ldr r0, [pc, #20] @ (8001954 <HAL_UART_MspInit+0xb8>)
8001940: f000 fcb6 bl 80022b0 <HAL_GPIO_Init>
/* USER CODE END USART6_MspInit 1 */
}
}
8001944: bf00 nop
8001946: 37a8 adds r7, #168 @ 0xa8
8001948: 46bd mov sp, r7
800194a: bd80 pop {r7, pc}
800194c: 40011400 .word 0x40011400
8001950: 40023800 .word 0x40023800
8001954: 40020800 .word 0x40020800
08001958 <HAL_FMC_MspInit>:
}
static uint32_t FMC_Initialized = 0;
static void HAL_FMC_MspInit(void){
8001958: b580 push {r7, lr}
800195a: b086 sub sp, #24
800195c: af00 add r7, sp, #0
/* USER CODE BEGIN FMC_MspInit 0 */
/* USER CODE END FMC_MspInit 0 */
GPIO_InitTypeDef GPIO_InitStruct ={0};
800195e: 1d3b adds r3, r7, #4
8001960: 2200 movs r2, #0
8001962: 601a str r2, [r3, #0]
8001964: 605a str r2, [r3, #4]
8001966: 609a str r2, [r3, #8]
8001968: 60da str r2, [r3, #12]
800196a: 611a str r2, [r3, #16]
if (FMC_Initialized) {
800196c: 4b33 ldr r3, [pc, #204] @ (8001a3c <HAL_FMC_MspInit+0xe4>)
800196e: 681b ldr r3, [r3, #0]
8001970: 2b00 cmp r3, #0
8001972: d15e bne.n 8001a32 <HAL_FMC_MspInit+0xda>
return;
}
FMC_Initialized = 1;
8001974: 4b31 ldr r3, [pc, #196] @ (8001a3c <HAL_FMC_MspInit+0xe4>)
8001976: 2201 movs r2, #1
8001978: 601a str r2, [r3, #0]
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_ENABLE();
800197a: 4b31 ldr r3, [pc, #196] @ (8001a40 <HAL_FMC_MspInit+0xe8>)
800197c: 6b9b ldr r3, [r3, #56] @ 0x38
800197e: 4a30 ldr r2, [pc, #192] @ (8001a40 <HAL_FMC_MspInit+0xe8>)
8001980: f043 0301 orr.w r3, r3, #1
8001984: 6393 str r3, [r2, #56] @ 0x38
8001986: 4b2e ldr r3, [pc, #184] @ (8001a40 <HAL_FMC_MspInit+0xe8>)
8001988: 6b9b ldr r3, [r3, #56] @ 0x38
800198a: f003 0301 and.w r3, r3, #1
800198e: 603b str r3, [r7, #0]
8001990: 683b ldr r3, [r7, #0]
PE7 ------> FMC_D4
PE10 ------> FMC_D7
PE12 ------> FMC_D9
PE15 ------> FMC_D12
*/
GPIO_InitStruct.Pin = PSRAM_NBL1_Pin|PSRAM_NBL0_Pin|LCD_PSRAM_D10_Pin|LCD_PSRAM_D5_Pin
8001992: f64f 7383 movw r3, #65411 @ 0xff83
8001996: 607b str r3, [r7, #4]
|LCD_PSRAM_D6_Pin|LCD_PSRAM_D8_Pin|LCD_PSRAM_D11_Pin|LCD_PSRAM_D4_Pin
|LCD_PSRAM_D7_Pin|LCD_PSRAM_D9_Pin|LCD_PSRAM_D12_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001998: 2302 movs r3, #2
800199a: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800199c: 2300 movs r3, #0
800199e: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80019a0: 2303 movs r3, #3
80019a2: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80019a4: 230c movs r3, #12
80019a6: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
80019a8: 1d3b adds r3, r7, #4
80019aa: 4619 mov r1, r3
80019ac: 4825 ldr r0, [pc, #148] @ (8001a44 <HAL_FMC_MspInit+0xec>)
80019ae: f000 fc7f bl 80022b0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = PSRAM_NE1_Pin|LCD_PSRAM_D2_Pin|LCD_PSRAM_NWE_Pin|LCD_PSRAM_D3_Pin
80019b2: f64d 73b3 movw r3, #57267 @ 0xdfb3
80019b6: 607b str r3, [r7, #4]
|LCD_PSRAM_NWED4_Pin|LCD_PSRAM_D1_Pin|LCD_PSRAM_D0_Pin|PSRAM_A17_Pin
|PSRAM_A16_Pin|LCD_PSRAM_D15_Pin|LCD_PSRAM_D14_Pin|LCD_PSRAM_D13_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80019b8: 2302 movs r3, #2
80019ba: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80019bc: 2300 movs r3, #0
80019be: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80019c0: 2303 movs r3, #3
80019c2: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80019c4: 230c movs r3, #12
80019c6: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
80019c8: 1d3b adds r3, r7, #4
80019ca: 4619 mov r1, r3
80019cc: 481e ldr r0, [pc, #120] @ (8001a48 <HAL_FMC_MspInit+0xf0>)
80019ce: f000 fc6f bl 80022b0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = NC1_Pin;
80019d2: 2380 movs r3, #128 @ 0x80
80019d4: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80019d6: 2302 movs r3, #2
80019d8: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80019da: 2300 movs r3, #0
80019dc: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80019de: 2303 movs r3, #3
80019e0: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80019e2: 230c movs r3, #12
80019e4: 617b str r3, [r7, #20]
HAL_GPIO_Init(NC1_GPIO_Port, &GPIO_InitStruct);
80019e6: 1d3b adds r3, r7, #4
80019e8: 4619 mov r1, r3
80019ea: 4818 ldr r0, [pc, #96] @ (8001a4c <HAL_FMC_MspInit+0xf4>)
80019ec: f000 fc60 bl 80022b0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_NE_Pin|PSRAM_A15_Pin|PSRAM_A14_Pin|PSRAM_A13_Pin
80019f0: f240 233f movw r3, #575 @ 0x23f
80019f4: 607b str r3, [r7, #4]
|PSRAM_A12_Pin|PSRAM_A11_Pin|PSRAM_A10_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80019f6: 2302 movs r3, #2
80019f8: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80019fa: 2300 movs r3, #0
80019fc: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80019fe: 2303 movs r3, #3
8001a00: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8001a02: 230c movs r3, #12
8001a04: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8001a06: 1d3b adds r3, r7, #4
8001a08: 4619 mov r1, r3
8001a0a: 4811 ldr r0, [pc, #68] @ (8001a50 <HAL_FMC_MspInit+0xf8>)
8001a0c: f000 fc50 bl 80022b0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = PSRAM_A0_Pin|PSRAM_A2_Pin|PSRAM_A1_Pin|PSRAM_A3_Pin
8001a10: f24f 033f movw r3, #61503 @ 0xf03f
8001a14: 607b str r3, [r7, #4]
|PSRAM_A4_Pin|PSRAM_A5_Pin|PSRAM_A7_Pin|PSRAM_A6_Pin
|PSRAM_A9_Pin|PSRAM_A8_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001a16: 2302 movs r3, #2
8001a18: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a1a: 2300 movs r3, #0
8001a1c: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001a1e: 2303 movs r3, #3
8001a20: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8001a22: 230c movs r3, #12
8001a24: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8001a26: 1d3b adds r3, r7, #4
8001a28: 4619 mov r1, r3
8001a2a: 480a ldr r0, [pc, #40] @ (8001a54 <HAL_FMC_MspInit+0xfc>)
8001a2c: f000 fc40 bl 80022b0 <HAL_GPIO_Init>
8001a30: e000 b.n 8001a34 <HAL_FMC_MspInit+0xdc>
return;
8001a32: bf00 nop
/* USER CODE BEGIN FMC_MspInit 1 */
/* USER CODE END FMC_MspInit 1 */
}
8001a34: 3718 adds r7, #24
8001a36: 46bd mov sp, r7
8001a38: bd80 pop {r7, pc}
8001a3a: bf00 nop
8001a3c: 2000066c .word 0x2000066c
8001a40: 40023800 .word 0x40023800
8001a44: 40021000 .word 0x40021000
8001a48: 40020c00 .word 0x40020c00
8001a4c: 40020400 .word 0x40020400
8001a50: 40021800 .word 0x40021800
8001a54: 40021400 .word 0x40021400
08001a58 <HAL_SRAM_MspInit>:
void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){
8001a58: b580 push {r7, lr}
8001a5a: b082 sub sp, #8
8001a5c: af00 add r7, sp, #0
8001a5e: 6078 str r0, [r7, #4]
/* USER CODE BEGIN SRAM_MspInit 0 */
/* USER CODE END SRAM_MspInit 0 */
HAL_FMC_MspInit();
8001a60: f7ff ff7a bl 8001958 <HAL_FMC_MspInit>
/* USER CODE BEGIN SRAM_MspInit 1 */
/* USER CODE END SRAM_MspInit 1 */
}
8001a64: bf00 nop
8001a66: 3708 adds r7, #8
8001a68: 46bd mov sp, r7
8001a6a: bd80 pop {r7, pc}
08001a6c <HAL_InitTick>:
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001a6c: b580 push {r7, lr}
8001a6e: b08e sub sp, #56 @ 0x38
8001a70: af00 add r7, sp, #0
8001a72: 6078 str r0, [r7, #4]
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock, uwAPB1Prescaler = 0U;
8001a74: 2300 movs r3, #0
8001a76: 62fb str r3, [r7, #44] @ 0x2c
uint32_t uwPrescalerValue = 0U;
8001a78: 2300 movs r3, #0
8001a7a: 62bb str r3, [r7, #40] @ 0x28
uint32_t pFLatency;
HAL_StatusTypeDef status;
/* Enable TIM14 clock */
__HAL_RCC_TIM14_CLK_ENABLE();
8001a7c: 4b33 ldr r3, [pc, #204] @ (8001b4c <HAL_InitTick+0xe0>)
8001a7e: 6c1b ldr r3, [r3, #64] @ 0x40
8001a80: 4a32 ldr r2, [pc, #200] @ (8001b4c <HAL_InitTick+0xe0>)
8001a82: f443 7380 orr.w r3, r3, #256 @ 0x100
8001a86: 6413 str r3, [r2, #64] @ 0x40
8001a88: 4b30 ldr r3, [pc, #192] @ (8001b4c <HAL_InitTick+0xe0>)
8001a8a: 6c1b ldr r3, [r3, #64] @ 0x40
8001a8c: f403 7380 and.w r3, r3, #256 @ 0x100
8001a90: 60fb str r3, [r7, #12]
8001a92: 68fb ldr r3, [r7, #12]
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
8001a94: f107 0210 add.w r2, r7, #16
8001a98: f107 0314 add.w r3, r7, #20
8001a9c: 4611 mov r1, r2
8001a9e: 4618 mov r0, r3
8001aa0: f001 fc0c bl 80032bc <HAL_RCC_GetClockConfig>
/* Get APB1 prescaler */
uwAPB1Prescaler = clkconfig.APB1CLKDivider;
8001aa4: 6a3b ldr r3, [r7, #32]
8001aa6: 62fb str r3, [r7, #44] @ 0x2c
/* Compute TIM14 clock */
if (uwAPB1Prescaler == RCC_HCLK_DIV1)
8001aa8: 6afb ldr r3, [r7, #44] @ 0x2c
8001aaa: 2b00 cmp r3, #0
8001aac: d103 bne.n 8001ab6 <HAL_InitTick+0x4a>
{
uwTimclock = HAL_RCC_GetPCLK1Freq();
8001aae: f001 fbdd bl 800326c <HAL_RCC_GetPCLK1Freq>
8001ab2: 6378 str r0, [r7, #52] @ 0x34
8001ab4: e004 b.n 8001ac0 <HAL_InitTick+0x54>
}
else
{
uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
8001ab6: f001 fbd9 bl 800326c <HAL_RCC_GetPCLK1Freq>
8001aba: 4603 mov r3, r0
8001abc: 005b lsls r3, r3, #1
8001abe: 637b str r3, [r7, #52] @ 0x34
}
/* Compute the prescaler value to have TIM14 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
8001ac0: 6b7b ldr r3, [r7, #52] @ 0x34
8001ac2: 4a23 ldr r2, [pc, #140] @ (8001b50 <HAL_InitTick+0xe4>)
8001ac4: fba2 2303 umull r2, r3, r2, r3
8001ac8: 0c9b lsrs r3, r3, #18
8001aca: 3b01 subs r3, #1
8001acc: 62bb str r3, [r7, #40] @ 0x28
/* Initialize TIM14 */
htim14.Instance = TIM14;
8001ace: 4b21 ldr r3, [pc, #132] @ (8001b54 <HAL_InitTick+0xe8>)
8001ad0: 4a21 ldr r2, [pc, #132] @ (8001b58 <HAL_InitTick+0xec>)
8001ad2: 601a str r2, [r3, #0]
* Period = [(TIM14CLK/1000) - 1]. to have a (1/1000) s time base.
* Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
* ClockDivision = 0
* Counter direction = Up
*/
htim14.Init.Period = (1000000U / 1000U) - 1U;
8001ad4: 4b1f ldr r3, [pc, #124] @ (8001b54 <HAL_InitTick+0xe8>)
8001ad6: f240 32e7 movw r2, #999 @ 0x3e7
8001ada: 60da str r2, [r3, #12]
htim14.Init.Prescaler = uwPrescalerValue;
8001adc: 4a1d ldr r2, [pc, #116] @ (8001b54 <HAL_InitTick+0xe8>)
8001ade: 6abb ldr r3, [r7, #40] @ 0x28
8001ae0: 6053 str r3, [r2, #4]
htim14.Init.ClockDivision = 0;
8001ae2: 4b1c ldr r3, [pc, #112] @ (8001b54 <HAL_InitTick+0xe8>)
8001ae4: 2200 movs r2, #0
8001ae6: 611a str r2, [r3, #16]
htim14.Init.CounterMode = TIM_COUNTERMODE_UP;
8001ae8: 4b1a ldr r3, [pc, #104] @ (8001b54 <HAL_InitTick+0xe8>)
8001aea: 2200 movs r2, #0
8001aec: 609a str r2, [r3, #8]
htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8001aee: 4b19 ldr r3, [pc, #100] @ (8001b54 <HAL_InitTick+0xe8>)
8001af0: 2200 movs r2, #0
8001af2: 619a str r2, [r3, #24]
status = HAL_TIM_Base_Init(&htim14);
8001af4: 4817 ldr r0, [pc, #92] @ (8001b54 <HAL_InitTick+0xe8>)
8001af6: f001 ffa5 bl 8003a44 <HAL_TIM_Base_Init>
8001afa: 4603 mov r3, r0
8001afc: f887 3033 strb.w r3, [r7, #51] @ 0x33
if (status == HAL_OK)
8001b00: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
8001b04: 2b00 cmp r3, #0
8001b06: d11b bne.n 8001b40 <HAL_InitTick+0xd4>
{
/* Start the TIM time Base generation in interrupt mode */
status = HAL_TIM_Base_Start_IT(&htim14);
8001b08: 4812 ldr r0, [pc, #72] @ (8001b54 <HAL_InitTick+0xe8>)
8001b0a: f001 fffd bl 8003b08 <HAL_TIM_Base_Start_IT>
8001b0e: 4603 mov r3, r0
8001b10: f887 3033 strb.w r3, [r7, #51] @ 0x33
if (status == HAL_OK)
8001b14: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
8001b18: 2b00 cmp r3, #0
8001b1a: d111 bne.n 8001b40 <HAL_InitTick+0xd4>
{
/* Enable the TIM14 global Interrupt */
HAL_NVIC_EnableIRQ(TIM8_TRG_COM_TIM14_IRQn);
8001b1c: 202d movs r0, #45 @ 0x2d
8001b1e: f000 fbb9 bl 8002294 <HAL_NVIC_EnableIRQ>
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001b22: 687b ldr r3, [r7, #4]
8001b24: 2b0f cmp r3, #15
8001b26: d808 bhi.n 8001b3a <HAL_InitTick+0xce>
{
/* Configure the TIM IRQ priority */
HAL_NVIC_SetPriority(TIM8_TRG_COM_TIM14_IRQn, TickPriority, 0U);
8001b28: 2200 movs r2, #0
8001b2a: 6879 ldr r1, [r7, #4]
8001b2c: 202d movs r0, #45 @ 0x2d
8001b2e: f000 fb95 bl 800225c <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8001b32: 4a0a ldr r2, [pc, #40] @ (8001b5c <HAL_InitTick+0xf0>)
8001b34: 687b ldr r3, [r7, #4]
8001b36: 6013 str r3, [r2, #0]
8001b38: e002 b.n 8001b40 <HAL_InitTick+0xd4>
}
else
{
status = HAL_ERROR;
8001b3a: 2301 movs r3, #1
8001b3c: f887 3033 strb.w r3, [r7, #51] @ 0x33
}
}
}
/* Return function status */
return status;
8001b40: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
}
8001b44: 4618 mov r0, r3
8001b46: 3738 adds r7, #56 @ 0x38
8001b48: 46bd mov sp, r7
8001b4a: bd80 pop {r7, pc}
8001b4c: 40023800 .word 0x40023800
8001b50: 431bde83 .word 0x431bde83
8001b54: 20000670 .word 0x20000670
8001b58: 40002000 .word 0x40002000
8001b5c: 20000004 .word 0x20000004
08001b60 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001b60: b480 push {r7}
8001b62: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001b64: bf00 nop
8001b66: e7fd b.n 8001b64 <NMI_Handler+0x4>
08001b68 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8001b68: b480 push {r7}
8001b6a: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001b6c: bf00 nop
8001b6e: e7fd b.n 8001b6c <HardFault_Handler+0x4>
08001b70 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001b70: b480 push {r7}
8001b72: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001b74: bf00 nop
8001b76: e7fd b.n 8001b74 <MemManage_Handler+0x4>
08001b78 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8001b78: b480 push {r7}
8001b7a: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8001b7c: bf00 nop
8001b7e: e7fd b.n 8001b7c <BusFault_Handler+0x4>
08001b80 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8001b80: b480 push {r7}
8001b82: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001b84: bf00 nop
8001b86: e7fd b.n 8001b84 <UsageFault_Handler+0x4>
08001b88 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8001b88: b480 push {r7}
8001b8a: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8001b8c: bf00 nop
8001b8e: 46bd mov sp, r7
8001b90: f85d 7b04 ldr.w r7, [sp], #4
8001b94: 4770 bx lr
...
08001b98 <TIM8_TRG_COM_TIM14_IRQHandler>:
/**
* @brief This function handles TIM8 trigger and commutation interrupts and TIM14 global interrupt.
*/
void TIM8_TRG_COM_TIM14_IRQHandler(void)
{
8001b98: b580 push {r7, lr}
8001b9a: af00 add r7, sp, #0
/* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 0 */
/* USER CODE END TIM8_TRG_COM_TIM14_IRQn 0 */
HAL_TIM_IRQHandler(&htim14);
8001b9c: 4802 ldr r0, [pc, #8] @ (8001ba8 <TIM8_TRG_COM_TIM14_IRQHandler+0x10>)
8001b9e: f002 f82b bl 8003bf8 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 1 */
/* USER CODE END TIM8_TRG_COM_TIM14_IRQn 1 */
}
8001ba2: bf00 nop
8001ba4: bd80 pop {r7, pc}
8001ba6: bf00 nop
8001ba8: 20000670 .word 0x20000670
08001bac <_read>:
_kill(status, -1);
while (1) {} /* Make sure we hang here */
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
8001bac: b580 push {r7, lr}
8001bae: b086 sub sp, #24
8001bb0: af00 add r7, sp, #0
8001bb2: 60f8 str r0, [r7, #12]
8001bb4: 60b9 str r1, [r7, #8]
8001bb6: 607a str r2, [r7, #4]
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
8001bb8: 2300 movs r3, #0
8001bba: 617b str r3, [r7, #20]
8001bbc: e00a b.n 8001bd4 <_read+0x28>
{
*ptr++ = __io_getchar();
8001bbe: f3af 8000 nop.w
8001bc2: 4601 mov r1, r0
8001bc4: 68bb ldr r3, [r7, #8]
8001bc6: 1c5a adds r2, r3, #1
8001bc8: 60ba str r2, [r7, #8]
8001bca: b2ca uxtb r2, r1
8001bcc: 701a strb r2, [r3, #0]
for (DataIdx = 0; DataIdx < len; DataIdx++)
8001bce: 697b ldr r3, [r7, #20]
8001bd0: 3301 adds r3, #1
8001bd2: 617b str r3, [r7, #20]
8001bd4: 697a ldr r2, [r7, #20]
8001bd6: 687b ldr r3, [r7, #4]
8001bd8: 429a cmp r2, r3
8001bda: dbf0 blt.n 8001bbe <_read+0x12>
}
return len;
8001bdc: 687b ldr r3, [r7, #4]
}
8001bde: 4618 mov r0, r3
8001be0: 3718 adds r7, #24
8001be2: 46bd mov sp, r7
8001be4: bd80 pop {r7, pc}
08001be6 <_close>:
}
return len;
}
int _close(int file)
{
8001be6: b480 push {r7}
8001be8: b083 sub sp, #12
8001bea: af00 add r7, sp, #0
8001bec: 6078 str r0, [r7, #4]
(void)file;
return -1;
8001bee: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
}
8001bf2: 4618 mov r0, r3
8001bf4: 370c adds r7, #12
8001bf6: 46bd mov sp, r7
8001bf8: f85d 7b04 ldr.w r7, [sp], #4
8001bfc: 4770 bx lr
08001bfe <_fstat>:
int _fstat(int file, struct stat *st)
{
8001bfe: b480 push {r7}
8001c00: b083 sub sp, #12
8001c02: af00 add r7, sp, #0
8001c04: 6078 str r0, [r7, #4]
8001c06: 6039 str r1, [r7, #0]
(void)file;
st->st_mode = S_IFCHR;
8001c08: 683b ldr r3, [r7, #0]
8001c0a: f44f 5200 mov.w r2, #8192 @ 0x2000
8001c0e: 605a str r2, [r3, #4]
return 0;
8001c10: 2300 movs r3, #0
}
8001c12: 4618 mov r0, r3
8001c14: 370c adds r7, #12
8001c16: 46bd mov sp, r7
8001c18: f85d 7b04 ldr.w r7, [sp], #4
8001c1c: 4770 bx lr
08001c1e <_isatty>:
int _isatty(int file)
{
8001c1e: b480 push {r7}
8001c20: b083 sub sp, #12
8001c22: af00 add r7, sp, #0
8001c24: 6078 str r0, [r7, #4]
(void)file;
return 1;
8001c26: 2301 movs r3, #1
}
8001c28: 4618 mov r0, r3
8001c2a: 370c adds r7, #12
8001c2c: 46bd mov sp, r7
8001c2e: f85d 7b04 ldr.w r7, [sp], #4
8001c32: 4770 bx lr
08001c34 <_lseek>:
int _lseek(int file, int ptr, int dir)
{
8001c34: b480 push {r7}
8001c36: b085 sub sp, #20
8001c38: af00 add r7, sp, #0
8001c3a: 60f8 str r0, [r7, #12]
8001c3c: 60b9 str r1, [r7, #8]
8001c3e: 607a str r2, [r7, #4]
(void)file;
(void)ptr;
(void)dir;
return 0;
8001c40: 2300 movs r3, #0
}
8001c42: 4618 mov r0, r3
8001c44: 3714 adds r7, #20
8001c46: 46bd mov sp, r7
8001c48: f85d 7b04 ldr.w r7, [sp], #4
8001c4c: 4770 bx lr
...
08001c50 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
8001c50: b580 push {r7, lr}
8001c52: b086 sub sp, #24
8001c54: af00 add r7, sp, #0
8001c56: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
8001c58: 4a14 ldr r2, [pc, #80] @ (8001cac <_sbrk+0x5c>)
8001c5a: 4b15 ldr r3, [pc, #84] @ (8001cb0 <_sbrk+0x60>)
8001c5c: 1ad3 subs r3, r2, r3
8001c5e: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
8001c60: 697b ldr r3, [r7, #20]
8001c62: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
8001c64: 4b13 ldr r3, [pc, #76] @ (8001cb4 <_sbrk+0x64>)
8001c66: 681b ldr r3, [r3, #0]
8001c68: 2b00 cmp r3, #0
8001c6a: d102 bne.n 8001c72 <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
8001c6c: 4b11 ldr r3, [pc, #68] @ (8001cb4 <_sbrk+0x64>)
8001c6e: 4a12 ldr r2, [pc, #72] @ (8001cb8 <_sbrk+0x68>)
8001c70: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
8001c72: 4b10 ldr r3, [pc, #64] @ (8001cb4 <_sbrk+0x64>)
8001c74: 681a ldr r2, [r3, #0]
8001c76: 687b ldr r3, [r7, #4]
8001c78: 4413 add r3, r2
8001c7a: 693a ldr r2, [r7, #16]
8001c7c: 429a cmp r2, r3
8001c7e: d207 bcs.n 8001c90 <_sbrk+0x40>
{
errno = ENOMEM;
8001c80: f005 fff6 bl 8007c70 <__errno>
8001c84: 4603 mov r3, r0
8001c86: 220c movs r2, #12
8001c88: 601a str r2, [r3, #0]
return (void *)-1;
8001c8a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
8001c8e: e009 b.n 8001ca4 <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
8001c90: 4b08 ldr r3, [pc, #32] @ (8001cb4 <_sbrk+0x64>)
8001c92: 681b ldr r3, [r3, #0]
8001c94: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
8001c96: 4b07 ldr r3, [pc, #28] @ (8001cb4 <_sbrk+0x64>)
8001c98: 681a ldr r2, [r3, #0]
8001c9a: 687b ldr r3, [r7, #4]
8001c9c: 4413 add r3, r2
8001c9e: 4a05 ldr r2, [pc, #20] @ (8001cb4 <_sbrk+0x64>)
8001ca0: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
8001ca2: 68fb ldr r3, [r7, #12]
}
8001ca4: 4618 mov r0, r3
8001ca6: 3718 adds r7, #24
8001ca8: 46bd mov sp, r7
8001caa: bd80 pop {r7, pc}
8001cac: 20040000 .word 0x20040000
8001cb0: 00000400 .word 0x00000400
8001cb4: 200006bc .word 0x200006bc
8001cb8: 20008e38 .word 0x20008e38
08001cbc <SystemInit>:
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
8001cbc: b480 push {r7}
8001cbe: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8001cc0: 4b06 ldr r3, [pc, #24] @ (8001cdc <SystemInit+0x20>)
8001cc2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8001cc6: 4a05 ldr r2, [pc, #20] @ (8001cdc <SystemInit+0x20>)
8001cc8: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
8001ccc: f8c2 3088 str.w r3, [r2, #136] @ 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8001cd0: bf00 nop
8001cd2: 46bd mov sp, r7
8001cd4: f85d 7b04 ldr.w r7, [sp], #4
8001cd8: 4770 bx lr
8001cda: bf00 nop
8001cdc: e000ed00 .word 0xe000ed00
08001ce0 <Usage_GetTicks>:
static TaskStatus_t *Usage_TaskStatusArraySort[TASKSTATUS_SIZE];
uint32_t Usage_TaskStatusTimePrev = 0;
static uint32_t Usage_SOL = 0;
uint32_t Usage_GetTicks( void )
{
8001ce0: b480 push {r7}
8001ce2: af00 add r7, sp, #0
return DWT->CYCCNT;
8001ce4: 4b03 ldr r3, [pc, #12] @ (8001cf4 <Usage_GetTicks+0x14>)
8001ce6: 685b ldr r3, [r3, #4]
}
8001ce8: 4618 mov r0, r3
8001cea: 46bd mov sp, r7
8001cec: f85d 7b04 ldr.w r7, [sp], #4
8001cf0: 4770 bx lr
8001cf2: bf00 nop
8001cf4: e0001000 .word 0xe0001000
08001cf8 <Usage_TaskSwitchedIn>:
void Usage_TaskSwitchedIn( void )
{
8001cf8: b580 push {r7, lr}
8001cfa: af00 add r7, sp, #0
if( pxCurrentTCB == xTaskGetIdleTaskHandle() ) {
8001cfc: f004 fa16 bl 800612c <xTaskGetIdleTaskHandle>
8001d00: 4602 mov r2, r0
8001d02: 4b05 ldr r3, [pc, #20] @ (8001d18 <Usage_TaskSwitchedIn+0x20>)
8001d04: 681b ldr r3, [r3, #0]
8001d06: 429a cmp r2, r3
8001d08: d104 bne.n 8001d14 <Usage_TaskSwitchedIn+0x1c>
Usage_IdleTickStart = Usage_GetTicks();
8001d0a: f7ff ffe9 bl 8001ce0 <Usage_GetTicks>
8001d0e: 4603 mov r3, r0
8001d10: 4a02 ldr r2, [pc, #8] @ (8001d1c <Usage_TaskSwitchedIn+0x24>)
8001d12: 6013 str r3, [r2, #0]
}
}
8001d14: bf00 nop
8001d16: bd80 pop {r7, pc}
8001d18: 20000b98 .word 0x20000b98
8001d1c: 200006c0 .word 0x200006c0
08001d20 <Usage_TaskSwitchedOut>:
void Usage_TaskSwitchedOut( void )
{
8001d20: b580 push {r7, lr}
8001d22: af00 add r7, sp, #0
if( pxCurrentTCB == xTaskGetIdleTaskHandle() ) {
8001d24: f004 fa02 bl 800612c <xTaskGetIdleTaskHandle>
8001d28: 4602 mov r2, r0
8001d2a: 4b0a ldr r3, [pc, #40] @ (8001d54 <Usage_TaskSwitchedOut+0x34>)
8001d2c: 681b ldr r3, [r3, #0]
8001d2e: 429a cmp r2, r3
8001d30: d10e bne.n 8001d50 <Usage_TaskSwitchedOut+0x30>
Usage_IdleTickEnd = Usage_GetTicks();
8001d32: f7ff ffd5 bl 8001ce0 <Usage_GetTicks>
8001d36: 4603 mov r3, r0
8001d38: 4a07 ldr r2, [pc, #28] @ (8001d58 <Usage_TaskSwitchedOut+0x38>)
8001d3a: 6013 str r3, [r2, #0]
Usage_IdleTickTotal += Usage_IdleTickEnd - Usage_IdleTickStart;
8001d3c: 4b06 ldr r3, [pc, #24] @ (8001d58 <Usage_TaskSwitchedOut+0x38>)
8001d3e: 681a ldr r2, [r3, #0]
8001d40: 4b06 ldr r3, [pc, #24] @ (8001d5c <Usage_TaskSwitchedOut+0x3c>)
8001d42: 681b ldr r3, [r3, #0]
8001d44: 1ad2 subs r2, r2, r3
8001d46: 4b06 ldr r3, [pc, #24] @ (8001d60 <Usage_TaskSwitchedOut+0x40>)
8001d48: 681b ldr r3, [r3, #0]
8001d4a: 4413 add r3, r2
8001d4c: 4a04 ldr r2, [pc, #16] @ (8001d60 <Usage_TaskSwitchedOut+0x40>)
8001d4e: 6013 str r3, [r2, #0]
}
}
8001d50: bf00 nop
8001d52: bd80 pop {r7, pc}
8001d54: 20000b98 .word 0x20000b98
8001d58: 200006c4 .word 0x200006c4
8001d5c: 200006c0 .word 0x200006c0
8001d60: 200006c8 .word 0x200006c8
08001d64 <Usage_TaskStatusCompare>:
}
static int Usage_TaskStatusCompare (const void * a, const void * b)
{
8001d64: b480 push {r7}
8001d66: b085 sub sp, #20
8001d68: af00 add r7, sp, #0
8001d6a: 6078 str r0, [r7, #4]
8001d6c: 6039 str r1, [r7, #0]
TaskStatus_t *aa = *((TaskStatus_t**) a);
8001d6e: 687b ldr r3, [r7, #4]
8001d70: 681b ldr r3, [r3, #0]
8001d72: 60fb str r3, [r7, #12]
TaskStatus_t *bb = *((TaskStatus_t**) b);
8001d74: 683b ldr r3, [r7, #0]
8001d76: 681b ldr r3, [r3, #0]
8001d78: 60bb str r3, [r7, #8]
return ((int)aa->xTaskNumber - (int)bb->xTaskNumber);
8001d7a: 68fb ldr r3, [r7, #12]
8001d7c: 689b ldr r3, [r3, #8]
8001d7e: 461a mov r2, r3
8001d80: 68bb ldr r3, [r7, #8]
8001d82: 689b ldr r3, [r3, #8]
8001d84: 1ad3 subs r3, r2, r3
}
8001d86: 4618 mov r0, r3
8001d88: 3714 adds r7, #20
8001d8a: 46bd mov sp, r7
8001d8c: f85d 7b04 ldr.w r7, [sp], #4
8001d90: 4770 bx lr
...
08001d94 <Usage_PrintStats>:
void Usage_PrintStats( void )
{
8001d94: b590 push {r4, r7, lr}
8001d96: b08d sub sp, #52 @ 0x34
8001d98: af02 add r7, sp, #8
uint32_t TaskCnt, x, i;
uint8_t Ignore = 0;
8001d9a: 2300 movs r3, #0
8001d9c: 76fb strb r3, [r7, #27]
int32_t DiffCounter;
TaskStatus_t *TS;
uint32_t TaskStatusTime, Usage, TotalTimeDiff;
uint32_t NonIdleCounter = 0;
8001d9e: 2300 movs r3, #0
8001da0: 60fb str r3, [r7, #12]
TaskCnt = uxTaskGetNumberOfTasks();
8001da2: f004 f927 bl 8005ff4 <uxTaskGetNumberOfTasks>
8001da6: 6278 str r0, [r7, #36] @ 0x24
if( TaskCnt > TASKSTATUS_SIZE ) {
8001da8: 6a7b ldr r3, [r7, #36] @ 0x24
8001daa: 2b10 cmp r3, #16
8001dac: d901 bls.n 8001db2 <Usage_PrintStats+0x1e>
TaskCnt = TASKSTATUS_SIZE;
8001dae: 2310 movs r3, #16
8001db0: 627b str r3, [r7, #36] @ 0x24
}
TaskCnt = uxTaskGetSystemState( Usage_TaskStatusArray, TaskCnt, &TaskStatusTime );
8001db2: 463b mov r3, r7
8001db4: 461a mov r2, r3
8001db6: 6a79 ldr r1, [r7, #36] @ 0x24
8001db8: 4879 ldr r0, [pc, #484] @ (8001fa0 <Usage_PrintStats+0x20c>)
8001dba: f004 f927 bl 800600c <uxTaskGetSystemState>
8001dbe: 6278 str r0, [r7, #36] @ 0x24
// Note: uxTaskGetSystemState stores the task information in TaskStatusArray in an arbitrary sequence.
// Sort TaskStatusArray by the task number!
for(i=0;i<TaskCnt;i++) {
8001dc0: 2300 movs r3, #0
8001dc2: 61fb str r3, [r7, #28]
8001dc4: e00d b.n 8001de2 <Usage_PrintStats+0x4e>
Usage_TaskStatusArraySort[i] = &Usage_TaskStatusArray[i];
8001dc6: 69fa ldr r2, [r7, #28]
8001dc8: 4613 mov r3, r2
8001dca: 00db lsls r3, r3, #3
8001dcc: 4413 add r3, r2
8001dce: 009b lsls r3, r3, #2
8001dd0: 4a73 ldr r2, [pc, #460] @ (8001fa0 <Usage_PrintStats+0x20c>)
8001dd2: 441a add r2, r3
8001dd4: 4973 ldr r1, [pc, #460] @ (8001fa4 <Usage_PrintStats+0x210>)
8001dd6: 69fb ldr r3, [r7, #28]
8001dd8: f841 2023 str.w r2, [r1, r3, lsl #2]
for(i=0;i<TaskCnt;i++) {
8001ddc: 69fb ldr r3, [r7, #28]
8001dde: 3301 adds r3, #1
8001de0: 61fb str r3, [r7, #28]
8001de2: 69fa ldr r2, [r7, #28]
8001de4: 6a7b ldr r3, [r7, #36] @ 0x24
8001de6: 429a cmp r2, r3
8001de8: d3ed bcc.n 8001dc6 <Usage_PrintStats+0x32>
}
qsort(Usage_TaskStatusArraySort,TaskCnt,sizeof(TaskStatus_t*),Usage_TaskStatusCompare);
8001dea: 4b6f ldr r3, [pc, #444] @ (8001fa8 <Usage_PrintStats+0x214>)
8001dec: 2204 movs r2, #4
8001dee: 6a79 ldr r1, [r7, #36] @ 0x24
8001df0: 486c ldr r0, [pc, #432] @ (8001fa4 <Usage_PrintStats+0x210>)
8001df2: f005 fc32 bl 800765a <qsort>
// Get time without idle:
NonIdleCounter = 0;
8001df6: 2300 movs r3, #0
8001df8: 60fb str r3, [r7, #12]
for( x = 0; x < TaskCnt; x++ ) {
8001dfa: 2300 movs r3, #0
8001dfc: 623b str r3, [r7, #32]
8001dfe: e041 b.n 8001e84 <Usage_PrintStats+0xf0>
TS = Usage_TaskStatusArraySort[ x ];
8001e00: 4a68 ldr r2, [pc, #416] @ (8001fa4 <Usage_PrintStats+0x210>)
8001e02: 6a3b ldr r3, [r7, #32]
8001e04: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001e08: 607b str r3, [r7, #4]
for( i = 0; i < TaskCnt; i++ ) {
8001e0a: 2300 movs r3, #0
8001e0c: 61fb str r3, [r7, #28]
8001e0e: e032 b.n 8001e76 <Usage_PrintStats+0xe2>
if( TS->xTaskNumber == Usage_TaskStatusArrayPrev[ i ].xTaskNumber ) {
8001e10: 687b ldr r3, [r7, #4]
8001e12: 6899 ldr r1, [r3, #8]
8001e14: 4865 ldr r0, [pc, #404] @ (8001fac <Usage_PrintStats+0x218>)
8001e16: 69fa ldr r2, [r7, #28]
8001e18: 4613 mov r3, r2
8001e1a: 00db lsls r3, r3, #3
8001e1c: 4413 add r3, r2
8001e1e: 009b lsls r3, r3, #2
8001e20: 4403 add r3, r0
8001e22: 3308 adds r3, #8
8001e24: 681b ldr r3, [r3, #0]
8001e26: 4299 cmp r1, r3
8001e28: d122 bne.n 8001e70 <Usage_PrintStats+0xdc>
if( Usage_TaskStatusArrayPrev[ i ].ulRunTimeCounter == 0 ) {
8001e2a: 4960 ldr r1, [pc, #384] @ (8001fac <Usage_PrintStats+0x218>)
8001e2c: 69fa ldr r2, [r7, #28]
8001e2e: 4613 mov r3, r2
8001e30: 00db lsls r3, r3, #3
8001e32: 4413 add r3, r2
8001e34: 009b lsls r3, r3, #2
8001e36: 440b add r3, r1
8001e38: 3318 adds r3, #24
8001e3a: 681b ldr r3, [r3, #0]
8001e3c: 2b00 cmp r3, #0
8001e3e: d101 bne.n 8001e44 <Usage_PrintStats+0xb0>
Ignore = 1;
8001e40: 2301 movs r3, #1
8001e42: 76fb strb r3, [r7, #27]
}
if( TS->xHandle != xTaskGetIdleTaskHandle() ) {
8001e44: 687b ldr r3, [r7, #4]
8001e46: 681c ldr r4, [r3, #0]
8001e48: f004 f970 bl 800612c <xTaskGetIdleTaskHandle>
8001e4c: 4603 mov r3, r0
8001e4e: 429c cmp r4, r3
8001e50: d00e beq.n 8001e70 <Usage_PrintStats+0xdc>
NonIdleCounter += TS->ulRunTimeCounter-Usage_TaskStatusArrayPrev[ i ].ulRunTimeCounter;
8001e52: 687b ldr r3, [r7, #4]
8001e54: 6999 ldr r1, [r3, #24]
8001e56: 4855 ldr r0, [pc, #340] @ (8001fac <Usage_PrintStats+0x218>)
8001e58: 69fa ldr r2, [r7, #28]
8001e5a: 4613 mov r3, r2
8001e5c: 00db lsls r3, r3, #3
8001e5e: 4413 add r3, r2
8001e60: 009b lsls r3, r3, #2
8001e62: 4403 add r3, r0
8001e64: 3318 adds r3, #24
8001e66: 681b ldr r3, [r3, #0]
8001e68: 1acb subs r3, r1, r3
8001e6a: 68fa ldr r2, [r7, #12]
8001e6c: 4413 add r3, r2
8001e6e: 60fb str r3, [r7, #12]
for( i = 0; i < TaskCnt; i++ ) {
8001e70: 69fb ldr r3, [r7, #28]
8001e72: 3301 adds r3, #1
8001e74: 61fb str r3, [r7, #28]
8001e76: 69fa ldr r2, [r7, #28]
8001e78: 6a7b ldr r3, [r7, #36] @ 0x24
8001e7a: 429a cmp r2, r3
8001e7c: d3c8 bcc.n 8001e10 <Usage_PrintStats+0x7c>
for( x = 0; x < TaskCnt; x++ ) {
8001e7e: 6a3b ldr r3, [r7, #32]
8001e80: 3301 adds r3, #1
8001e82: 623b str r3, [r7, #32]
8001e84: 6a3a ldr r2, [r7, #32]
8001e86: 6a7b ldr r3, [r7, #36] @ 0x24
8001e88: 429a cmp r2, r3
8001e8a: d3b9 bcc.n 8001e00 <Usage_PrintStats+0x6c>
}
}
}
}
TotalTimeDiff = TaskStatusTime - Usage_TaskStatusTimePrev;
8001e8c: 683a ldr r2, [r7, #0]
8001e8e: 4b48 ldr r3, [pc, #288] @ (8001fb0 <Usage_PrintStats+0x21c>)
8001e90: 681b ldr r3, [r3, #0]
8001e92: 1ad3 subs r3, r2, r3
8001e94: 60bb str r3, [r7, #8]
TotalTimeDiff /= 100UL; // For percentage calculations.
8001e96: 68bb ldr r3, [r7, #8]
8001e98: 4a46 ldr r2, [pc, #280] @ (8001fb4 <Usage_PrintStats+0x220>)
8001e9a: fba2 2303 umull r2, r3, r2, r3
8001e9e: 095b lsrs r3, r3, #5
8001ea0: 60bb str r3, [r7, #8]
if( TaskStatusTime > 0 && Usage_TaskStatusTimePrev != 0 && !Ignore ) {
8001ea2: 683b ldr r3, [r7, #0]
8001ea4: 2b00 cmp r3, #0
8001ea6: d06b beq.n 8001f80 <Usage_PrintStats+0x1ec>
8001ea8: 4b41 ldr r3, [pc, #260] @ (8001fb0 <Usage_PrintStats+0x21c>)
8001eaa: 681b ldr r3, [r3, #0]
8001eac: 2b00 cmp r3, #0
8001eae: d067 beq.n 8001f80 <Usage_PrintStats+0x1ec>
8001eb0: 7efb ldrb r3, [r7, #27]
8001eb2: 2b00 cmp r3, #0
8001eb4: d164 bne.n 8001f80 <Usage_PrintStats+0x1ec>
printf("CPU usage without idle: %d%%, free RTOS heap: %d, SOL: %d\n", (int) (NonIdleCounter/TotalTimeDiff), xPortGetFreeHeapSize(), (int) Usage_SOL );
8001eb6: 68fa ldr r2, [r7, #12]
8001eb8: 68bb ldr r3, [r7, #8]
8001eba: fbb2 f3f3 udiv r3, r2, r3
8001ebe: 461c mov r4, r3
8001ec0: f005 faca bl 8007458 <xPortGetFreeHeapSize>
8001ec4: 4602 mov r2, r0
8001ec6: 4b3c ldr r3, [pc, #240] @ (8001fb8 <Usage_PrintStats+0x224>)
8001ec8: 681b ldr r3, [r3, #0]
8001eca: 4621 mov r1, r4
8001ecc: 483b ldr r0, [pc, #236] @ (8001fbc <Usage_PrintStats+0x228>)
8001ece: f005 fdcd bl 8007a6c <iprintf>
Usage_SOL++;
8001ed2: 4b39 ldr r3, [pc, #228] @ (8001fb8 <Usage_PrintStats+0x224>)
8001ed4: 681b ldr r3, [r3, #0]
8001ed6: 3301 adds r3, #1
8001ed8: 4a37 ldr r2, [pc, #220] @ (8001fb8 <Usage_PrintStats+0x224>)
8001eda: 6013 str r3, [r2, #0]
for( x = 0; x < TaskCnt; x++ ) {
8001edc: 2300 movs r3, #0
8001ede: 623b str r3, [r7, #32]
8001ee0: e04a b.n 8001f78 <Usage_PrintStats+0x1e4>
TS = Usage_TaskStatusArraySort[ x ];
8001ee2: 4a30 ldr r2, [pc, #192] @ (8001fa4 <Usage_PrintStats+0x210>)
8001ee4: 6a3b ldr r3, [r7, #32]
8001ee6: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001eea: 607b str r3, [r7, #4]
DiffCounter = -1;
8001eec: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
8001ef0: 617b str r3, [r7, #20]
for( i = 0; i < TaskCnt; i++ ) {
8001ef2: 2300 movs r3, #0
8001ef4: 61fb str r3, [r7, #28]
8001ef6: e01d b.n 8001f34 <Usage_PrintStats+0x1a0>
if( TS->xTaskNumber == Usage_TaskStatusArrayPrev[ i ].xTaskNumber ) {
8001ef8: 687b ldr r3, [r7, #4]
8001efa: 6899 ldr r1, [r3, #8]
8001efc: 482b ldr r0, [pc, #172] @ (8001fac <Usage_PrintStats+0x218>)
8001efe: 69fa ldr r2, [r7, #28]
8001f00: 4613 mov r3, r2
8001f02: 00db lsls r3, r3, #3
8001f04: 4413 add r3, r2
8001f06: 009b lsls r3, r3, #2
8001f08: 4403 add r3, r0
8001f0a: 3308 adds r3, #8
8001f0c: 681b ldr r3, [r3, #0]
8001f0e: 4299 cmp r1, r3
8001f10: d10d bne.n 8001f2e <Usage_PrintStats+0x19a>
DiffCounter = TS->ulRunTimeCounter-Usage_TaskStatusArrayPrev[ i ].ulRunTimeCounter;
8001f12: 687b ldr r3, [r7, #4]
8001f14: 6999 ldr r1, [r3, #24]
8001f16: 4825 ldr r0, [pc, #148] @ (8001fac <Usage_PrintStats+0x218>)
8001f18: 69fa ldr r2, [r7, #28]
8001f1a: 4613 mov r3, r2
8001f1c: 00db lsls r3, r3, #3
8001f1e: 4413 add r3, r2
8001f20: 009b lsls r3, r3, #2
8001f22: 4403 add r3, r0
8001f24: 3318 adds r3, #24
8001f26: 681b ldr r3, [r3, #0]
8001f28: 1acb subs r3, r1, r3
8001f2a: 617b str r3, [r7, #20]
break;
8001f2c: e006 b.n 8001f3c <Usage_PrintStats+0x1a8>
for( i = 0; i < TaskCnt; i++ ) {
8001f2e: 69fb ldr r3, [r7, #28]
8001f30: 3301 adds r3, #1
8001f32: 61fb str r3, [r7, #28]
8001f34: 69fa ldr r2, [r7, #28]
8001f36: 6a7b ldr r3, [r7, #36] @ 0x24
8001f38: 429a cmp r2, r3
8001f3a: d3dd bcc.n 8001ef8 <Usage_PrintStats+0x164>
}
}
if( DiffCounter >= 0 ) {
8001f3c: 697b ldr r3, [r7, #20]
8001f3e: 2b00 cmp r3, #0
8001f40: db09 blt.n 8001f56 <Usage_PrintStats+0x1c2>
Usage = (DiffCounter) / TotalTimeDiff;
8001f42: 697a ldr r2, [r7, #20]
8001f44: 68bb ldr r3, [r7, #8]
8001f46: fbb2 f3f3 udiv r3, r2, r3
8001f4a: 613b str r3, [r7, #16]
if( Usage > 100 ) {
8001f4c: 693b ldr r3, [r7, #16]
8001f4e: 2b64 cmp r3, #100 @ 0x64
8001f50: d901 bls.n 8001f56 <Usage_PrintStats+0x1c2>
Usage = 100;
8001f52: 2364 movs r3, #100 @ 0x64
8001f54: 613b str r3, [r7, #16]
}
}
printf(" %2d: %-16s: CPU: %3u%%, free stack: %3u\n",
(int) TS->xTaskNumber, TS->pcTaskName, (int) Usage,
8001f56: 687b ldr r3, [r7, #4]
8001f58: 689b ldr r3, [r3, #8]
printf(" %2d: %-16s: CPU: %3u%%, free stack: %3u\n",
8001f5a: 4618 mov r0, r3
8001f5c: 687b ldr r3, [r7, #4]
8001f5e: 685a ldr r2, [r3, #4]
8001f60: 6939 ldr r1, [r7, #16]
TS->usStackHighWaterMark );
8001f62: 687b ldr r3, [r7, #4]
8001f64: 8c1b ldrh r3, [r3, #32]
printf(" %2d: %-16s: CPU: %3u%%, free stack: %3u\n",
8001f66: 9300 str r3, [sp, #0]
8001f68: 460b mov r3, r1
8001f6a: 4601 mov r1, r0
8001f6c: 4814 ldr r0, [pc, #80] @ (8001fc0 <Usage_PrintStats+0x22c>)
8001f6e: f005 fd7d bl 8007a6c <iprintf>
for( x = 0; x < TaskCnt; x++ ) {
8001f72: 6a3b ldr r3, [r7, #32]
8001f74: 3301 adds r3, #1
8001f76: 623b str r3, [r7, #32]
8001f78: 6a3a ldr r2, [r7, #32]
8001f7a: 6a7b ldr r3, [r7, #36] @ 0x24
8001f7c: 429a cmp r2, r3
8001f7e: d3b0 bcc.n 8001ee2 <Usage_PrintStats+0x14e>
}
}
memcpy(Usage_TaskStatusArrayPrev,Usage_TaskStatusArray,sizeof(Usage_TaskStatusArrayPrev));
8001f80: 4a0a ldr r2, [pc, #40] @ (8001fac <Usage_PrintStats+0x218>)
8001f82: 4b07 ldr r3, [pc, #28] @ (8001fa0 <Usage_PrintStats+0x20c>)
8001f84: 4610 mov r0, r2
8001f86: 4619 mov r1, r3
8001f88: f44f 7310 mov.w r3, #576 @ 0x240
8001f8c: 461a mov r2, r3
8001f8e: f005 fe9c bl 8007cca <memcpy>
Usage_TaskStatusTimePrev = TaskStatusTime;
8001f92: 683b ldr r3, [r7, #0]
8001f94: 4a06 ldr r2, [pc, #24] @ (8001fb0 <Usage_PrintStats+0x21c>)
8001f96: 6013 str r3, [r2, #0]
}
8001f98: bf00 nop
8001f9a: 372c adds r7, #44 @ 0x2c
8001f9c: 46bd mov sp, r7
8001f9e: bd90 pop {r4, r7, pc}
8001fa0: 200006cc .word 0x200006cc
8001fa4: 20000b4c .word 0x20000b4c
8001fa8: 08001d65 .word 0x08001d65
8001fac: 2000090c .word 0x2000090c
8001fb0: 20000b8c .word 0x20000b8c
8001fb4: 51eb851f .word 0x51eb851f
8001fb8: 20000b90 .word 0x20000b90
8001fbc: 08008954 .word 0x08008954
8001fc0: 08008990 .word 0x08008990
08001fc4 <Usage_Init>:
void Usage_Init(void)
{
8001fc4: b480 push {r7}
8001fc6: af00 add r7, sp, #0
// Use core tick timer (implemented in the data watchpoint and trace unit, available in STM32F4 only!)
//DEMCR |= (1<<24);
//DWT_CTRL |= (1<<0);
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
8001fc8: 4b09 ldr r3, [pc, #36] @ (8001ff0 <Usage_Init+0x2c>)
8001fca: 68db ldr r3, [r3, #12]
8001fcc: 4a08 ldr r2, [pc, #32] @ (8001ff0 <Usage_Init+0x2c>)
8001fce: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8001fd2: 60d3 str r3, [r2, #12]
DWT->CYCCNT = 0;
8001fd4: 4b07 ldr r3, [pc, #28] @ (8001ff4 <Usage_Init+0x30>)
8001fd6: 2200 movs r2, #0
8001fd8: 605a str r2, [r3, #4]
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
8001fda: 4b06 ldr r3, [pc, #24] @ (8001ff4 <Usage_Init+0x30>)
8001fdc: 681b ldr r3, [r3, #0]
8001fde: 4a05 ldr r2, [pc, #20] @ (8001ff4 <Usage_Init+0x30>)
8001fe0: f043 0301 orr.w r3, r3, #1
8001fe4: 6013 str r3, [r2, #0]
}
8001fe6: bf00 nop
8001fe8: 46bd mov sp, r7
8001fea: f85d 7b04 ldr.w r7, [sp], #4
8001fee: 4770 bx lr
8001ff0: e000edf0 .word 0xe000edf0
8001ff4: e0001000 .word 0xe0001000
08001ff8 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8001ff8: f8df d034 ldr.w sp, [pc, #52] @ 8002030 <LoopFillZerobss+0xe>
/* Call the clock system initialization function.*/
bl SystemInit
8001ffc: f7ff fe5e bl 8001cbc <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8002000: 480c ldr r0, [pc, #48] @ (8002034 <LoopFillZerobss+0x12>)
ldr r1, =_edata
8002002: 490d ldr r1, [pc, #52] @ (8002038 <LoopFillZerobss+0x16>)
ldr r2, =_sidata
8002004: 4a0d ldr r2, [pc, #52] @ (800203c <LoopFillZerobss+0x1a>)
movs r3, #0
8002006: 2300 movs r3, #0
b LoopCopyDataInit
8002008: e002 b.n 8002010 <LoopCopyDataInit>
0800200a <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
800200a: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
800200c: 50c4 str r4, [r0, r3]
adds r3, r3, #4
800200e: 3304 adds r3, #4
08002010 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8002010: 18c4 adds r4, r0, r3
cmp r4, r1
8002012: 428c cmp r4, r1
bcc CopyDataInit
8002014: d3f9 bcc.n 800200a <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8002016: 4a0a ldr r2, [pc, #40] @ (8002040 <LoopFillZerobss+0x1e>)
ldr r4, =_ebss
8002018: 4c0a ldr r4, [pc, #40] @ (8002044 <LoopFillZerobss+0x22>)
movs r3, #0
800201a: 2300 movs r3, #0
b LoopFillZerobss
800201c: e001 b.n 8002022 <LoopFillZerobss>
0800201e <FillZerobss>:
FillZerobss:
str r3, [r2]
800201e: 6013 str r3, [r2, #0]
adds r2, r2, #4
8002020: 3204 adds r2, #4
08002022 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8002022: 42a2 cmp r2, r4
bcc FillZerobss
8002024: d3fb bcc.n 800201e <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8002026: f005 fe29 bl 8007c7c <__libc_init_array>
/* Call the application's entry point.*/
bl main
800202a: f7fe fdf3 bl 8000c14 <main>
bx lr
800202e: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8002030: 20040000 .word 0x20040000
ldr r0, =_sdata
8002034: 20000000 .word 0x20000000
ldr r1, =_edata
8002038: 2000006c .word 0x2000006c
ldr r2, =_sidata
800203c: 08008a84 .word 0x08008a84
ldr r2, =_sbss
8002040: 2000006c .word 0x2000006c
ldr r4, =_ebss
8002044: 20008e38 .word 0x20008e38
08002048 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8002048: e7fe b.n 8002048 <ADC_IRQHandler>
0800204a <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
800204a: b580 push {r7, lr}
800204c: af00 add r7, sp, #0
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
800204e: 2003 movs r0, #3
8002050: f000 f8f9 bl 8002246 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8002054: 200f movs r0, #15
8002056: f7ff fd09 bl 8001a6c <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
800205a: f7ff fb73 bl 8001744 <HAL_MspInit>
/* Return function status */
return HAL_OK;
800205e: 2300 movs r3, #0
}
8002060: 4618 mov r0, r3
8002062: bd80 pop {r7, pc}
08002064 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8002064: b480 push {r7}
8002066: af00 add r7, sp, #0
uwTick += uwTickFreq;
8002068: 4b06 ldr r3, [pc, #24] @ (8002084 <HAL_IncTick+0x20>)
800206a: 781b ldrb r3, [r3, #0]
800206c: 461a mov r2, r3
800206e: 4b06 ldr r3, [pc, #24] @ (8002088 <HAL_IncTick+0x24>)
8002070: 681b ldr r3, [r3, #0]
8002072: 4413 add r3, r2
8002074: 4a04 ldr r2, [pc, #16] @ (8002088 <HAL_IncTick+0x24>)
8002076: 6013 str r3, [r2, #0]
}
8002078: bf00 nop
800207a: 46bd mov sp, r7
800207c: f85d 7b04 ldr.w r7, [sp], #4
8002080: 4770 bx lr
8002082: bf00 nop
8002084: 20000008 .word 0x20000008
8002088: 20000b94 .word 0x20000b94
0800208c <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
800208c: b480 push {r7}
800208e: af00 add r7, sp, #0
return uwTick;
8002090: 4b03 ldr r3, [pc, #12] @ (80020a0 <HAL_GetTick+0x14>)
8002092: 681b ldr r3, [r3, #0]
}
8002094: 4618 mov r0, r3
8002096: 46bd mov sp, r7
8002098: f85d 7b04 ldr.w r7, [sp], #4
800209c: 4770 bx lr
800209e: bf00 nop
80020a0: 20000b94 .word 0x20000b94
080020a4 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
80020a4: b580 push {r7, lr}
80020a6: b084 sub sp, #16
80020a8: af00 add r7, sp, #0
80020aa: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
80020ac: f7ff ffee bl 800208c <HAL_GetTick>
80020b0: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
80020b2: 687b ldr r3, [r7, #4]
80020b4: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
80020b6: 68fb ldr r3, [r7, #12]
80020b8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80020bc: d005 beq.n 80020ca <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
80020be: 4b0a ldr r3, [pc, #40] @ (80020e8 <HAL_Delay+0x44>)
80020c0: 781b ldrb r3, [r3, #0]
80020c2: 461a mov r2, r3
80020c4: 68fb ldr r3, [r7, #12]
80020c6: 4413 add r3, r2
80020c8: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
80020ca: bf00 nop
80020cc: f7ff ffde bl 800208c <HAL_GetTick>
80020d0: 4602 mov r2, r0
80020d2: 68bb ldr r3, [r7, #8]
80020d4: 1ad3 subs r3, r2, r3
80020d6: 68fa ldr r2, [r7, #12]
80020d8: 429a cmp r2, r3
80020da: d8f7 bhi.n 80020cc <HAL_Delay+0x28>
{
}
}
80020dc: bf00 nop
80020de: bf00 nop
80020e0: 3710 adds r7, #16
80020e2: 46bd mov sp, r7
80020e4: bd80 pop {r7, pc}
80020e6: bf00 nop
80020e8: 20000008 .word 0x20000008
080020ec <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80020ec: b480 push {r7}
80020ee: b085 sub sp, #20
80020f0: af00 add r7, sp, #0
80020f2: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80020f4: 687b ldr r3, [r7, #4]
80020f6: f003 0307 and.w r3, r3, #7
80020fa: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80020fc: 4b0b ldr r3, [pc, #44] @ (800212c <__NVIC_SetPriorityGrouping+0x40>)
80020fe: 68db ldr r3, [r3, #12]
8002100: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8002102: 68ba ldr r2, [r7, #8]
8002104: f64f 03ff movw r3, #63743 @ 0xf8ff
8002108: 4013 ands r3, r2
800210a: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
800210c: 68fb ldr r3, [r7, #12]
800210e: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8002110: 68bb ldr r3, [r7, #8]
8002112: 431a orrs r2, r3
reg_value = (reg_value |
8002114: 4b06 ldr r3, [pc, #24] @ (8002130 <__NVIC_SetPriorityGrouping+0x44>)
8002116: 4313 orrs r3, r2
8002118: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
800211a: 4a04 ldr r2, [pc, #16] @ (800212c <__NVIC_SetPriorityGrouping+0x40>)
800211c: 68bb ldr r3, [r7, #8]
800211e: 60d3 str r3, [r2, #12]
}
8002120: bf00 nop
8002122: 3714 adds r7, #20
8002124: 46bd mov sp, r7
8002126: f85d 7b04 ldr.w r7, [sp], #4
800212a: 4770 bx lr
800212c: e000ed00 .word 0xe000ed00
8002130: 05fa0000 .word 0x05fa0000
08002134 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8002134: b480 push {r7}
8002136: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8002138: 4b04 ldr r3, [pc, #16] @ (800214c <__NVIC_GetPriorityGrouping+0x18>)
800213a: 68db ldr r3, [r3, #12]
800213c: 0a1b lsrs r3, r3, #8
800213e: f003 0307 and.w r3, r3, #7
}
8002142: 4618 mov r0, r3
8002144: 46bd mov sp, r7
8002146: f85d 7b04 ldr.w r7, [sp], #4
800214a: 4770 bx lr
800214c: e000ed00 .word 0xe000ed00
08002150 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8002150: b480 push {r7}
8002152: b083 sub sp, #12
8002154: af00 add r7, sp, #0
8002156: 4603 mov r3, r0
8002158: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800215a: f997 3007 ldrsb.w r3, [r7, #7]
800215e: 2b00 cmp r3, #0
8002160: db0b blt.n 800217a <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8002162: 79fb ldrb r3, [r7, #7]
8002164: f003 021f and.w r2, r3, #31
8002168: 4907 ldr r1, [pc, #28] @ (8002188 <__NVIC_EnableIRQ+0x38>)
800216a: f997 3007 ldrsb.w r3, [r7, #7]
800216e: 095b lsrs r3, r3, #5
8002170: 2001 movs r0, #1
8002172: fa00 f202 lsl.w r2, r0, r2
8002176: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
800217a: bf00 nop
800217c: 370c adds r7, #12
800217e: 46bd mov sp, r7
8002180: f85d 7b04 ldr.w r7, [sp], #4
8002184: 4770 bx lr
8002186: bf00 nop
8002188: e000e100 .word 0xe000e100
0800218c <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
800218c: b480 push {r7}
800218e: b083 sub sp, #12
8002190: af00 add r7, sp, #0
8002192: 4603 mov r3, r0
8002194: 6039 str r1, [r7, #0]
8002196: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8002198: f997 3007 ldrsb.w r3, [r7, #7]
800219c: 2b00 cmp r3, #0
800219e: db0a blt.n 80021b6 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80021a0: 683b ldr r3, [r7, #0]
80021a2: b2da uxtb r2, r3
80021a4: 490c ldr r1, [pc, #48] @ (80021d8 <__NVIC_SetPriority+0x4c>)
80021a6: f997 3007 ldrsb.w r3, [r7, #7]
80021aa: 0112 lsls r2, r2, #4
80021ac: b2d2 uxtb r2, r2
80021ae: 440b add r3, r1
80021b0: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80021b4: e00a b.n 80021cc <__NVIC_SetPriority+0x40>
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80021b6: 683b ldr r3, [r7, #0]
80021b8: b2da uxtb r2, r3
80021ba: 4908 ldr r1, [pc, #32] @ (80021dc <__NVIC_SetPriority+0x50>)
80021bc: 79fb ldrb r3, [r7, #7]
80021be: f003 030f and.w r3, r3, #15
80021c2: 3b04 subs r3, #4
80021c4: 0112 lsls r2, r2, #4
80021c6: b2d2 uxtb r2, r2
80021c8: 440b add r3, r1
80021ca: 761a strb r2, [r3, #24]
}
80021cc: bf00 nop
80021ce: 370c adds r7, #12
80021d0: 46bd mov sp, r7
80021d2: f85d 7b04 ldr.w r7, [sp], #4
80021d6: 4770 bx lr
80021d8: e000e100 .word 0xe000e100
80021dc: e000ed00 .word 0xe000ed00
080021e0 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80021e0: b480 push {r7}
80021e2: b089 sub sp, #36 @ 0x24
80021e4: af00 add r7, sp, #0
80021e6: 60f8 str r0, [r7, #12]
80021e8: 60b9 str r1, [r7, #8]
80021ea: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80021ec: 68fb ldr r3, [r7, #12]
80021ee: f003 0307 and.w r3, r3, #7
80021f2: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80021f4: 69fb ldr r3, [r7, #28]
80021f6: f1c3 0307 rsb r3, r3, #7
80021fa: 2b04 cmp r3, #4
80021fc: bf28 it cs
80021fe: 2304 movcs r3, #4
8002200: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8002202: 69fb ldr r3, [r7, #28]
8002204: 3304 adds r3, #4
8002206: 2b06 cmp r3, #6
8002208: d902 bls.n 8002210 <NVIC_EncodePriority+0x30>
800220a: 69fb ldr r3, [r7, #28]
800220c: 3b03 subs r3, #3
800220e: e000 b.n 8002212 <NVIC_EncodePriority+0x32>
8002210: 2300 movs r3, #0
8002212: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8002214: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8002218: 69bb ldr r3, [r7, #24]
800221a: fa02 f303 lsl.w r3, r2, r3
800221e: 43da mvns r2, r3
8002220: 68bb ldr r3, [r7, #8]
8002222: 401a ands r2, r3
8002224: 697b ldr r3, [r7, #20]
8002226: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8002228: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
800222c: 697b ldr r3, [r7, #20]
800222e: fa01 f303 lsl.w r3, r1, r3
8002232: 43d9 mvns r1, r3
8002234: 687b ldr r3, [r7, #4]
8002236: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8002238: 4313 orrs r3, r2
);
}
800223a: 4618 mov r0, r3
800223c: 3724 adds r7, #36 @ 0x24
800223e: 46bd mov sp, r7
8002240: f85d 7b04 ldr.w r7, [sp], #4
8002244: 4770 bx lr
08002246 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8002246: b580 push {r7, lr}
8002248: b082 sub sp, #8
800224a: af00 add r7, sp, #0
800224c: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
800224e: 6878 ldr r0, [r7, #4]
8002250: f7ff ff4c bl 80020ec <__NVIC_SetPriorityGrouping>
}
8002254: bf00 nop
8002256: 3708 adds r7, #8
8002258: 46bd mov sp, r7
800225a: bd80 pop {r7, pc}
0800225c <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
800225c: b580 push {r7, lr}
800225e: b086 sub sp, #24
8002260: af00 add r7, sp, #0
8002262: 4603 mov r3, r0
8002264: 60b9 str r1, [r7, #8]
8002266: 607a str r2, [r7, #4]
8002268: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
800226a: 2300 movs r3, #0
800226c: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
800226e: f7ff ff61 bl 8002134 <__NVIC_GetPriorityGrouping>
8002272: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8002274: 687a ldr r2, [r7, #4]
8002276: 68b9 ldr r1, [r7, #8]
8002278: 6978 ldr r0, [r7, #20]
800227a: f7ff ffb1 bl 80021e0 <NVIC_EncodePriority>
800227e: 4602 mov r2, r0
8002280: f997 300f ldrsb.w r3, [r7, #15]
8002284: 4611 mov r1, r2
8002286: 4618 mov r0, r3
8002288: f7ff ff80 bl 800218c <__NVIC_SetPriority>
}
800228c: bf00 nop
800228e: 3718 adds r7, #24
8002290: 46bd mov sp, r7
8002292: bd80 pop {r7, pc}
08002294 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8002294: b580 push {r7, lr}
8002296: b082 sub sp, #8
8002298: af00 add r7, sp, #0
800229a: 4603 mov r3, r0
800229c: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
800229e: f997 3007 ldrsb.w r3, [r7, #7]
80022a2: 4618 mov r0, r3
80022a4: f7ff ff54 bl 8002150 <__NVIC_EnableIRQ>
}
80022a8: bf00 nop
80022aa: 3708 adds r7, #8
80022ac: 46bd mov sp, r7
80022ae: bd80 pop {r7, pc}
080022b0 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80022b0: b480 push {r7}
80022b2: b089 sub sp, #36 @ 0x24
80022b4: af00 add r7, sp, #0
80022b6: 6078 str r0, [r7, #4]
80022b8: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
80022ba: 2300 movs r3, #0
80022bc: 61fb str r3, [r7, #28]
uint32_t ioposition = 0x00;
80022be: 2300 movs r3, #0
80022c0: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
80022c2: 2300 movs r3, #0
80022c4: 613b str r3, [r7, #16]
uint32_t temp = 0x00;
80022c6: 2300 movs r3, #0
80022c8: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for (position = 0; position < GPIO_NUMBER; position++)
80022ca: 2300 movs r3, #0
80022cc: 61fb str r3, [r7, #28]
80022ce: e169 b.n 80025a4 <HAL_GPIO_Init+0x2f4>
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
80022d0: 2201 movs r2, #1
80022d2: 69fb ldr r3, [r7, #28]
80022d4: fa02 f303 lsl.w r3, r2, r3
80022d8: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
80022da: 683b ldr r3, [r7, #0]
80022dc: 681b ldr r3, [r3, #0]
80022de: 697a ldr r2, [r7, #20]
80022e0: 4013 ands r3, r2
80022e2: 613b str r3, [r7, #16]
if (iocurrent == ioposition)
80022e4: 693a ldr r2, [r7, #16]
80022e6: 697b ldr r3, [r7, #20]
80022e8: 429a cmp r2, r3
80022ea: f040 8158 bne.w 800259e <HAL_GPIO_Init+0x2ee>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
80022ee: 683b ldr r3, [r7, #0]
80022f0: 685b ldr r3, [r3, #4]
80022f2: f003 0303 and.w r3, r3, #3
80022f6: 2b01 cmp r3, #1
80022f8: d005 beq.n 8002306 <HAL_GPIO_Init+0x56>
80022fa: 683b ldr r3, [r7, #0]
80022fc: 685b ldr r3, [r3, #4]
80022fe: f003 0303 and.w r3, r3, #3
8002302: 2b02 cmp r3, #2
8002304: d130 bne.n 8002368 <HAL_GPIO_Init+0xb8>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8002306: 687b ldr r3, [r7, #4]
8002308: 689b ldr r3, [r3, #8]
800230a: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
800230c: 69fb ldr r3, [r7, #28]
800230e: 005b lsls r3, r3, #1
8002310: 2203 movs r2, #3
8002312: fa02 f303 lsl.w r3, r2, r3
8002316: 43db mvns r3, r3
8002318: 69ba ldr r2, [r7, #24]
800231a: 4013 ands r3, r2
800231c: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2));
800231e: 683b ldr r3, [r7, #0]
8002320: 68da ldr r2, [r3, #12]
8002322: 69fb ldr r3, [r7, #28]
8002324: 005b lsls r3, r3, #1
8002326: fa02 f303 lsl.w r3, r2, r3
800232a: 69ba ldr r2, [r7, #24]
800232c: 4313 orrs r3, r2
800232e: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8002330: 687b ldr r3, [r7, #4]
8002332: 69ba ldr r2, [r7, #24]
8002334: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8002336: 687b ldr r3, [r7, #4]
8002338: 685b ldr r3, [r3, #4]
800233a: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
800233c: 2201 movs r2, #1
800233e: 69fb ldr r3, [r7, #28]
8002340: fa02 f303 lsl.w r3, r2, r3
8002344: 43db mvns r3, r3
8002346: 69ba ldr r2, [r7, #24]
8002348: 4013 ands r3, r2
800234a: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
800234c: 683b ldr r3, [r7, #0]
800234e: 685b ldr r3, [r3, #4]
8002350: 091b lsrs r3, r3, #4
8002352: f003 0201 and.w r2, r3, #1
8002356: 69fb ldr r3, [r7, #28]
8002358: fa02 f303 lsl.w r3, r2, r3
800235c: 69ba ldr r2, [r7, #24]
800235e: 4313 orrs r3, r2
8002360: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
8002362: 687b ldr r3, [r7, #4]
8002364: 69ba ldr r2, [r7, #24]
8002366: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8002368: 683b ldr r3, [r7, #0]
800236a: 685b ldr r3, [r3, #4]
800236c: f003 0303 and.w r3, r3, #3
8002370: 2b03 cmp r3, #3
8002372: d017 beq.n 80023a4 <HAL_GPIO_Init+0xf4>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8002374: 687b ldr r3, [r7, #4]
8002376: 68db ldr r3, [r3, #12]
8002378: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
800237a: 69fb ldr r3, [r7, #28]
800237c: 005b lsls r3, r3, #1
800237e: 2203 movs r2, #3
8002380: fa02 f303 lsl.w r3, r2, r3
8002384: 43db mvns r3, r3
8002386: 69ba ldr r2, [r7, #24]
8002388: 4013 ands r3, r2
800238a: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2));
800238c: 683b ldr r3, [r7, #0]
800238e: 689a ldr r2, [r3, #8]
8002390: 69fb ldr r3, [r7, #28]
8002392: 005b lsls r3, r3, #1
8002394: fa02 f303 lsl.w r3, r2, r3
8002398: 69ba ldr r2, [r7, #24]
800239a: 4313 orrs r3, r2
800239c: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
800239e: 687b ldr r3, [r7, #4]
80023a0: 69ba ldr r2, [r7, #24]
80023a2: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80023a4: 683b ldr r3, [r7, #0]
80023a6: 685b ldr r3, [r3, #4]
80023a8: f003 0303 and.w r3, r3, #3
80023ac: 2b02 cmp r3, #2
80023ae: d123 bne.n 80023f8 <HAL_GPIO_Init+0x148>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
80023b0: 69fb ldr r3, [r7, #28]
80023b2: 08da lsrs r2, r3, #3
80023b4: 687b ldr r3, [r7, #4]
80023b6: 3208 adds r2, #8
80023b8: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80023bc: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
80023be: 69fb ldr r3, [r7, #28]
80023c0: f003 0307 and.w r3, r3, #7
80023c4: 009b lsls r3, r3, #2
80023c6: 220f movs r2, #15
80023c8: fa02 f303 lsl.w r3, r2, r3
80023cc: 43db mvns r3, r3
80023ce: 69ba ldr r2, [r7, #24]
80023d0: 4013 ands r3, r2
80023d2: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
80023d4: 683b ldr r3, [r7, #0]
80023d6: 691a ldr r2, [r3, #16]
80023d8: 69fb ldr r3, [r7, #28]
80023da: f003 0307 and.w r3, r3, #7
80023de: 009b lsls r3, r3, #2
80023e0: fa02 f303 lsl.w r3, r2, r3
80023e4: 69ba ldr r2, [r7, #24]
80023e6: 4313 orrs r3, r2
80023e8: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3] = temp;
80023ea: 69fb ldr r3, [r7, #28]
80023ec: 08da lsrs r2, r3, #3
80023ee: 687b ldr r3, [r7, #4]
80023f0: 3208 adds r2, #8
80023f2: 69b9 ldr r1, [r7, #24]
80023f4: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
80023f8: 687b ldr r3, [r7, #4]
80023fa: 681b ldr r3, [r3, #0]
80023fc: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
80023fe: 69fb ldr r3, [r7, #28]
8002400: 005b lsls r3, r3, #1
8002402: 2203 movs r2, #3
8002404: fa02 f303 lsl.w r3, r2, r3
8002408: 43db mvns r3, r3
800240a: 69ba ldr r2, [r7, #24]
800240c: 4013 ands r3, r2
800240e: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
8002410: 683b ldr r3, [r7, #0]
8002412: 685b ldr r3, [r3, #4]
8002414: f003 0203 and.w r2, r3, #3
8002418: 69fb ldr r3, [r7, #28]
800241a: 005b lsls r3, r3, #1
800241c: fa02 f303 lsl.w r3, r2, r3
8002420: 69ba ldr r2, [r7, #24]
8002422: 4313 orrs r3, r2
8002424: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8002426: 687b ldr r3, [r7, #4]
8002428: 69ba ldr r2, [r7, #24]
800242a: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
800242c: 683b ldr r3, [r7, #0]
800242e: 685b ldr r3, [r3, #4]
8002430: f403 3340 and.w r3, r3, #196608 @ 0x30000
8002434: 2b00 cmp r3, #0
8002436: f000 80b2 beq.w 800259e <HAL_GPIO_Init+0x2ee>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800243a: 4b60 ldr r3, [pc, #384] @ (80025bc <HAL_GPIO_Init+0x30c>)
800243c: 6c5b ldr r3, [r3, #68] @ 0x44
800243e: 4a5f ldr r2, [pc, #380] @ (80025bc <HAL_GPIO_Init+0x30c>)
8002440: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8002444: 6453 str r3, [r2, #68] @ 0x44
8002446: 4b5d ldr r3, [pc, #372] @ (80025bc <HAL_GPIO_Init+0x30c>)
8002448: 6c5b ldr r3, [r3, #68] @ 0x44
800244a: f403 4380 and.w r3, r3, #16384 @ 0x4000
800244e: 60fb str r3, [r7, #12]
8002450: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2];
8002452: 4a5b ldr r2, [pc, #364] @ (80025c0 <HAL_GPIO_Init+0x310>)
8002454: 69fb ldr r3, [r7, #28]
8002456: 089b lsrs r3, r3, #2
8002458: 3302 adds r3, #2
800245a: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800245e: 61bb str r3, [r7, #24]
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
8002460: 69fb ldr r3, [r7, #28]
8002462: f003 0303 and.w r3, r3, #3
8002466: 009b lsls r3, r3, #2
8002468: 220f movs r2, #15
800246a: fa02 f303 lsl.w r3, r2, r3
800246e: 43db mvns r3, r3
8002470: 69ba ldr r2, [r7, #24]
8002472: 4013 ands r3, r2
8002474: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
8002476: 687b ldr r3, [r7, #4]
8002478: 4a52 ldr r2, [pc, #328] @ (80025c4 <HAL_GPIO_Init+0x314>)
800247a: 4293 cmp r3, r2
800247c: d02b beq.n 80024d6 <HAL_GPIO_Init+0x226>
800247e: 687b ldr r3, [r7, #4]
8002480: 4a51 ldr r2, [pc, #324] @ (80025c8 <HAL_GPIO_Init+0x318>)
8002482: 4293 cmp r3, r2
8002484: d025 beq.n 80024d2 <HAL_GPIO_Init+0x222>
8002486: 687b ldr r3, [r7, #4]
8002488: 4a50 ldr r2, [pc, #320] @ (80025cc <HAL_GPIO_Init+0x31c>)
800248a: 4293 cmp r3, r2
800248c: d01f beq.n 80024ce <HAL_GPIO_Init+0x21e>
800248e: 687b ldr r3, [r7, #4]
8002490: 4a4f ldr r2, [pc, #316] @ (80025d0 <HAL_GPIO_Init+0x320>)
8002492: 4293 cmp r3, r2
8002494: d019 beq.n 80024ca <HAL_GPIO_Init+0x21a>
8002496: 687b ldr r3, [r7, #4]
8002498: 4a4e ldr r2, [pc, #312] @ (80025d4 <HAL_GPIO_Init+0x324>)
800249a: 4293 cmp r3, r2
800249c: d013 beq.n 80024c6 <HAL_GPIO_Init+0x216>
800249e: 687b ldr r3, [r7, #4]
80024a0: 4a4d ldr r2, [pc, #308] @ (80025d8 <HAL_GPIO_Init+0x328>)
80024a2: 4293 cmp r3, r2
80024a4: d00d beq.n 80024c2 <HAL_GPIO_Init+0x212>
80024a6: 687b ldr r3, [r7, #4]
80024a8: 4a4c ldr r2, [pc, #304] @ (80025dc <HAL_GPIO_Init+0x32c>)
80024aa: 4293 cmp r3, r2
80024ac: d007 beq.n 80024be <HAL_GPIO_Init+0x20e>
80024ae: 687b ldr r3, [r7, #4]
80024b0: 4a4b ldr r2, [pc, #300] @ (80025e0 <HAL_GPIO_Init+0x330>)
80024b2: 4293 cmp r3, r2
80024b4: d101 bne.n 80024ba <HAL_GPIO_Init+0x20a>
80024b6: 2307 movs r3, #7
80024b8: e00e b.n 80024d8 <HAL_GPIO_Init+0x228>
80024ba: 2308 movs r3, #8
80024bc: e00c b.n 80024d8 <HAL_GPIO_Init+0x228>
80024be: 2306 movs r3, #6
80024c0: e00a b.n 80024d8 <HAL_GPIO_Init+0x228>
80024c2: 2305 movs r3, #5
80024c4: e008 b.n 80024d8 <HAL_GPIO_Init+0x228>
80024c6: 2304 movs r3, #4
80024c8: e006 b.n 80024d8 <HAL_GPIO_Init+0x228>
80024ca: 2303 movs r3, #3
80024cc: e004 b.n 80024d8 <HAL_GPIO_Init+0x228>
80024ce: 2302 movs r3, #2
80024d0: e002 b.n 80024d8 <HAL_GPIO_Init+0x228>
80024d2: 2301 movs r3, #1
80024d4: e000 b.n 80024d8 <HAL_GPIO_Init+0x228>
80024d6: 2300 movs r3, #0
80024d8: 69fa ldr r2, [r7, #28]
80024da: f002 0203 and.w r2, r2, #3
80024de: 0092 lsls r2, r2, #2
80024e0: 4093 lsls r3, r2
80024e2: 69ba ldr r2, [r7, #24]
80024e4: 4313 orrs r3, r2
80024e6: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2] = temp;
80024e8: 4935 ldr r1, [pc, #212] @ (80025c0 <HAL_GPIO_Init+0x310>)
80024ea: 69fb ldr r3, [r7, #28]
80024ec: 089b lsrs r3, r3, #2
80024ee: 3302 adds r3, #2
80024f0: 69ba ldr r2, [r7, #24]
80024f2: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
80024f6: 4b3b ldr r3, [pc, #236] @ (80025e4 <HAL_GPIO_Init+0x334>)
80024f8: 689b ldr r3, [r3, #8]
80024fa: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80024fc: 693b ldr r3, [r7, #16]
80024fe: 43db mvns r3, r3
8002500: 69ba ldr r2, [r7, #24]
8002502: 4013 ands r3, r2
8002504: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8002506: 683b ldr r3, [r7, #0]
8002508: 685b ldr r3, [r3, #4]
800250a: f403 1380 and.w r3, r3, #1048576 @ 0x100000
800250e: 2b00 cmp r3, #0
8002510: d003 beq.n 800251a <HAL_GPIO_Init+0x26a>
{
temp |= iocurrent;
8002512: 69ba ldr r2, [r7, #24]
8002514: 693b ldr r3, [r7, #16]
8002516: 4313 orrs r3, r2
8002518: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
800251a: 4a32 ldr r2, [pc, #200] @ (80025e4 <HAL_GPIO_Init+0x334>)
800251c: 69bb ldr r3, [r7, #24]
800251e: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8002520: 4b30 ldr r3, [pc, #192] @ (80025e4 <HAL_GPIO_Init+0x334>)
8002522: 68db ldr r3, [r3, #12]
8002524: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8002526: 693b ldr r3, [r7, #16]
8002528: 43db mvns r3, r3
800252a: 69ba ldr r2, [r7, #24]
800252c: 4013 ands r3, r2
800252e: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8002530: 683b ldr r3, [r7, #0]
8002532: 685b ldr r3, [r3, #4]
8002534: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8002538: 2b00 cmp r3, #0
800253a: d003 beq.n 8002544 <HAL_GPIO_Init+0x294>
{
temp |= iocurrent;
800253c: 69ba ldr r2, [r7, #24]
800253e: 693b ldr r3, [r7, #16]
8002540: 4313 orrs r3, r2
8002542: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8002544: 4a27 ldr r2, [pc, #156] @ (80025e4 <HAL_GPIO_Init+0x334>)
8002546: 69bb ldr r3, [r7, #24]
8002548: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
800254a: 4b26 ldr r3, [pc, #152] @ (80025e4 <HAL_GPIO_Init+0x334>)
800254c: 685b ldr r3, [r3, #4]
800254e: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8002550: 693b ldr r3, [r7, #16]
8002552: 43db mvns r3, r3
8002554: 69ba ldr r2, [r7, #24]
8002556: 4013 ands r3, r2
8002558: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
800255a: 683b ldr r3, [r7, #0]
800255c: 685b ldr r3, [r3, #4]
800255e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002562: 2b00 cmp r3, #0
8002564: d003 beq.n 800256e <HAL_GPIO_Init+0x2be>
{
temp |= iocurrent;
8002566: 69ba ldr r2, [r7, #24]
8002568: 693b ldr r3, [r7, #16]
800256a: 4313 orrs r3, r2
800256c: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
800256e: 4a1d ldr r2, [pc, #116] @ (80025e4 <HAL_GPIO_Init+0x334>)
8002570: 69bb ldr r3, [r7, #24]
8002572: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8002574: 4b1b ldr r3, [pc, #108] @ (80025e4 <HAL_GPIO_Init+0x334>)
8002576: 681b ldr r3, [r3, #0]
8002578: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
800257a: 693b ldr r3, [r7, #16]
800257c: 43db mvns r3, r3
800257e: 69ba ldr r2, [r7, #24]
8002580: 4013 ands r3, r2
8002582: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8002584: 683b ldr r3, [r7, #0]
8002586: 685b ldr r3, [r3, #4]
8002588: f403 3380 and.w r3, r3, #65536 @ 0x10000
800258c: 2b00 cmp r3, #0
800258e: d003 beq.n 8002598 <HAL_GPIO_Init+0x2e8>
{
temp |= iocurrent;
8002590: 69ba ldr r2, [r7, #24]
8002592: 693b ldr r3, [r7, #16]
8002594: 4313 orrs r3, r2
8002596: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
8002598: 4a12 ldr r2, [pc, #72] @ (80025e4 <HAL_GPIO_Init+0x334>)
800259a: 69bb ldr r3, [r7, #24]
800259c: 6013 str r3, [r2, #0]
for (position = 0; position < GPIO_NUMBER; position++)
800259e: 69fb ldr r3, [r7, #28]
80025a0: 3301 adds r3, #1
80025a2: 61fb str r3, [r7, #28]
80025a4: 69fb ldr r3, [r7, #28]
80025a6: 2b0f cmp r3, #15
80025a8: f67f ae92 bls.w 80022d0 <HAL_GPIO_Init+0x20>
}
}
}
}
80025ac: bf00 nop
80025ae: bf00 nop
80025b0: 3724 adds r7, #36 @ 0x24
80025b2: 46bd mov sp, r7
80025b4: f85d 7b04 ldr.w r7, [sp], #4
80025b8: 4770 bx lr
80025ba: bf00 nop
80025bc: 40023800 .word 0x40023800
80025c0: 40013800 .word 0x40013800
80025c4: 40020000 .word 0x40020000
80025c8: 40020400 .word 0x40020400
80025cc: 40020800 .word 0x40020800
80025d0: 40020c00 .word 0x40020c00
80025d4: 40021000 .word 0x40021000
80025d8: 40021400 .word 0x40021400
80025dc: 40021800 .word 0x40021800
80025e0: 40021c00 .word 0x40021c00
80025e4: 40013c00 .word 0x40013c00
080025e8 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
80025e8: b480 push {r7}
80025ea: b085 sub sp, #20
80025ec: af00 add r7, sp, #0
80025ee: 6078 str r0, [r7, #4]
80025f0: 460b mov r3, r1
80025f2: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
80025f4: 687b ldr r3, [r7, #4]
80025f6: 691a ldr r2, [r3, #16]
80025f8: 887b ldrh r3, [r7, #2]
80025fa: 4013 ands r3, r2
80025fc: 2b00 cmp r3, #0
80025fe: d002 beq.n 8002606 <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8002600: 2301 movs r3, #1
8002602: 73fb strb r3, [r7, #15]
8002604: e001 b.n 800260a <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
8002606: 2300 movs r3, #0
8002608: 73fb strb r3, [r7, #15]
}
return bitstatus;
800260a: 7bfb ldrb r3, [r7, #15]
}
800260c: 4618 mov r0, r3
800260e: 3714 adds r7, #20
8002610: 46bd mov sp, r7
8002612: f85d 7b04 ldr.w r7, [sp], #4
8002616: 4770 bx lr
08002618 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8002618: b480 push {r7}
800261a: b083 sub sp, #12
800261c: af00 add r7, sp, #0
800261e: 6078 str r0, [r7, #4]
8002620: 460b mov r3, r1
8002622: 807b strh r3, [r7, #2]
8002624: 4613 mov r3, r2
8002626: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8002628: 787b ldrb r3, [r7, #1]
800262a: 2b00 cmp r3, #0
800262c: d003 beq.n 8002636 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
800262e: 887a ldrh r2, [r7, #2]
8002630: 687b ldr r3, [r7, #4]
8002632: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
}
}
8002634: e003 b.n 800263e <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
8002636: 887b ldrh r3, [r7, #2]
8002638: 041a lsls r2, r3, #16
800263a: 687b ldr r3, [r7, #4]
800263c: 619a str r2, [r3, #24]
}
800263e: bf00 nop
8002640: 370c adds r7, #12
8002642: 46bd mov sp, r7
8002644: f85d 7b04 ldr.w r7, [sp], #4
8002648: 4770 bx lr
0800264a <HAL_GPIO_TogglePin>:
* @param GPIO_Pin Specifies the pins to be toggled.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
800264a: b480 push {r7}
800264c: b085 sub sp, #20
800264e: af00 add r7, sp, #0
8002650: 6078 str r0, [r7, #4]
8002652: 460b mov r3, r1
8002654: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
8002656: 687b ldr r3, [r7, #4]
8002658: 695b ldr r3, [r3, #20]
800265a: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
800265c: 887a ldrh r2, [r7, #2]
800265e: 68fb ldr r3, [r7, #12]
8002660: 4013 ands r3, r2
8002662: 041a lsls r2, r3, #16
8002664: 68fb ldr r3, [r7, #12]
8002666: 43d9 mvns r1, r3
8002668: 887b ldrh r3, [r7, #2]
800266a: 400b ands r3, r1
800266c: 431a orrs r2, r3
800266e: 687b ldr r3, [r7, #4]
8002670: 619a str r2, [r3, #24]
}
8002672: bf00 nop
8002674: 3714 adds r7, #20
8002676: 46bd mov sp, r7
8002678: f85d 7b04 ldr.w r7, [sp], #4
800267c: 4770 bx lr
...
08002680 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8002680: b580 push {r7, lr}
8002682: b082 sub sp, #8
8002684: af00 add r7, sp, #0
8002686: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
8002688: 687b ldr r3, [r7, #4]
800268a: 2b00 cmp r3, #0
800268c: d101 bne.n 8002692 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
800268e: 2301 movs r3, #1
8002690: e08b b.n 80027aa <HAL_I2C_Init+0x12a>
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8002692: 687b ldr r3, [r7, #4]
8002694: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8002698: b2db uxtb r3, r3
800269a: 2b00 cmp r3, #0
800269c: d106 bne.n 80026ac <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
800269e: 687b ldr r3, [r7, #4]
80026a0: 2200 movs r2, #0
80026a2: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
80026a6: 6878 ldr r0, [r7, #4]
80026a8: f7ff f874 bl 8001794 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
80026ac: 687b ldr r3, [r7, #4]
80026ae: 2224 movs r2, #36 @ 0x24
80026b0: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
80026b4: 687b ldr r3, [r7, #4]
80026b6: 681b ldr r3, [r3, #0]
80026b8: 681a ldr r2, [r3, #0]
80026ba: 687b ldr r3, [r7, #4]
80026bc: 681b ldr r3, [r3, #0]
80026be: f022 0201 bic.w r2, r2, #1
80026c2: 601a str r2, [r3, #0]
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
80026c4: 687b ldr r3, [r7, #4]
80026c6: 685a ldr r2, [r3, #4]
80026c8: 687b ldr r3, [r7, #4]
80026ca: 681b ldr r3, [r3, #0]
80026cc: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000
80026d0: 611a str r2, [r3, #16]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
80026d2: 687b ldr r3, [r7, #4]
80026d4: 681b ldr r3, [r3, #0]
80026d6: 689a ldr r2, [r3, #8]
80026d8: 687b ldr r3, [r7, #4]
80026da: 681b ldr r3, [r3, #0]
80026dc: f422 4200 bic.w r2, r2, #32768 @ 0x8000
80026e0: 609a str r2, [r3, #8]
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
80026e2: 687b ldr r3, [r7, #4]
80026e4: 68db ldr r3, [r3, #12]
80026e6: 2b01 cmp r3, #1
80026e8: d107 bne.n 80026fa <HAL_I2C_Init+0x7a>
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
80026ea: 687b ldr r3, [r7, #4]
80026ec: 689a ldr r2, [r3, #8]
80026ee: 687b ldr r3, [r7, #4]
80026f0: 681b ldr r3, [r3, #0]
80026f2: f442 4200 orr.w r2, r2, #32768 @ 0x8000
80026f6: 609a str r2, [r3, #8]
80026f8: e006 b.n 8002708 <HAL_I2C_Init+0x88>
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
80026fa: 687b ldr r3, [r7, #4]
80026fc: 689a ldr r2, [r3, #8]
80026fe: 687b ldr r3, [r7, #4]
8002700: 681b ldr r3, [r3, #0]
8002702: f442 4204 orr.w r2, r2, #33792 @ 0x8400
8002706: 609a str r2, [r3, #8]
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
8002708: 687b ldr r3, [r7, #4]
800270a: 68db ldr r3, [r3, #12]
800270c: 2b02 cmp r3, #2
800270e: d108 bne.n 8002722 <HAL_I2C_Init+0xa2>
{
SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
8002710: 687b ldr r3, [r7, #4]
8002712: 681b ldr r3, [r3, #0]
8002714: 685a ldr r2, [r3, #4]
8002716: 687b ldr r3, [r7, #4]
8002718: 681b ldr r3, [r3, #0]
800271a: f442 6200 orr.w r2, r2, #2048 @ 0x800
800271e: 605a str r2, [r3, #4]
8002720: e007 b.n 8002732 <HAL_I2C_Init+0xb2>
}
else
{
/* Clear the I2C ADD10 bit */
CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
8002722: 687b ldr r3, [r7, #4]
8002724: 681b ldr r3, [r3, #0]
8002726: 685a ldr r2, [r3, #4]
8002728: 687b ldr r3, [r7, #4]
800272a: 681b ldr r3, [r3, #0]
800272c: f422 6200 bic.w r2, r2, #2048 @ 0x800
8002730: 605a str r2, [r3, #4]
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
8002732: 687b ldr r3, [r7, #4]
8002734: 681b ldr r3, [r3, #0]
8002736: 6859 ldr r1, [r3, #4]
8002738: 687b ldr r3, [r7, #4]
800273a: 681a ldr r2, [r3, #0]
800273c: 4b1d ldr r3, [pc, #116] @ (80027b4 <HAL_I2C_Init+0x134>)
800273e: 430b orrs r3, r1
8002740: 6053 str r3, [r2, #4]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
8002742: 687b ldr r3, [r7, #4]
8002744: 681b ldr r3, [r3, #0]
8002746: 68da ldr r2, [r3, #12]
8002748: 687b ldr r3, [r7, #4]
800274a: 681b ldr r3, [r3, #0]
800274c: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8002750: 60da str r2, [r3, #12]
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
8002752: 687b ldr r3, [r7, #4]
8002754: 691a ldr r2, [r3, #16]
8002756: 687b ldr r3, [r7, #4]
8002758: 695b ldr r3, [r3, #20]
800275a: ea42 0103 orr.w r1, r2, r3
(hi2c->Init.OwnAddress2Masks << 8));
800275e: 687b ldr r3, [r7, #4]
8002760: 699b ldr r3, [r3, #24]
8002762: 021a lsls r2, r3, #8
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
8002764: 687b ldr r3, [r7, #4]
8002766: 681b ldr r3, [r3, #0]
8002768: 430a orrs r2, r1
800276a: 60da str r2, [r3, #12]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
800276c: 687b ldr r3, [r7, #4]
800276e: 69d9 ldr r1, [r3, #28]
8002770: 687b ldr r3, [r7, #4]
8002772: 6a1a ldr r2, [r3, #32]
8002774: 687b ldr r3, [r7, #4]
8002776: 681b ldr r3, [r3, #0]
8002778: 430a orrs r2, r1
800277a: 601a str r2, [r3, #0]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
800277c: 687b ldr r3, [r7, #4]
800277e: 681b ldr r3, [r3, #0]
8002780: 681a ldr r2, [r3, #0]
8002782: 687b ldr r3, [r7, #4]
8002784: 681b ldr r3, [r3, #0]
8002786: f042 0201 orr.w r2, r2, #1
800278a: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
800278c: 687b ldr r3, [r7, #4]
800278e: 2200 movs r2, #0
8002790: 645a str r2, [r3, #68] @ 0x44
hi2c->State = HAL_I2C_STATE_READY;
8002792: 687b ldr r3, [r7, #4]
8002794: 2220 movs r2, #32
8002796: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_NONE;
800279a: 687b ldr r3, [r7, #4]
800279c: 2200 movs r2, #0
800279e: 631a str r2, [r3, #48] @ 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
80027a0: 687b ldr r3, [r7, #4]
80027a2: 2200 movs r2, #0
80027a4: f883 2042 strb.w r2, [r3, #66] @ 0x42
return HAL_OK;
80027a8: 2300 movs r3, #0
}
80027aa: 4618 mov r0, r3
80027ac: 3708 adds r7, #8
80027ae: 46bd mov sp, r7
80027b0: bd80 pop {r7, pc}
80027b2: bf00 nop
80027b4: 02008000 .word 0x02008000
080027b8 <HAL_I2CEx_ConfigAnalogFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
80027b8: b480 push {r7}
80027ba: b083 sub sp, #12
80027bc: af00 add r7, sp, #0
80027be: 6078 str r0, [r7, #4]
80027c0: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
80027c2: 687b ldr r3, [r7, #4]
80027c4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
80027c8: b2db uxtb r3, r3
80027ca: 2b20 cmp r3, #32
80027cc: d138 bne.n 8002840 <HAL_I2CEx_ConfigAnalogFilter+0x88>
{
/* Process Locked */
__HAL_LOCK(hi2c);
80027ce: 687b ldr r3, [r7, #4]
80027d0: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
80027d4: 2b01 cmp r3, #1
80027d6: d101 bne.n 80027dc <HAL_I2CEx_ConfigAnalogFilter+0x24>
80027d8: 2302 movs r3, #2
80027da: e032 b.n 8002842 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
80027dc: 687b ldr r3, [r7, #4]
80027de: 2201 movs r2, #1
80027e0: f883 2040 strb.w r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
80027e4: 687b ldr r3, [r7, #4]
80027e6: 2224 movs r2, #36 @ 0x24
80027e8: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
80027ec: 687b ldr r3, [r7, #4]
80027ee: 681b ldr r3, [r3, #0]
80027f0: 681a ldr r2, [r3, #0]
80027f2: 687b ldr r3, [r7, #4]
80027f4: 681b ldr r3, [r3, #0]
80027f6: f022 0201 bic.w r2, r2, #1
80027fa: 601a str r2, [r3, #0]
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
80027fc: 687b ldr r3, [r7, #4]
80027fe: 681b ldr r3, [r3, #0]
8002800: 681a ldr r2, [r3, #0]
8002802: 687b ldr r3, [r7, #4]
8002804: 681b ldr r3, [r3, #0]
8002806: f422 5280 bic.w r2, r2, #4096 @ 0x1000
800280a: 601a str r2, [r3, #0]
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
800280c: 687b ldr r3, [r7, #4]
800280e: 681b ldr r3, [r3, #0]
8002810: 6819 ldr r1, [r3, #0]
8002812: 687b ldr r3, [r7, #4]
8002814: 681b ldr r3, [r3, #0]
8002816: 683a ldr r2, [r7, #0]
8002818: 430a orrs r2, r1
800281a: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
800281c: 687b ldr r3, [r7, #4]
800281e: 681b ldr r3, [r3, #0]
8002820: 681a ldr r2, [r3, #0]
8002822: 687b ldr r3, [r7, #4]
8002824: 681b ldr r3, [r3, #0]
8002826: f042 0201 orr.w r2, r2, #1
800282a: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
800282c: 687b ldr r3, [r7, #4]
800282e: 2220 movs r2, #32
8002830: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8002834: 687b ldr r3, [r7, #4]
8002836: 2200 movs r2, #0
8002838: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
800283c: 2300 movs r3, #0
800283e: e000 b.n 8002842 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
}
else
{
return HAL_BUSY;
8002840: 2302 movs r3, #2
}
}
8002842: 4618 mov r0, r3
8002844: 370c adds r7, #12
8002846: 46bd mov sp, r7
8002848: f85d 7b04 ldr.w r7, [sp], #4
800284c: 4770 bx lr
0800284e <HAL_I2CEx_ConfigDigitalFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
800284e: b480 push {r7}
8002850: b085 sub sp, #20
8002852: af00 add r7, sp, #0
8002854: 6078 str r0, [r7, #4]
8002856: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
8002858: 687b ldr r3, [r7, #4]
800285a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800285e: b2db uxtb r3, r3
8002860: 2b20 cmp r3, #32
8002862: d139 bne.n 80028d8 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8002864: 687b ldr r3, [r7, #4]
8002866: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
800286a: 2b01 cmp r3, #1
800286c: d101 bne.n 8002872 <HAL_I2CEx_ConfigDigitalFilter+0x24>
800286e: 2302 movs r3, #2
8002870: e033 b.n 80028da <HAL_I2CEx_ConfigDigitalFilter+0x8c>
8002872: 687b ldr r3, [r7, #4]
8002874: 2201 movs r2, #1
8002876: f883 2040 strb.w r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
800287a: 687b ldr r3, [r7, #4]
800287c: 2224 movs r2, #36 @ 0x24
800287e: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8002882: 687b ldr r3, [r7, #4]
8002884: 681b ldr r3, [r3, #0]
8002886: 681a ldr r2, [r3, #0]
8002888: 687b ldr r3, [r7, #4]
800288a: 681b ldr r3, [r3, #0]
800288c: f022 0201 bic.w r2, r2, #1
8002890: 601a str r2, [r3, #0]
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
8002892: 687b ldr r3, [r7, #4]
8002894: 681b ldr r3, [r3, #0]
8002896: 681b ldr r3, [r3, #0]
8002898: 60fb str r3, [r7, #12]
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
800289a: 68fb ldr r3, [r7, #12]
800289c: f423 6370 bic.w r3, r3, #3840 @ 0xf00
80028a0: 60fb str r3, [r7, #12]
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
80028a2: 683b ldr r3, [r7, #0]
80028a4: 021b lsls r3, r3, #8
80028a6: 68fa ldr r2, [r7, #12]
80028a8: 4313 orrs r3, r2
80028aa: 60fb str r3, [r7, #12]
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
80028ac: 687b ldr r3, [r7, #4]
80028ae: 681b ldr r3, [r3, #0]
80028b0: 68fa ldr r2, [r7, #12]
80028b2: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
80028b4: 687b ldr r3, [r7, #4]
80028b6: 681b ldr r3, [r3, #0]
80028b8: 681a ldr r2, [r3, #0]
80028ba: 687b ldr r3, [r7, #4]
80028bc: 681b ldr r3, [r3, #0]
80028be: f042 0201 orr.w r2, r2, #1
80028c2: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
80028c4: 687b ldr r3, [r7, #4]
80028c6: 2220 movs r2, #32
80028c8: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80028cc: 687b ldr r3, [r7, #4]
80028ce: 2200 movs r2, #0
80028d0: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
80028d4: 2300 movs r3, #0
80028d6: e000 b.n 80028da <HAL_I2CEx_ConfigDigitalFilter+0x8c>
}
else
{
return HAL_BUSY;
80028d8: 2302 movs r3, #2
}
}
80028da: 4618 mov r0, r3
80028dc: 3714 adds r7, #20
80028de: 46bd mov sp, r7
80028e0: f85d 7b04 ldr.w r7, [sp], #4
80028e4: 4770 bx lr
...
080028e8 <HAL_PWR_EnableBkUpAccess>:
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
80028e8: b480 push {r7}
80028ea: af00 add r7, sp, #0
/* Enable access to RTC and backup registers */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
80028ec: 4b05 ldr r3, [pc, #20] @ (8002904 <HAL_PWR_EnableBkUpAccess+0x1c>)
80028ee: 681b ldr r3, [r3, #0]
80028f0: 4a04 ldr r2, [pc, #16] @ (8002904 <HAL_PWR_EnableBkUpAccess+0x1c>)
80028f2: f443 7380 orr.w r3, r3, #256 @ 0x100
80028f6: 6013 str r3, [r2, #0]
}
80028f8: bf00 nop
80028fa: 46bd mov sp, r7
80028fc: f85d 7b04 ldr.w r7, [sp], #4
8002900: 4770 bx lr
8002902: bf00 nop
8002904: 40007000 .word 0x40007000
08002908 <HAL_PWREx_EnableOverDrive>:
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
{
8002908: b580 push {r7, lr}
800290a: b082 sub sp, #8
800290c: af00 add r7, sp, #0
uint32_t tickstart = 0;
800290e: 2300 movs r3, #0
8002910: 607b str r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8002912: 4b23 ldr r3, [pc, #140] @ (80029a0 <HAL_PWREx_EnableOverDrive+0x98>)
8002914: 6c1b ldr r3, [r3, #64] @ 0x40
8002916: 4a22 ldr r2, [pc, #136] @ (80029a0 <HAL_PWREx_EnableOverDrive+0x98>)
8002918: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800291c: 6413 str r3, [r2, #64] @ 0x40
800291e: 4b20 ldr r3, [pc, #128] @ (80029a0 <HAL_PWREx_EnableOverDrive+0x98>)
8002920: 6c1b ldr r3, [r3, #64] @ 0x40
8002922: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002926: 603b str r3, [r7, #0]
8002928: 683b ldr r3, [r7, #0]
/* Enable the Over-drive to extend the clock frequency to 216 MHz */
__HAL_PWR_OVERDRIVE_ENABLE();
800292a: 4b1e ldr r3, [pc, #120] @ (80029a4 <HAL_PWREx_EnableOverDrive+0x9c>)
800292c: 681b ldr r3, [r3, #0]
800292e: 4a1d ldr r2, [pc, #116] @ (80029a4 <HAL_PWREx_EnableOverDrive+0x9c>)
8002930: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002934: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8002936: f7ff fba9 bl 800208c <HAL_GetTick>
800293a: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
800293c: e009 b.n 8002952 <HAL_PWREx_EnableOverDrive+0x4a>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
800293e: f7ff fba5 bl 800208c <HAL_GetTick>
8002942: 4602 mov r2, r0
8002944: 687b ldr r3, [r7, #4]
8002946: 1ad3 subs r3, r2, r3
8002948: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
800294c: d901 bls.n 8002952 <HAL_PWREx_EnableOverDrive+0x4a>
{
return HAL_TIMEOUT;
800294e: 2303 movs r3, #3
8002950: e022 b.n 8002998 <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
8002952: 4b14 ldr r3, [pc, #80] @ (80029a4 <HAL_PWREx_EnableOverDrive+0x9c>)
8002954: 685b ldr r3, [r3, #4]
8002956: f403 3380 and.w r3, r3, #65536 @ 0x10000
800295a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
800295e: d1ee bne.n 800293e <HAL_PWREx_EnableOverDrive+0x36>
}
}
/* Enable the Over-drive switch */
__HAL_PWR_OVERDRIVESWITCHING_ENABLE();
8002960: 4b10 ldr r3, [pc, #64] @ (80029a4 <HAL_PWREx_EnableOverDrive+0x9c>)
8002962: 681b ldr r3, [r3, #0]
8002964: 4a0f ldr r2, [pc, #60] @ (80029a4 <HAL_PWREx_EnableOverDrive+0x9c>)
8002966: f443 3300 orr.w r3, r3, #131072 @ 0x20000
800296a: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
800296c: f7ff fb8e bl 800208c <HAL_GetTick>
8002970: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
8002972: e009 b.n 8002988 <HAL_PWREx_EnableOverDrive+0x80>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8002974: f7ff fb8a bl 800208c <HAL_GetTick>
8002978: 4602 mov r2, r0
800297a: 687b ldr r3, [r7, #4]
800297c: 1ad3 subs r3, r2, r3
800297e: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
8002982: d901 bls.n 8002988 <HAL_PWREx_EnableOverDrive+0x80>
{
return HAL_TIMEOUT;
8002984: 2303 movs r3, #3
8002986: e007 b.n 8002998 <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
8002988: 4b06 ldr r3, [pc, #24] @ (80029a4 <HAL_PWREx_EnableOverDrive+0x9c>)
800298a: 685b ldr r3, [r3, #4]
800298c: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002990: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
8002994: d1ee bne.n 8002974 <HAL_PWREx_EnableOverDrive+0x6c>
}
}
return HAL_OK;
8002996: 2300 movs r3, #0
}
8002998: 4618 mov r0, r3
800299a: 3708 adds r7, #8
800299c: 46bd mov sp, r7
800299e: bd80 pop {r7, pc}
80029a0: 40023800 .word 0x40023800
80029a4: 40007000 .word 0x40007000
080029a8 <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80029a8: b580 push {r7, lr}
80029aa: b086 sub sp, #24
80029ac: af00 add r7, sp, #0
80029ae: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
FlagStatus pwrclkchanged = RESET;
80029b0: 2300 movs r3, #0
80029b2: 75fb strb r3, [r7, #23]
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
80029b4: 687b ldr r3, [r7, #4]
80029b6: 2b00 cmp r3, #0
80029b8: d101 bne.n 80029be <HAL_RCC_OscConfig+0x16>
{
return HAL_ERROR;
80029ba: 2301 movs r3, #1
80029bc: e291 b.n 8002ee2 <HAL_RCC_OscConfig+0x53a>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80029be: 687b ldr r3, [r7, #4]
80029c0: 681b ldr r3, [r3, #0]
80029c2: f003 0301 and.w r3, r3, #1
80029c6: 2b00 cmp r3, #0
80029c8: f000 8087 beq.w 8002ada <HAL_RCC_OscConfig+0x132>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
80029cc: 4b96 ldr r3, [pc, #600] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
80029ce: 689b ldr r3, [r3, #8]
80029d0: f003 030c and.w r3, r3, #12
80029d4: 2b04 cmp r3, #4
80029d6: d00c beq.n 80029f2 <HAL_RCC_OscConfig+0x4a>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
80029d8: 4b93 ldr r3, [pc, #588] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
80029da: 689b ldr r3, [r3, #8]
80029dc: f003 030c and.w r3, r3, #12
80029e0: 2b08 cmp r3, #8
80029e2: d112 bne.n 8002a0a <HAL_RCC_OscConfig+0x62>
80029e4: 4b90 ldr r3, [pc, #576] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
80029e6: 685b ldr r3, [r3, #4]
80029e8: f403 0380 and.w r3, r3, #4194304 @ 0x400000
80029ec: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
80029f0: d10b bne.n 8002a0a <HAL_RCC_OscConfig+0x62>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80029f2: 4b8d ldr r3, [pc, #564] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
80029f4: 681b ldr r3, [r3, #0]
80029f6: f403 3300 and.w r3, r3, #131072 @ 0x20000
80029fa: 2b00 cmp r3, #0
80029fc: d06c beq.n 8002ad8 <HAL_RCC_OscConfig+0x130>
80029fe: 687b ldr r3, [r7, #4]
8002a00: 685b ldr r3, [r3, #4]
8002a02: 2b00 cmp r3, #0
8002a04: d168 bne.n 8002ad8 <HAL_RCC_OscConfig+0x130>
{
return HAL_ERROR;
8002a06: 2301 movs r3, #1
8002a08: e26b b.n 8002ee2 <HAL_RCC_OscConfig+0x53a>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8002a0a: 687b ldr r3, [r7, #4]
8002a0c: 685b ldr r3, [r3, #4]
8002a0e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8002a12: d106 bne.n 8002a22 <HAL_RCC_OscConfig+0x7a>
8002a14: 4b84 ldr r3, [pc, #528] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002a16: 681b ldr r3, [r3, #0]
8002a18: 4a83 ldr r2, [pc, #524] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002a1a: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002a1e: 6013 str r3, [r2, #0]
8002a20: e02e b.n 8002a80 <HAL_RCC_OscConfig+0xd8>
8002a22: 687b ldr r3, [r7, #4]
8002a24: 685b ldr r3, [r3, #4]
8002a26: 2b00 cmp r3, #0
8002a28: d10c bne.n 8002a44 <HAL_RCC_OscConfig+0x9c>
8002a2a: 4b7f ldr r3, [pc, #508] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002a2c: 681b ldr r3, [r3, #0]
8002a2e: 4a7e ldr r2, [pc, #504] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002a30: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8002a34: 6013 str r3, [r2, #0]
8002a36: 4b7c ldr r3, [pc, #496] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002a38: 681b ldr r3, [r3, #0]
8002a3a: 4a7b ldr r2, [pc, #492] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002a3c: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8002a40: 6013 str r3, [r2, #0]
8002a42: e01d b.n 8002a80 <HAL_RCC_OscConfig+0xd8>
8002a44: 687b ldr r3, [r7, #4]
8002a46: 685b ldr r3, [r3, #4]
8002a48: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8002a4c: d10c bne.n 8002a68 <HAL_RCC_OscConfig+0xc0>
8002a4e: 4b76 ldr r3, [pc, #472] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002a50: 681b ldr r3, [r3, #0]
8002a52: 4a75 ldr r2, [pc, #468] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002a54: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8002a58: 6013 str r3, [r2, #0]
8002a5a: 4b73 ldr r3, [pc, #460] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002a5c: 681b ldr r3, [r3, #0]
8002a5e: 4a72 ldr r2, [pc, #456] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002a60: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002a64: 6013 str r3, [r2, #0]
8002a66: e00b b.n 8002a80 <HAL_RCC_OscConfig+0xd8>
8002a68: 4b6f ldr r3, [pc, #444] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002a6a: 681b ldr r3, [r3, #0]
8002a6c: 4a6e ldr r2, [pc, #440] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002a6e: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8002a72: 6013 str r3, [r2, #0]
8002a74: 4b6c ldr r3, [pc, #432] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002a76: 681b ldr r3, [r3, #0]
8002a78: 4a6b ldr r2, [pc, #428] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002a7a: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8002a7e: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8002a80: 687b ldr r3, [r7, #4]
8002a82: 685b ldr r3, [r3, #4]
8002a84: 2b00 cmp r3, #0
8002a86: d013 beq.n 8002ab0 <HAL_RCC_OscConfig+0x108>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002a88: f7ff fb00 bl 800208c <HAL_GetTick>
8002a8c: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002a8e: e008 b.n 8002aa2 <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8002a90: f7ff fafc bl 800208c <HAL_GetTick>
8002a94: 4602 mov r2, r0
8002a96: 693b ldr r3, [r7, #16]
8002a98: 1ad3 subs r3, r2, r3
8002a9a: 2b64 cmp r3, #100 @ 0x64
8002a9c: d901 bls.n 8002aa2 <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
8002a9e: 2303 movs r3, #3
8002aa0: e21f b.n 8002ee2 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002aa2: 4b61 ldr r3, [pc, #388] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002aa4: 681b ldr r3, [r3, #0]
8002aa6: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002aaa: 2b00 cmp r3, #0
8002aac: d0f0 beq.n 8002a90 <HAL_RCC_OscConfig+0xe8>
8002aae: e014 b.n 8002ada <HAL_RCC_OscConfig+0x132>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002ab0: f7ff faec bl 800208c <HAL_GetTick>
8002ab4: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8002ab6: e008 b.n 8002aca <HAL_RCC_OscConfig+0x122>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8002ab8: f7ff fae8 bl 800208c <HAL_GetTick>
8002abc: 4602 mov r2, r0
8002abe: 693b ldr r3, [r7, #16]
8002ac0: 1ad3 subs r3, r2, r3
8002ac2: 2b64 cmp r3, #100 @ 0x64
8002ac4: d901 bls.n 8002aca <HAL_RCC_OscConfig+0x122>
{
return HAL_TIMEOUT;
8002ac6: 2303 movs r3, #3
8002ac8: e20b b.n 8002ee2 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8002aca: 4b57 ldr r3, [pc, #348] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002acc: 681b ldr r3, [r3, #0]
8002ace: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002ad2: 2b00 cmp r3, #0
8002ad4: d1f0 bne.n 8002ab8 <HAL_RCC_OscConfig+0x110>
8002ad6: e000 b.n 8002ada <HAL_RCC_OscConfig+0x132>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002ad8: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8002ada: 687b ldr r3, [r7, #4]
8002adc: 681b ldr r3, [r3, #0]
8002ade: f003 0302 and.w r3, r3, #2
8002ae2: 2b00 cmp r3, #0
8002ae4: d069 beq.n 8002bba <HAL_RCC_OscConfig+0x212>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8002ae6: 4b50 ldr r3, [pc, #320] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002ae8: 689b ldr r3, [r3, #8]
8002aea: f003 030c and.w r3, r3, #12
8002aee: 2b00 cmp r3, #0
8002af0: d00b beq.n 8002b0a <HAL_RCC_OscConfig+0x162>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
8002af2: 4b4d ldr r3, [pc, #308] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002af4: 689b ldr r3, [r3, #8]
8002af6: f003 030c and.w r3, r3, #12
8002afa: 2b08 cmp r3, #8
8002afc: d11c bne.n 8002b38 <HAL_RCC_OscConfig+0x190>
8002afe: 4b4a ldr r3, [pc, #296] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002b00: 685b ldr r3, [r3, #4]
8002b02: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8002b06: 2b00 cmp r3, #0
8002b08: d116 bne.n 8002b38 <HAL_RCC_OscConfig+0x190>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002b0a: 4b47 ldr r3, [pc, #284] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002b0c: 681b ldr r3, [r3, #0]
8002b0e: f003 0302 and.w r3, r3, #2
8002b12: 2b00 cmp r3, #0
8002b14: d005 beq.n 8002b22 <HAL_RCC_OscConfig+0x17a>
8002b16: 687b ldr r3, [r7, #4]
8002b18: 68db ldr r3, [r3, #12]
8002b1a: 2b01 cmp r3, #1
8002b1c: d001 beq.n 8002b22 <HAL_RCC_OscConfig+0x17a>
{
return HAL_ERROR;
8002b1e: 2301 movs r3, #1
8002b20: e1df b.n 8002ee2 <HAL_RCC_OscConfig+0x53a>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002b22: 4b41 ldr r3, [pc, #260] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002b24: 681b ldr r3, [r3, #0]
8002b26: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8002b2a: 687b ldr r3, [r7, #4]
8002b2c: 691b ldr r3, [r3, #16]
8002b2e: 00db lsls r3, r3, #3
8002b30: 493d ldr r1, [pc, #244] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002b32: 4313 orrs r3, r2
8002b34: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002b36: e040 b.n 8002bba <HAL_RCC_OscConfig+0x212>
}
}
else
{
/* Check the HSI State */
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
8002b38: 687b ldr r3, [r7, #4]
8002b3a: 68db ldr r3, [r3, #12]
8002b3c: 2b00 cmp r3, #0
8002b3e: d023 beq.n 8002b88 <HAL_RCC_OscConfig+0x1e0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8002b40: 4b39 ldr r3, [pc, #228] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002b42: 681b ldr r3, [r3, #0]
8002b44: 4a38 ldr r2, [pc, #224] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002b46: f043 0301 orr.w r3, r3, #1
8002b4a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002b4c: f7ff fa9e bl 800208c <HAL_GetTick>
8002b50: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002b52: e008 b.n 8002b66 <HAL_RCC_OscConfig+0x1be>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8002b54: f7ff fa9a bl 800208c <HAL_GetTick>
8002b58: 4602 mov r2, r0
8002b5a: 693b ldr r3, [r7, #16]
8002b5c: 1ad3 subs r3, r2, r3
8002b5e: 2b02 cmp r3, #2
8002b60: d901 bls.n 8002b66 <HAL_RCC_OscConfig+0x1be>
{
return HAL_TIMEOUT;
8002b62: 2303 movs r3, #3
8002b64: e1bd b.n 8002ee2 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002b66: 4b30 ldr r3, [pc, #192] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002b68: 681b ldr r3, [r3, #0]
8002b6a: f003 0302 and.w r3, r3, #2
8002b6e: 2b00 cmp r3, #0
8002b70: d0f0 beq.n 8002b54 <HAL_RCC_OscConfig+0x1ac>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002b72: 4b2d ldr r3, [pc, #180] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002b74: 681b ldr r3, [r3, #0]
8002b76: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8002b7a: 687b ldr r3, [r7, #4]
8002b7c: 691b ldr r3, [r3, #16]
8002b7e: 00db lsls r3, r3, #3
8002b80: 4929 ldr r1, [pc, #164] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002b82: 4313 orrs r3, r2
8002b84: 600b str r3, [r1, #0]
8002b86: e018 b.n 8002bba <HAL_RCC_OscConfig+0x212>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8002b88: 4b27 ldr r3, [pc, #156] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002b8a: 681b ldr r3, [r3, #0]
8002b8c: 4a26 ldr r2, [pc, #152] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002b8e: f023 0301 bic.w r3, r3, #1
8002b92: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002b94: f7ff fa7a bl 800208c <HAL_GetTick>
8002b98: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8002b9a: e008 b.n 8002bae <HAL_RCC_OscConfig+0x206>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8002b9c: f7ff fa76 bl 800208c <HAL_GetTick>
8002ba0: 4602 mov r2, r0
8002ba2: 693b ldr r3, [r7, #16]
8002ba4: 1ad3 subs r3, r2, r3
8002ba6: 2b02 cmp r3, #2
8002ba8: d901 bls.n 8002bae <HAL_RCC_OscConfig+0x206>
{
return HAL_TIMEOUT;
8002baa: 2303 movs r3, #3
8002bac: e199 b.n 8002ee2 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8002bae: 4b1e ldr r3, [pc, #120] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002bb0: 681b ldr r3, [r3, #0]
8002bb2: f003 0302 and.w r3, r3, #2
8002bb6: 2b00 cmp r3, #0
8002bb8: d1f0 bne.n 8002b9c <HAL_RCC_OscConfig+0x1f4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8002bba: 687b ldr r3, [r7, #4]
8002bbc: 681b ldr r3, [r3, #0]
8002bbe: f003 0308 and.w r3, r3, #8
8002bc2: 2b00 cmp r3, #0
8002bc4: d038 beq.n 8002c38 <HAL_RCC_OscConfig+0x290>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
8002bc6: 687b ldr r3, [r7, #4]
8002bc8: 695b ldr r3, [r3, #20]
8002bca: 2b00 cmp r3, #0
8002bcc: d019 beq.n 8002c02 <HAL_RCC_OscConfig+0x25a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8002bce: 4b16 ldr r3, [pc, #88] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002bd0: 6f5b ldr r3, [r3, #116] @ 0x74
8002bd2: 4a15 ldr r2, [pc, #84] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002bd4: f043 0301 orr.w r3, r3, #1
8002bd8: 6753 str r3, [r2, #116] @ 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002bda: f7ff fa57 bl 800208c <HAL_GetTick>
8002bde: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8002be0: e008 b.n 8002bf4 <HAL_RCC_OscConfig+0x24c>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8002be2: f7ff fa53 bl 800208c <HAL_GetTick>
8002be6: 4602 mov r2, r0
8002be8: 693b ldr r3, [r7, #16]
8002bea: 1ad3 subs r3, r2, r3
8002bec: 2b02 cmp r3, #2
8002bee: d901 bls.n 8002bf4 <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
8002bf0: 2303 movs r3, #3
8002bf2: e176 b.n 8002ee2 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8002bf4: 4b0c ldr r3, [pc, #48] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002bf6: 6f5b ldr r3, [r3, #116] @ 0x74
8002bf8: f003 0302 and.w r3, r3, #2
8002bfc: 2b00 cmp r3, #0
8002bfe: d0f0 beq.n 8002be2 <HAL_RCC_OscConfig+0x23a>
8002c00: e01a b.n 8002c38 <HAL_RCC_OscConfig+0x290>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8002c02: 4b09 ldr r3, [pc, #36] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002c04: 6f5b ldr r3, [r3, #116] @ 0x74
8002c06: 4a08 ldr r2, [pc, #32] @ (8002c28 <HAL_RCC_OscConfig+0x280>)
8002c08: f023 0301 bic.w r3, r3, #1
8002c0c: 6753 str r3, [r2, #116] @ 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002c0e: f7ff fa3d bl 800208c <HAL_GetTick>
8002c12: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8002c14: e00a b.n 8002c2c <HAL_RCC_OscConfig+0x284>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8002c16: f7ff fa39 bl 800208c <HAL_GetTick>
8002c1a: 4602 mov r2, r0
8002c1c: 693b ldr r3, [r7, #16]
8002c1e: 1ad3 subs r3, r2, r3
8002c20: 2b02 cmp r3, #2
8002c22: d903 bls.n 8002c2c <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
8002c24: 2303 movs r3, #3
8002c26: e15c b.n 8002ee2 <HAL_RCC_OscConfig+0x53a>
8002c28: 40023800 .word 0x40023800
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8002c2c: 4b91 ldr r3, [pc, #580] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002c2e: 6f5b ldr r3, [r3, #116] @ 0x74
8002c30: f003 0302 and.w r3, r3, #2
8002c34: 2b00 cmp r3, #0
8002c36: d1ee bne.n 8002c16 <HAL_RCC_OscConfig+0x26e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8002c38: 687b ldr r3, [r7, #4]
8002c3a: 681b ldr r3, [r3, #0]
8002c3c: f003 0304 and.w r3, r3, #4
8002c40: 2b00 cmp r3, #0
8002c42: f000 80a4 beq.w 8002d8e <HAL_RCC_OscConfig+0x3e6>
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8002c46: 4b8b ldr r3, [pc, #556] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002c48: 6c1b ldr r3, [r3, #64] @ 0x40
8002c4a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002c4e: 2b00 cmp r3, #0
8002c50: d10d bne.n 8002c6e <HAL_RCC_OscConfig+0x2c6>
{
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
8002c52: 4b88 ldr r3, [pc, #544] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002c54: 6c1b ldr r3, [r3, #64] @ 0x40
8002c56: 4a87 ldr r2, [pc, #540] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002c58: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002c5c: 6413 str r3, [r2, #64] @ 0x40
8002c5e: 4b85 ldr r3, [pc, #532] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002c60: 6c1b ldr r3, [r3, #64] @ 0x40
8002c62: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002c66: 60bb str r3, [r7, #8]
8002c68: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8002c6a: 2301 movs r3, #1
8002c6c: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8002c6e: 4b82 ldr r3, [pc, #520] @ (8002e78 <HAL_RCC_OscConfig+0x4d0>)
8002c70: 681b ldr r3, [r3, #0]
8002c72: f403 7380 and.w r3, r3, #256 @ 0x100
8002c76: 2b00 cmp r3, #0
8002c78: d118 bne.n 8002cac <HAL_RCC_OscConfig+0x304>
{
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
8002c7a: 4b7f ldr r3, [pc, #508] @ (8002e78 <HAL_RCC_OscConfig+0x4d0>)
8002c7c: 681b ldr r3, [r3, #0]
8002c7e: 4a7e ldr r2, [pc, #504] @ (8002e78 <HAL_RCC_OscConfig+0x4d0>)
8002c80: f443 7380 orr.w r3, r3, #256 @ 0x100
8002c84: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8002c86: f7ff fa01 bl 800208c <HAL_GetTick>
8002c8a: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8002c8c: e008 b.n 8002ca0 <HAL_RCC_OscConfig+0x2f8>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8002c8e: f7ff f9fd bl 800208c <HAL_GetTick>
8002c92: 4602 mov r2, r0
8002c94: 693b ldr r3, [r7, #16]
8002c96: 1ad3 subs r3, r2, r3
8002c98: 2b64 cmp r3, #100 @ 0x64
8002c9a: d901 bls.n 8002ca0 <HAL_RCC_OscConfig+0x2f8>
{
return HAL_TIMEOUT;
8002c9c: 2303 movs r3, #3
8002c9e: e120 b.n 8002ee2 <HAL_RCC_OscConfig+0x53a>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8002ca0: 4b75 ldr r3, [pc, #468] @ (8002e78 <HAL_RCC_OscConfig+0x4d0>)
8002ca2: 681b ldr r3, [r3, #0]
8002ca4: f403 7380 and.w r3, r3, #256 @ 0x100
8002ca8: 2b00 cmp r3, #0
8002caa: d0f0 beq.n 8002c8e <HAL_RCC_OscConfig+0x2e6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8002cac: 687b ldr r3, [r7, #4]
8002cae: 689b ldr r3, [r3, #8]
8002cb0: 2b01 cmp r3, #1
8002cb2: d106 bne.n 8002cc2 <HAL_RCC_OscConfig+0x31a>
8002cb4: 4b6f ldr r3, [pc, #444] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002cb6: 6f1b ldr r3, [r3, #112] @ 0x70
8002cb8: 4a6e ldr r2, [pc, #440] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002cba: f043 0301 orr.w r3, r3, #1
8002cbe: 6713 str r3, [r2, #112] @ 0x70
8002cc0: e02d b.n 8002d1e <HAL_RCC_OscConfig+0x376>
8002cc2: 687b ldr r3, [r7, #4]
8002cc4: 689b ldr r3, [r3, #8]
8002cc6: 2b00 cmp r3, #0
8002cc8: d10c bne.n 8002ce4 <HAL_RCC_OscConfig+0x33c>
8002cca: 4b6a ldr r3, [pc, #424] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002ccc: 6f1b ldr r3, [r3, #112] @ 0x70
8002cce: 4a69 ldr r2, [pc, #420] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002cd0: f023 0301 bic.w r3, r3, #1
8002cd4: 6713 str r3, [r2, #112] @ 0x70
8002cd6: 4b67 ldr r3, [pc, #412] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002cd8: 6f1b ldr r3, [r3, #112] @ 0x70
8002cda: 4a66 ldr r2, [pc, #408] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002cdc: f023 0304 bic.w r3, r3, #4
8002ce0: 6713 str r3, [r2, #112] @ 0x70
8002ce2: e01c b.n 8002d1e <HAL_RCC_OscConfig+0x376>
8002ce4: 687b ldr r3, [r7, #4]
8002ce6: 689b ldr r3, [r3, #8]
8002ce8: 2b05 cmp r3, #5
8002cea: d10c bne.n 8002d06 <HAL_RCC_OscConfig+0x35e>
8002cec: 4b61 ldr r3, [pc, #388] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002cee: 6f1b ldr r3, [r3, #112] @ 0x70
8002cf0: 4a60 ldr r2, [pc, #384] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002cf2: f043 0304 orr.w r3, r3, #4
8002cf6: 6713 str r3, [r2, #112] @ 0x70
8002cf8: 4b5e ldr r3, [pc, #376] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002cfa: 6f1b ldr r3, [r3, #112] @ 0x70
8002cfc: 4a5d ldr r2, [pc, #372] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002cfe: f043 0301 orr.w r3, r3, #1
8002d02: 6713 str r3, [r2, #112] @ 0x70
8002d04: e00b b.n 8002d1e <HAL_RCC_OscConfig+0x376>
8002d06: 4b5b ldr r3, [pc, #364] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002d08: 6f1b ldr r3, [r3, #112] @ 0x70
8002d0a: 4a5a ldr r2, [pc, #360] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002d0c: f023 0301 bic.w r3, r3, #1
8002d10: 6713 str r3, [r2, #112] @ 0x70
8002d12: 4b58 ldr r3, [pc, #352] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002d14: 6f1b ldr r3, [r3, #112] @ 0x70
8002d16: 4a57 ldr r2, [pc, #348] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002d18: f023 0304 bic.w r3, r3, #4
8002d1c: 6713 str r3, [r2, #112] @ 0x70
/* Check the LSE State */
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8002d1e: 687b ldr r3, [r7, #4]
8002d20: 689b ldr r3, [r3, #8]
8002d22: 2b00 cmp r3, #0
8002d24: d015 beq.n 8002d52 <HAL_RCC_OscConfig+0x3aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002d26: f7ff f9b1 bl 800208c <HAL_GetTick>
8002d2a: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002d2c: e00a b.n 8002d44 <HAL_RCC_OscConfig+0x39c>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8002d2e: f7ff f9ad bl 800208c <HAL_GetTick>
8002d32: 4602 mov r2, r0
8002d34: 693b ldr r3, [r7, #16]
8002d36: 1ad3 subs r3, r2, r3
8002d38: f241 3288 movw r2, #5000 @ 0x1388
8002d3c: 4293 cmp r3, r2
8002d3e: d901 bls.n 8002d44 <HAL_RCC_OscConfig+0x39c>
{
return HAL_TIMEOUT;
8002d40: 2303 movs r3, #3
8002d42: e0ce b.n 8002ee2 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002d44: 4b4b ldr r3, [pc, #300] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002d46: 6f1b ldr r3, [r3, #112] @ 0x70
8002d48: f003 0302 and.w r3, r3, #2
8002d4c: 2b00 cmp r3, #0
8002d4e: d0ee beq.n 8002d2e <HAL_RCC_OscConfig+0x386>
8002d50: e014 b.n 8002d7c <HAL_RCC_OscConfig+0x3d4>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002d52: f7ff f99b bl 800208c <HAL_GetTick>
8002d56: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8002d58: e00a b.n 8002d70 <HAL_RCC_OscConfig+0x3c8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8002d5a: f7ff f997 bl 800208c <HAL_GetTick>
8002d5e: 4602 mov r2, r0
8002d60: 693b ldr r3, [r7, #16]
8002d62: 1ad3 subs r3, r2, r3
8002d64: f241 3288 movw r2, #5000 @ 0x1388
8002d68: 4293 cmp r3, r2
8002d6a: d901 bls.n 8002d70 <HAL_RCC_OscConfig+0x3c8>
{
return HAL_TIMEOUT;
8002d6c: 2303 movs r3, #3
8002d6e: e0b8 b.n 8002ee2 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8002d70: 4b40 ldr r3, [pc, #256] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002d72: 6f1b ldr r3, [r3, #112] @ 0x70
8002d74: f003 0302 and.w r3, r3, #2
8002d78: 2b00 cmp r3, #0
8002d7a: d1ee bne.n 8002d5a <HAL_RCC_OscConfig+0x3b2>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
8002d7c: 7dfb ldrb r3, [r7, #23]
8002d7e: 2b01 cmp r3, #1
8002d80: d105 bne.n 8002d8e <HAL_RCC_OscConfig+0x3e6>
{
__HAL_RCC_PWR_CLK_DISABLE();
8002d82: 4b3c ldr r3, [pc, #240] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002d84: 6c1b ldr r3, [r3, #64] @ 0x40
8002d86: 4a3b ldr r2, [pc, #236] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002d88: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8002d8c: 6413 str r3, [r2, #64] @ 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8002d8e: 687b ldr r3, [r7, #4]
8002d90: 699b ldr r3, [r3, #24]
8002d92: 2b00 cmp r3, #0
8002d94: f000 80a4 beq.w 8002ee0 <HAL_RCC_OscConfig+0x538>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8002d98: 4b36 ldr r3, [pc, #216] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002d9a: 689b ldr r3, [r3, #8]
8002d9c: f003 030c and.w r3, r3, #12
8002da0: 2b08 cmp r3, #8
8002da2: d06b beq.n 8002e7c <HAL_RCC_OscConfig+0x4d4>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8002da4: 687b ldr r3, [r7, #4]
8002da6: 699b ldr r3, [r3, #24]
8002da8: 2b02 cmp r3, #2
8002daa: d149 bne.n 8002e40 <HAL_RCC_OscConfig+0x498>
#if defined (RCC_PLLCFGR_PLLR)
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002dac: 4b31 ldr r3, [pc, #196] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002dae: 681b ldr r3, [r3, #0]
8002db0: 4a30 ldr r2, [pc, #192] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002db2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8002db6: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002db8: f7ff f968 bl 800208c <HAL_GetTick>
8002dbc: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002dbe: e008 b.n 8002dd2 <HAL_RCC_OscConfig+0x42a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002dc0: f7ff f964 bl 800208c <HAL_GetTick>
8002dc4: 4602 mov r2, r0
8002dc6: 693b ldr r3, [r7, #16]
8002dc8: 1ad3 subs r3, r2, r3
8002dca: 2b02 cmp r3, #2
8002dcc: d901 bls.n 8002dd2 <HAL_RCC_OscConfig+0x42a>
{
return HAL_TIMEOUT;
8002dce: 2303 movs r3, #3
8002dd0: e087 b.n 8002ee2 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002dd2: 4b28 ldr r3, [pc, #160] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002dd4: 681b ldr r3, [r3, #0]
8002dd6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002dda: 2b00 cmp r3, #0
8002ddc: d1f0 bne.n 8002dc0 <HAL_RCC_OscConfig+0x418>
RCC_OscInitStruct->PLL.PLLN,
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#else
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8002dde: 687b ldr r3, [r7, #4]
8002de0: 69da ldr r2, [r3, #28]
8002de2: 687b ldr r3, [r7, #4]
8002de4: 6a1b ldr r3, [r3, #32]
8002de6: 431a orrs r2, r3
8002de8: 687b ldr r3, [r7, #4]
8002dea: 6a5b ldr r3, [r3, #36] @ 0x24
8002dec: 019b lsls r3, r3, #6
8002dee: 431a orrs r2, r3
8002df0: 687b ldr r3, [r7, #4]
8002df2: 6a9b ldr r3, [r3, #40] @ 0x28
8002df4: 085b lsrs r3, r3, #1
8002df6: 3b01 subs r3, #1
8002df8: 041b lsls r3, r3, #16
8002dfa: 431a orrs r2, r3
8002dfc: 687b ldr r3, [r7, #4]
8002dfe: 6adb ldr r3, [r3, #44] @ 0x2c
8002e00: 061b lsls r3, r3, #24
8002e02: 4313 orrs r3, r2
8002e04: 4a1b ldr r2, [pc, #108] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002e06: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
8002e0a: 6053 str r3, [r2, #4]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8002e0c: 4b19 ldr r3, [pc, #100] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002e0e: 681b ldr r3, [r3, #0]
8002e10: 4a18 ldr r2, [pc, #96] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002e12: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8002e16: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002e18: f7ff f938 bl 800208c <HAL_GetTick>
8002e1c: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002e1e: e008 b.n 8002e32 <HAL_RCC_OscConfig+0x48a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002e20: f7ff f934 bl 800208c <HAL_GetTick>
8002e24: 4602 mov r2, r0
8002e26: 693b ldr r3, [r7, #16]
8002e28: 1ad3 subs r3, r2, r3
8002e2a: 2b02 cmp r3, #2
8002e2c: d901 bls.n 8002e32 <HAL_RCC_OscConfig+0x48a>
{
return HAL_TIMEOUT;
8002e2e: 2303 movs r3, #3
8002e30: e057 b.n 8002ee2 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002e32: 4b10 ldr r3, [pc, #64] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002e34: 681b ldr r3, [r3, #0]
8002e36: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002e3a: 2b00 cmp r3, #0
8002e3c: d0f0 beq.n 8002e20 <HAL_RCC_OscConfig+0x478>
8002e3e: e04f b.n 8002ee0 <HAL_RCC_OscConfig+0x538>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002e40: 4b0c ldr r3, [pc, #48] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002e42: 681b ldr r3, [r3, #0]
8002e44: 4a0b ldr r2, [pc, #44] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002e46: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8002e4a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002e4c: f7ff f91e bl 800208c <HAL_GetTick>
8002e50: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002e52: e008 b.n 8002e66 <HAL_RCC_OscConfig+0x4be>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002e54: f7ff f91a bl 800208c <HAL_GetTick>
8002e58: 4602 mov r2, r0
8002e5a: 693b ldr r3, [r7, #16]
8002e5c: 1ad3 subs r3, r2, r3
8002e5e: 2b02 cmp r3, #2
8002e60: d901 bls.n 8002e66 <HAL_RCC_OscConfig+0x4be>
{
return HAL_TIMEOUT;
8002e62: 2303 movs r3, #3
8002e64: e03d b.n 8002ee2 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002e66: 4b03 ldr r3, [pc, #12] @ (8002e74 <HAL_RCC_OscConfig+0x4cc>)
8002e68: 681b ldr r3, [r3, #0]
8002e6a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002e6e: 2b00 cmp r3, #0
8002e70: d1f0 bne.n 8002e54 <HAL_RCC_OscConfig+0x4ac>
8002e72: e035 b.n 8002ee0 <HAL_RCC_OscConfig+0x538>
8002e74: 40023800 .word 0x40023800
8002e78: 40007000 .word 0x40007000
}
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
8002e7c: 4b1b ldr r3, [pc, #108] @ (8002eec <HAL_RCC_OscConfig+0x544>)
8002e7e: 685b ldr r3, [r3, #4]
8002e80: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8002e82: 687b ldr r3, [r7, #4]
8002e84: 699b ldr r3, [r3, #24]
8002e86: 2b01 cmp r3, #1
8002e88: d028 beq.n 8002edc <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002e8a: 68fb ldr r3, [r7, #12]
8002e8c: f403 0280 and.w r2, r3, #4194304 @ 0x400000
8002e90: 687b ldr r3, [r7, #4]
8002e92: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8002e94: 429a cmp r2, r3
8002e96: d121 bne.n 8002edc <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8002e98: 68fb ldr r3, [r7, #12]
8002e9a: f003 023f and.w r2, r3, #63 @ 0x3f
8002e9e: 687b ldr r3, [r7, #4]
8002ea0: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002ea2: 429a cmp r2, r3
8002ea4: d11a bne.n 8002edc <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8002ea6: 68fa ldr r2, [r7, #12]
8002ea8: f647 73c0 movw r3, #32704 @ 0x7fc0
8002eac: 4013 ands r3, r2
8002eae: 687a ldr r2, [r7, #4]
8002eb0: 6a52 ldr r2, [r2, #36] @ 0x24
8002eb2: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8002eb4: 4293 cmp r3, r2
8002eb6: d111 bne.n 8002edc <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
8002eb8: 68fb ldr r3, [r7, #12]
8002eba: f403 3240 and.w r2, r3, #196608 @ 0x30000
8002ebe: 687b ldr r3, [r7, #4]
8002ec0: 6a9b ldr r3, [r3, #40] @ 0x28
8002ec2: 085b lsrs r3, r3, #1
8002ec4: 3b01 subs r3, #1
8002ec6: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8002ec8: 429a cmp r2, r3
8002eca: d107 bne.n 8002edc <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
8002ecc: 68fb ldr r3, [r7, #12]
8002ece: f003 6270 and.w r2, r3, #251658240 @ 0xf000000
8002ed2: 687b ldr r3, [r7, #4]
8002ed4: 6adb ldr r3, [r3, #44] @ 0x2c
8002ed6: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
8002ed8: 429a cmp r2, r3
8002eda: d001 beq.n 8002ee0 <HAL_RCC_OscConfig+0x538>
#endif
{
return HAL_ERROR;
8002edc: 2301 movs r3, #1
8002ede: e000 b.n 8002ee2 <HAL_RCC_OscConfig+0x53a>
}
}
}
return HAL_OK;
8002ee0: 2300 movs r3, #0
}
8002ee2: 4618 mov r0, r3
8002ee4: 3718 adds r7, #24
8002ee6: 46bd mov sp, r7
8002ee8: bd80 pop {r7, pc}
8002eea: bf00 nop
8002eec: 40023800 .word 0x40023800
08002ef0 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8002ef0: b580 push {r7, lr}
8002ef2: b084 sub sp, #16
8002ef4: af00 add r7, sp, #0
8002ef6: 6078 str r0, [r7, #4]
8002ef8: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
8002efa: 2300 movs r3, #0
8002efc: 60fb str r3, [r7, #12]
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8002efe: 687b ldr r3, [r7, #4]
8002f00: 2b00 cmp r3, #0
8002f02: d101 bne.n 8002f08 <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8002f04: 2301 movs r3, #1
8002f06: e0d0 b.n 80030aa <HAL_RCC_ClockConfig+0x1ba>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8002f08: 4b6a ldr r3, [pc, #424] @ (80030b4 <HAL_RCC_ClockConfig+0x1c4>)
8002f0a: 681b ldr r3, [r3, #0]
8002f0c: f003 030f and.w r3, r3, #15
8002f10: 683a ldr r2, [r7, #0]
8002f12: 429a cmp r2, r3
8002f14: d910 bls.n 8002f38 <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002f16: 4b67 ldr r3, [pc, #412] @ (80030b4 <HAL_RCC_ClockConfig+0x1c4>)
8002f18: 681b ldr r3, [r3, #0]
8002f1a: f023 020f bic.w r2, r3, #15
8002f1e: 4965 ldr r1, [pc, #404] @ (80030b4 <HAL_RCC_ClockConfig+0x1c4>)
8002f20: 683b ldr r3, [r7, #0]
8002f22: 4313 orrs r3, r2
8002f24: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8002f26: 4b63 ldr r3, [pc, #396] @ (80030b4 <HAL_RCC_ClockConfig+0x1c4>)
8002f28: 681b ldr r3, [r3, #0]
8002f2a: f003 030f and.w r3, r3, #15
8002f2e: 683a ldr r2, [r7, #0]
8002f30: 429a cmp r2, r3
8002f32: d001 beq.n 8002f38 <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
8002f34: 2301 movs r3, #1
8002f36: e0b8 b.n 80030aa <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002f38: 687b ldr r3, [r7, #4]
8002f3a: 681b ldr r3, [r3, #0]
8002f3c: f003 0302 and.w r3, r3, #2
8002f40: 2b00 cmp r3, #0
8002f42: d020 beq.n 8002f86 <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002f44: 687b ldr r3, [r7, #4]
8002f46: 681b ldr r3, [r3, #0]
8002f48: f003 0304 and.w r3, r3, #4
8002f4c: 2b00 cmp r3, #0
8002f4e: d005 beq.n 8002f5c <HAL_RCC_ClockConfig+0x6c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8002f50: 4b59 ldr r3, [pc, #356] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
8002f52: 689b ldr r3, [r3, #8]
8002f54: 4a58 ldr r2, [pc, #352] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
8002f56: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00
8002f5a: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002f5c: 687b ldr r3, [r7, #4]
8002f5e: 681b ldr r3, [r3, #0]
8002f60: f003 0308 and.w r3, r3, #8
8002f64: 2b00 cmp r3, #0
8002f66: d005 beq.n 8002f74 <HAL_RCC_ClockConfig+0x84>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8002f68: 4b53 ldr r3, [pc, #332] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
8002f6a: 689b ldr r3, [r3, #8]
8002f6c: 4a52 ldr r2, [pc, #328] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
8002f6e: f443 4360 orr.w r3, r3, #57344 @ 0xe000
8002f72: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002f74: 4b50 ldr r3, [pc, #320] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
8002f76: 689b ldr r3, [r3, #8]
8002f78: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8002f7c: 687b ldr r3, [r7, #4]
8002f7e: 689b ldr r3, [r3, #8]
8002f80: 494d ldr r1, [pc, #308] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
8002f82: 4313 orrs r3, r2
8002f84: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8002f86: 687b ldr r3, [r7, #4]
8002f88: 681b ldr r3, [r3, #0]
8002f8a: f003 0301 and.w r3, r3, #1
8002f8e: 2b00 cmp r3, #0
8002f90: d040 beq.n 8003014 <HAL_RCC_ClockConfig+0x124>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8002f92: 687b ldr r3, [r7, #4]
8002f94: 685b ldr r3, [r3, #4]
8002f96: 2b01 cmp r3, #1
8002f98: d107 bne.n 8002faa <HAL_RCC_ClockConfig+0xba>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002f9a: 4b47 ldr r3, [pc, #284] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
8002f9c: 681b ldr r3, [r3, #0]
8002f9e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002fa2: 2b00 cmp r3, #0
8002fa4: d115 bne.n 8002fd2 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
8002fa6: 2301 movs r3, #1
8002fa8: e07f b.n 80030aa <HAL_RCC_ClockConfig+0x1ba>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8002faa: 687b ldr r3, [r7, #4]
8002fac: 685b ldr r3, [r3, #4]
8002fae: 2b02 cmp r3, #2
8002fb0: d107 bne.n 8002fc2 <HAL_RCC_ClockConfig+0xd2>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002fb2: 4b41 ldr r3, [pc, #260] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
8002fb4: 681b ldr r3, [r3, #0]
8002fb6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002fba: 2b00 cmp r3, #0
8002fbc: d109 bne.n 8002fd2 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
8002fbe: 2301 movs r3, #1
8002fc0: e073 b.n 80030aa <HAL_RCC_ClockConfig+0x1ba>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002fc2: 4b3d ldr r3, [pc, #244] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
8002fc4: 681b ldr r3, [r3, #0]
8002fc6: f003 0302 and.w r3, r3, #2
8002fca: 2b00 cmp r3, #0
8002fcc: d101 bne.n 8002fd2 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
8002fce: 2301 movs r3, #1
8002fd0: e06b b.n 80030aa <HAL_RCC_ClockConfig+0x1ba>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8002fd2: 4b39 ldr r3, [pc, #228] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
8002fd4: 689b ldr r3, [r3, #8]
8002fd6: f023 0203 bic.w r2, r3, #3
8002fda: 687b ldr r3, [r7, #4]
8002fdc: 685b ldr r3, [r3, #4]
8002fde: 4936 ldr r1, [pc, #216] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
8002fe0: 4313 orrs r3, r2
8002fe2: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002fe4: f7ff f852 bl 800208c <HAL_GetTick>
8002fe8: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002fea: e00a b.n 8003002 <HAL_RCC_ClockConfig+0x112>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8002fec: f7ff f84e bl 800208c <HAL_GetTick>
8002ff0: 4602 mov r2, r0
8002ff2: 68fb ldr r3, [r7, #12]
8002ff4: 1ad3 subs r3, r2, r3
8002ff6: f241 3288 movw r2, #5000 @ 0x1388
8002ffa: 4293 cmp r3, r2
8002ffc: d901 bls.n 8003002 <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
8002ffe: 2303 movs r3, #3
8003000: e053 b.n 80030aa <HAL_RCC_ClockConfig+0x1ba>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8003002: 4b2d ldr r3, [pc, #180] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
8003004: 689b ldr r3, [r3, #8]
8003006: f003 020c and.w r2, r3, #12
800300a: 687b ldr r3, [r7, #4]
800300c: 685b ldr r3, [r3, #4]
800300e: 009b lsls r3, r3, #2
8003010: 429a cmp r2, r3
8003012: d1eb bne.n 8002fec <HAL_RCC_ClockConfig+0xfc>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8003014: 4b27 ldr r3, [pc, #156] @ (80030b4 <HAL_RCC_ClockConfig+0x1c4>)
8003016: 681b ldr r3, [r3, #0]
8003018: f003 030f and.w r3, r3, #15
800301c: 683a ldr r2, [r7, #0]
800301e: 429a cmp r2, r3
8003020: d210 bcs.n 8003044 <HAL_RCC_ClockConfig+0x154>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8003022: 4b24 ldr r3, [pc, #144] @ (80030b4 <HAL_RCC_ClockConfig+0x1c4>)
8003024: 681b ldr r3, [r3, #0]
8003026: f023 020f bic.w r2, r3, #15
800302a: 4922 ldr r1, [pc, #136] @ (80030b4 <HAL_RCC_ClockConfig+0x1c4>)
800302c: 683b ldr r3, [r7, #0]
800302e: 4313 orrs r3, r2
8003030: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8003032: 4b20 ldr r3, [pc, #128] @ (80030b4 <HAL_RCC_ClockConfig+0x1c4>)
8003034: 681b ldr r3, [r3, #0]
8003036: f003 030f and.w r3, r3, #15
800303a: 683a ldr r2, [r7, #0]
800303c: 429a cmp r2, r3
800303e: d001 beq.n 8003044 <HAL_RCC_ClockConfig+0x154>
{
return HAL_ERROR;
8003040: 2301 movs r3, #1
8003042: e032 b.n 80030aa <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8003044: 687b ldr r3, [r7, #4]
8003046: 681b ldr r3, [r3, #0]
8003048: f003 0304 and.w r3, r3, #4
800304c: 2b00 cmp r3, #0
800304e: d008 beq.n 8003062 <HAL_RCC_ClockConfig+0x172>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8003050: 4b19 ldr r3, [pc, #100] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
8003052: 689b ldr r3, [r3, #8]
8003054: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00
8003058: 687b ldr r3, [r7, #4]
800305a: 68db ldr r3, [r3, #12]
800305c: 4916 ldr r1, [pc, #88] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
800305e: 4313 orrs r3, r2
8003060: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8003062: 687b ldr r3, [r7, #4]
8003064: 681b ldr r3, [r3, #0]
8003066: f003 0308 and.w r3, r3, #8
800306a: 2b00 cmp r3, #0
800306c: d009 beq.n 8003082 <HAL_RCC_ClockConfig+0x192>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
800306e: 4b12 ldr r3, [pc, #72] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
8003070: 689b ldr r3, [r3, #8]
8003072: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8003076: 687b ldr r3, [r7, #4]
8003078: 691b ldr r3, [r3, #16]
800307a: 00db lsls r3, r3, #3
800307c: 490e ldr r1, [pc, #56] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
800307e: 4313 orrs r3, r2
8003080: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8003082: f000 f821 bl 80030c8 <HAL_RCC_GetSysClockFreq>
8003086: 4602 mov r2, r0
8003088: 4b0b ldr r3, [pc, #44] @ (80030b8 <HAL_RCC_ClockConfig+0x1c8>)
800308a: 689b ldr r3, [r3, #8]
800308c: 091b lsrs r3, r3, #4
800308e: f003 030f and.w r3, r3, #15
8003092: 490a ldr r1, [pc, #40] @ (80030bc <HAL_RCC_ClockConfig+0x1cc>)
8003094: 5ccb ldrb r3, [r1, r3]
8003096: fa22 f303 lsr.w r3, r2, r3
800309a: 4a09 ldr r2, [pc, #36] @ (80030c0 <HAL_RCC_ClockConfig+0x1d0>)
800309c: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
800309e: 4b09 ldr r3, [pc, #36] @ (80030c4 <HAL_RCC_ClockConfig+0x1d4>)
80030a0: 681b ldr r3, [r3, #0]
80030a2: 4618 mov r0, r3
80030a4: f7fe fce2 bl 8001a6c <HAL_InitTick>
return HAL_OK;
80030a8: 2300 movs r3, #0
}
80030aa: 4618 mov r0, r3
80030ac: 3710 adds r7, #16
80030ae: 46bd mov sp, r7
80030b0: bd80 pop {r7, pc}
80030b2: bf00 nop
80030b4: 40023c00 .word 0x40023c00
80030b8: 40023800 .word 0x40023800
80030bc: 08008a28 .word 0x08008a28
80030c0: 20000000 .word 0x20000000
80030c4: 20000004 .word 0x20000004
080030c8 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
80030c8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
80030cc: b090 sub sp, #64 @ 0x40
80030ce: af00 add r7, sp, #0
uint32_t pllm = 0, pllvco = 0, pllp = 0;
80030d0: 2300 movs r3, #0
80030d2: 637b str r3, [r7, #52] @ 0x34
80030d4: 2300 movs r3, #0
80030d6: 63fb str r3, [r7, #60] @ 0x3c
80030d8: 2300 movs r3, #0
80030da: 633b str r3, [r7, #48] @ 0x30
uint32_t sysclockfreq = 0;
80030dc: 2300 movs r3, #0
80030de: 63bb str r3, [r7, #56] @ 0x38
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
80030e0: 4b59 ldr r3, [pc, #356] @ (8003248 <HAL_RCC_GetSysClockFreq+0x180>)
80030e2: 689b ldr r3, [r3, #8]
80030e4: f003 030c and.w r3, r3, #12
80030e8: 2b08 cmp r3, #8
80030ea: d00d beq.n 8003108 <HAL_RCC_GetSysClockFreq+0x40>
80030ec: 2b08 cmp r3, #8
80030ee: f200 80a1 bhi.w 8003234 <HAL_RCC_GetSysClockFreq+0x16c>
80030f2: 2b00 cmp r3, #0
80030f4: d002 beq.n 80030fc <HAL_RCC_GetSysClockFreq+0x34>
80030f6: 2b04 cmp r3, #4
80030f8: d003 beq.n 8003102 <HAL_RCC_GetSysClockFreq+0x3a>
80030fa: e09b b.n 8003234 <HAL_RCC_GetSysClockFreq+0x16c>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
80030fc: 4b53 ldr r3, [pc, #332] @ (800324c <HAL_RCC_GetSysClockFreq+0x184>)
80030fe: 63bb str r3, [r7, #56] @ 0x38
break;
8003100: e09b b.n 800323a <HAL_RCC_GetSysClockFreq+0x172>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8003102: 4b53 ldr r3, [pc, #332] @ (8003250 <HAL_RCC_GetSysClockFreq+0x188>)
8003104: 63bb str r3, [r7, #56] @ 0x38
break;
8003106: e098 b.n 800323a <HAL_RCC_GetSysClockFreq+0x172>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8003108: 4b4f ldr r3, [pc, #316] @ (8003248 <HAL_RCC_GetSysClockFreq+0x180>)
800310a: 685b ldr r3, [r3, #4]
800310c: f003 033f and.w r3, r3, #63 @ 0x3f
8003110: 637b str r3, [r7, #52] @ 0x34
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
8003112: 4b4d ldr r3, [pc, #308] @ (8003248 <HAL_RCC_GetSysClockFreq+0x180>)
8003114: 685b ldr r3, [r3, #4]
8003116: f403 0380 and.w r3, r3, #4194304 @ 0x400000
800311a: 2b00 cmp r3, #0
800311c: d028 beq.n 8003170 <HAL_RCC_GetSysClockFreq+0xa8>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
800311e: 4b4a ldr r3, [pc, #296] @ (8003248 <HAL_RCC_GetSysClockFreq+0x180>)
8003120: 685b ldr r3, [r3, #4]
8003122: 099b lsrs r3, r3, #6
8003124: 2200 movs r2, #0
8003126: 623b str r3, [r7, #32]
8003128: 627a str r2, [r7, #36] @ 0x24
800312a: 6a3b ldr r3, [r7, #32]
800312c: f3c3 0008 ubfx r0, r3, #0, #9
8003130: 2100 movs r1, #0
8003132: 4b47 ldr r3, [pc, #284] @ (8003250 <HAL_RCC_GetSysClockFreq+0x188>)
8003134: fb03 f201 mul.w r2, r3, r1
8003138: 2300 movs r3, #0
800313a: fb00 f303 mul.w r3, r0, r3
800313e: 4413 add r3, r2
8003140: 4a43 ldr r2, [pc, #268] @ (8003250 <HAL_RCC_GetSysClockFreq+0x188>)
8003142: fba0 1202 umull r1, r2, r0, r2
8003146: 62fa str r2, [r7, #44] @ 0x2c
8003148: 460a mov r2, r1
800314a: 62ba str r2, [r7, #40] @ 0x28
800314c: 6afa ldr r2, [r7, #44] @ 0x2c
800314e: 4413 add r3, r2
8003150: 62fb str r3, [r7, #44] @ 0x2c
8003152: 6b7b ldr r3, [r7, #52] @ 0x34
8003154: 2200 movs r2, #0
8003156: 61bb str r3, [r7, #24]
8003158: 61fa str r2, [r7, #28]
800315a: e9d7 2306 ldrd r2, r3, [r7, #24]
800315e: e9d7 010a ldrd r0, r1, [r7, #40] @ 0x28
8003162: f7fd f8ad bl 80002c0 <__aeabi_uldivmod>
8003166: 4602 mov r2, r0
8003168: 460b mov r3, r1
800316a: 4613 mov r3, r2
800316c: 63fb str r3, [r7, #60] @ 0x3c
800316e: e053 b.n 8003218 <HAL_RCC_GetSysClockFreq+0x150>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8003170: 4b35 ldr r3, [pc, #212] @ (8003248 <HAL_RCC_GetSysClockFreq+0x180>)
8003172: 685b ldr r3, [r3, #4]
8003174: 099b lsrs r3, r3, #6
8003176: 2200 movs r2, #0
8003178: 613b str r3, [r7, #16]
800317a: 617a str r2, [r7, #20]
800317c: 693b ldr r3, [r7, #16]
800317e: f3c3 0a08 ubfx sl, r3, #0, #9
8003182: f04f 0b00 mov.w fp, #0
8003186: 4652 mov r2, sl
8003188: 465b mov r3, fp
800318a: f04f 0000 mov.w r0, #0
800318e: f04f 0100 mov.w r1, #0
8003192: 0159 lsls r1, r3, #5
8003194: ea41 61d2 orr.w r1, r1, r2, lsr #27
8003198: 0150 lsls r0, r2, #5
800319a: 4602 mov r2, r0
800319c: 460b mov r3, r1
800319e: ebb2 080a subs.w r8, r2, sl
80031a2: eb63 090b sbc.w r9, r3, fp
80031a6: f04f 0200 mov.w r2, #0
80031aa: f04f 0300 mov.w r3, #0
80031ae: ea4f 1389 mov.w r3, r9, lsl #6
80031b2: ea43 6398 orr.w r3, r3, r8, lsr #26
80031b6: ea4f 1288 mov.w r2, r8, lsl #6
80031ba: ebb2 0408 subs.w r4, r2, r8
80031be: eb63 0509 sbc.w r5, r3, r9
80031c2: f04f 0200 mov.w r2, #0
80031c6: f04f 0300 mov.w r3, #0
80031ca: 00eb lsls r3, r5, #3
80031cc: ea43 7354 orr.w r3, r3, r4, lsr #29
80031d0: 00e2 lsls r2, r4, #3
80031d2: 4614 mov r4, r2
80031d4: 461d mov r5, r3
80031d6: eb14 030a adds.w r3, r4, sl
80031da: 603b str r3, [r7, #0]
80031dc: eb45 030b adc.w r3, r5, fp
80031e0: 607b str r3, [r7, #4]
80031e2: f04f 0200 mov.w r2, #0
80031e6: f04f 0300 mov.w r3, #0
80031ea: e9d7 4500 ldrd r4, r5, [r7]
80031ee: 4629 mov r1, r5
80031f0: 028b lsls r3, r1, #10
80031f2: 4621 mov r1, r4
80031f4: ea43 5391 orr.w r3, r3, r1, lsr #22
80031f8: 4621 mov r1, r4
80031fa: 028a lsls r2, r1, #10
80031fc: 4610 mov r0, r2
80031fe: 4619 mov r1, r3
8003200: 6b7b ldr r3, [r7, #52] @ 0x34
8003202: 2200 movs r2, #0
8003204: 60bb str r3, [r7, #8]
8003206: 60fa str r2, [r7, #12]
8003208: e9d7 2302 ldrd r2, r3, [r7, #8]
800320c: f7fd f858 bl 80002c0 <__aeabi_uldivmod>
8003210: 4602 mov r2, r0
8003212: 460b mov r3, r1
8003214: 4613 mov r3, r2
8003216: 63fb str r3, [r7, #60] @ 0x3c
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
8003218: 4b0b ldr r3, [pc, #44] @ (8003248 <HAL_RCC_GetSysClockFreq+0x180>)
800321a: 685b ldr r3, [r3, #4]
800321c: 0c1b lsrs r3, r3, #16
800321e: f003 0303 and.w r3, r3, #3
8003222: 3301 adds r3, #1
8003224: 005b lsls r3, r3, #1
8003226: 633b str r3, [r7, #48] @ 0x30
sysclockfreq = pllvco / pllp;
8003228: 6bfa ldr r2, [r7, #60] @ 0x3c
800322a: 6b3b ldr r3, [r7, #48] @ 0x30
800322c: fbb2 f3f3 udiv r3, r2, r3
8003230: 63bb str r3, [r7, #56] @ 0x38
break;
8003232: e002 b.n 800323a <HAL_RCC_GetSysClockFreq+0x172>
}
default:
{
sysclockfreq = HSI_VALUE;
8003234: 4b05 ldr r3, [pc, #20] @ (800324c <HAL_RCC_GetSysClockFreq+0x184>)
8003236: 63bb str r3, [r7, #56] @ 0x38
break;
8003238: bf00 nop
}
}
return sysclockfreq;
800323a: 6bbb ldr r3, [r7, #56] @ 0x38
}
800323c: 4618 mov r0, r3
800323e: 3740 adds r7, #64 @ 0x40
8003240: 46bd mov sp, r7
8003242: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8003246: bf00 nop
8003248: 40023800 .word 0x40023800
800324c: 00f42400 .word 0x00f42400
8003250: 017d7840 .word 0x017d7840
08003254 <HAL_RCC_GetHCLKFreq>:
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8003254: b480 push {r7}
8003256: af00 add r7, sp, #0
return SystemCoreClock;
8003258: 4b03 ldr r3, [pc, #12] @ (8003268 <HAL_RCC_GetHCLKFreq+0x14>)
800325a: 681b ldr r3, [r3, #0]
}
800325c: 4618 mov r0, r3
800325e: 46bd mov sp, r7
8003260: f85d 7b04 ldr.w r7, [sp], #4
8003264: 4770 bx lr
8003266: bf00 nop
8003268: 20000000 .word 0x20000000
0800326c <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
800326c: b580 push {r7, lr}
800326e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8003270: f7ff fff0 bl 8003254 <HAL_RCC_GetHCLKFreq>
8003274: 4602 mov r2, r0
8003276: 4b05 ldr r3, [pc, #20] @ (800328c <HAL_RCC_GetPCLK1Freq+0x20>)
8003278: 689b ldr r3, [r3, #8]
800327a: 0a9b lsrs r3, r3, #10
800327c: f003 0307 and.w r3, r3, #7
8003280: 4903 ldr r1, [pc, #12] @ (8003290 <HAL_RCC_GetPCLK1Freq+0x24>)
8003282: 5ccb ldrb r3, [r1, r3]
8003284: fa22 f303 lsr.w r3, r2, r3
}
8003288: 4618 mov r0, r3
800328a: bd80 pop {r7, pc}
800328c: 40023800 .word 0x40023800
8003290: 08008a38 .word 0x08008a38
08003294 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8003294: b580 push {r7, lr}
8003296: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
8003298: f7ff ffdc bl 8003254 <HAL_RCC_GetHCLKFreq>
800329c: 4602 mov r2, r0
800329e: 4b05 ldr r3, [pc, #20] @ (80032b4 <HAL_RCC_GetPCLK2Freq+0x20>)
80032a0: 689b ldr r3, [r3, #8]
80032a2: 0b5b lsrs r3, r3, #13
80032a4: f003 0307 and.w r3, r3, #7
80032a8: 4903 ldr r1, [pc, #12] @ (80032b8 <HAL_RCC_GetPCLK2Freq+0x24>)
80032aa: 5ccb ldrb r3, [r1, r3]
80032ac: fa22 f303 lsr.w r3, r2, r3
}
80032b0: 4618 mov r0, r3
80032b2: bd80 pop {r7, pc}
80032b4: 40023800 .word 0x40023800
80032b8: 08008a38 .word 0x08008a38
080032bc <HAL_RCC_GetClockConfig>:
* will be configured.
* @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
80032bc: b480 push {r7}
80032be: b083 sub sp, #12
80032c0: af00 add r7, sp, #0
80032c2: 6078 str r0, [r7, #4]
80032c4: 6039 str r1, [r7, #0]
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
80032c6: 687b ldr r3, [r7, #4]
80032c8: 220f movs r2, #15
80032ca: 601a str r2, [r3, #0]
/* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
80032cc: 4b12 ldr r3, [pc, #72] @ (8003318 <HAL_RCC_GetClockConfig+0x5c>)
80032ce: 689b ldr r3, [r3, #8]
80032d0: f003 0203 and.w r2, r3, #3
80032d4: 687b ldr r3, [r7, #4]
80032d6: 605a str r2, [r3, #4]
/* Get the HCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
80032d8: 4b0f ldr r3, [pc, #60] @ (8003318 <HAL_RCC_GetClockConfig+0x5c>)
80032da: 689b ldr r3, [r3, #8]
80032dc: f003 02f0 and.w r2, r3, #240 @ 0xf0
80032e0: 687b ldr r3, [r7, #4]
80032e2: 609a str r2, [r3, #8]
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
80032e4: 4b0c ldr r3, [pc, #48] @ (8003318 <HAL_RCC_GetClockConfig+0x5c>)
80032e6: 689b ldr r3, [r3, #8]
80032e8: f403 52e0 and.w r2, r3, #7168 @ 0x1c00
80032ec: 687b ldr r3, [r7, #4]
80032ee: 60da str r2, [r3, #12]
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
80032f0: 4b09 ldr r3, [pc, #36] @ (8003318 <HAL_RCC_GetClockConfig+0x5c>)
80032f2: 689b ldr r3, [r3, #8]
80032f4: 08db lsrs r3, r3, #3
80032f6: f403 52e0 and.w r2, r3, #7168 @ 0x1c00
80032fa: 687b ldr r3, [r7, #4]
80032fc: 611a str r2, [r3, #16]
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
80032fe: 4b07 ldr r3, [pc, #28] @ (800331c <HAL_RCC_GetClockConfig+0x60>)
8003300: 681b ldr r3, [r3, #0]
8003302: f003 020f and.w r2, r3, #15
8003306: 683b ldr r3, [r7, #0]
8003308: 601a str r2, [r3, #0]
}
800330a: bf00 nop
800330c: 370c adds r7, #12
800330e: 46bd mov sp, r7
8003310: f85d 7b04 ldr.w r7, [sp], #4
8003314: 4770 bx lr
8003316: bf00 nop
8003318: 40023800 .word 0x40023800
800331c: 40023c00 .word 0x40023c00
08003320 <HAL_RCCEx_PeriphCLKConfig>:
* the backup registers) are set to their reset values.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8003320: b580 push {r7, lr}
8003322: b088 sub sp, #32
8003324: af00 add r7, sp, #0
8003326: 6078 str r0, [r7, #4]
uint32_t tickstart = 0;
8003328: 2300 movs r3, #0
800332a: 617b str r3, [r7, #20]
uint32_t tmpreg0 = 0;
800332c: 2300 movs r3, #0
800332e: 613b str r3, [r7, #16]
uint32_t plli2sused = 0;
8003330: 2300 movs r3, #0
8003332: 61fb str r3, [r7, #28]
uint32_t pllsaiused = 0;
8003334: 2300 movs r3, #0
8003336: 61bb str r3, [r7, #24]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*----------------------------------- I2S configuration ----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
8003338: 687b ldr r3, [r7, #4]
800333a: 681b ldr r3, [r3, #0]
800333c: f003 0301 and.w r3, r3, #1
8003340: 2b00 cmp r3, #0
8003342: d012 beq.n 800336a <HAL_RCCEx_PeriphCLKConfig+0x4a>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure I2S Clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
8003344: 4b65 ldr r3, [pc, #404] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8003346: 689b ldr r3, [r3, #8]
8003348: 4a64 ldr r2, [pc, #400] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
800334a: f423 0300 bic.w r3, r3, #8388608 @ 0x800000
800334e: 6093 str r3, [r2, #8]
8003350: 4b62 ldr r3, [pc, #392] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8003352: 689a ldr r2, [r3, #8]
8003354: 687b ldr r3, [r7, #4]
8003356: 6adb ldr r3, [r3, #44] @ 0x2c
8003358: 4960 ldr r1, [pc, #384] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
800335a: 4313 orrs r3, r2
800335c: 608b str r3, [r1, #8]
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
800335e: 687b ldr r3, [r7, #4]
8003360: 6adb ldr r3, [r3, #44] @ 0x2c
8003362: 2b00 cmp r3, #0
8003364: d101 bne.n 800336a <HAL_RCCEx_PeriphCLKConfig+0x4a>
{
plli2sused = 1;
8003366: 2301 movs r3, #1
8003368: 61fb str r3, [r7, #28]
}
}
/*------------------------------------ SAI1 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
800336a: 687b ldr r3, [r7, #4]
800336c: 681b ldr r3, [r3, #0]
800336e: f403 2300 and.w r3, r3, #524288 @ 0x80000
8003372: 2b00 cmp r3, #0
8003374: d017 beq.n 80033a6 <HAL_RCCEx_PeriphCLKConfig+0x86>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure SAI1 Clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
8003376: 4b59 ldr r3, [pc, #356] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8003378: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
800337c: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
8003380: 687b ldr r3, [r7, #4]
8003382: 6b5b ldr r3, [r3, #52] @ 0x34
8003384: 4955 ldr r1, [pc, #340] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8003386: 4313 orrs r3, r2
8003388: f8c1 308c str.w r3, [r1, #140] @ 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
800338c: 687b ldr r3, [r7, #4]
800338e: 6b5b ldr r3, [r3, #52] @ 0x34
8003390: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8003394: d101 bne.n 800339a <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
plli2sused = 1;
8003396: 2301 movs r3, #1
8003398: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
800339a: 687b ldr r3, [r7, #4]
800339c: 6b5b ldr r3, [r3, #52] @ 0x34
800339e: 2b00 cmp r3, #0
80033a0: d101 bne.n 80033a6 <HAL_RCCEx_PeriphCLKConfig+0x86>
{
pllsaiused = 1;
80033a2: 2301 movs r3, #1
80033a4: 61bb str r3, [r7, #24]
}
}
/*------------------------------------ SAI2 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
80033a6: 687b ldr r3, [r7, #4]
80033a8: 681b ldr r3, [r3, #0]
80033aa: f403 1380 and.w r3, r3, #1048576 @ 0x100000
80033ae: 2b00 cmp r3, #0
80033b0: d017 beq.n 80033e2 <HAL_RCCEx_PeriphCLKConfig+0xc2>
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
/* Configure SAI2 Clock source */
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
80033b2: 4b4a ldr r3, [pc, #296] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80033b4: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
80033b8: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
80033bc: 687b ldr r3, [r7, #4]
80033be: 6b9b ldr r3, [r3, #56] @ 0x38
80033c0: 4946 ldr r1, [pc, #280] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80033c2: 4313 orrs r3, r2
80033c4: f8c1 308c str.w r3, [r1, #140] @ 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
80033c8: 687b ldr r3, [r7, #4]
80033ca: 6b9b ldr r3, [r3, #56] @ 0x38
80033cc: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
80033d0: d101 bne.n 80033d6 <HAL_RCCEx_PeriphCLKConfig+0xb6>
{
plli2sused = 1;
80033d2: 2301 movs r3, #1
80033d4: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
80033d6: 687b ldr r3, [r7, #4]
80033d8: 6b9b ldr r3, [r3, #56] @ 0x38
80033da: 2b00 cmp r3, #0
80033dc: d101 bne.n 80033e2 <HAL_RCCEx_PeriphCLKConfig+0xc2>
{
pllsaiused = 1;
80033de: 2301 movs r3, #1
80033e0: 61bb str r3, [r7, #24]
}
}
/*------------------------------------ RTC configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
80033e2: 687b ldr r3, [r7, #4]
80033e4: 681b ldr r3, [r3, #0]
80033e6: f003 0320 and.w r3, r3, #32
80033ea: 2b00 cmp r3, #0
80033ec: f000 808b beq.w 8003506 <HAL_RCCEx_PeriphCLKConfig+0x1e6>
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
80033f0: 4b3a ldr r3, [pc, #232] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80033f2: 6c1b ldr r3, [r3, #64] @ 0x40
80033f4: 4a39 ldr r2, [pc, #228] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80033f6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80033fa: 6413 str r3, [r2, #64] @ 0x40
80033fc: 4b37 ldr r3, [pc, #220] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80033fe: 6c1b ldr r3, [r3, #64] @ 0x40
8003400: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003404: 60fb str r3, [r7, #12]
8003406: 68fb ldr r3, [r7, #12]
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
8003408: 4b35 ldr r3, [pc, #212] @ (80034e0 <HAL_RCCEx_PeriphCLKConfig+0x1c0>)
800340a: 681b ldr r3, [r3, #0]
800340c: 4a34 ldr r2, [pc, #208] @ (80034e0 <HAL_RCCEx_PeriphCLKConfig+0x1c0>)
800340e: f443 7380 orr.w r3, r3, #256 @ 0x100
8003412: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003414: f7fe fe3a bl 800208c <HAL_GetTick>
8003418: 6178 str r0, [r7, #20]
/* Wait for Backup domain Write protection disable */
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
800341a: e008 b.n 800342e <HAL_RCCEx_PeriphCLKConfig+0x10e>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
800341c: f7fe fe36 bl 800208c <HAL_GetTick>
8003420: 4602 mov r2, r0
8003422: 697b ldr r3, [r7, #20]
8003424: 1ad3 subs r3, r2, r3
8003426: 2b64 cmp r3, #100 @ 0x64
8003428: d901 bls.n 800342e <HAL_RCCEx_PeriphCLKConfig+0x10e>
{
return HAL_TIMEOUT;
800342a: 2303 movs r3, #3
800342c: e2bc b.n 80039a8 <HAL_RCCEx_PeriphCLKConfig+0x688>
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
800342e: 4b2c ldr r3, [pc, #176] @ (80034e0 <HAL_RCCEx_PeriphCLKConfig+0x1c0>)
8003430: 681b ldr r3, [r3, #0]
8003432: f403 7380 and.w r3, r3, #256 @ 0x100
8003436: 2b00 cmp r3, #0
8003438: d0f0 beq.n 800341c <HAL_RCCEx_PeriphCLKConfig+0xfc>
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified */
tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
800343a: 4b28 ldr r3, [pc, #160] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
800343c: 6f1b ldr r3, [r3, #112] @ 0x70
800343e: f403 7340 and.w r3, r3, #768 @ 0x300
8003442: 613b str r3, [r7, #16]
if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
8003444: 693b ldr r3, [r7, #16]
8003446: 2b00 cmp r3, #0
8003448: d035 beq.n 80034b6 <HAL_RCCEx_PeriphCLKConfig+0x196>
800344a: 687b ldr r3, [r7, #4]
800344c: 6a9b ldr r3, [r3, #40] @ 0x28
800344e: f403 7340 and.w r3, r3, #768 @ 0x300
8003452: 693a ldr r2, [r7, #16]
8003454: 429a cmp r2, r3
8003456: d02e beq.n 80034b6 <HAL_RCCEx_PeriphCLKConfig+0x196>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8003458: 4b20 ldr r3, [pc, #128] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
800345a: 6f1b ldr r3, [r3, #112] @ 0x70
800345c: f423 7340 bic.w r3, r3, #768 @ 0x300
8003460: 613b str r3, [r7, #16]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8003462: 4b1e ldr r3, [pc, #120] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8003464: 6f1b ldr r3, [r3, #112] @ 0x70
8003466: 4a1d ldr r2, [pc, #116] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8003468: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800346c: 6713 str r3, [r2, #112] @ 0x70
__HAL_RCC_BACKUPRESET_RELEASE();
800346e: 4b1b ldr r3, [pc, #108] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8003470: 6f1b ldr r3, [r3, #112] @ 0x70
8003472: 4a1a ldr r2, [pc, #104] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8003474: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8003478: 6713 str r3, [r2, #112] @ 0x70
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg0;
800347a: 4a18 ldr r2, [pc, #96] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
800347c: 693b ldr r3, [r7, #16]
800347e: 6713 str r3, [r2, #112] @ 0x70
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
8003480: 4b16 ldr r3, [pc, #88] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8003482: 6f1b ldr r3, [r3, #112] @ 0x70
8003484: f003 0301 and.w r3, r3, #1
8003488: 2b01 cmp r3, #1
800348a: d114 bne.n 80034b6 <HAL_RCCEx_PeriphCLKConfig+0x196>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800348c: f7fe fdfe bl 800208c <HAL_GetTick>
8003490: 6178 str r0, [r7, #20]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8003492: e00a b.n 80034aa <HAL_RCCEx_PeriphCLKConfig+0x18a>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8003494: f7fe fdfa bl 800208c <HAL_GetTick>
8003498: 4602 mov r2, r0
800349a: 697b ldr r3, [r7, #20]
800349c: 1ad3 subs r3, r2, r3
800349e: f241 3288 movw r2, #5000 @ 0x1388
80034a2: 4293 cmp r3, r2
80034a4: d901 bls.n 80034aa <HAL_RCCEx_PeriphCLKConfig+0x18a>
{
return HAL_TIMEOUT;
80034a6: 2303 movs r3, #3
80034a8: e27e b.n 80039a8 <HAL_RCCEx_PeriphCLKConfig+0x688>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80034aa: 4b0c ldr r3, [pc, #48] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80034ac: 6f1b ldr r3, [r3, #112] @ 0x70
80034ae: f003 0302 and.w r3, r3, #2
80034b2: 2b00 cmp r3, #0
80034b4: d0ee beq.n 8003494 <HAL_RCCEx_PeriphCLKConfig+0x174>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
80034b6: 687b ldr r3, [r7, #4]
80034b8: 6a9b ldr r3, [r3, #40] @ 0x28
80034ba: f403 7340 and.w r3, r3, #768 @ 0x300
80034be: f5b3 7f40 cmp.w r3, #768 @ 0x300
80034c2: d111 bne.n 80034e8 <HAL_RCCEx_PeriphCLKConfig+0x1c8>
80034c4: 4b05 ldr r3, [pc, #20] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80034c6: 689b ldr r3, [r3, #8]
80034c8: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000
80034cc: 687b ldr r3, [r7, #4]
80034ce: 6a99 ldr r1, [r3, #40] @ 0x28
80034d0: 4b04 ldr r3, [pc, #16] @ (80034e4 <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
80034d2: 400b ands r3, r1
80034d4: 4901 ldr r1, [pc, #4] @ (80034dc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80034d6: 4313 orrs r3, r2
80034d8: 608b str r3, [r1, #8]
80034da: e00b b.n 80034f4 <HAL_RCCEx_PeriphCLKConfig+0x1d4>
80034dc: 40023800 .word 0x40023800
80034e0: 40007000 .word 0x40007000
80034e4: 0ffffcff .word 0x0ffffcff
80034e8: 4ba4 ldr r3, [pc, #656] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80034ea: 689b ldr r3, [r3, #8]
80034ec: 4aa3 ldr r2, [pc, #652] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80034ee: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000
80034f2: 6093 str r3, [r2, #8]
80034f4: 4ba1 ldr r3, [pc, #644] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80034f6: 6f1a ldr r2, [r3, #112] @ 0x70
80034f8: 687b ldr r3, [r7, #4]
80034fa: 6a9b ldr r3, [r3, #40] @ 0x28
80034fc: f3c3 030b ubfx r3, r3, #0, #12
8003500: 499e ldr r1, [pc, #632] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003502: 4313 orrs r3, r2
8003504: 670b str r3, [r1, #112] @ 0x70
}
/*------------------------------------ TIM configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
8003506: 687b ldr r3, [r7, #4]
8003508: 681b ldr r3, [r3, #0]
800350a: f003 0310 and.w r3, r3, #16
800350e: 2b00 cmp r3, #0
8003510: d010 beq.n 8003534 <HAL_RCCEx_PeriphCLKConfig+0x214>
{
/* Check the parameters */
assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
/* Configure Timer Prescaler */
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
8003512: 4b9a ldr r3, [pc, #616] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003514: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8003518: 4a98 ldr r2, [pc, #608] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800351a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
800351e: f8c2 308c str.w r3, [r2, #140] @ 0x8c
8003522: 4b96 ldr r3, [pc, #600] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003524: f8d3 208c ldr.w r2, [r3, #140] @ 0x8c
8003528: 687b ldr r3, [r7, #4]
800352a: 6b1b ldr r3, [r3, #48] @ 0x30
800352c: 4993 ldr r1, [pc, #588] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800352e: 4313 orrs r3, r2
8003530: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*-------------------------------------- I2C1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
8003534: 687b ldr r3, [r7, #4]
8003536: 681b ldr r3, [r3, #0]
8003538: f403 4380 and.w r3, r3, #16384 @ 0x4000
800353c: 2b00 cmp r3, #0
800353e: d00a beq.n 8003556 <HAL_RCCEx_PeriphCLKConfig+0x236>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
8003540: 4b8e ldr r3, [pc, #568] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003542: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003546: f423 3240 bic.w r2, r3, #196608 @ 0x30000
800354a: 687b ldr r3, [r7, #4]
800354c: 6ddb ldr r3, [r3, #92] @ 0x5c
800354e: 498b ldr r1, [pc, #556] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003550: 4313 orrs r3, r2
8003552: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- I2C2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
8003556: 687b ldr r3, [r7, #4]
8003558: 681b ldr r3, [r3, #0]
800355a: f403 4300 and.w r3, r3, #32768 @ 0x8000
800355e: 2b00 cmp r3, #0
8003560: d00a beq.n 8003578 <HAL_RCCEx_PeriphCLKConfig+0x258>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
8003562: 4b86 ldr r3, [pc, #536] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003564: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003568: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
800356c: 687b ldr r3, [r7, #4]
800356e: 6e1b ldr r3, [r3, #96] @ 0x60
8003570: 4982 ldr r1, [pc, #520] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003572: 4313 orrs r3, r2
8003574: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- I2C3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
8003578: 687b ldr r3, [r7, #4]
800357a: 681b ldr r3, [r3, #0]
800357c: f403 3380 and.w r3, r3, #65536 @ 0x10000
8003580: 2b00 cmp r3, #0
8003582: d00a beq.n 800359a <HAL_RCCEx_PeriphCLKConfig+0x27a>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
8003584: 4b7d ldr r3, [pc, #500] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003586: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800358a: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
800358e: 687b ldr r3, [r7, #4]
8003590: 6e5b ldr r3, [r3, #100] @ 0x64
8003592: 497a ldr r1, [pc, #488] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003594: 4313 orrs r3, r2
8003596: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
800359a: 687b ldr r3, [r7, #4]
800359c: 681b ldr r3, [r3, #0]
800359e: f003 0340 and.w r3, r3, #64 @ 0x40
80035a2: 2b00 cmp r3, #0
80035a4: d00a beq.n 80035bc <HAL_RCCEx_PeriphCLKConfig+0x29c>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
80035a6: 4b75 ldr r3, [pc, #468] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80035a8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80035ac: f023 0203 bic.w r2, r3, #3
80035b0: 687b ldr r3, [r7, #4]
80035b2: 6bdb ldr r3, [r3, #60] @ 0x3c
80035b4: 4971 ldr r1, [pc, #452] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80035b6: 4313 orrs r3, r2
80035b8: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
80035bc: 687b ldr r3, [r7, #4]
80035be: 681b ldr r3, [r3, #0]
80035c0: f003 0380 and.w r3, r3, #128 @ 0x80
80035c4: 2b00 cmp r3, #0
80035c6: d00a beq.n 80035de <HAL_RCCEx_PeriphCLKConfig+0x2be>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
80035c8: 4b6c ldr r3, [pc, #432] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80035ca: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80035ce: f023 020c bic.w r2, r3, #12
80035d2: 687b ldr r3, [r7, #4]
80035d4: 6c1b ldr r3, [r3, #64] @ 0x40
80035d6: 4969 ldr r1, [pc, #420] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80035d8: 4313 orrs r3, r2
80035da: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
80035de: 687b ldr r3, [r7, #4]
80035e0: 681b ldr r3, [r3, #0]
80035e2: f403 7380 and.w r3, r3, #256 @ 0x100
80035e6: 2b00 cmp r3, #0
80035e8: d00a beq.n 8003600 <HAL_RCCEx_PeriphCLKConfig+0x2e0>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
80035ea: 4b64 ldr r3, [pc, #400] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80035ec: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80035f0: f023 0230 bic.w r2, r3, #48 @ 0x30
80035f4: 687b ldr r3, [r7, #4]
80035f6: 6c5b ldr r3, [r3, #68] @ 0x44
80035f8: 4960 ldr r1, [pc, #384] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80035fa: 4313 orrs r3, r2
80035fc: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
8003600: 687b ldr r3, [r7, #4]
8003602: 681b ldr r3, [r3, #0]
8003604: f403 7300 and.w r3, r3, #512 @ 0x200
8003608: 2b00 cmp r3, #0
800360a: d00a beq.n 8003622 <HAL_RCCEx_PeriphCLKConfig+0x302>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
800360c: 4b5b ldr r3, [pc, #364] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800360e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003612: f023 02c0 bic.w r2, r3, #192 @ 0xc0
8003616: 687b ldr r3, [r7, #4]
8003618: 6c9b ldr r3, [r3, #72] @ 0x48
800361a: 4958 ldr r1, [pc, #352] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800361c: 4313 orrs r3, r2
800361e: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART5 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
8003622: 687b ldr r3, [r7, #4]
8003624: 681b ldr r3, [r3, #0]
8003626: f403 6380 and.w r3, r3, #1024 @ 0x400
800362a: 2b00 cmp r3, #0
800362c: d00a beq.n 8003644 <HAL_RCCEx_PeriphCLKConfig+0x324>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
800362e: 4b53 ldr r3, [pc, #332] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003630: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003634: f423 7240 bic.w r2, r3, #768 @ 0x300
8003638: 687b ldr r3, [r7, #4]
800363a: 6cdb ldr r3, [r3, #76] @ 0x4c
800363c: 494f ldr r1, [pc, #316] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800363e: 4313 orrs r3, r2
8003640: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART6 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
8003644: 687b ldr r3, [r7, #4]
8003646: 681b ldr r3, [r3, #0]
8003648: f403 6300 and.w r3, r3, #2048 @ 0x800
800364c: 2b00 cmp r3, #0
800364e: d00a beq.n 8003666 <HAL_RCCEx_PeriphCLKConfig+0x346>
{
/* Check the parameters */
assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
/* Configure the USART6 clock source */
__HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
8003650: 4b4a ldr r3, [pc, #296] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003652: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003656: f423 6240 bic.w r2, r3, #3072 @ 0xc00
800365a: 687b ldr r3, [r7, #4]
800365c: 6d1b ldr r3, [r3, #80] @ 0x50
800365e: 4947 ldr r1, [pc, #284] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003660: 4313 orrs r3, r2
8003662: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART7 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
8003666: 687b ldr r3, [r7, #4]
8003668: 681b ldr r3, [r3, #0]
800366a: f403 5380 and.w r3, r3, #4096 @ 0x1000
800366e: 2b00 cmp r3, #0
8003670: d00a beq.n 8003688 <HAL_RCCEx_PeriphCLKConfig+0x368>
{
/* Check the parameters */
assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
/* Configure the UART7 clock source */
__HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
8003672: 4b42 ldr r3, [pc, #264] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003674: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003678: f423 5240 bic.w r2, r3, #12288 @ 0x3000
800367c: 687b ldr r3, [r7, #4]
800367e: 6d5b ldr r3, [r3, #84] @ 0x54
8003680: 493e ldr r1, [pc, #248] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003682: 4313 orrs r3, r2
8003684: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART8 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
8003688: 687b ldr r3, [r7, #4]
800368a: 681b ldr r3, [r3, #0]
800368c: f403 5300 and.w r3, r3, #8192 @ 0x2000
8003690: 2b00 cmp r3, #0
8003692: d00a beq.n 80036aa <HAL_RCCEx_PeriphCLKConfig+0x38a>
{
/* Check the parameters */
assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
/* Configure the UART8 clock source */
__HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
8003694: 4b39 ldr r3, [pc, #228] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003696: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800369a: f423 4240 bic.w r2, r3, #49152 @ 0xc000
800369e: 687b ldr r3, [r7, #4]
80036a0: 6d9b ldr r3, [r3, #88] @ 0x58
80036a2: 4936 ldr r1, [pc, #216] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80036a4: 4313 orrs r3, r2
80036a6: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- CK48 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
80036aa: 687b ldr r3, [r7, #4]
80036ac: 681b ldr r3, [r3, #0]
80036ae: f403 1300 and.w r3, r3, #2097152 @ 0x200000
80036b2: 2b00 cmp r3, #0
80036b4: d011 beq.n 80036da <HAL_RCCEx_PeriphCLKConfig+0x3ba>
{
/* Check the parameters */
assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
/* Configure the CLK48 source */
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
80036b6: 4b31 ldr r3, [pc, #196] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80036b8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80036bc: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000
80036c0: 687b ldr r3, [r7, #4]
80036c2: 6f5b ldr r3, [r3, #116] @ 0x74
80036c4: 492d ldr r1, [pc, #180] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80036c6: 4313 orrs r3, r2
80036c8: f8c1 3090 str.w r3, [r1, #144] @ 0x90
/* Enable the PLLSAI when it's used as clock source for CK48 */
if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
80036cc: 687b ldr r3, [r7, #4]
80036ce: 6f5b ldr r3, [r3, #116] @ 0x74
80036d0: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
80036d4: d101 bne.n 80036da <HAL_RCCEx_PeriphCLKConfig+0x3ba>
{
pllsaiused = 1;
80036d6: 2301 movs r3, #1
80036d8: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
80036da: 687b ldr r3, [r7, #4]
80036dc: 681b ldr r3, [r3, #0]
80036de: f403 2380 and.w r3, r3, #262144 @ 0x40000
80036e2: 2b00 cmp r3, #0
80036e4: d00a beq.n 80036fc <HAL_RCCEx_PeriphCLKConfig+0x3dc>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LTPIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
80036e6: 4b25 ldr r3, [pc, #148] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80036e8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80036ec: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
80036f0: 687b ldr r3, [r7, #4]
80036f2: 6edb ldr r3, [r3, #108] @ 0x6c
80036f4: 4921 ldr r1, [pc, #132] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80036f6: 4313 orrs r3, r2
80036f8: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*------------------------------------- SDMMC1 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
80036fc: 687b ldr r3, [r7, #4]
80036fe: 681b ldr r3, [r3, #0]
8003700: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8003704: 2b00 cmp r3, #0
8003706: d00a beq.n 800371e <HAL_RCCEx_PeriphCLKConfig+0x3fe>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
/* Configure the SDMMC1 clock source */
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
8003708: 4b1c ldr r3, [pc, #112] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800370a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800370e: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000
8003712: 687b ldr r3, [r7, #4]
8003714: 6f9b ldr r3, [r3, #120] @ 0x78
8003716: 4919 ldr r1, [pc, #100] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003718: 4313 orrs r3, r2
800371a: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*------------------------------------- SDMMC2 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
800371e: 687b ldr r3, [r7, #4]
8003720: 681b ldr r3, [r3, #0]
8003722: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
8003726: 2b00 cmp r3, #0
8003728: d00a beq.n 8003740 <HAL_RCCEx_PeriphCLKConfig+0x420>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
/* Configure the SDMMC2 clock source */
__HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
800372a: 4b14 ldr r3, [pc, #80] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800372c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003730: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000
8003734: 687b ldr r3, [r7, #4]
8003736: 6fdb ldr r3, [r3, #124] @ 0x7c
8003738: 4910 ldr r1, [pc, #64] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800373a: 4313 orrs r3, r2
800373c: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */
if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
8003740: 69fb ldr r3, [r7, #28]
8003742: 2b01 cmp r3, #1
8003744: d006 beq.n 8003754 <HAL_RCCEx_PeriphCLKConfig+0x434>
8003746: 687b ldr r3, [r7, #4]
8003748: 681b ldr r3, [r3, #0]
800374a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800374e: 2b00 cmp r3, #0
8003750: f000 809d beq.w 800388e <HAL_RCCEx_PeriphCLKConfig+0x56e>
{
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
8003754: 4b09 ldr r3, [pc, #36] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003756: 681b ldr r3, [r3, #0]
8003758: 4a08 ldr r2, [pc, #32] @ (800377c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800375a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
800375e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003760: f7fe fc94 bl 800208c <HAL_GetTick>
8003764: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8003766: e00b b.n 8003780 <HAL_RCCEx_PeriphCLKConfig+0x460>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
8003768: f7fe fc90 bl 800208c <HAL_GetTick>
800376c: 4602 mov r2, r0
800376e: 697b ldr r3, [r7, #20]
8003770: 1ad3 subs r3, r2, r3
8003772: 2b64 cmp r3, #100 @ 0x64
8003774: d904 bls.n 8003780 <HAL_RCCEx_PeriphCLKConfig+0x460>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8003776: 2303 movs r3, #3
8003778: e116 b.n 80039a8 <HAL_RCCEx_PeriphCLKConfig+0x688>
800377a: bf00 nop
800377c: 40023800 .word 0x40023800
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8003780: 4b8b ldr r3, [pc, #556] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003782: 681b ldr r3, [r3, #0]
8003784: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
8003788: 2b00 cmp r3, #0
800378a: d1ed bne.n 8003768 <HAL_RCCEx_PeriphCLKConfig+0x448>
/* check for common PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
/*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
800378c: 687b ldr r3, [r7, #4]
800378e: 681b ldr r3, [r3, #0]
8003790: f003 0301 and.w r3, r3, #1
8003794: 2b00 cmp r3, #0
8003796: d017 beq.n 80037c8 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
8003798: 687b ldr r3, [r7, #4]
800379a: 6adb ldr r3, [r3, #44] @ 0x2c
800379c: 2b00 cmp r3, #0
800379e: d113 bne.n 80037c8 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
80037a0: 4b83 ldr r3, [pc, #524] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80037a2: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
80037a6: 0e1b lsrs r3, r3, #24
80037a8: f003 030f and.w r3, r3, #15
80037ac: 613b str r3, [r7, #16]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2SR);
80037ae: 687b ldr r3, [r7, #4]
80037b0: 685b ldr r3, [r3, #4]
80037b2: 019a lsls r2, r3, #6
80037b4: 693b ldr r3, [r7, #16]
80037b6: 061b lsls r3, r3, #24
80037b8: 431a orrs r2, r3
80037ba: 687b ldr r3, [r7, #4]
80037bc: 689b ldr r3, [r3, #8]
80037be: 071b lsls r3, r3, #28
80037c0: 497b ldr r1, [pc, #492] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80037c2: 4313 orrs r3, r2
80037c4: f8c1 3084 str.w r3, [r1, #132] @ 0x84
}
/*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
80037c8: 687b ldr r3, [r7, #4]
80037ca: 681b ldr r3, [r3, #0]
80037cc: f403 2300 and.w r3, r3, #524288 @ 0x80000
80037d0: 2b00 cmp r3, #0
80037d2: d004 beq.n 80037de <HAL_RCCEx_PeriphCLKConfig+0x4be>
80037d4: 687b ldr r3, [r7, #4]
80037d6: 6b5b ldr r3, [r3, #52] @ 0x34
80037d8: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
80037dc: d00a beq.n 80037f4 <HAL_RCCEx_PeriphCLKConfig+0x4d4>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
80037de: 687b ldr r3, [r7, #4]
80037e0: 681b ldr r3, [r3, #0]
80037e2: f403 1380 and.w r3, r3, #1048576 @ 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
80037e6: 2b00 cmp r3, #0
80037e8: d024 beq.n 8003834 <HAL_RCCEx_PeriphCLKConfig+0x514>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
80037ea: 687b ldr r3, [r7, #4]
80037ec: 6b9b ldr r3, [r3, #56] @ 0x38
80037ee: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
80037f2: d11f bne.n 8003834 <HAL_RCCEx_PeriphCLKConfig+0x514>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Check for PLLI2S/DIVQ parameters */
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
80037f4: 4b6e ldr r3, [pc, #440] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80037f6: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
80037fa: 0f1b lsrs r3, r3, #28
80037fc: f003 0307 and.w r3, r3, #7
8003800: 613b str r3, [r7, #16]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0);
8003802: 687b ldr r3, [r7, #4]
8003804: 685b ldr r3, [r3, #4]
8003806: 019a lsls r2, r3, #6
8003808: 687b ldr r3, [r7, #4]
800380a: 68db ldr r3, [r3, #12]
800380c: 061b lsls r3, r3, #24
800380e: 431a orrs r2, r3
8003810: 693b ldr r3, [r7, #16]
8003812: 071b lsls r3, r3, #28
8003814: 4966 ldr r1, [pc, #408] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003816: 4313 orrs r3, r2
8003818: f8c1 3084 str.w r3, [r1, #132] @ 0x84
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
800381c: 4b64 ldr r3, [pc, #400] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800381e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8003822: f023 021f bic.w r2, r3, #31
8003826: 687b ldr r3, [r7, #4]
8003828: 69db ldr r3, [r3, #28]
800382a: 3b01 subs r3, #1
800382c: 4960 ldr r1, [pc, #384] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800382e: 4313 orrs r3, r2
8003830: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
8003834: 687b ldr r3, [r7, #4]
8003836: 681b ldr r3, [r3, #0]
8003838: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800383c: 2b00 cmp r3, #0
800383e: d00d beq.n 800385c <HAL_RCCEx_PeriphCLKConfig+0x53c>
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
8003840: 687b ldr r3, [r7, #4]
8003842: 685b ldr r3, [r3, #4]
8003844: 019a lsls r2, r3, #6
8003846: 687b ldr r3, [r7, #4]
8003848: 68db ldr r3, [r3, #12]
800384a: 061b lsls r3, r3, #24
800384c: 431a orrs r2, r3
800384e: 687b ldr r3, [r7, #4]
8003850: 689b ldr r3, [r3, #8]
8003852: 071b lsls r3, r3, #28
8003854: 4956 ldr r1, [pc, #344] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003856: 4313 orrs r3, r2
8003858: f8c1 3084 str.w r3, [r1, #132] @ 0x84
}
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
800385c: 4b54 ldr r3, [pc, #336] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800385e: 681b ldr r3, [r3, #0]
8003860: 4a53 ldr r2, [pc, #332] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003862: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
8003866: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003868: f7fe fc10 bl 800208c <HAL_GetTick>
800386c: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
800386e: e008 b.n 8003882 <HAL_RCCEx_PeriphCLKConfig+0x562>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
8003870: f7fe fc0c bl 800208c <HAL_GetTick>
8003874: 4602 mov r2, r0
8003876: 697b ldr r3, [r7, #20]
8003878: 1ad3 subs r3, r2, r3
800387a: 2b64 cmp r3, #100 @ 0x64
800387c: d901 bls.n 8003882 <HAL_RCCEx_PeriphCLKConfig+0x562>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
800387e: 2303 movs r3, #3
8003880: e092 b.n 80039a8 <HAL_RCCEx_PeriphCLKConfig+0x688>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
8003882: 4b4b ldr r3, [pc, #300] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003884: 681b ldr r3, [r3, #0]
8003886: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
800388a: 2b00 cmp r3, #0
800388c: d0f0 beq.n 8003870 <HAL_RCCEx_PeriphCLKConfig+0x550>
}
}
/*-------------------------------------- PLLSAI Configuration ---------------------------------*/
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
if(pllsaiused == 1)
800388e: 69bb ldr r3, [r7, #24]
8003890: 2b01 cmp r3, #1
8003892: f040 8088 bne.w 80039a6 <HAL_RCCEx_PeriphCLKConfig+0x686>
{
/* Disable PLLSAI Clock */
__HAL_RCC_PLLSAI_DISABLE();
8003896: 4b46 ldr r3, [pc, #280] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003898: 681b ldr r3, [r3, #0]
800389a: 4a45 ldr r2, [pc, #276] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800389c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80038a0: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80038a2: f7fe fbf3 bl 800208c <HAL_GetTick>
80038a6: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
80038a8: e008 b.n 80038bc <HAL_RCCEx_PeriphCLKConfig+0x59c>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
80038aa: f7fe fbef bl 800208c <HAL_GetTick>
80038ae: 4602 mov r2, r0
80038b0: 697b ldr r3, [r7, #20]
80038b2: 1ad3 subs r3, r2, r3
80038b4: 2b64 cmp r3, #100 @ 0x64
80038b6: d901 bls.n 80038bc <HAL_RCCEx_PeriphCLKConfig+0x59c>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
80038b8: 2303 movs r3, #3
80038ba: e075 b.n 80039a8 <HAL_RCCEx_PeriphCLKConfig+0x688>
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
80038bc: 4b3c ldr r3, [pc, #240] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80038be: 681b ldr r3, [r3, #0]
80038c0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
80038c4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
80038c8: d0ef beq.n 80038aa <HAL_RCCEx_PeriphCLKConfig+0x58a>
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
/*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
80038ca: 687b ldr r3, [r7, #4]
80038cc: 681b ldr r3, [r3, #0]
80038ce: f403 2300 and.w r3, r3, #524288 @ 0x80000
80038d2: 2b00 cmp r3, #0
80038d4: d003 beq.n 80038de <HAL_RCCEx_PeriphCLKConfig+0x5be>
80038d6: 687b ldr r3, [r7, #4]
80038d8: 6b5b ldr r3, [r3, #52] @ 0x34
80038da: 2b00 cmp r3, #0
80038dc: d009 beq.n 80038f2 <HAL_RCCEx_PeriphCLKConfig+0x5d2>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
80038de: 687b ldr r3, [r7, #4]
80038e0: 681b ldr r3, [r3, #0]
80038e2: f403 1380 and.w r3, r3, #1048576 @ 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
80038e6: 2b00 cmp r3, #0
80038e8: d024 beq.n 8003934 <HAL_RCCEx_PeriphCLKConfig+0x614>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
80038ea: 687b ldr r3, [r7, #4]
80038ec: 6b9b ldr r3, [r3, #56] @ 0x38
80038ee: 2b00 cmp r3, #0
80038f0: d120 bne.n 8003934 <HAL_RCCEx_PeriphCLKConfig+0x614>
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
/* check for PLLSAI/DIVQ Parameter */
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
80038f2: 4b2f ldr r3, [pc, #188] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80038f4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80038f8: 0c1b lsrs r3, r3, #16
80038fa: f003 0303 and.w r3, r3, #3
80038fe: 613b str r3, [r7, #16]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ);
8003900: 687b ldr r3, [r7, #4]
8003902: 691b ldr r3, [r3, #16]
8003904: 019a lsls r2, r3, #6
8003906: 693b ldr r3, [r7, #16]
8003908: 041b lsls r3, r3, #16
800390a: 431a orrs r2, r3
800390c: 687b ldr r3, [r7, #4]
800390e: 695b ldr r3, [r3, #20]
8003910: 061b lsls r3, r3, #24
8003912: 4927 ldr r1, [pc, #156] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003914: 4313 orrs r3, r2
8003916: f8c1 3088 str.w r3, [r1, #136] @ 0x88
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
800391a: 4b25 ldr r3, [pc, #148] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800391c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8003920: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
8003924: 687b ldr r3, [r7, #4]
8003926: 6a1b ldr r3, [r3, #32]
8003928: 3b01 subs r3, #1
800392a: 021b lsls r3, r3, #8
800392c: 4920 ldr r1, [pc, #128] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800392e: 4313 orrs r3, r2
8003930: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
/* In Case of PLLI2S is selected as source clock for CK48 */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
8003934: 687b ldr r3, [r7, #4]
8003936: 681b ldr r3, [r3, #0]
8003938: f403 1300 and.w r3, r3, #2097152 @ 0x200000
800393c: 2b00 cmp r3, #0
800393e: d018 beq.n 8003972 <HAL_RCCEx_PeriphCLKConfig+0x652>
8003940: 687b ldr r3, [r7, #4]
8003942: 6f5b ldr r3, [r3, #116] @ 0x74
8003944: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
8003948: d113 bne.n 8003972 <HAL_RCCEx_PeriphCLKConfig+0x652>
{
/* check for Parameters */
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
800394a: 4b19 ldr r3, [pc, #100] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800394c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003950: 0e1b lsrs r3, r3, #24
8003952: f003 030f and.w r3, r3, #15
8003956: 613b str r3, [r7, #16]
/* Configure the PLLSAI division factors */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0);
8003958: 687b ldr r3, [r7, #4]
800395a: 691b ldr r3, [r3, #16]
800395c: 019a lsls r2, r3, #6
800395e: 687b ldr r3, [r7, #4]
8003960: 699b ldr r3, [r3, #24]
8003962: 041b lsls r3, r3, #16
8003964: 431a orrs r2, r3
8003966: 693b ldr r3, [r7, #16]
8003968: 061b lsls r3, r3, #24
800396a: 4911 ldr r1, [pc, #68] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800396c: 4313 orrs r3, r2
800396e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
8003972: 4b0f ldr r3, [pc, #60] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003974: 681b ldr r3, [r3, #0]
8003976: 4a0e ldr r2, [pc, #56] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003978: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800397c: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800397e: f7fe fb85 bl 800208c <HAL_GetTick>
8003982: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is ready */
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
8003984: e008 b.n 8003998 <HAL_RCCEx_PeriphCLKConfig+0x678>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
8003986: f7fe fb81 bl 800208c <HAL_GetTick>
800398a: 4602 mov r2, r0
800398c: 697b ldr r3, [r7, #20]
800398e: 1ad3 subs r3, r2, r3
8003990: 2b64 cmp r3, #100 @ 0x64
8003992: d901 bls.n 8003998 <HAL_RCCEx_PeriphCLKConfig+0x678>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8003994: 2303 movs r3, #3
8003996: e007 b.n 80039a8 <HAL_RCCEx_PeriphCLKConfig+0x688>
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
8003998: 4b05 ldr r3, [pc, #20] @ (80039b0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800399a: 681b ldr r3, [r3, #0]
800399c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
80039a0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
80039a4: d1ef bne.n 8003986 <HAL_RCCEx_PeriphCLKConfig+0x666>
}
}
}
return HAL_OK;
80039a6: 2300 movs r3, #0
}
80039a8: 4618 mov r0, r3
80039aa: 3720 adds r7, #32
80039ac: 46bd mov sp, r7
80039ae: bd80 pop {r7, pc}
80039b0: 40023800 .word 0x40023800
080039b4 <HAL_SRAM_Init>:
* @param ExtTiming Pointer to SRAM extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
FMC_NORSRAM_TimingTypeDef *ExtTiming)
{
80039b4: b580 push {r7, lr}
80039b6: b084 sub sp, #16
80039b8: af00 add r7, sp, #0
80039ba: 60f8 str r0, [r7, #12]
80039bc: 60b9 str r1, [r7, #8]
80039be: 607a str r2, [r7, #4]
/* Check the SRAM handle parameter */
if (hsram == NULL)
80039c0: 68fb ldr r3, [r7, #12]
80039c2: 2b00 cmp r3, #0
80039c4: d101 bne.n 80039ca <HAL_SRAM_Init+0x16>
{
return HAL_ERROR;
80039c6: 2301 movs r3, #1
80039c8: e038 b.n 8003a3c <HAL_SRAM_Init+0x88>
}
if (hsram->State == HAL_SRAM_STATE_RESET)
80039ca: 68fb ldr r3, [r7, #12]
80039cc: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
80039d0: b2db uxtb r3, r3
80039d2: 2b00 cmp r3, #0
80039d4: d106 bne.n 80039e4 <HAL_SRAM_Init+0x30>
{
/* Allocate lock resource and initialize it */
hsram->Lock = HAL_UNLOCKED;
80039d6: 68fb ldr r3, [r7, #12]
80039d8: 2200 movs r2, #0
80039da: f883 2044 strb.w r2, [r3, #68] @ 0x44
/* Init the low level hardware */
hsram->MspInitCallback(hsram);
#else
/* Initialize the low level hardware (MSP) */
HAL_SRAM_MspInit(hsram);
80039de: 68f8 ldr r0, [r7, #12]
80039e0: f7fe f83a bl 8001a58 <HAL_SRAM_MspInit>
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
/* Initialize SRAM control Interface */
(void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
80039e4: 68fb ldr r3, [r7, #12]
80039e6: 681a ldr r2, [r3, #0]
80039e8: 68fb ldr r3, [r7, #12]
80039ea: 3308 adds r3, #8
80039ec: 4619 mov r1, r3
80039ee: 4610 mov r0, r2
80039f0: f000 fffc bl 80049ec <FMC_NORSRAM_Init>
/* Initialize SRAM timing Interface */
(void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
80039f4: 68fb ldr r3, [r7, #12]
80039f6: 6818 ldr r0, [r3, #0]
80039f8: 68fb ldr r3, [r7, #12]
80039fa: 689b ldr r3, [r3, #8]
80039fc: 461a mov r2, r3
80039fe: 68b9 ldr r1, [r7, #8]
8003a00: f001 f884 bl 8004b0c <FMC_NORSRAM_Timing_Init>
/* Initialize SRAM extended mode timing Interface */
(void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
8003a04: 68fb ldr r3, [r7, #12]
8003a06: 6858 ldr r0, [r3, #4]
8003a08: 68fb ldr r3, [r7, #12]
8003a0a: 689a ldr r2, [r3, #8]
8003a0c: 68fb ldr r3, [r7, #12]
8003a0e: 6adb ldr r3, [r3, #44] @ 0x2c
8003a10: 6879 ldr r1, [r7, #4]
8003a12: f001 f8c5 bl 8004ba0 <FMC_NORSRAM_Extended_Timing_Init>
hsram->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
8003a16: 68fb ldr r3, [r7, #12]
8003a18: 681b ldr r3, [r3, #0]
8003a1a: 68fa ldr r2, [r7, #12]
8003a1c: 6892 ldr r2, [r2, #8]
8003a1e: f853 1022 ldr.w r1, [r3, r2, lsl #2]
8003a22: 68fb ldr r3, [r7, #12]
8003a24: 681b ldr r3, [r3, #0]
8003a26: 68fa ldr r2, [r7, #12]
8003a28: 6892 ldr r2, [r2, #8]
8003a2a: f041 0101 orr.w r1, r1, #1
8003a2e: f843 1022 str.w r1, [r3, r2, lsl #2]
/* Initialize the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
8003a32: 68fb ldr r3, [r7, #12]
8003a34: 2201 movs r2, #1
8003a36: f883 2045 strb.w r2, [r3, #69] @ 0x45
return HAL_OK;
8003a3a: 2300 movs r3, #0
}
8003a3c: 4618 mov r0, r3
8003a3e: 3710 adds r7, #16
8003a40: 46bd mov sp, r7
8003a42: bd80 pop {r7, pc}
08003a44 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8003a44: b580 push {r7, lr}
8003a46: b082 sub sp, #8
8003a48: af00 add r7, sp, #0
8003a4a: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8003a4c: 687b ldr r3, [r7, #4]
8003a4e: 2b00 cmp r3, #0
8003a50: d101 bne.n 8003a56 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8003a52: 2301 movs r3, #1
8003a54: e049 b.n 8003aea <HAL_TIM_Base_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8003a56: 687b ldr r3, [r7, #4]
8003a58: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8003a5c: b2db uxtb r3, r3
8003a5e: 2b00 cmp r3, #0
8003a60: d106 bne.n 8003a70 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8003a62: 687b ldr r3, [r7, #4]
8003a64: 2200 movs r2, #0
8003a66: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8003a6a: 6878 ldr r0, [r7, #4]
8003a6c: f000 f841 bl 8003af2 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8003a70: 687b ldr r3, [r7, #4]
8003a72: 2202 movs r2, #2
8003a74: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8003a78: 687b ldr r3, [r7, #4]
8003a7a: 681a ldr r2, [r3, #0]
8003a7c: 687b ldr r3, [r7, #4]
8003a7e: 3304 adds r3, #4
8003a80: 4619 mov r1, r3
8003a82: 4610 mov r0, r2
8003a84: f000 f9e8 bl 8003e58 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8003a88: 687b ldr r3, [r7, #4]
8003a8a: 2201 movs r2, #1
8003a8c: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8003a90: 687b ldr r3, [r7, #4]
8003a92: 2201 movs r2, #1
8003a94: f883 203e strb.w r2, [r3, #62] @ 0x3e
8003a98: 687b ldr r3, [r7, #4]
8003a9a: 2201 movs r2, #1
8003a9c: f883 203f strb.w r2, [r3, #63] @ 0x3f
8003aa0: 687b ldr r3, [r7, #4]
8003aa2: 2201 movs r2, #1
8003aa4: f883 2040 strb.w r2, [r3, #64] @ 0x40
8003aa8: 687b ldr r3, [r7, #4]
8003aaa: 2201 movs r2, #1
8003aac: f883 2041 strb.w r2, [r3, #65] @ 0x41
8003ab0: 687b ldr r3, [r7, #4]
8003ab2: 2201 movs r2, #1
8003ab4: f883 2042 strb.w r2, [r3, #66] @ 0x42
8003ab8: 687b ldr r3, [r7, #4]
8003aba: 2201 movs r2, #1
8003abc: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8003ac0: 687b ldr r3, [r7, #4]
8003ac2: 2201 movs r2, #1
8003ac4: f883 2044 strb.w r2, [r3, #68] @ 0x44
8003ac8: 687b ldr r3, [r7, #4]
8003aca: 2201 movs r2, #1
8003acc: f883 2045 strb.w r2, [r3, #69] @ 0x45
8003ad0: 687b ldr r3, [r7, #4]
8003ad2: 2201 movs r2, #1
8003ad4: f883 2046 strb.w r2, [r3, #70] @ 0x46
8003ad8: 687b ldr r3, [r7, #4]
8003ada: 2201 movs r2, #1
8003adc: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8003ae0: 687b ldr r3, [r7, #4]
8003ae2: 2201 movs r2, #1
8003ae4: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8003ae8: 2300 movs r3, #0
}
8003aea: 4618 mov r0, r3
8003aec: 3708 adds r7, #8
8003aee: 46bd mov sp, r7
8003af0: bd80 pop {r7, pc}
08003af2 <HAL_TIM_Base_MspInit>:
* @brief Initializes the TIM Base MSP.
* @param htim TIM Base handle
* @retval None
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
8003af2: b480 push {r7}
8003af4: b083 sub sp, #12
8003af6: af00 add r7, sp, #0
8003af8: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Base_MspInit could be implemented in the user file
*/
}
8003afa: bf00 nop
8003afc: 370c adds r7, #12
8003afe: 46bd mov sp, r7
8003b00: f85d 7b04 ldr.w r7, [sp], #4
8003b04: 4770 bx lr
...
08003b08 <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8003b08: b480 push {r7}
8003b0a: b085 sub sp, #20
8003b0c: af00 add r7, sp, #0
8003b0e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
8003b10: 687b ldr r3, [r7, #4]
8003b12: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8003b16: b2db uxtb r3, r3
8003b18: 2b01 cmp r3, #1
8003b1a: d001 beq.n 8003b20 <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
8003b1c: 2301 movs r3, #1
8003b1e: e054 b.n 8003bca <HAL_TIM_Base_Start_IT+0xc2>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8003b20: 687b ldr r3, [r7, #4]
8003b22: 2202 movs r2, #2
8003b24: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8003b28: 687b ldr r3, [r7, #4]
8003b2a: 681b ldr r3, [r3, #0]
8003b2c: 68da ldr r2, [r3, #12]
8003b2e: 687b ldr r3, [r7, #4]
8003b30: 681b ldr r3, [r3, #0]
8003b32: f042 0201 orr.w r2, r2, #1
8003b36: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8003b38: 687b ldr r3, [r7, #4]
8003b3a: 681b ldr r3, [r3, #0]
8003b3c: 4a26 ldr r2, [pc, #152] @ (8003bd8 <HAL_TIM_Base_Start_IT+0xd0>)
8003b3e: 4293 cmp r3, r2
8003b40: d022 beq.n 8003b88 <HAL_TIM_Base_Start_IT+0x80>
8003b42: 687b ldr r3, [r7, #4]
8003b44: 681b ldr r3, [r3, #0]
8003b46: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8003b4a: d01d beq.n 8003b88 <HAL_TIM_Base_Start_IT+0x80>
8003b4c: 687b ldr r3, [r7, #4]
8003b4e: 681b ldr r3, [r3, #0]
8003b50: 4a22 ldr r2, [pc, #136] @ (8003bdc <HAL_TIM_Base_Start_IT+0xd4>)
8003b52: 4293 cmp r3, r2
8003b54: d018 beq.n 8003b88 <HAL_TIM_Base_Start_IT+0x80>
8003b56: 687b ldr r3, [r7, #4]
8003b58: 681b ldr r3, [r3, #0]
8003b5a: 4a21 ldr r2, [pc, #132] @ (8003be0 <HAL_TIM_Base_Start_IT+0xd8>)
8003b5c: 4293 cmp r3, r2
8003b5e: d013 beq.n 8003b88 <HAL_TIM_Base_Start_IT+0x80>
8003b60: 687b ldr r3, [r7, #4]
8003b62: 681b ldr r3, [r3, #0]
8003b64: 4a1f ldr r2, [pc, #124] @ (8003be4 <HAL_TIM_Base_Start_IT+0xdc>)
8003b66: 4293 cmp r3, r2
8003b68: d00e beq.n 8003b88 <HAL_TIM_Base_Start_IT+0x80>
8003b6a: 687b ldr r3, [r7, #4]
8003b6c: 681b ldr r3, [r3, #0]
8003b6e: 4a1e ldr r2, [pc, #120] @ (8003be8 <HAL_TIM_Base_Start_IT+0xe0>)
8003b70: 4293 cmp r3, r2
8003b72: d009 beq.n 8003b88 <HAL_TIM_Base_Start_IT+0x80>
8003b74: 687b ldr r3, [r7, #4]
8003b76: 681b ldr r3, [r3, #0]
8003b78: 4a1c ldr r2, [pc, #112] @ (8003bec <HAL_TIM_Base_Start_IT+0xe4>)
8003b7a: 4293 cmp r3, r2
8003b7c: d004 beq.n 8003b88 <HAL_TIM_Base_Start_IT+0x80>
8003b7e: 687b ldr r3, [r7, #4]
8003b80: 681b ldr r3, [r3, #0]
8003b82: 4a1b ldr r2, [pc, #108] @ (8003bf0 <HAL_TIM_Base_Start_IT+0xe8>)
8003b84: 4293 cmp r3, r2
8003b86: d115 bne.n 8003bb4 <HAL_TIM_Base_Start_IT+0xac>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8003b88: 687b ldr r3, [r7, #4]
8003b8a: 681b ldr r3, [r3, #0]
8003b8c: 689a ldr r2, [r3, #8]
8003b8e: 4b19 ldr r3, [pc, #100] @ (8003bf4 <HAL_TIM_Base_Start_IT+0xec>)
8003b90: 4013 ands r3, r2
8003b92: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8003b94: 68fb ldr r3, [r7, #12]
8003b96: 2b06 cmp r3, #6
8003b98: d015 beq.n 8003bc6 <HAL_TIM_Base_Start_IT+0xbe>
8003b9a: 68fb ldr r3, [r7, #12]
8003b9c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8003ba0: d011 beq.n 8003bc6 <HAL_TIM_Base_Start_IT+0xbe>
{
__HAL_TIM_ENABLE(htim);
8003ba2: 687b ldr r3, [r7, #4]
8003ba4: 681b ldr r3, [r3, #0]
8003ba6: 681a ldr r2, [r3, #0]
8003ba8: 687b ldr r3, [r7, #4]
8003baa: 681b ldr r3, [r3, #0]
8003bac: f042 0201 orr.w r2, r2, #1
8003bb0: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8003bb2: e008 b.n 8003bc6 <HAL_TIM_Base_Start_IT+0xbe>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8003bb4: 687b ldr r3, [r7, #4]
8003bb6: 681b ldr r3, [r3, #0]
8003bb8: 681a ldr r2, [r3, #0]
8003bba: 687b ldr r3, [r7, #4]
8003bbc: 681b ldr r3, [r3, #0]
8003bbe: f042 0201 orr.w r2, r2, #1
8003bc2: 601a str r2, [r3, #0]
8003bc4: e000 b.n 8003bc8 <HAL_TIM_Base_Start_IT+0xc0>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8003bc6: bf00 nop
}
/* Return function status */
return HAL_OK;
8003bc8: 2300 movs r3, #0
}
8003bca: 4618 mov r0, r3
8003bcc: 3714 adds r7, #20
8003bce: 46bd mov sp, r7
8003bd0: f85d 7b04 ldr.w r7, [sp], #4
8003bd4: 4770 bx lr
8003bd6: bf00 nop
8003bd8: 40010000 .word 0x40010000
8003bdc: 40000400 .word 0x40000400
8003be0: 40000800 .word 0x40000800
8003be4: 40000c00 .word 0x40000c00
8003be8: 40010400 .word 0x40010400
8003bec: 40014000 .word 0x40014000
8003bf0: 40001800 .word 0x40001800
8003bf4: 00010007 .word 0x00010007
08003bf8 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8003bf8: b580 push {r7, lr}
8003bfa: b084 sub sp, #16
8003bfc: af00 add r7, sp, #0
8003bfe: 6078 str r0, [r7, #4]
uint32_t itsource = htim->Instance->DIER;
8003c00: 687b ldr r3, [r7, #4]
8003c02: 681b ldr r3, [r3, #0]
8003c04: 68db ldr r3, [r3, #12]
8003c06: 60fb str r3, [r7, #12]
uint32_t itflag = htim->Instance->SR;
8003c08: 687b ldr r3, [r7, #4]
8003c0a: 681b ldr r3, [r3, #0]
8003c0c: 691b ldr r3, [r3, #16]
8003c0e: 60bb str r3, [r7, #8]
/* Capture compare 1 event */
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
8003c10: 68bb ldr r3, [r7, #8]
8003c12: f003 0302 and.w r3, r3, #2
8003c16: 2b00 cmp r3, #0
8003c18: d020 beq.n 8003c5c <HAL_TIM_IRQHandler+0x64>
{
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
8003c1a: 68fb ldr r3, [r7, #12]
8003c1c: f003 0302 and.w r3, r3, #2
8003c20: 2b00 cmp r3, #0
8003c22: d01b beq.n 8003c5c <HAL_TIM_IRQHandler+0x64>
{
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
8003c24: 687b ldr r3, [r7, #4]
8003c26: 681b ldr r3, [r3, #0]
8003c28: f06f 0202 mvn.w r2, #2
8003c2c: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8003c2e: 687b ldr r3, [r7, #4]
8003c30: 2201 movs r2, #1
8003c32: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8003c34: 687b ldr r3, [r7, #4]
8003c36: 681b ldr r3, [r3, #0]
8003c38: 699b ldr r3, [r3, #24]
8003c3a: f003 0303 and.w r3, r3, #3
8003c3e: 2b00 cmp r3, #0
8003c40: d003 beq.n 8003c4a <HAL_TIM_IRQHandler+0x52>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8003c42: 6878 ldr r0, [r7, #4]
8003c44: f000 f8e9 bl 8003e1a <HAL_TIM_IC_CaptureCallback>
8003c48: e005 b.n 8003c56 <HAL_TIM_IRQHandler+0x5e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8003c4a: 6878 ldr r0, [r7, #4]
8003c4c: f000 f8db bl 8003e06 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003c50: 6878 ldr r0, [r7, #4]
8003c52: f000 f8ec bl 8003e2e <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003c56: 687b ldr r3, [r7, #4]
8003c58: 2200 movs r2, #0
8003c5a: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
8003c5c: 68bb ldr r3, [r7, #8]
8003c5e: f003 0304 and.w r3, r3, #4
8003c62: 2b00 cmp r3, #0
8003c64: d020 beq.n 8003ca8 <HAL_TIM_IRQHandler+0xb0>
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
8003c66: 68fb ldr r3, [r7, #12]
8003c68: f003 0304 and.w r3, r3, #4
8003c6c: 2b00 cmp r3, #0
8003c6e: d01b beq.n 8003ca8 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
8003c70: 687b ldr r3, [r7, #4]
8003c72: 681b ldr r3, [r3, #0]
8003c74: f06f 0204 mvn.w r2, #4
8003c78: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8003c7a: 687b ldr r3, [r7, #4]
8003c7c: 2202 movs r2, #2
8003c7e: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8003c80: 687b ldr r3, [r7, #4]
8003c82: 681b ldr r3, [r3, #0]
8003c84: 699b ldr r3, [r3, #24]
8003c86: f403 7340 and.w r3, r3, #768 @ 0x300
8003c8a: 2b00 cmp r3, #0
8003c8c: d003 beq.n 8003c96 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8003c8e: 6878 ldr r0, [r7, #4]
8003c90: f000 f8c3 bl 8003e1a <HAL_TIM_IC_CaptureCallback>
8003c94: e005 b.n 8003ca2 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8003c96: 6878 ldr r0, [r7, #4]
8003c98: f000 f8b5 bl 8003e06 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003c9c: 6878 ldr r0, [r7, #4]
8003c9e: f000 f8c6 bl 8003e2e <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003ca2: 687b ldr r3, [r7, #4]
8003ca4: 2200 movs r2, #0
8003ca6: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
8003ca8: 68bb ldr r3, [r7, #8]
8003caa: f003 0308 and.w r3, r3, #8
8003cae: 2b00 cmp r3, #0
8003cb0: d020 beq.n 8003cf4 <HAL_TIM_IRQHandler+0xfc>
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
8003cb2: 68fb ldr r3, [r7, #12]
8003cb4: f003 0308 and.w r3, r3, #8
8003cb8: 2b00 cmp r3, #0
8003cba: d01b beq.n 8003cf4 <HAL_TIM_IRQHandler+0xfc>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
8003cbc: 687b ldr r3, [r7, #4]
8003cbe: 681b ldr r3, [r3, #0]
8003cc0: f06f 0208 mvn.w r2, #8
8003cc4: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8003cc6: 687b ldr r3, [r7, #4]
8003cc8: 2204 movs r2, #4
8003cca: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8003ccc: 687b ldr r3, [r7, #4]
8003cce: 681b ldr r3, [r3, #0]
8003cd0: 69db ldr r3, [r3, #28]
8003cd2: f003 0303 and.w r3, r3, #3
8003cd6: 2b00 cmp r3, #0
8003cd8: d003 beq.n 8003ce2 <HAL_TIM_IRQHandler+0xea>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8003cda: 6878 ldr r0, [r7, #4]
8003cdc: f000 f89d bl 8003e1a <HAL_TIM_IC_CaptureCallback>
8003ce0: e005 b.n 8003cee <HAL_TIM_IRQHandler+0xf6>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8003ce2: 6878 ldr r0, [r7, #4]
8003ce4: f000 f88f bl 8003e06 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003ce8: 6878 ldr r0, [r7, #4]
8003cea: f000 f8a0 bl 8003e2e <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003cee: 687b ldr r3, [r7, #4]
8003cf0: 2200 movs r2, #0
8003cf2: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
8003cf4: 68bb ldr r3, [r7, #8]
8003cf6: f003 0310 and.w r3, r3, #16
8003cfa: 2b00 cmp r3, #0
8003cfc: d020 beq.n 8003d40 <HAL_TIM_IRQHandler+0x148>
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
8003cfe: 68fb ldr r3, [r7, #12]
8003d00: f003 0310 and.w r3, r3, #16
8003d04: 2b00 cmp r3, #0
8003d06: d01b beq.n 8003d40 <HAL_TIM_IRQHandler+0x148>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
8003d08: 687b ldr r3, [r7, #4]
8003d0a: 681b ldr r3, [r3, #0]
8003d0c: f06f 0210 mvn.w r2, #16
8003d10: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8003d12: 687b ldr r3, [r7, #4]
8003d14: 2208 movs r2, #8
8003d16: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8003d18: 687b ldr r3, [r7, #4]
8003d1a: 681b ldr r3, [r3, #0]
8003d1c: 69db ldr r3, [r3, #28]
8003d1e: f403 7340 and.w r3, r3, #768 @ 0x300
8003d22: 2b00 cmp r3, #0
8003d24: d003 beq.n 8003d2e <HAL_TIM_IRQHandler+0x136>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8003d26: 6878 ldr r0, [r7, #4]
8003d28: f000 f877 bl 8003e1a <HAL_TIM_IC_CaptureCallback>
8003d2c: e005 b.n 8003d3a <HAL_TIM_IRQHandler+0x142>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8003d2e: 6878 ldr r0, [r7, #4]
8003d30: f000 f869 bl 8003e06 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003d34: 6878 ldr r0, [r7, #4]
8003d36: f000 f87a bl 8003e2e <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003d3a: 687b ldr r3, [r7, #4]
8003d3c: 2200 movs r2, #0
8003d3e: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
8003d40: 68bb ldr r3, [r7, #8]
8003d42: f003 0301 and.w r3, r3, #1
8003d46: 2b00 cmp r3, #0
8003d48: d00c beq.n 8003d64 <HAL_TIM_IRQHandler+0x16c>
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
8003d4a: 68fb ldr r3, [r7, #12]
8003d4c: f003 0301 and.w r3, r3, #1
8003d50: 2b00 cmp r3, #0
8003d52: d007 beq.n 8003d64 <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
8003d54: 687b ldr r3, [r7, #4]
8003d56: 681b ldr r3, [r3, #0]
8003d58: f06f 0201 mvn.w r2, #1
8003d5c: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8003d5e: 6878 ldr r0, [r7, #4]
8003d60: f7fd fcd8 bl 8001714 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
8003d64: 68bb ldr r3, [r7, #8]
8003d66: f003 0380 and.w r3, r3, #128 @ 0x80
8003d6a: 2b00 cmp r3, #0
8003d6c: d104 bne.n 8003d78 <HAL_TIM_IRQHandler+0x180>
((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
8003d6e: 68bb ldr r3, [r7, #8]
8003d70: f403 5300 and.w r3, r3, #8192 @ 0x2000
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
8003d74: 2b00 cmp r3, #0
8003d76: d00c beq.n 8003d92 <HAL_TIM_IRQHandler+0x19a>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
8003d78: 68fb ldr r3, [r7, #12]
8003d7a: f003 0380 and.w r3, r3, #128 @ 0x80
8003d7e: 2b00 cmp r3, #0
8003d80: d007 beq.n 8003d92 <HAL_TIM_IRQHandler+0x19a>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
8003d82: 687b ldr r3, [r7, #4]
8003d84: 681b ldr r3, [r3, #0]
8003d86: f46f 5202 mvn.w r2, #8320 @ 0x2080
8003d8a: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8003d8c: 6878 ldr r0, [r7, #4]
8003d8e: f000 f913 bl 8003fb8 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
8003d92: 68bb ldr r3, [r7, #8]
8003d94: f403 7380 and.w r3, r3, #256 @ 0x100
8003d98: 2b00 cmp r3, #0
8003d9a: d00c beq.n 8003db6 <HAL_TIM_IRQHandler+0x1be>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
8003d9c: 68fb ldr r3, [r7, #12]
8003d9e: f003 0380 and.w r3, r3, #128 @ 0x80
8003da2: 2b00 cmp r3, #0
8003da4: d007 beq.n 8003db6 <HAL_TIM_IRQHandler+0x1be>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
8003da6: 687b ldr r3, [r7, #4]
8003da8: 681b ldr r3, [r3, #0]
8003daa: f46f 7280 mvn.w r2, #256 @ 0x100
8003dae: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
8003db0: 6878 ldr r0, [r7, #4]
8003db2: f000 f90b bl 8003fcc <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
8003db6: 68bb ldr r3, [r7, #8]
8003db8: f003 0340 and.w r3, r3, #64 @ 0x40
8003dbc: 2b00 cmp r3, #0
8003dbe: d00c beq.n 8003dda <HAL_TIM_IRQHandler+0x1e2>
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
8003dc0: 68fb ldr r3, [r7, #12]
8003dc2: f003 0340 and.w r3, r3, #64 @ 0x40
8003dc6: 2b00 cmp r3, #0
8003dc8: d007 beq.n 8003dda <HAL_TIM_IRQHandler+0x1e2>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
8003dca: 687b ldr r3, [r7, #4]
8003dcc: 681b ldr r3, [r3, #0]
8003dce: f06f 0240 mvn.w r2, #64 @ 0x40
8003dd2: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8003dd4: 6878 ldr r0, [r7, #4]
8003dd6: f000 f834 bl 8003e42 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
8003dda: 68bb ldr r3, [r7, #8]
8003ddc: f003 0320 and.w r3, r3, #32
8003de0: 2b00 cmp r3, #0
8003de2: d00c beq.n 8003dfe <HAL_TIM_IRQHandler+0x206>
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
8003de4: 68fb ldr r3, [r7, #12]
8003de6: f003 0320 and.w r3, r3, #32
8003dea: 2b00 cmp r3, #0
8003dec: d007 beq.n 8003dfe <HAL_TIM_IRQHandler+0x206>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
8003dee: 687b ldr r3, [r7, #4]
8003df0: 681b ldr r3, [r3, #0]
8003df2: f06f 0220 mvn.w r2, #32
8003df6: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8003df8: 6878 ldr r0, [r7, #4]
8003dfa: f000 f8d3 bl 8003fa4 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8003dfe: bf00 nop
8003e00: 3710 adds r7, #16
8003e02: 46bd mov sp, r7
8003e04: bd80 pop {r7, pc}
08003e06 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8003e06: b480 push {r7}
8003e08: b083 sub sp, #12
8003e0a: af00 add r7, sp, #0
8003e0c: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8003e0e: bf00 nop
8003e10: 370c adds r7, #12
8003e12: 46bd mov sp, r7
8003e14: f85d 7b04 ldr.w r7, [sp], #4
8003e18: 4770 bx lr
08003e1a <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8003e1a: b480 push {r7}
8003e1c: b083 sub sp, #12
8003e1e: af00 add r7, sp, #0
8003e20: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8003e22: bf00 nop
8003e24: 370c adds r7, #12
8003e26: 46bd mov sp, r7
8003e28: f85d 7b04 ldr.w r7, [sp], #4
8003e2c: 4770 bx lr
08003e2e <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8003e2e: b480 push {r7}
8003e30: b083 sub sp, #12
8003e32: af00 add r7, sp, #0
8003e34: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8003e36: bf00 nop
8003e38: 370c adds r7, #12
8003e3a: 46bd mov sp, r7
8003e3c: f85d 7b04 ldr.w r7, [sp], #4
8003e40: 4770 bx lr
08003e42 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8003e42: b480 push {r7}
8003e44: b083 sub sp, #12
8003e46: af00 add r7, sp, #0
8003e48: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8003e4a: bf00 nop
8003e4c: 370c adds r7, #12
8003e4e: 46bd mov sp, r7
8003e50: f85d 7b04 ldr.w r7, [sp], #4
8003e54: 4770 bx lr
...
08003e58 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8003e58: b480 push {r7}
8003e5a: b085 sub sp, #20
8003e5c: af00 add r7, sp, #0
8003e5e: 6078 str r0, [r7, #4]
8003e60: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8003e62: 687b ldr r3, [r7, #4]
8003e64: 681b ldr r3, [r3, #0]
8003e66: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8003e68: 687b ldr r3, [r7, #4]
8003e6a: 4a43 ldr r2, [pc, #268] @ (8003f78 <TIM_Base_SetConfig+0x120>)
8003e6c: 4293 cmp r3, r2
8003e6e: d013 beq.n 8003e98 <TIM_Base_SetConfig+0x40>
8003e70: 687b ldr r3, [r7, #4]
8003e72: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8003e76: d00f beq.n 8003e98 <TIM_Base_SetConfig+0x40>
8003e78: 687b ldr r3, [r7, #4]
8003e7a: 4a40 ldr r2, [pc, #256] @ (8003f7c <TIM_Base_SetConfig+0x124>)
8003e7c: 4293 cmp r3, r2
8003e7e: d00b beq.n 8003e98 <TIM_Base_SetConfig+0x40>
8003e80: 687b ldr r3, [r7, #4]
8003e82: 4a3f ldr r2, [pc, #252] @ (8003f80 <TIM_Base_SetConfig+0x128>)
8003e84: 4293 cmp r3, r2
8003e86: d007 beq.n 8003e98 <TIM_Base_SetConfig+0x40>
8003e88: 687b ldr r3, [r7, #4]
8003e8a: 4a3e ldr r2, [pc, #248] @ (8003f84 <TIM_Base_SetConfig+0x12c>)
8003e8c: 4293 cmp r3, r2
8003e8e: d003 beq.n 8003e98 <TIM_Base_SetConfig+0x40>
8003e90: 687b ldr r3, [r7, #4]
8003e92: 4a3d ldr r2, [pc, #244] @ (8003f88 <TIM_Base_SetConfig+0x130>)
8003e94: 4293 cmp r3, r2
8003e96: d108 bne.n 8003eaa <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8003e98: 68fb ldr r3, [r7, #12]
8003e9a: f023 0370 bic.w r3, r3, #112 @ 0x70
8003e9e: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8003ea0: 683b ldr r3, [r7, #0]
8003ea2: 685b ldr r3, [r3, #4]
8003ea4: 68fa ldr r2, [r7, #12]
8003ea6: 4313 orrs r3, r2
8003ea8: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8003eaa: 687b ldr r3, [r7, #4]
8003eac: 4a32 ldr r2, [pc, #200] @ (8003f78 <TIM_Base_SetConfig+0x120>)
8003eae: 4293 cmp r3, r2
8003eb0: d02b beq.n 8003f0a <TIM_Base_SetConfig+0xb2>
8003eb2: 687b ldr r3, [r7, #4]
8003eb4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8003eb8: d027 beq.n 8003f0a <TIM_Base_SetConfig+0xb2>
8003eba: 687b ldr r3, [r7, #4]
8003ebc: 4a2f ldr r2, [pc, #188] @ (8003f7c <TIM_Base_SetConfig+0x124>)
8003ebe: 4293 cmp r3, r2
8003ec0: d023 beq.n 8003f0a <TIM_Base_SetConfig+0xb2>
8003ec2: 687b ldr r3, [r7, #4]
8003ec4: 4a2e ldr r2, [pc, #184] @ (8003f80 <TIM_Base_SetConfig+0x128>)
8003ec6: 4293 cmp r3, r2
8003ec8: d01f beq.n 8003f0a <TIM_Base_SetConfig+0xb2>
8003eca: 687b ldr r3, [r7, #4]
8003ecc: 4a2d ldr r2, [pc, #180] @ (8003f84 <TIM_Base_SetConfig+0x12c>)
8003ece: 4293 cmp r3, r2
8003ed0: d01b beq.n 8003f0a <TIM_Base_SetConfig+0xb2>
8003ed2: 687b ldr r3, [r7, #4]
8003ed4: 4a2c ldr r2, [pc, #176] @ (8003f88 <TIM_Base_SetConfig+0x130>)
8003ed6: 4293 cmp r3, r2
8003ed8: d017 beq.n 8003f0a <TIM_Base_SetConfig+0xb2>
8003eda: 687b ldr r3, [r7, #4]
8003edc: 4a2b ldr r2, [pc, #172] @ (8003f8c <TIM_Base_SetConfig+0x134>)
8003ede: 4293 cmp r3, r2
8003ee0: d013 beq.n 8003f0a <TIM_Base_SetConfig+0xb2>
8003ee2: 687b ldr r3, [r7, #4]
8003ee4: 4a2a ldr r2, [pc, #168] @ (8003f90 <TIM_Base_SetConfig+0x138>)
8003ee6: 4293 cmp r3, r2
8003ee8: d00f beq.n 8003f0a <TIM_Base_SetConfig+0xb2>
8003eea: 687b ldr r3, [r7, #4]
8003eec: 4a29 ldr r2, [pc, #164] @ (8003f94 <TIM_Base_SetConfig+0x13c>)
8003eee: 4293 cmp r3, r2
8003ef0: d00b beq.n 8003f0a <TIM_Base_SetConfig+0xb2>
8003ef2: 687b ldr r3, [r7, #4]
8003ef4: 4a28 ldr r2, [pc, #160] @ (8003f98 <TIM_Base_SetConfig+0x140>)
8003ef6: 4293 cmp r3, r2
8003ef8: d007 beq.n 8003f0a <TIM_Base_SetConfig+0xb2>
8003efa: 687b ldr r3, [r7, #4]
8003efc: 4a27 ldr r2, [pc, #156] @ (8003f9c <TIM_Base_SetConfig+0x144>)
8003efe: 4293 cmp r3, r2
8003f00: d003 beq.n 8003f0a <TIM_Base_SetConfig+0xb2>
8003f02: 687b ldr r3, [r7, #4]
8003f04: 4a26 ldr r2, [pc, #152] @ (8003fa0 <TIM_Base_SetConfig+0x148>)
8003f06: 4293 cmp r3, r2
8003f08: d108 bne.n 8003f1c <TIM_Base_SetConfig+0xc4>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8003f0a: 68fb ldr r3, [r7, #12]
8003f0c: f423 7340 bic.w r3, r3, #768 @ 0x300
8003f10: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8003f12: 683b ldr r3, [r7, #0]
8003f14: 68db ldr r3, [r3, #12]
8003f16: 68fa ldr r2, [r7, #12]
8003f18: 4313 orrs r3, r2
8003f1a: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8003f1c: 68fb ldr r3, [r7, #12]
8003f1e: f023 0280 bic.w r2, r3, #128 @ 0x80
8003f22: 683b ldr r3, [r7, #0]
8003f24: 695b ldr r3, [r3, #20]
8003f26: 4313 orrs r3, r2
8003f28: 60fb str r3, [r7, #12]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8003f2a: 683b ldr r3, [r7, #0]
8003f2c: 689a ldr r2, [r3, #8]
8003f2e: 687b ldr r3, [r7, #4]
8003f30: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8003f32: 683b ldr r3, [r7, #0]
8003f34: 681a ldr r2, [r3, #0]
8003f36: 687b ldr r3, [r7, #4]
8003f38: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8003f3a: 687b ldr r3, [r7, #4]
8003f3c: 4a0e ldr r2, [pc, #56] @ (8003f78 <TIM_Base_SetConfig+0x120>)
8003f3e: 4293 cmp r3, r2
8003f40: d003 beq.n 8003f4a <TIM_Base_SetConfig+0xf2>
8003f42: 687b ldr r3, [r7, #4]
8003f44: 4a10 ldr r2, [pc, #64] @ (8003f88 <TIM_Base_SetConfig+0x130>)
8003f46: 4293 cmp r3, r2
8003f48: d103 bne.n 8003f52 <TIM_Base_SetConfig+0xfa>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8003f4a: 683b ldr r3, [r7, #0]
8003f4c: 691a ldr r2, [r3, #16]
8003f4e: 687b ldr r3, [r7, #4]
8003f50: 631a str r2, [r3, #48] @ 0x30
}
/* Disable Update Event (UEV) with Update Generation (UG)
by changing Update Request Source (URS) to avoid Update flag (UIF) */
SET_BIT(TIMx->CR1, TIM_CR1_URS);
8003f52: 687b ldr r3, [r7, #4]
8003f54: 681b ldr r3, [r3, #0]
8003f56: f043 0204 orr.w r2, r3, #4
8003f5a: 687b ldr r3, [r7, #4]
8003f5c: 601a str r2, [r3, #0]
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8003f5e: 687b ldr r3, [r7, #4]
8003f60: 2201 movs r2, #1
8003f62: 615a str r2, [r3, #20]
TIMx->CR1 = tmpcr1;
8003f64: 687b ldr r3, [r7, #4]
8003f66: 68fa ldr r2, [r7, #12]
8003f68: 601a str r2, [r3, #0]
}
8003f6a: bf00 nop
8003f6c: 3714 adds r7, #20
8003f6e: 46bd mov sp, r7
8003f70: f85d 7b04 ldr.w r7, [sp], #4
8003f74: 4770 bx lr
8003f76: bf00 nop
8003f78: 40010000 .word 0x40010000
8003f7c: 40000400 .word 0x40000400
8003f80: 40000800 .word 0x40000800
8003f84: 40000c00 .word 0x40000c00
8003f88: 40010400 .word 0x40010400
8003f8c: 40014000 .word 0x40014000
8003f90: 40014400 .word 0x40014400
8003f94: 40014800 .word 0x40014800
8003f98: 40001800 .word 0x40001800
8003f9c: 40001c00 .word 0x40001c00
8003fa0: 40002000 .word 0x40002000
08003fa4 <HAL_TIMEx_CommutCallback>:
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8003fa4: b480 push {r7}
8003fa6: b083 sub sp, #12
8003fa8: af00 add r7, sp, #0
8003faa: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8003fac: bf00 nop
8003fae: 370c adds r7, #12
8003fb0: 46bd mov sp, r7
8003fb2: f85d 7b04 ldr.w r7, [sp], #4
8003fb6: 4770 bx lr
08003fb8 <HAL_TIMEx_BreakCallback>:
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8003fb8: b480 push {r7}
8003fba: b083 sub sp, #12
8003fbc: af00 add r7, sp, #0
8003fbe: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
8003fc0: bf00 nop
8003fc2: 370c adds r7, #12
8003fc4: 46bd mov sp, r7
8003fc6: f85d 7b04 ldr.w r7, [sp], #4
8003fca: 4770 bx lr
08003fcc <HAL_TIMEx_Break2Callback>:
* @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
8003fcc: b480 push {r7}
8003fce: b083 sub sp, #12
8003fd0: af00 add r7, sp, #0
8003fd2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
8003fd4: bf00 nop
8003fd6: 370c adds r7, #12
8003fd8: 46bd mov sp, r7
8003fda: f85d 7b04 ldr.w r7, [sp], #4
8003fde: 4770 bx lr
08003fe0 <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8003fe0: b580 push {r7, lr}
8003fe2: b082 sub sp, #8
8003fe4: af00 add r7, sp, #0
8003fe6: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8003fe8: 687b ldr r3, [r7, #4]
8003fea: 2b00 cmp r3, #0
8003fec: d101 bne.n 8003ff2 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8003fee: 2301 movs r3, #1
8003ff0: e040 b.n 8004074 <HAL_UART_Init+0x94>
{
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
}
if (huart->gState == HAL_UART_STATE_RESET)
8003ff2: 687b ldr r3, [r7, #4]
8003ff4: 6fdb ldr r3, [r3, #124] @ 0x7c
8003ff6: 2b00 cmp r3, #0
8003ff8: d106 bne.n 8004008 <HAL_UART_Init+0x28>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8003ffa: 687b ldr r3, [r7, #4]
8003ffc: 2200 movs r2, #0
8003ffe: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8004002: 6878 ldr r0, [r7, #4]
8004004: f7fd fc4a bl 800189c <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8004008: 687b ldr r3, [r7, #4]
800400a: 2224 movs r2, #36 @ 0x24
800400c: 67da str r2, [r3, #124] @ 0x7c
__HAL_UART_DISABLE(huart);
800400e: 687b ldr r3, [r7, #4]
8004010: 681b ldr r3, [r3, #0]
8004012: 681a ldr r2, [r3, #0]
8004014: 687b ldr r3, [r7, #4]
8004016: 681b ldr r3, [r3, #0]
8004018: f022 0201 bic.w r2, r2, #1
800401c: 601a str r2, [r3, #0]
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
800401e: 687b ldr r3, [r7, #4]
8004020: 6a5b ldr r3, [r3, #36] @ 0x24
8004022: 2b00 cmp r3, #0
8004024: d002 beq.n 800402c <HAL_UART_Init+0x4c>
{
UART_AdvFeatureConfig(huart);
8004026: 6878 ldr r0, [r7, #4]
8004028: f000 fb16 bl 8004658 <UART_AdvFeatureConfig>
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
800402c: 6878 ldr r0, [r7, #4]
800402e: f000 f8af bl 8004190 <UART_SetConfig>
8004032: 4603 mov r3, r0
8004034: 2b01 cmp r3, #1
8004036: d101 bne.n 800403c <HAL_UART_Init+0x5c>
{
return HAL_ERROR;
8004038: 2301 movs r3, #1
800403a: e01b b.n 8004074 <HAL_UART_Init+0x94>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
800403c: 687b ldr r3, [r7, #4]
800403e: 681b ldr r3, [r3, #0]
8004040: 685a ldr r2, [r3, #4]
8004042: 687b ldr r3, [r7, #4]
8004044: 681b ldr r3, [r3, #0]
8004046: f422 4290 bic.w r2, r2, #18432 @ 0x4800
800404a: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
800404c: 687b ldr r3, [r7, #4]
800404e: 681b ldr r3, [r3, #0]
8004050: 689a ldr r2, [r3, #8]
8004052: 687b ldr r3, [r7, #4]
8004054: 681b ldr r3, [r3, #0]
8004056: f022 022a bic.w r2, r2, #42 @ 0x2a
800405a: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
800405c: 687b ldr r3, [r7, #4]
800405e: 681b ldr r3, [r3, #0]
8004060: 681a ldr r2, [r3, #0]
8004062: 687b ldr r3, [r7, #4]
8004064: 681b ldr r3, [r3, #0]
8004066: f042 0201 orr.w r2, r2, #1
800406a: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
800406c: 6878 ldr r0, [r7, #4]
800406e: f000 fb95 bl 800479c <UART_CheckIdleState>
8004072: 4603 mov r3, r0
}
8004074: 4618 mov r0, r3
8004076: 3708 adds r7, #8
8004078: 46bd mov sp, r7
800407a: bd80 pop {r7, pc}
0800407c <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
800407c: b580 push {r7, lr}
800407e: b08a sub sp, #40 @ 0x28
8004080: af02 add r7, sp, #8
8004082: 60f8 str r0, [r7, #12]
8004084: 60b9 str r1, [r7, #8]
8004086: 603b str r3, [r7, #0]
8004088: 4613 mov r3, r2
800408a: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
800408c: 68fb ldr r3, [r7, #12]
800408e: 6fdb ldr r3, [r3, #124] @ 0x7c
8004090: 2b20 cmp r3, #32
8004092: d177 bne.n 8004184 <HAL_UART_Transmit+0x108>
{
if ((pData == NULL) || (Size == 0U))
8004094: 68bb ldr r3, [r7, #8]
8004096: 2b00 cmp r3, #0
8004098: d002 beq.n 80040a0 <HAL_UART_Transmit+0x24>
800409a: 88fb ldrh r3, [r7, #6]
800409c: 2b00 cmp r3, #0
800409e: d101 bne.n 80040a4 <HAL_UART_Transmit+0x28>
{
return HAL_ERROR;
80040a0: 2301 movs r3, #1
80040a2: e070 b.n 8004186 <HAL_UART_Transmit+0x10a>
}
huart->ErrorCode = HAL_UART_ERROR_NONE;
80040a4: 68fb ldr r3, [r7, #12]
80040a6: 2200 movs r2, #0
80040a8: f8c3 2084 str.w r2, [r3, #132] @ 0x84
huart->gState = HAL_UART_STATE_BUSY_TX;
80040ac: 68fb ldr r3, [r7, #12]
80040ae: 2221 movs r2, #33 @ 0x21
80040b0: 67da str r2, [r3, #124] @ 0x7c
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
80040b2: f7fd ffeb bl 800208c <HAL_GetTick>
80040b6: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
80040b8: 68fb ldr r3, [r7, #12]
80040ba: 88fa ldrh r2, [r7, #6]
80040bc: f8a3 2050 strh.w r2, [r3, #80] @ 0x50
huart->TxXferCount = Size;
80040c0: 68fb ldr r3, [r7, #12]
80040c2: 88fa ldrh r2, [r7, #6]
80040c4: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
80040c8: 68fb ldr r3, [r7, #12]
80040ca: 689b ldr r3, [r3, #8]
80040cc: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80040d0: d108 bne.n 80040e4 <HAL_UART_Transmit+0x68>
80040d2: 68fb ldr r3, [r7, #12]
80040d4: 691b ldr r3, [r3, #16]
80040d6: 2b00 cmp r3, #0
80040d8: d104 bne.n 80040e4 <HAL_UART_Transmit+0x68>
{
pdata8bits = NULL;
80040da: 2300 movs r3, #0
80040dc: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
80040de: 68bb ldr r3, [r7, #8]
80040e0: 61bb str r3, [r7, #24]
80040e2: e003 b.n 80040ec <HAL_UART_Transmit+0x70>
}
else
{
pdata8bits = pData;
80040e4: 68bb ldr r3, [r7, #8]
80040e6: 61fb str r3, [r7, #28]
pdata16bits = NULL;
80040e8: 2300 movs r3, #0
80040ea: 61bb str r3, [r7, #24]
}
while (huart->TxXferCount > 0U)
80040ec: e02f b.n 800414e <HAL_UART_Transmit+0xd2>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
80040ee: 683b ldr r3, [r7, #0]
80040f0: 9300 str r3, [sp, #0]
80040f2: 697b ldr r3, [r7, #20]
80040f4: 2200 movs r2, #0
80040f6: 2180 movs r1, #128 @ 0x80
80040f8: 68f8 ldr r0, [r7, #12]
80040fa: f000 fba6 bl 800484a <UART_WaitOnFlagUntilTimeout>
80040fe: 4603 mov r3, r0
8004100: 2b00 cmp r3, #0
8004102: d004 beq.n 800410e <HAL_UART_Transmit+0x92>
{
huart->gState = HAL_UART_STATE_READY;
8004104: 68fb ldr r3, [r7, #12]
8004106: 2220 movs r2, #32
8004108: 67da str r2, [r3, #124] @ 0x7c
return HAL_TIMEOUT;
800410a: 2303 movs r3, #3
800410c: e03b b.n 8004186 <HAL_UART_Transmit+0x10a>
}
if (pdata8bits == NULL)
800410e: 69fb ldr r3, [r7, #28]
8004110: 2b00 cmp r3, #0
8004112: d10b bne.n 800412c <HAL_UART_Transmit+0xb0>
{
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
8004114: 69bb ldr r3, [r7, #24]
8004116: 881b ldrh r3, [r3, #0]
8004118: 461a mov r2, r3
800411a: 68fb ldr r3, [r7, #12]
800411c: 681b ldr r3, [r3, #0]
800411e: f3c2 0208 ubfx r2, r2, #0, #9
8004122: 629a str r2, [r3, #40] @ 0x28
pdata16bits++;
8004124: 69bb ldr r3, [r7, #24]
8004126: 3302 adds r3, #2
8004128: 61bb str r3, [r7, #24]
800412a: e007 b.n 800413c <HAL_UART_Transmit+0xc0>
}
else
{
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
800412c: 69fb ldr r3, [r7, #28]
800412e: 781a ldrb r2, [r3, #0]
8004130: 68fb ldr r3, [r7, #12]
8004132: 681b ldr r3, [r3, #0]
8004134: 629a str r2, [r3, #40] @ 0x28
pdata8bits++;
8004136: 69fb ldr r3, [r7, #28]
8004138: 3301 adds r3, #1
800413a: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
800413c: 68fb ldr r3, [r7, #12]
800413e: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
8004142: b29b uxth r3, r3
8004144: 3b01 subs r3, #1
8004146: b29a uxth r2, r3
8004148: 68fb ldr r3, [r7, #12]
800414a: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
while (huart->TxXferCount > 0U)
800414e: 68fb ldr r3, [r7, #12]
8004150: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
8004154: b29b uxth r3, r3
8004156: 2b00 cmp r3, #0
8004158: d1c9 bne.n 80040ee <HAL_UART_Transmit+0x72>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
800415a: 683b ldr r3, [r7, #0]
800415c: 9300 str r3, [sp, #0]
800415e: 697b ldr r3, [r7, #20]
8004160: 2200 movs r2, #0
8004162: 2140 movs r1, #64 @ 0x40
8004164: 68f8 ldr r0, [r7, #12]
8004166: f000 fb70 bl 800484a <UART_WaitOnFlagUntilTimeout>
800416a: 4603 mov r3, r0
800416c: 2b00 cmp r3, #0
800416e: d004 beq.n 800417a <HAL_UART_Transmit+0xfe>
{
huart->gState = HAL_UART_STATE_READY;
8004170: 68fb ldr r3, [r7, #12]
8004172: 2220 movs r2, #32
8004174: 67da str r2, [r3, #124] @ 0x7c
return HAL_TIMEOUT;
8004176: 2303 movs r3, #3
8004178: e005 b.n 8004186 <HAL_UART_Transmit+0x10a>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
800417a: 68fb ldr r3, [r7, #12]
800417c: 2220 movs r2, #32
800417e: 67da str r2, [r3, #124] @ 0x7c
return HAL_OK;
8004180: 2300 movs r3, #0
8004182: e000 b.n 8004186 <HAL_UART_Transmit+0x10a>
}
else
{
return HAL_BUSY;
8004184: 2302 movs r3, #2
}
}
8004186: 4618 mov r0, r3
8004188: 3720 adds r7, #32
800418a: 46bd mov sp, r7
800418c: bd80 pop {r7, pc}
...
08004190 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8004190: b580 push {r7, lr}
8004192: b088 sub sp, #32
8004194: af00 add r7, sp, #0
8004196: 6078 str r0, [r7, #4]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
8004198: 2300 movs r3, #0
800419a: 77bb strb r3, [r7, #30]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
800419c: 687b ldr r3, [r7, #4]
800419e: 689a ldr r2, [r3, #8]
80041a0: 687b ldr r3, [r7, #4]
80041a2: 691b ldr r3, [r3, #16]
80041a4: 431a orrs r2, r3
80041a6: 687b ldr r3, [r7, #4]
80041a8: 695b ldr r3, [r3, #20]
80041aa: 431a orrs r2, r3
80041ac: 687b ldr r3, [r7, #4]
80041ae: 69db ldr r3, [r3, #28]
80041b0: 4313 orrs r3, r2
80041b2: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
80041b4: 687b ldr r3, [r7, #4]
80041b6: 681b ldr r3, [r3, #0]
80041b8: 681a ldr r2, [r3, #0]
80041ba: 4ba6 ldr r3, [pc, #664] @ (8004454 <UART_SetConfig+0x2c4>)
80041bc: 4013 ands r3, r2
80041be: 687a ldr r2, [r7, #4]
80041c0: 6812 ldr r2, [r2, #0]
80041c2: 6979 ldr r1, [r7, #20]
80041c4: 430b orrs r3, r1
80041c6: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
80041c8: 687b ldr r3, [r7, #4]
80041ca: 681b ldr r3, [r3, #0]
80041cc: 685b ldr r3, [r3, #4]
80041ce: f423 5140 bic.w r1, r3, #12288 @ 0x3000
80041d2: 687b ldr r3, [r7, #4]
80041d4: 68da ldr r2, [r3, #12]
80041d6: 687b ldr r3, [r7, #4]
80041d8: 681b ldr r3, [r3, #0]
80041da: 430a orrs r2, r1
80041dc: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
80041de: 687b ldr r3, [r7, #4]
80041e0: 699b ldr r3, [r3, #24]
80041e2: 617b str r3, [r7, #20]
tmpreg |= huart->Init.OneBitSampling;
80041e4: 687b ldr r3, [r7, #4]
80041e6: 6a1b ldr r3, [r3, #32]
80041e8: 697a ldr r2, [r7, #20]
80041ea: 4313 orrs r3, r2
80041ec: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
80041ee: 687b ldr r3, [r7, #4]
80041f0: 681b ldr r3, [r3, #0]
80041f2: 689b ldr r3, [r3, #8]
80041f4: f423 6130 bic.w r1, r3, #2816 @ 0xb00
80041f8: 687b ldr r3, [r7, #4]
80041fa: 681b ldr r3, [r3, #0]
80041fc: 697a ldr r2, [r7, #20]
80041fe: 430a orrs r2, r1
8004200: 609a str r2, [r3, #8]
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
8004202: 687b ldr r3, [r7, #4]
8004204: 681b ldr r3, [r3, #0]
8004206: 4a94 ldr r2, [pc, #592] @ (8004458 <UART_SetConfig+0x2c8>)
8004208: 4293 cmp r3, r2
800420a: d120 bne.n 800424e <UART_SetConfig+0xbe>
800420c: 4b93 ldr r3, [pc, #588] @ (800445c <UART_SetConfig+0x2cc>)
800420e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004212: f003 0303 and.w r3, r3, #3
8004216: 2b03 cmp r3, #3
8004218: d816 bhi.n 8004248 <UART_SetConfig+0xb8>
800421a: a201 add r2, pc, #4 @ (adr r2, 8004220 <UART_SetConfig+0x90>)
800421c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8004220: 08004231 .word 0x08004231
8004224: 0800423d .word 0x0800423d
8004228: 08004237 .word 0x08004237
800422c: 08004243 .word 0x08004243
8004230: 2301 movs r3, #1
8004232: 77fb strb r3, [r7, #31]
8004234: e150 b.n 80044d8 <UART_SetConfig+0x348>
8004236: 2302 movs r3, #2
8004238: 77fb strb r3, [r7, #31]
800423a: e14d b.n 80044d8 <UART_SetConfig+0x348>
800423c: 2304 movs r3, #4
800423e: 77fb strb r3, [r7, #31]
8004240: e14a b.n 80044d8 <UART_SetConfig+0x348>
8004242: 2308 movs r3, #8
8004244: 77fb strb r3, [r7, #31]
8004246: e147 b.n 80044d8 <UART_SetConfig+0x348>
8004248: 2310 movs r3, #16
800424a: 77fb strb r3, [r7, #31]
800424c: e144 b.n 80044d8 <UART_SetConfig+0x348>
800424e: 687b ldr r3, [r7, #4]
8004250: 681b ldr r3, [r3, #0]
8004252: 4a83 ldr r2, [pc, #524] @ (8004460 <UART_SetConfig+0x2d0>)
8004254: 4293 cmp r3, r2
8004256: d132 bne.n 80042be <UART_SetConfig+0x12e>
8004258: 4b80 ldr r3, [pc, #512] @ (800445c <UART_SetConfig+0x2cc>)
800425a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800425e: f003 030c and.w r3, r3, #12
8004262: 2b0c cmp r3, #12
8004264: d828 bhi.n 80042b8 <UART_SetConfig+0x128>
8004266: a201 add r2, pc, #4 @ (adr r2, 800426c <UART_SetConfig+0xdc>)
8004268: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800426c: 080042a1 .word 0x080042a1
8004270: 080042b9 .word 0x080042b9
8004274: 080042b9 .word 0x080042b9
8004278: 080042b9 .word 0x080042b9
800427c: 080042ad .word 0x080042ad
8004280: 080042b9 .word 0x080042b9
8004284: 080042b9 .word 0x080042b9
8004288: 080042b9 .word 0x080042b9
800428c: 080042a7 .word 0x080042a7
8004290: 080042b9 .word 0x080042b9
8004294: 080042b9 .word 0x080042b9
8004298: 080042b9 .word 0x080042b9
800429c: 080042b3 .word 0x080042b3
80042a0: 2300 movs r3, #0
80042a2: 77fb strb r3, [r7, #31]
80042a4: e118 b.n 80044d8 <UART_SetConfig+0x348>
80042a6: 2302 movs r3, #2
80042a8: 77fb strb r3, [r7, #31]
80042aa: e115 b.n 80044d8 <UART_SetConfig+0x348>
80042ac: 2304 movs r3, #4
80042ae: 77fb strb r3, [r7, #31]
80042b0: e112 b.n 80044d8 <UART_SetConfig+0x348>
80042b2: 2308 movs r3, #8
80042b4: 77fb strb r3, [r7, #31]
80042b6: e10f b.n 80044d8 <UART_SetConfig+0x348>
80042b8: 2310 movs r3, #16
80042ba: 77fb strb r3, [r7, #31]
80042bc: e10c b.n 80044d8 <UART_SetConfig+0x348>
80042be: 687b ldr r3, [r7, #4]
80042c0: 681b ldr r3, [r3, #0]
80042c2: 4a68 ldr r2, [pc, #416] @ (8004464 <UART_SetConfig+0x2d4>)
80042c4: 4293 cmp r3, r2
80042c6: d120 bne.n 800430a <UART_SetConfig+0x17a>
80042c8: 4b64 ldr r3, [pc, #400] @ (800445c <UART_SetConfig+0x2cc>)
80042ca: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80042ce: f003 0330 and.w r3, r3, #48 @ 0x30
80042d2: 2b30 cmp r3, #48 @ 0x30
80042d4: d013 beq.n 80042fe <UART_SetConfig+0x16e>
80042d6: 2b30 cmp r3, #48 @ 0x30
80042d8: d814 bhi.n 8004304 <UART_SetConfig+0x174>
80042da: 2b20 cmp r3, #32
80042dc: d009 beq.n 80042f2 <UART_SetConfig+0x162>
80042de: 2b20 cmp r3, #32
80042e0: d810 bhi.n 8004304 <UART_SetConfig+0x174>
80042e2: 2b00 cmp r3, #0
80042e4: d002 beq.n 80042ec <UART_SetConfig+0x15c>
80042e6: 2b10 cmp r3, #16
80042e8: d006 beq.n 80042f8 <UART_SetConfig+0x168>
80042ea: e00b b.n 8004304 <UART_SetConfig+0x174>
80042ec: 2300 movs r3, #0
80042ee: 77fb strb r3, [r7, #31]
80042f0: e0f2 b.n 80044d8 <UART_SetConfig+0x348>
80042f2: 2302 movs r3, #2
80042f4: 77fb strb r3, [r7, #31]
80042f6: e0ef b.n 80044d8 <UART_SetConfig+0x348>
80042f8: 2304 movs r3, #4
80042fa: 77fb strb r3, [r7, #31]
80042fc: e0ec b.n 80044d8 <UART_SetConfig+0x348>
80042fe: 2308 movs r3, #8
8004300: 77fb strb r3, [r7, #31]
8004302: e0e9 b.n 80044d8 <UART_SetConfig+0x348>
8004304: 2310 movs r3, #16
8004306: 77fb strb r3, [r7, #31]
8004308: e0e6 b.n 80044d8 <UART_SetConfig+0x348>
800430a: 687b ldr r3, [r7, #4]
800430c: 681b ldr r3, [r3, #0]
800430e: 4a56 ldr r2, [pc, #344] @ (8004468 <UART_SetConfig+0x2d8>)
8004310: 4293 cmp r3, r2
8004312: d120 bne.n 8004356 <UART_SetConfig+0x1c6>
8004314: 4b51 ldr r3, [pc, #324] @ (800445c <UART_SetConfig+0x2cc>)
8004316: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800431a: f003 03c0 and.w r3, r3, #192 @ 0xc0
800431e: 2bc0 cmp r3, #192 @ 0xc0
8004320: d013 beq.n 800434a <UART_SetConfig+0x1ba>
8004322: 2bc0 cmp r3, #192 @ 0xc0
8004324: d814 bhi.n 8004350 <UART_SetConfig+0x1c0>
8004326: 2b80 cmp r3, #128 @ 0x80
8004328: d009 beq.n 800433e <UART_SetConfig+0x1ae>
800432a: 2b80 cmp r3, #128 @ 0x80
800432c: d810 bhi.n 8004350 <UART_SetConfig+0x1c0>
800432e: 2b00 cmp r3, #0
8004330: d002 beq.n 8004338 <UART_SetConfig+0x1a8>
8004332: 2b40 cmp r3, #64 @ 0x40
8004334: d006 beq.n 8004344 <UART_SetConfig+0x1b4>
8004336: e00b b.n 8004350 <UART_SetConfig+0x1c0>
8004338: 2300 movs r3, #0
800433a: 77fb strb r3, [r7, #31]
800433c: e0cc b.n 80044d8 <UART_SetConfig+0x348>
800433e: 2302 movs r3, #2
8004340: 77fb strb r3, [r7, #31]
8004342: e0c9 b.n 80044d8 <UART_SetConfig+0x348>
8004344: 2304 movs r3, #4
8004346: 77fb strb r3, [r7, #31]
8004348: e0c6 b.n 80044d8 <UART_SetConfig+0x348>
800434a: 2308 movs r3, #8
800434c: 77fb strb r3, [r7, #31]
800434e: e0c3 b.n 80044d8 <UART_SetConfig+0x348>
8004350: 2310 movs r3, #16
8004352: 77fb strb r3, [r7, #31]
8004354: e0c0 b.n 80044d8 <UART_SetConfig+0x348>
8004356: 687b ldr r3, [r7, #4]
8004358: 681b ldr r3, [r3, #0]
800435a: 4a44 ldr r2, [pc, #272] @ (800446c <UART_SetConfig+0x2dc>)
800435c: 4293 cmp r3, r2
800435e: d125 bne.n 80043ac <UART_SetConfig+0x21c>
8004360: 4b3e ldr r3, [pc, #248] @ (800445c <UART_SetConfig+0x2cc>)
8004362: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004366: f403 7340 and.w r3, r3, #768 @ 0x300
800436a: f5b3 7f40 cmp.w r3, #768 @ 0x300
800436e: d017 beq.n 80043a0 <UART_SetConfig+0x210>
8004370: f5b3 7f40 cmp.w r3, #768 @ 0x300
8004374: d817 bhi.n 80043a6 <UART_SetConfig+0x216>
8004376: f5b3 7f00 cmp.w r3, #512 @ 0x200
800437a: d00b beq.n 8004394 <UART_SetConfig+0x204>
800437c: f5b3 7f00 cmp.w r3, #512 @ 0x200
8004380: d811 bhi.n 80043a6 <UART_SetConfig+0x216>
8004382: 2b00 cmp r3, #0
8004384: d003 beq.n 800438e <UART_SetConfig+0x1fe>
8004386: f5b3 7f80 cmp.w r3, #256 @ 0x100
800438a: d006 beq.n 800439a <UART_SetConfig+0x20a>
800438c: e00b b.n 80043a6 <UART_SetConfig+0x216>
800438e: 2300 movs r3, #0
8004390: 77fb strb r3, [r7, #31]
8004392: e0a1 b.n 80044d8 <UART_SetConfig+0x348>
8004394: 2302 movs r3, #2
8004396: 77fb strb r3, [r7, #31]
8004398: e09e b.n 80044d8 <UART_SetConfig+0x348>
800439a: 2304 movs r3, #4
800439c: 77fb strb r3, [r7, #31]
800439e: e09b b.n 80044d8 <UART_SetConfig+0x348>
80043a0: 2308 movs r3, #8
80043a2: 77fb strb r3, [r7, #31]
80043a4: e098 b.n 80044d8 <UART_SetConfig+0x348>
80043a6: 2310 movs r3, #16
80043a8: 77fb strb r3, [r7, #31]
80043aa: e095 b.n 80044d8 <UART_SetConfig+0x348>
80043ac: 687b ldr r3, [r7, #4]
80043ae: 681b ldr r3, [r3, #0]
80043b0: 4a2f ldr r2, [pc, #188] @ (8004470 <UART_SetConfig+0x2e0>)
80043b2: 4293 cmp r3, r2
80043b4: d125 bne.n 8004402 <UART_SetConfig+0x272>
80043b6: 4b29 ldr r3, [pc, #164] @ (800445c <UART_SetConfig+0x2cc>)
80043b8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80043bc: f403 6340 and.w r3, r3, #3072 @ 0xc00
80043c0: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
80043c4: d017 beq.n 80043f6 <UART_SetConfig+0x266>
80043c6: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
80043ca: d817 bhi.n 80043fc <UART_SetConfig+0x26c>
80043cc: f5b3 6f00 cmp.w r3, #2048 @ 0x800
80043d0: d00b beq.n 80043ea <UART_SetConfig+0x25a>
80043d2: f5b3 6f00 cmp.w r3, #2048 @ 0x800
80043d6: d811 bhi.n 80043fc <UART_SetConfig+0x26c>
80043d8: 2b00 cmp r3, #0
80043da: d003 beq.n 80043e4 <UART_SetConfig+0x254>
80043dc: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80043e0: d006 beq.n 80043f0 <UART_SetConfig+0x260>
80043e2: e00b b.n 80043fc <UART_SetConfig+0x26c>
80043e4: 2301 movs r3, #1
80043e6: 77fb strb r3, [r7, #31]
80043e8: e076 b.n 80044d8 <UART_SetConfig+0x348>
80043ea: 2302 movs r3, #2
80043ec: 77fb strb r3, [r7, #31]
80043ee: e073 b.n 80044d8 <UART_SetConfig+0x348>
80043f0: 2304 movs r3, #4
80043f2: 77fb strb r3, [r7, #31]
80043f4: e070 b.n 80044d8 <UART_SetConfig+0x348>
80043f6: 2308 movs r3, #8
80043f8: 77fb strb r3, [r7, #31]
80043fa: e06d b.n 80044d8 <UART_SetConfig+0x348>
80043fc: 2310 movs r3, #16
80043fe: 77fb strb r3, [r7, #31]
8004400: e06a b.n 80044d8 <UART_SetConfig+0x348>
8004402: 687b ldr r3, [r7, #4]
8004404: 681b ldr r3, [r3, #0]
8004406: 4a1b ldr r2, [pc, #108] @ (8004474 <UART_SetConfig+0x2e4>)
8004408: 4293 cmp r3, r2
800440a: d138 bne.n 800447e <UART_SetConfig+0x2ee>
800440c: 4b13 ldr r3, [pc, #76] @ (800445c <UART_SetConfig+0x2cc>)
800440e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004412: f403 5340 and.w r3, r3, #12288 @ 0x3000
8004416: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
800441a: d017 beq.n 800444c <UART_SetConfig+0x2bc>
800441c: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
8004420: d82a bhi.n 8004478 <UART_SetConfig+0x2e8>
8004422: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8004426: d00b beq.n 8004440 <UART_SetConfig+0x2b0>
8004428: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
800442c: d824 bhi.n 8004478 <UART_SetConfig+0x2e8>
800442e: 2b00 cmp r3, #0
8004430: d003 beq.n 800443a <UART_SetConfig+0x2aa>
8004432: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8004436: d006 beq.n 8004446 <UART_SetConfig+0x2b6>
8004438: e01e b.n 8004478 <UART_SetConfig+0x2e8>
800443a: 2300 movs r3, #0
800443c: 77fb strb r3, [r7, #31]
800443e: e04b b.n 80044d8 <UART_SetConfig+0x348>
8004440: 2302 movs r3, #2
8004442: 77fb strb r3, [r7, #31]
8004444: e048 b.n 80044d8 <UART_SetConfig+0x348>
8004446: 2304 movs r3, #4
8004448: 77fb strb r3, [r7, #31]
800444a: e045 b.n 80044d8 <UART_SetConfig+0x348>
800444c: 2308 movs r3, #8
800444e: 77fb strb r3, [r7, #31]
8004450: e042 b.n 80044d8 <UART_SetConfig+0x348>
8004452: bf00 nop
8004454: efff69f3 .word 0xefff69f3
8004458: 40011000 .word 0x40011000
800445c: 40023800 .word 0x40023800
8004460: 40004400 .word 0x40004400
8004464: 40004800 .word 0x40004800
8004468: 40004c00 .word 0x40004c00
800446c: 40005000 .word 0x40005000
8004470: 40011400 .word 0x40011400
8004474: 40007800 .word 0x40007800
8004478: 2310 movs r3, #16
800447a: 77fb strb r3, [r7, #31]
800447c: e02c b.n 80044d8 <UART_SetConfig+0x348>
800447e: 687b ldr r3, [r7, #4]
8004480: 681b ldr r3, [r3, #0]
8004482: 4a72 ldr r2, [pc, #456] @ (800464c <UART_SetConfig+0x4bc>)
8004484: 4293 cmp r3, r2
8004486: d125 bne.n 80044d4 <UART_SetConfig+0x344>
8004488: 4b71 ldr r3, [pc, #452] @ (8004650 <UART_SetConfig+0x4c0>)
800448a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800448e: f403 4340 and.w r3, r3, #49152 @ 0xc000
8004492: f5b3 4f40 cmp.w r3, #49152 @ 0xc000
8004496: d017 beq.n 80044c8 <UART_SetConfig+0x338>
8004498: f5b3 4f40 cmp.w r3, #49152 @ 0xc000
800449c: d817 bhi.n 80044ce <UART_SetConfig+0x33e>
800449e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
80044a2: d00b beq.n 80044bc <UART_SetConfig+0x32c>
80044a4: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
80044a8: d811 bhi.n 80044ce <UART_SetConfig+0x33e>
80044aa: 2b00 cmp r3, #0
80044ac: d003 beq.n 80044b6 <UART_SetConfig+0x326>
80044ae: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
80044b2: d006 beq.n 80044c2 <UART_SetConfig+0x332>
80044b4: e00b b.n 80044ce <UART_SetConfig+0x33e>
80044b6: 2300 movs r3, #0
80044b8: 77fb strb r3, [r7, #31]
80044ba: e00d b.n 80044d8 <UART_SetConfig+0x348>
80044bc: 2302 movs r3, #2
80044be: 77fb strb r3, [r7, #31]
80044c0: e00a b.n 80044d8 <UART_SetConfig+0x348>
80044c2: 2304 movs r3, #4
80044c4: 77fb strb r3, [r7, #31]
80044c6: e007 b.n 80044d8 <UART_SetConfig+0x348>
80044c8: 2308 movs r3, #8
80044ca: 77fb strb r3, [r7, #31]
80044cc: e004 b.n 80044d8 <UART_SetConfig+0x348>
80044ce: 2310 movs r3, #16
80044d0: 77fb strb r3, [r7, #31]
80044d2: e001 b.n 80044d8 <UART_SetConfig+0x348>
80044d4: 2310 movs r3, #16
80044d6: 77fb strb r3, [r7, #31]
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
80044d8: 687b ldr r3, [r7, #4]
80044da: 69db ldr r3, [r3, #28]
80044dc: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
80044e0: d15b bne.n 800459a <UART_SetConfig+0x40a>
{
switch (clocksource)
80044e2: 7ffb ldrb r3, [r7, #31]
80044e4: 2b08 cmp r3, #8
80044e6: d828 bhi.n 800453a <UART_SetConfig+0x3aa>
80044e8: a201 add r2, pc, #4 @ (adr r2, 80044f0 <UART_SetConfig+0x360>)
80044ea: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80044ee: bf00 nop
80044f0: 08004515 .word 0x08004515
80044f4: 0800451d .word 0x0800451d
80044f8: 08004525 .word 0x08004525
80044fc: 0800453b .word 0x0800453b
8004500: 0800452b .word 0x0800452b
8004504: 0800453b .word 0x0800453b
8004508: 0800453b .word 0x0800453b
800450c: 0800453b .word 0x0800453b
8004510: 08004533 .word 0x08004533
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8004514: f7fe feaa bl 800326c <HAL_RCC_GetPCLK1Freq>
8004518: 61b8 str r0, [r7, #24]
break;
800451a: e013 b.n 8004544 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
800451c: f7fe feba bl 8003294 <HAL_RCC_GetPCLK2Freq>
8004520: 61b8 str r0, [r7, #24]
break;
8004522: e00f b.n 8004544 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8004524: 4b4b ldr r3, [pc, #300] @ (8004654 <UART_SetConfig+0x4c4>)
8004526: 61bb str r3, [r7, #24]
break;
8004528: e00c b.n 8004544 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
800452a: f7fe fdcd bl 80030c8 <HAL_RCC_GetSysClockFreq>
800452e: 61b8 str r0, [r7, #24]
break;
8004530: e008 b.n 8004544 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8004532: f44f 4300 mov.w r3, #32768 @ 0x8000
8004536: 61bb str r3, [r7, #24]
break;
8004538: e004 b.n 8004544 <UART_SetConfig+0x3b4>
default:
pclk = 0U;
800453a: 2300 movs r3, #0
800453c: 61bb str r3, [r7, #24]
ret = HAL_ERROR;
800453e: 2301 movs r3, #1
8004540: 77bb strb r3, [r7, #30]
break;
8004542: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
8004544: 69bb ldr r3, [r7, #24]
8004546: 2b00 cmp r3, #0
8004548: d074 beq.n 8004634 <UART_SetConfig+0x4a4>
{
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
800454a: 69bb ldr r3, [r7, #24]
800454c: 005a lsls r2, r3, #1
800454e: 687b ldr r3, [r7, #4]
8004550: 685b ldr r3, [r3, #4]
8004552: 085b lsrs r3, r3, #1
8004554: 441a add r2, r3
8004556: 687b ldr r3, [r7, #4]
8004558: 685b ldr r3, [r3, #4]
800455a: fbb2 f3f3 udiv r3, r2, r3
800455e: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8004560: 693b ldr r3, [r7, #16]
8004562: 2b0f cmp r3, #15
8004564: d916 bls.n 8004594 <UART_SetConfig+0x404>
8004566: 693b ldr r3, [r7, #16]
8004568: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
800456c: d212 bcs.n 8004594 <UART_SetConfig+0x404>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
800456e: 693b ldr r3, [r7, #16]
8004570: b29b uxth r3, r3
8004572: f023 030f bic.w r3, r3, #15
8004576: 81fb strh r3, [r7, #14]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8004578: 693b ldr r3, [r7, #16]
800457a: 085b lsrs r3, r3, #1
800457c: b29b uxth r3, r3
800457e: f003 0307 and.w r3, r3, #7
8004582: b29a uxth r2, r3
8004584: 89fb ldrh r3, [r7, #14]
8004586: 4313 orrs r3, r2
8004588: 81fb strh r3, [r7, #14]
huart->Instance->BRR = brrtemp;
800458a: 687b ldr r3, [r7, #4]
800458c: 681b ldr r3, [r3, #0]
800458e: 89fa ldrh r2, [r7, #14]
8004590: 60da str r2, [r3, #12]
8004592: e04f b.n 8004634 <UART_SetConfig+0x4a4>
}
else
{
ret = HAL_ERROR;
8004594: 2301 movs r3, #1
8004596: 77bb strb r3, [r7, #30]
8004598: e04c b.n 8004634 <UART_SetConfig+0x4a4>
}
}
}
else
{
switch (clocksource)
800459a: 7ffb ldrb r3, [r7, #31]
800459c: 2b08 cmp r3, #8
800459e: d828 bhi.n 80045f2 <UART_SetConfig+0x462>
80045a0: a201 add r2, pc, #4 @ (adr r2, 80045a8 <UART_SetConfig+0x418>)
80045a2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80045a6: bf00 nop
80045a8: 080045cd .word 0x080045cd
80045ac: 080045d5 .word 0x080045d5
80045b0: 080045dd .word 0x080045dd
80045b4: 080045f3 .word 0x080045f3
80045b8: 080045e3 .word 0x080045e3
80045bc: 080045f3 .word 0x080045f3
80045c0: 080045f3 .word 0x080045f3
80045c4: 080045f3 .word 0x080045f3
80045c8: 080045eb .word 0x080045eb
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
80045cc: f7fe fe4e bl 800326c <HAL_RCC_GetPCLK1Freq>
80045d0: 61b8 str r0, [r7, #24]
break;
80045d2: e013 b.n 80045fc <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
80045d4: f7fe fe5e bl 8003294 <HAL_RCC_GetPCLK2Freq>
80045d8: 61b8 str r0, [r7, #24]
break;
80045da: e00f b.n 80045fc <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
80045dc: 4b1d ldr r3, [pc, #116] @ (8004654 <UART_SetConfig+0x4c4>)
80045de: 61bb str r3, [r7, #24]
break;
80045e0: e00c b.n 80045fc <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80045e2: f7fe fd71 bl 80030c8 <HAL_RCC_GetSysClockFreq>
80045e6: 61b8 str r0, [r7, #24]
break;
80045e8: e008 b.n 80045fc <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
80045ea: f44f 4300 mov.w r3, #32768 @ 0x8000
80045ee: 61bb str r3, [r7, #24]
break;
80045f0: e004 b.n 80045fc <UART_SetConfig+0x46c>
default:
pclk = 0U;
80045f2: 2300 movs r3, #0
80045f4: 61bb str r3, [r7, #24]
ret = HAL_ERROR;
80045f6: 2301 movs r3, #1
80045f8: 77bb strb r3, [r7, #30]
break;
80045fa: bf00 nop
}
if (pclk != 0U)
80045fc: 69bb ldr r3, [r7, #24]
80045fe: 2b00 cmp r3, #0
8004600: d018 beq.n 8004634 <UART_SetConfig+0x4a4>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
8004602: 687b ldr r3, [r7, #4]
8004604: 685b ldr r3, [r3, #4]
8004606: 085a lsrs r2, r3, #1
8004608: 69bb ldr r3, [r7, #24]
800460a: 441a add r2, r3
800460c: 687b ldr r3, [r7, #4]
800460e: 685b ldr r3, [r3, #4]
8004610: fbb2 f3f3 udiv r3, r2, r3
8004614: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8004616: 693b ldr r3, [r7, #16]
8004618: 2b0f cmp r3, #15
800461a: d909 bls.n 8004630 <UART_SetConfig+0x4a0>
800461c: 693b ldr r3, [r7, #16]
800461e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8004622: d205 bcs.n 8004630 <UART_SetConfig+0x4a0>
{
huart->Instance->BRR = (uint16_t)usartdiv;
8004624: 693b ldr r3, [r7, #16]
8004626: b29a uxth r2, r3
8004628: 687b ldr r3, [r7, #4]
800462a: 681b ldr r3, [r3, #0]
800462c: 60da str r2, [r3, #12]
800462e: e001 b.n 8004634 <UART_SetConfig+0x4a4>
}
else
{
ret = HAL_ERROR;
8004630: 2301 movs r3, #1
8004632: 77bb strb r3, [r7, #30]
}
}
/* Clear ISR function pointers */
huart->RxISR = NULL;
8004634: 687b ldr r3, [r7, #4]
8004636: 2200 movs r2, #0
8004638: 669a str r2, [r3, #104] @ 0x68
huart->TxISR = NULL;
800463a: 687b ldr r3, [r7, #4]
800463c: 2200 movs r2, #0
800463e: 66da str r2, [r3, #108] @ 0x6c
return ret;
8004640: 7fbb ldrb r3, [r7, #30]
}
8004642: 4618 mov r0, r3
8004644: 3720 adds r7, #32
8004646: 46bd mov sp, r7
8004648: bd80 pop {r7, pc}
800464a: bf00 nop
800464c: 40007c00 .word 0x40007c00
8004650: 40023800 .word 0x40023800
8004654: 00f42400 .word 0x00f42400
08004658 <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
8004658: b480 push {r7}
800465a: b083 sub sp, #12
800465c: af00 add r7, sp, #0
800465e: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
8004660: 687b ldr r3, [r7, #4]
8004662: 6a5b ldr r3, [r3, #36] @ 0x24
8004664: f003 0308 and.w r3, r3, #8
8004668: 2b00 cmp r3, #0
800466a: d00a beq.n 8004682 <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
800466c: 687b ldr r3, [r7, #4]
800466e: 681b ldr r3, [r3, #0]
8004670: 685b ldr r3, [r3, #4]
8004672: f423 4100 bic.w r1, r3, #32768 @ 0x8000
8004676: 687b ldr r3, [r7, #4]
8004678: 6b5a ldr r2, [r3, #52] @ 0x34
800467a: 687b ldr r3, [r7, #4]
800467c: 681b ldr r3, [r3, #0]
800467e: 430a orrs r2, r1
8004680: 605a str r2, [r3, #4]
}
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
8004682: 687b ldr r3, [r7, #4]
8004684: 6a5b ldr r3, [r3, #36] @ 0x24
8004686: f003 0301 and.w r3, r3, #1
800468a: 2b00 cmp r3, #0
800468c: d00a beq.n 80046a4 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
800468e: 687b ldr r3, [r7, #4]
8004690: 681b ldr r3, [r3, #0]
8004692: 685b ldr r3, [r3, #4]
8004694: f423 3100 bic.w r1, r3, #131072 @ 0x20000
8004698: 687b ldr r3, [r7, #4]
800469a: 6a9a ldr r2, [r3, #40] @ 0x28
800469c: 687b ldr r3, [r7, #4]
800469e: 681b ldr r3, [r3, #0]
80046a0: 430a orrs r2, r1
80046a2: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
80046a4: 687b ldr r3, [r7, #4]
80046a6: 6a5b ldr r3, [r3, #36] @ 0x24
80046a8: f003 0302 and.w r3, r3, #2
80046ac: 2b00 cmp r3, #0
80046ae: d00a beq.n 80046c6 <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
80046b0: 687b ldr r3, [r7, #4]
80046b2: 681b ldr r3, [r3, #0]
80046b4: 685b ldr r3, [r3, #4]
80046b6: f423 3180 bic.w r1, r3, #65536 @ 0x10000
80046ba: 687b ldr r3, [r7, #4]
80046bc: 6ada ldr r2, [r3, #44] @ 0x2c
80046be: 687b ldr r3, [r7, #4]
80046c0: 681b ldr r3, [r3, #0]
80046c2: 430a orrs r2, r1
80046c4: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
80046c6: 687b ldr r3, [r7, #4]
80046c8: 6a5b ldr r3, [r3, #36] @ 0x24
80046ca: f003 0304 and.w r3, r3, #4
80046ce: 2b00 cmp r3, #0
80046d0: d00a beq.n 80046e8 <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
80046d2: 687b ldr r3, [r7, #4]
80046d4: 681b ldr r3, [r3, #0]
80046d6: 685b ldr r3, [r3, #4]
80046d8: f423 2180 bic.w r1, r3, #262144 @ 0x40000
80046dc: 687b ldr r3, [r7, #4]
80046de: 6b1a ldr r2, [r3, #48] @ 0x30
80046e0: 687b ldr r3, [r7, #4]
80046e2: 681b ldr r3, [r3, #0]
80046e4: 430a orrs r2, r1
80046e6: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
80046e8: 687b ldr r3, [r7, #4]
80046ea: 6a5b ldr r3, [r3, #36] @ 0x24
80046ec: f003 0310 and.w r3, r3, #16
80046f0: 2b00 cmp r3, #0
80046f2: d00a beq.n 800470a <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
80046f4: 687b ldr r3, [r7, #4]
80046f6: 681b ldr r3, [r3, #0]
80046f8: 689b ldr r3, [r3, #8]
80046fa: f423 5180 bic.w r1, r3, #4096 @ 0x1000
80046fe: 687b ldr r3, [r7, #4]
8004700: 6b9a ldr r2, [r3, #56] @ 0x38
8004702: 687b ldr r3, [r7, #4]
8004704: 681b ldr r3, [r3, #0]
8004706: 430a orrs r2, r1
8004708: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
800470a: 687b ldr r3, [r7, #4]
800470c: 6a5b ldr r3, [r3, #36] @ 0x24
800470e: f003 0320 and.w r3, r3, #32
8004712: 2b00 cmp r3, #0
8004714: d00a beq.n 800472c <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
8004716: 687b ldr r3, [r7, #4]
8004718: 681b ldr r3, [r3, #0]
800471a: 689b ldr r3, [r3, #8]
800471c: f423 5100 bic.w r1, r3, #8192 @ 0x2000
8004720: 687b ldr r3, [r7, #4]
8004722: 6bda ldr r2, [r3, #60] @ 0x3c
8004724: 687b ldr r3, [r7, #4]
8004726: 681b ldr r3, [r3, #0]
8004728: 430a orrs r2, r1
800472a: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
800472c: 687b ldr r3, [r7, #4]
800472e: 6a5b ldr r3, [r3, #36] @ 0x24
8004730: f003 0340 and.w r3, r3, #64 @ 0x40
8004734: 2b00 cmp r3, #0
8004736: d01a beq.n 800476e <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
8004738: 687b ldr r3, [r7, #4]
800473a: 681b ldr r3, [r3, #0]
800473c: 685b ldr r3, [r3, #4]
800473e: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
8004742: 687b ldr r3, [r7, #4]
8004744: 6c1a ldr r2, [r3, #64] @ 0x40
8004746: 687b ldr r3, [r7, #4]
8004748: 681b ldr r3, [r3, #0]
800474a: 430a orrs r2, r1
800474c: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
800474e: 687b ldr r3, [r7, #4]
8004750: 6c1b ldr r3, [r3, #64] @ 0x40
8004752: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8004756: d10a bne.n 800476e <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
8004758: 687b ldr r3, [r7, #4]
800475a: 681b ldr r3, [r3, #0]
800475c: 685b ldr r3, [r3, #4]
800475e: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
8004762: 687b ldr r3, [r7, #4]
8004764: 6c5a ldr r2, [r3, #68] @ 0x44
8004766: 687b ldr r3, [r7, #4]
8004768: 681b ldr r3, [r3, #0]
800476a: 430a orrs r2, r1
800476c: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
800476e: 687b ldr r3, [r7, #4]
8004770: 6a5b ldr r3, [r3, #36] @ 0x24
8004772: f003 0380 and.w r3, r3, #128 @ 0x80
8004776: 2b00 cmp r3, #0
8004778: d00a beq.n 8004790 <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
800477a: 687b ldr r3, [r7, #4]
800477c: 681b ldr r3, [r3, #0]
800477e: 685b ldr r3, [r3, #4]
8004780: f423 2100 bic.w r1, r3, #524288 @ 0x80000
8004784: 687b ldr r3, [r7, #4]
8004786: 6c9a ldr r2, [r3, #72] @ 0x48
8004788: 687b ldr r3, [r7, #4]
800478a: 681b ldr r3, [r3, #0]
800478c: 430a orrs r2, r1
800478e: 605a str r2, [r3, #4]
}
}
8004790: bf00 nop
8004792: 370c adds r7, #12
8004794: 46bd mov sp, r7
8004796: f85d 7b04 ldr.w r7, [sp], #4
800479a: 4770 bx lr
0800479c <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
800479c: b580 push {r7, lr}
800479e: b08c sub sp, #48 @ 0x30
80047a0: af02 add r7, sp, #8
80047a2: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80047a4: 687b ldr r3, [r7, #4]
80047a6: 2200 movs r2, #0
80047a8: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
80047ac: f7fd fc6e bl 800208c <HAL_GetTick>
80047b0: 6278 str r0, [r7, #36] @ 0x24
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
80047b2: 687b ldr r3, [r7, #4]
80047b4: 681b ldr r3, [r3, #0]
80047b6: 681b ldr r3, [r3, #0]
80047b8: f003 0308 and.w r3, r3, #8
80047bc: 2b08 cmp r3, #8
80047be: d12e bne.n 800481e <UART_CheckIdleState+0x82>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
80047c0: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
80047c4: 9300 str r3, [sp, #0]
80047c6: 6a7b ldr r3, [r7, #36] @ 0x24
80047c8: 2200 movs r2, #0
80047ca: f44f 1100 mov.w r1, #2097152 @ 0x200000
80047ce: 6878 ldr r0, [r7, #4]
80047d0: f000 f83b bl 800484a <UART_WaitOnFlagUntilTimeout>
80047d4: 4603 mov r3, r0
80047d6: 2b00 cmp r3, #0
80047d8: d021 beq.n 800481e <UART_CheckIdleState+0x82>
{
/* Disable TXE interrupt for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
80047da: 687b ldr r3, [r7, #4]
80047dc: 681b ldr r3, [r3, #0]
80047de: 613b str r3, [r7, #16]
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80047e0: 693b ldr r3, [r7, #16]
80047e2: e853 3f00 ldrex r3, [r3]
80047e6: 60fb str r3, [r7, #12]
return(result);
80047e8: 68fb ldr r3, [r7, #12]
80047ea: f023 0380 bic.w r3, r3, #128 @ 0x80
80047ee: 623b str r3, [r7, #32]
80047f0: 687b ldr r3, [r7, #4]
80047f2: 681b ldr r3, [r3, #0]
80047f4: 461a mov r2, r3
80047f6: 6a3b ldr r3, [r7, #32]
80047f8: 61fb str r3, [r7, #28]
80047fa: 61ba str r2, [r7, #24]
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80047fc: 69b9 ldr r1, [r7, #24]
80047fe: 69fa ldr r2, [r7, #28]
8004800: e841 2300 strex r3, r2, [r1]
8004804: 617b str r3, [r7, #20]
return(result);
8004806: 697b ldr r3, [r7, #20]
8004808: 2b00 cmp r3, #0
800480a: d1e6 bne.n 80047da <UART_CheckIdleState+0x3e>
huart->gState = HAL_UART_STATE_READY;
800480c: 687b ldr r3, [r7, #4]
800480e: 2220 movs r2, #32
8004810: 67da str r2, [r3, #124] @ 0x7c
__HAL_UNLOCK(huart);
8004812: 687b ldr r3, [r7, #4]
8004814: 2200 movs r2, #0
8004816: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Timeout occurred */
return HAL_TIMEOUT;
800481a: 2303 movs r3, #3
800481c: e011 b.n 8004842 <UART_CheckIdleState+0xa6>
}
}
#endif /* USART_ISR_REACK */
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
800481e: 687b ldr r3, [r7, #4]
8004820: 2220 movs r2, #32
8004822: 67da str r2, [r3, #124] @ 0x7c
huart->RxState = HAL_UART_STATE_READY;
8004824: 687b ldr r3, [r7, #4]
8004826: 2220 movs r2, #32
8004828: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
800482c: 687b ldr r3, [r7, #4]
800482e: 2200 movs r2, #0
8004830: 661a str r2, [r3, #96] @ 0x60
huart->RxEventType = HAL_UART_RXEVENT_TC;
8004832: 687b ldr r3, [r7, #4]
8004834: 2200 movs r2, #0
8004836: 665a str r2, [r3, #100] @ 0x64
__HAL_UNLOCK(huart);
8004838: 687b ldr r3, [r7, #4]
800483a: 2200 movs r2, #0
800483c: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_OK;
8004840: 2300 movs r3, #0
}
8004842: 4618 mov r0, r3
8004844: 3728 adds r7, #40 @ 0x28
8004846: 46bd mov sp, r7
8004848: bd80 pop {r7, pc}
0800484a <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
800484a: b580 push {r7, lr}
800484c: b084 sub sp, #16
800484e: af00 add r7, sp, #0
8004850: 60f8 str r0, [r7, #12]
8004852: 60b9 str r1, [r7, #8]
8004854: 603b str r3, [r7, #0]
8004856: 4613 mov r3, r2
8004858: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
800485a: e04f b.n 80048fc <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
800485c: 69bb ldr r3, [r7, #24]
800485e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8004862: d04b beq.n 80048fc <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004864: f7fd fc12 bl 800208c <HAL_GetTick>
8004868: 4602 mov r2, r0
800486a: 683b ldr r3, [r7, #0]
800486c: 1ad3 subs r3, r2, r3
800486e: 69ba ldr r2, [r7, #24]
8004870: 429a cmp r2, r3
8004872: d302 bcc.n 800487a <UART_WaitOnFlagUntilTimeout+0x30>
8004874: 69bb ldr r3, [r7, #24]
8004876: 2b00 cmp r3, #0
8004878: d101 bne.n 800487e <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
800487a: 2303 movs r3, #3
800487c: e04e b.n 800491c <UART_WaitOnFlagUntilTimeout+0xd2>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
800487e: 68fb ldr r3, [r7, #12]
8004880: 681b ldr r3, [r3, #0]
8004882: 681b ldr r3, [r3, #0]
8004884: f003 0304 and.w r3, r3, #4
8004888: 2b00 cmp r3, #0
800488a: d037 beq.n 80048fc <UART_WaitOnFlagUntilTimeout+0xb2>
800488c: 68bb ldr r3, [r7, #8]
800488e: 2b80 cmp r3, #128 @ 0x80
8004890: d034 beq.n 80048fc <UART_WaitOnFlagUntilTimeout+0xb2>
8004892: 68bb ldr r3, [r7, #8]
8004894: 2b40 cmp r3, #64 @ 0x40
8004896: d031 beq.n 80048fc <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
8004898: 68fb ldr r3, [r7, #12]
800489a: 681b ldr r3, [r3, #0]
800489c: 69db ldr r3, [r3, #28]
800489e: f003 0308 and.w r3, r3, #8
80048a2: 2b08 cmp r3, #8
80048a4: d110 bne.n 80048c8 <UART_WaitOnFlagUntilTimeout+0x7e>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
80048a6: 68fb ldr r3, [r7, #12]
80048a8: 681b ldr r3, [r3, #0]
80048aa: 2208 movs r2, #8
80048ac: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
80048ae: 68f8 ldr r0, [r7, #12]
80048b0: f000 f838 bl 8004924 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
80048b4: 68fb ldr r3, [r7, #12]
80048b6: 2208 movs r2, #8
80048b8: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
80048bc: 68fb ldr r3, [r7, #12]
80048be: 2200 movs r2, #0
80048c0: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_ERROR;
80048c4: 2301 movs r3, #1
80048c6: e029 b.n 800491c <UART_WaitOnFlagUntilTimeout+0xd2>
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
80048c8: 68fb ldr r3, [r7, #12]
80048ca: 681b ldr r3, [r3, #0]
80048cc: 69db ldr r3, [r3, #28]
80048ce: f403 6300 and.w r3, r3, #2048 @ 0x800
80048d2: f5b3 6f00 cmp.w r3, #2048 @ 0x800
80048d6: d111 bne.n 80048fc <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
80048d8: 68fb ldr r3, [r7, #12]
80048da: 681b ldr r3, [r3, #0]
80048dc: f44f 6200 mov.w r2, #2048 @ 0x800
80048e0: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
80048e2: 68f8 ldr r0, [r7, #12]
80048e4: f000 f81e bl 8004924 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
80048e8: 68fb ldr r3, [r7, #12]
80048ea: 2220 movs r2, #32
80048ec: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
80048f0: 68fb ldr r3, [r7, #12]
80048f2: 2200 movs r2, #0
80048f4: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_TIMEOUT;
80048f8: 2303 movs r3, #3
80048fa: e00f b.n 800491c <UART_WaitOnFlagUntilTimeout+0xd2>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80048fc: 68fb ldr r3, [r7, #12]
80048fe: 681b ldr r3, [r3, #0]
8004900: 69da ldr r2, [r3, #28]
8004902: 68bb ldr r3, [r7, #8]
8004904: 4013 ands r3, r2
8004906: 68ba ldr r2, [r7, #8]
8004908: 429a cmp r2, r3
800490a: bf0c ite eq
800490c: 2301 moveq r3, #1
800490e: 2300 movne r3, #0
8004910: b2db uxtb r3, r3
8004912: 461a mov r2, r3
8004914: 79fb ldrb r3, [r7, #7]
8004916: 429a cmp r2, r3
8004918: d0a0 beq.n 800485c <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
800491a: 2300 movs r3, #0
}
800491c: 4618 mov r0, r3
800491e: 3710 adds r7, #16
8004920: 46bd mov sp, r7
8004922: bd80 pop {r7, pc}
08004924 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8004924: b480 push {r7}
8004926: b095 sub sp, #84 @ 0x54
8004928: af00 add r7, sp, #0
800492a: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
800492c: 687b ldr r3, [r7, #4]
800492e: 681b ldr r3, [r3, #0]
8004930: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004932: 6b7b ldr r3, [r7, #52] @ 0x34
8004934: e853 3f00 ldrex r3, [r3]
8004938: 633b str r3, [r7, #48] @ 0x30
return(result);
800493a: 6b3b ldr r3, [r7, #48] @ 0x30
800493c: f423 7390 bic.w r3, r3, #288 @ 0x120
8004940: 64fb str r3, [r7, #76] @ 0x4c
8004942: 687b ldr r3, [r7, #4]
8004944: 681b ldr r3, [r3, #0]
8004946: 461a mov r2, r3
8004948: 6cfb ldr r3, [r7, #76] @ 0x4c
800494a: 643b str r3, [r7, #64] @ 0x40
800494c: 63fa str r2, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800494e: 6bf9 ldr r1, [r7, #60] @ 0x3c
8004950: 6c3a ldr r2, [r7, #64] @ 0x40
8004952: e841 2300 strex r3, r2, [r1]
8004956: 63bb str r3, [r7, #56] @ 0x38
return(result);
8004958: 6bbb ldr r3, [r7, #56] @ 0x38
800495a: 2b00 cmp r3, #0
800495c: d1e6 bne.n 800492c <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
800495e: 687b ldr r3, [r7, #4]
8004960: 681b ldr r3, [r3, #0]
8004962: 3308 adds r3, #8
8004964: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004966: 6a3b ldr r3, [r7, #32]
8004968: e853 3f00 ldrex r3, [r3]
800496c: 61fb str r3, [r7, #28]
return(result);
800496e: 69fb ldr r3, [r7, #28]
8004970: f023 0301 bic.w r3, r3, #1
8004974: 64bb str r3, [r7, #72] @ 0x48
8004976: 687b ldr r3, [r7, #4]
8004978: 681b ldr r3, [r3, #0]
800497a: 3308 adds r3, #8
800497c: 6cba ldr r2, [r7, #72] @ 0x48
800497e: 62fa str r2, [r7, #44] @ 0x2c
8004980: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004982: 6ab9 ldr r1, [r7, #40] @ 0x28
8004984: 6afa ldr r2, [r7, #44] @ 0x2c
8004986: e841 2300 strex r3, r2, [r1]
800498a: 627b str r3, [r7, #36] @ 0x24
return(result);
800498c: 6a7b ldr r3, [r7, #36] @ 0x24
800498e: 2b00 cmp r3, #0
8004990: d1e5 bne.n 800495e <UART_EndRxTransfer+0x3a>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8004992: 687b ldr r3, [r7, #4]
8004994: 6e1b ldr r3, [r3, #96] @ 0x60
8004996: 2b01 cmp r3, #1
8004998: d118 bne.n 80049cc <UART_EndRxTransfer+0xa8>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800499a: 687b ldr r3, [r7, #4]
800499c: 681b ldr r3, [r3, #0]
800499e: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80049a0: 68fb ldr r3, [r7, #12]
80049a2: e853 3f00 ldrex r3, [r3]
80049a6: 60bb str r3, [r7, #8]
return(result);
80049a8: 68bb ldr r3, [r7, #8]
80049aa: f023 0310 bic.w r3, r3, #16
80049ae: 647b str r3, [r7, #68] @ 0x44
80049b0: 687b ldr r3, [r7, #4]
80049b2: 681b ldr r3, [r3, #0]
80049b4: 461a mov r2, r3
80049b6: 6c7b ldr r3, [r7, #68] @ 0x44
80049b8: 61bb str r3, [r7, #24]
80049ba: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80049bc: 6979 ldr r1, [r7, #20]
80049be: 69ba ldr r2, [r7, #24]
80049c0: e841 2300 strex r3, r2, [r1]
80049c4: 613b str r3, [r7, #16]
return(result);
80049c6: 693b ldr r3, [r7, #16]
80049c8: 2b00 cmp r3, #0
80049ca: d1e6 bne.n 800499a <UART_EndRxTransfer+0x76>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80049cc: 687b ldr r3, [r7, #4]
80049ce: 2220 movs r2, #32
80049d0: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80049d4: 687b ldr r3, [r7, #4]
80049d6: 2200 movs r2, #0
80049d8: 661a str r2, [r3, #96] @ 0x60
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
80049da: 687b ldr r3, [r7, #4]
80049dc: 2200 movs r2, #0
80049de: 669a str r2, [r3, #104] @ 0x68
}
80049e0: bf00 nop
80049e2: 3754 adds r7, #84 @ 0x54
80049e4: 46bd mov sp, r7
80049e6: f85d 7b04 ldr.w r7, [sp], #4
80049ea: 4770 bx lr
080049ec <FMC_NORSRAM_Init>:
* @param Init Pointer to NORSRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
const FMC_NORSRAM_InitTypeDef *Init)
{
80049ec: b480 push {r7}
80049ee: b087 sub sp, #28
80049f0: af00 add r7, sp, #0
80049f2: 6078 str r0, [r7, #4]
80049f4: 6039 str r1, [r7, #0]
assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
assert_param(IS_FMC_PAGESIZE(Init->PageSize));
/* Disable NORSRAM Device */
__FMC_NORSRAM_DISABLE(Device, Init->NSBank);
80049f6: 683b ldr r3, [r7, #0]
80049f8: 681a ldr r2, [r3, #0]
80049fa: 687b ldr r3, [r7, #4]
80049fc: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8004a00: 683a ldr r2, [r7, #0]
8004a02: 6812 ldr r2, [r2, #0]
8004a04: f023 0101 bic.w r1, r3, #1
8004a08: 687b ldr r3, [r7, #4]
8004a0a: f843 1022 str.w r1, [r3, r2, lsl #2]
/* Set NORSRAM device control parameters */
if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
8004a0e: 683b ldr r3, [r7, #0]
8004a10: 689b ldr r3, [r3, #8]
8004a12: 2b08 cmp r3, #8
8004a14: d102 bne.n 8004a1c <FMC_NORSRAM_Init+0x30>
{
flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
8004a16: 2340 movs r3, #64 @ 0x40
8004a18: 617b str r3, [r7, #20]
8004a1a: e001 b.n 8004a20 <FMC_NORSRAM_Init+0x34>
}
else
{
flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
8004a1c: 2300 movs r3, #0
8004a1e: 617b str r3, [r7, #20]
}
btcr_reg = (flashaccess | \
Init->DataAddressMux | \
8004a20: 683b ldr r3, [r7, #0]
8004a22: 685a ldr r2, [r3, #4]
btcr_reg = (flashaccess | \
8004a24: 697b ldr r3, [r7, #20]
8004a26: 431a orrs r2, r3
Init->MemoryType | \
8004a28: 683b ldr r3, [r7, #0]
8004a2a: 689b ldr r3, [r3, #8]
Init->DataAddressMux | \
8004a2c: 431a orrs r2, r3
Init->MemoryDataWidth | \
8004a2e: 683b ldr r3, [r7, #0]
8004a30: 68db ldr r3, [r3, #12]
Init->MemoryType | \
8004a32: 431a orrs r2, r3
Init->BurstAccessMode | \
8004a34: 683b ldr r3, [r7, #0]
8004a36: 691b ldr r3, [r3, #16]
Init->MemoryDataWidth | \
8004a38: 431a orrs r2, r3
Init->WaitSignalPolarity | \
8004a3a: 683b ldr r3, [r7, #0]
8004a3c: 695b ldr r3, [r3, #20]
Init->BurstAccessMode | \
8004a3e: 431a orrs r2, r3
Init->WaitSignalActive | \
8004a40: 683b ldr r3, [r7, #0]
8004a42: 699b ldr r3, [r3, #24]
Init->WaitSignalPolarity | \
8004a44: 431a orrs r2, r3
Init->WriteOperation | \
8004a46: 683b ldr r3, [r7, #0]
8004a48: 69db ldr r3, [r3, #28]
Init->WaitSignalActive | \
8004a4a: 431a orrs r2, r3
Init->WaitSignal | \
8004a4c: 683b ldr r3, [r7, #0]
8004a4e: 6a1b ldr r3, [r3, #32]
Init->WriteOperation | \
8004a50: 431a orrs r2, r3
Init->ExtendedMode | \
8004a52: 683b ldr r3, [r7, #0]
8004a54: 6a5b ldr r3, [r3, #36] @ 0x24
Init->WaitSignal | \
8004a56: 431a orrs r2, r3
Init->AsynchronousWait | \
8004a58: 683b ldr r3, [r7, #0]
8004a5a: 6a9b ldr r3, [r3, #40] @ 0x28
Init->ExtendedMode | \
8004a5c: 431a orrs r2, r3
Init->WriteBurst);
8004a5e: 683b ldr r3, [r7, #0]
8004a60: 6adb ldr r3, [r3, #44] @ 0x2c
btcr_reg = (flashaccess | \
8004a62: 4313 orrs r3, r2
8004a64: 613b str r3, [r7, #16]
btcr_reg |= Init->ContinuousClock;
8004a66: 683b ldr r3, [r7, #0]
8004a68: 6b1b ldr r3, [r3, #48] @ 0x30
8004a6a: 693a ldr r2, [r7, #16]
8004a6c: 4313 orrs r3, r2
8004a6e: 613b str r3, [r7, #16]
btcr_reg |= Init->WriteFifo;
8004a70: 683b ldr r3, [r7, #0]
8004a72: 6b5b ldr r3, [r3, #52] @ 0x34
8004a74: 693a ldr r2, [r7, #16]
8004a76: 4313 orrs r3, r2
8004a78: 613b str r3, [r7, #16]
btcr_reg |= Init->PageSize;
8004a7a: 683b ldr r3, [r7, #0]
8004a7c: 6b9b ldr r3, [r3, #56] @ 0x38
8004a7e: 693a ldr r2, [r7, #16]
8004a80: 4313 orrs r3, r2
8004a82: 613b str r3, [r7, #16]
mask = (FMC_BCR1_MBKEN |
8004a84: 4b20 ldr r3, [pc, #128] @ (8004b08 <FMC_NORSRAM_Init+0x11c>)
8004a86: 60fb str r3, [r7, #12]
FMC_BCR1_WAITEN |
FMC_BCR1_EXTMOD |
FMC_BCR1_ASYNCWAIT |
FMC_BCR1_CBURSTRW);
mask |= FMC_BCR1_CCLKEN;
8004a88: 68fb ldr r3, [r7, #12]
8004a8a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8004a8e: 60fb str r3, [r7, #12]
mask |= FMC_BCR1_WFDIS;
8004a90: 68fb ldr r3, [r7, #12]
8004a92: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
8004a96: 60fb str r3, [r7, #12]
mask |= FMC_BCR1_CPSIZE;
8004a98: 68fb ldr r3, [r7, #12]
8004a9a: f443 23e0 orr.w r3, r3, #458752 @ 0x70000
8004a9e: 60fb str r3, [r7, #12]
MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
8004aa0: 683b ldr r3, [r7, #0]
8004aa2: 681a ldr r2, [r3, #0]
8004aa4: 687b ldr r3, [r7, #4]
8004aa6: f853 2022 ldr.w r2, [r3, r2, lsl #2]
8004aaa: 68fb ldr r3, [r7, #12]
8004aac: 43db mvns r3, r3
8004aae: ea02 0103 and.w r1, r2, r3
8004ab2: 683b ldr r3, [r7, #0]
8004ab4: 681a ldr r2, [r3, #0]
8004ab6: 693b ldr r3, [r7, #16]
8004ab8: 4319 orrs r1, r3
8004aba: 687b ldr r3, [r7, #4]
8004abc: f843 1022 str.w r1, [r3, r2, lsl #2]
/* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
8004ac0: 683b ldr r3, [r7, #0]
8004ac2: 6b1b ldr r3, [r3, #48] @ 0x30
8004ac4: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8004ac8: d10c bne.n 8004ae4 <FMC_NORSRAM_Init+0xf8>
8004aca: 683b ldr r3, [r7, #0]
8004acc: 681b ldr r3, [r3, #0]
8004ace: 2b00 cmp r3, #0
8004ad0: d008 beq.n 8004ae4 <FMC_NORSRAM_Init+0xf8>
{
MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
8004ad2: 687b ldr r3, [r7, #4]
8004ad4: 681b ldr r3, [r3, #0]
8004ad6: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
8004ada: 683b ldr r3, [r7, #0]
8004adc: 6b1b ldr r3, [r3, #48] @ 0x30
8004ade: 431a orrs r2, r3
8004ae0: 687b ldr r3, [r7, #4]
8004ae2: 601a str r2, [r3, #0]
}
if (Init->NSBank != FMC_NORSRAM_BANK1)
8004ae4: 683b ldr r3, [r7, #0]
8004ae6: 681b ldr r3, [r3, #0]
8004ae8: 2b00 cmp r3, #0
8004aea: d006 beq.n 8004afa <FMC_NORSRAM_Init+0x10e>
{
/* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
8004aec: 687b ldr r3, [r7, #4]
8004aee: 681a ldr r2, [r3, #0]
8004af0: 683b ldr r3, [r7, #0]
8004af2: 6b5b ldr r3, [r3, #52] @ 0x34
8004af4: 431a orrs r2, r3
8004af6: 687b ldr r3, [r7, #4]
8004af8: 601a str r2, [r3, #0]
}
return HAL_OK;
8004afa: 2300 movs r3, #0
}
8004afc: 4618 mov r0, r3
8004afe: 371c adds r7, #28
8004b00: 46bd mov sp, r7
8004b02: f85d 7b04 ldr.w r7, [sp], #4
8004b06: 4770 bx lr
8004b08: 0008fb7f .word 0x0008fb7f
08004b0c <FMC_NORSRAM_Timing_Init>:
* @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
{
8004b0c: b480 push {r7}
8004b0e: b087 sub sp, #28
8004b10: af00 add r7, sp, #0
8004b12: 60f8 str r0, [r7, #12]
8004b14: 60b9 str r1, [r7, #8]
8004b16: 607a str r2, [r7, #4]
assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
/* Set FMC_NORSRAM device timing parameters */
Device->BTCR[Bank + 1U] =
(Timing->AddressSetupTime << FMC_BTR1_ADDSET_Pos) |
8004b18: 68bb ldr r3, [r7, #8]
8004b1a: 681a ldr r2, [r3, #0]
(Timing->AddressHoldTime << FMC_BTR1_ADDHLD_Pos) |
8004b1c: 68bb ldr r3, [r7, #8]
8004b1e: 685b ldr r3, [r3, #4]
8004b20: 011b lsls r3, r3, #4
(Timing->AddressSetupTime << FMC_BTR1_ADDSET_Pos) |
8004b22: 431a orrs r2, r3
(Timing->DataSetupTime << FMC_BTR1_DATAST_Pos) |
8004b24: 68bb ldr r3, [r7, #8]
8004b26: 689b ldr r3, [r3, #8]
8004b28: 021b lsls r3, r3, #8
(Timing->AddressHoldTime << FMC_BTR1_ADDHLD_Pos) |
8004b2a: 431a orrs r2, r3
(Timing->BusTurnAroundDuration << FMC_BTR1_BUSTURN_Pos) |
8004b2c: 68bb ldr r3, [r7, #8]
8004b2e: 68db ldr r3, [r3, #12]
8004b30: 041b lsls r3, r3, #16
(Timing->DataSetupTime << FMC_BTR1_DATAST_Pos) |
8004b32: 431a orrs r2, r3
((Timing->CLKDivision - 1U) << FMC_BTR1_CLKDIV_Pos) |
8004b34: 68bb ldr r3, [r7, #8]
8004b36: 691b ldr r3, [r3, #16]
8004b38: 3b01 subs r3, #1
8004b3a: 051b lsls r3, r3, #20
(Timing->BusTurnAroundDuration << FMC_BTR1_BUSTURN_Pos) |
8004b3c: 431a orrs r2, r3
((Timing->DataLatency - 2U) << FMC_BTR1_DATLAT_Pos) |
8004b3e: 68bb ldr r3, [r7, #8]
8004b40: 695b ldr r3, [r3, #20]
8004b42: 3b02 subs r3, #2
8004b44: 061b lsls r3, r3, #24
((Timing->CLKDivision - 1U) << FMC_BTR1_CLKDIV_Pos) |
8004b46: ea42 0103 orr.w r1, r2, r3
Timing->AccessMode;
8004b4a: 68bb ldr r3, [r7, #8]
8004b4c: 699b ldr r3, [r3, #24]
Device->BTCR[Bank + 1U] =
8004b4e: 687a ldr r2, [r7, #4]
8004b50: 3201 adds r2, #1
((Timing->DataLatency - 2U) << FMC_BTR1_DATLAT_Pos) |
8004b52: 4319 orrs r1, r3
Device->BTCR[Bank + 1U] =
8004b54: 68fb ldr r3, [r7, #12]
8004b56: f843 1022 str.w r1, [r3, r2, lsl #2]
/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
8004b5a: 68fb ldr r3, [r7, #12]
8004b5c: 681b ldr r3, [r3, #0]
8004b5e: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8004b62: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8004b66: d113 bne.n 8004b90 <FMC_NORSRAM_Timing_Init+0x84>
{
tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos));
8004b68: 68fb ldr r3, [r7, #12]
8004b6a: 685b ldr r3, [r3, #4]
8004b6c: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
8004b70: 617b str r3, [r7, #20]
tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos);
8004b72: 68bb ldr r3, [r7, #8]
8004b74: 691b ldr r3, [r3, #16]
8004b76: 3b01 subs r3, #1
8004b78: 051b lsls r3, r3, #20
8004b7a: 697a ldr r2, [r7, #20]
8004b7c: 4313 orrs r3, r2
8004b7e: 617b str r3, [r7, #20]
MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr);
8004b80: 68fb ldr r3, [r7, #12]
8004b82: 685b ldr r3, [r3, #4]
8004b84: f423 0270 bic.w r2, r3, #15728640 @ 0xf00000
8004b88: 697b ldr r3, [r7, #20]
8004b8a: 431a orrs r2, r3
8004b8c: 68fb ldr r3, [r7, #12]
8004b8e: 605a str r2, [r3, #4]
}
return HAL_OK;
8004b90: 2300 movs r3, #0
}
8004b92: 4618 mov r0, r3
8004b94: 371c adds r7, #28
8004b96: 46bd mov sp, r7
8004b98: f85d 7b04 ldr.w r7, [sp], #4
8004b9c: 4770 bx lr
...
08004ba0 <FMC_NORSRAM_Extended_Timing_Init>:
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
uint32_t ExtendedMode)
{
8004ba0: b480 push {r7}
8004ba2: b085 sub sp, #20
8004ba4: af00 add r7, sp, #0
8004ba6: 60f8 str r0, [r7, #12]
8004ba8: 60b9 str r1, [r7, #8]
8004baa: 607a str r2, [r7, #4]
8004bac: 603b str r3, [r7, #0]
/* Check the parameters */
assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
8004bae: 683b ldr r3, [r7, #0]
8004bb0: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
8004bb4: d11d bne.n 8004bf2 <FMC_NORSRAM_Extended_Timing_Init+0x52>
assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
8004bb6: 68fb ldr r3, [r7, #12]
8004bb8: 687a ldr r2, [r7, #4]
8004bba: f853 2022 ldr.w r2, [r3, r2, lsl #2]
8004bbe: 4b13 ldr r3, [pc, #76] @ (8004c0c <FMC_NORSRAM_Extended_Timing_Init+0x6c>)
8004bc0: 4013 ands r3, r2
8004bc2: 68ba ldr r2, [r7, #8]
8004bc4: 6811 ldr r1, [r2, #0]
8004bc6: 68ba ldr r2, [r7, #8]
8004bc8: 6852 ldr r2, [r2, #4]
8004bca: 0112 lsls r2, r2, #4
8004bcc: 4311 orrs r1, r2
8004bce: 68ba ldr r2, [r7, #8]
8004bd0: 6892 ldr r2, [r2, #8]
8004bd2: 0212 lsls r2, r2, #8
8004bd4: 4311 orrs r1, r2
8004bd6: 68ba ldr r2, [r7, #8]
8004bd8: 6992 ldr r2, [r2, #24]
8004bda: 4311 orrs r1, r2
8004bdc: 68ba ldr r2, [r7, #8]
8004bde: 68d2 ldr r2, [r2, #12]
8004be0: 0412 lsls r2, r2, #16
8004be2: 430a orrs r2, r1
8004be4: ea43 0102 orr.w r1, r3, r2
8004be8: 68fb ldr r3, [r7, #12]
8004bea: 687a ldr r2, [r7, #4]
8004bec: f843 1022 str.w r1, [r3, r2, lsl #2]
8004bf0: e005 b.n 8004bfe <FMC_NORSRAM_Extended_Timing_Init+0x5e>
Timing->AccessMode |
((Timing->BusTurnAroundDuration) << FMC_BWTR1_BUSTURN_Pos)));
}
else
{
Device->BWTR[Bank] = 0x0FFFFFFFU;
8004bf2: 68fb ldr r3, [r7, #12]
8004bf4: 687a ldr r2, [r7, #4]
8004bf6: f06f 4170 mvn.w r1, #4026531840 @ 0xf0000000
8004bfa: f843 1022 str.w r1, [r3, r2, lsl #2]
}
return HAL_OK;
8004bfe: 2300 movs r3, #0
}
8004c00: 4618 mov r0, r3
8004c02: 3714 adds r7, #20
8004c04: 46bd mov sp, r7
8004c06: f85d 7b04 ldr.w r7, [sp], #4
8004c0a: 4770 bx lr
8004c0c: cff00000 .word 0xcff00000
08004c10 <makeFreeRtosPriority>:
extern void xPortSysTickHandler(void);
/* Convert from CMSIS type osPriority to FreeRTOS priority number */
static unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority)
{
8004c10: b480 push {r7}
8004c12: b085 sub sp, #20
8004c14: af00 add r7, sp, #0
8004c16: 4603 mov r3, r0
8004c18: 80fb strh r3, [r7, #6]
unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY;
8004c1a: 2300 movs r3, #0
8004c1c: 60fb str r3, [r7, #12]
if (priority != osPriorityError) {
8004c1e: f9b7 3006 ldrsh.w r3, [r7, #6]
8004c22: 2b84 cmp r3, #132 @ 0x84
8004c24: d005 beq.n 8004c32 <makeFreeRtosPriority+0x22>
fpriority += (priority - osPriorityIdle);
8004c26: f9b7 2006 ldrsh.w r2, [r7, #6]
8004c2a: 68fb ldr r3, [r7, #12]
8004c2c: 4413 add r3, r2
8004c2e: 3303 adds r3, #3
8004c30: 60fb str r3, [r7, #12]
}
return fpriority;
8004c32: 68fb ldr r3, [r7, #12]
}
8004c34: 4618 mov r0, r3
8004c36: 3714 adds r7, #20
8004c38: 46bd mov sp, r7
8004c3a: f85d 7b04 ldr.w r7, [sp], #4
8004c3e: 4770 bx lr
08004c40 <osKernelStart>:
* @param argument pointer that is passed to the thread function as start argument.
* @retval status code that indicates the execution status of the function
* @note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
*/
osStatus osKernelStart (void)
{
8004c40: b580 push {r7, lr}
8004c42: af00 add r7, sp, #0
vTaskStartScheduler();
8004c44: f001 f8b6 bl 8005db4 <vTaskStartScheduler>
return osOK;
8004c48: 2300 movs r3, #0
}
8004c4a: 4618 mov r0, r3
8004c4c: bd80 pop {r7, pc}
08004c4e <osThreadCreate>:
* @param argument pointer that is passed to the thread function as start argument.
* @retval thread ID for reference by other functions or NULL in case of error.
* @note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
*/
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument)
{
8004c4e: b5f0 push {r4, r5, r6, r7, lr}
8004c50: b089 sub sp, #36 @ 0x24
8004c52: af04 add r7, sp, #16
8004c54: 6078 str r0, [r7, #4]
8004c56: 6039 str r1, [r7, #0]
TaskHandle_t handle;
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
if((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) {
8004c58: 687b ldr r3, [r7, #4]
8004c5a: 695b ldr r3, [r3, #20]
8004c5c: 2b00 cmp r3, #0
8004c5e: d020 beq.n 8004ca2 <osThreadCreate+0x54>
8004c60: 687b ldr r3, [r7, #4]
8004c62: 699b ldr r3, [r3, #24]
8004c64: 2b00 cmp r3, #0
8004c66: d01c beq.n 8004ca2 <osThreadCreate+0x54>
handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
8004c68: 687b ldr r3, [r7, #4]
8004c6a: 685c ldr r4, [r3, #4]
8004c6c: 687b ldr r3, [r7, #4]
8004c6e: 681d ldr r5, [r3, #0]
thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
8004c70: 687b ldr r3, [r7, #4]
8004c72: 691e ldr r6, [r3, #16]
8004c74: 687b ldr r3, [r7, #4]
8004c76: f9b3 3008 ldrsh.w r3, [r3, #8]
handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
8004c7a: 4618 mov r0, r3
8004c7c: f7ff ffc8 bl 8004c10 <makeFreeRtosPriority>
8004c80: 4601 mov r1, r0
thread_def->buffer, thread_def->controlblock);
8004c82: 687b ldr r3, [r7, #4]
8004c84: 695b ldr r3, [r3, #20]
8004c86: 687a ldr r2, [r7, #4]
8004c88: 6992 ldr r2, [r2, #24]
handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
8004c8a: 9202 str r2, [sp, #8]
8004c8c: 9301 str r3, [sp, #4]
8004c8e: 9100 str r1, [sp, #0]
8004c90: 683b ldr r3, [r7, #0]
8004c92: 4632 mov r2, r6
8004c94: 4629 mov r1, r5
8004c96: 4620 mov r0, r4
8004c98: f000 fe24 bl 80058e4 <xTaskCreateStatic>
8004c9c: 4603 mov r3, r0
8004c9e: 60fb str r3, [r7, #12]
8004ca0: e01c b.n 8004cdc <osThreadCreate+0x8e>
}
else {
if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
8004ca2: 687b ldr r3, [r7, #4]
8004ca4: 685c ldr r4, [r3, #4]
8004ca6: 687b ldr r3, [r7, #4]
8004ca8: 681d ldr r5, [r3, #0]
thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
8004caa: 687b ldr r3, [r7, #4]
8004cac: 691b ldr r3, [r3, #16]
if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
8004cae: b29e uxth r6, r3
thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
8004cb0: 687b ldr r3, [r7, #4]
8004cb2: f9b3 3008 ldrsh.w r3, [r3, #8]
if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
8004cb6: 4618 mov r0, r3
8004cb8: f7ff ffaa bl 8004c10 <makeFreeRtosPriority>
8004cbc: 4602 mov r2, r0
8004cbe: f107 030c add.w r3, r7, #12
8004cc2: 9301 str r3, [sp, #4]
8004cc4: 9200 str r2, [sp, #0]
8004cc6: 683b ldr r3, [r7, #0]
8004cc8: 4632 mov r2, r6
8004cca: 4629 mov r1, r5
8004ccc: 4620 mov r0, r4
8004cce: f000 fe6f bl 80059b0 <xTaskCreate>
8004cd2: 4603 mov r3, r0
8004cd4: 2b01 cmp r3, #1
8004cd6: d001 beq.n 8004cdc <osThreadCreate+0x8e>
&handle) != pdPASS) {
return NULL;
8004cd8: 2300 movs r3, #0
8004cda: e000 b.n 8004cde <osThreadCreate+0x90>
&handle) != pdPASS) {
return NULL;
}
#endif
return handle;
8004cdc: 68fb ldr r3, [r7, #12]
}
8004cde: 4618 mov r0, r3
8004ce0: 3714 adds r7, #20
8004ce2: 46bd mov sp, r7
8004ce4: bdf0 pop {r4, r5, r6, r7, pc}
08004ce6 <osDelay>:
* @brief Wait for Timeout (Time Delay)
* @param millisec time delay value
* @retval status code that indicates the execution status of the function.
*/
osStatus osDelay (uint32_t millisec)
{
8004ce6: b580 push {r7, lr}
8004ce8: b084 sub sp, #16
8004cea: af00 add r7, sp, #0
8004cec: 6078 str r0, [r7, #4]
#if INCLUDE_vTaskDelay
TickType_t ticks = millisec / portTICK_PERIOD_MS;
8004cee: 687b ldr r3, [r7, #4]
8004cf0: 60fb str r3, [r7, #12]
vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */
8004cf2: 68fb ldr r3, [r7, #12]
8004cf4: 2b00 cmp r3, #0
8004cf6: d001 beq.n 8004cfc <osDelay+0x16>
8004cf8: 68fb ldr r3, [r7, #12]
8004cfa: e000 b.n 8004cfe <osDelay+0x18>
8004cfc: 2301 movs r3, #1
8004cfe: 4618 mov r0, r3
8004d00: f000 ffb6 bl 8005c70 <vTaskDelay>
return osOK;
8004d04: 2300 movs r3, #0
#else
(void) millisec;
return osErrorResource;
#endif
}
8004d06: 4618 mov r0, r3
8004d08: 3710 adds r7, #16
8004d0a: 46bd mov sp, r7
8004d0c: bd80 pop {r7, pc}
08004d0e <vListInitialise>:
/*-----------------------------------------------------------
* PUBLIC LIST API documented in list.h
*----------------------------------------------------------*/
void vListInitialise( List_t * const pxList )
{
8004d0e: b480 push {r7}
8004d10: b083 sub sp, #12
8004d12: af00 add r7, sp, #0
8004d14: 6078 str r0, [r7, #4]
/* The list structure contains a list item which is used to mark the
end of the list. To initialise the list the list end is inserted
as the only list entry. */
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
8004d16: 687b ldr r3, [r7, #4]
8004d18: f103 0208 add.w r2, r3, #8
8004d1c: 687b ldr r3, [r7, #4]
8004d1e: 605a str r2, [r3, #4]
/* The list end value is the highest possible value in the list to
ensure it remains at the end of the list. */
pxList->xListEnd.xItemValue = portMAX_DELAY;
8004d20: 687b ldr r3, [r7, #4]
8004d22: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8004d26: 609a str r2, [r3, #8]
/* The list end next and previous pointers point to itself so we know
when the list is empty. */
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
8004d28: 687b ldr r3, [r7, #4]
8004d2a: f103 0208 add.w r2, r3, #8
8004d2e: 687b ldr r3, [r7, #4]
8004d30: 60da str r2, [r3, #12]
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
8004d32: 687b ldr r3, [r7, #4]
8004d34: f103 0208 add.w r2, r3, #8
8004d38: 687b ldr r3, [r7, #4]
8004d3a: 611a str r2, [r3, #16]
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
8004d3c: 687b ldr r3, [r7, #4]
8004d3e: 2200 movs r2, #0
8004d40: 601a str r2, [r3, #0]
/* Write known values into the list if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
}
8004d42: bf00 nop
8004d44: 370c adds r7, #12
8004d46: 46bd mov sp, r7
8004d48: f85d 7b04 ldr.w r7, [sp], #4
8004d4c: 4770 bx lr
08004d4e <vListInitialiseItem>:
/*-----------------------------------------------------------*/
void vListInitialiseItem( ListItem_t * const pxItem )
{
8004d4e: b480 push {r7}
8004d50: b083 sub sp, #12
8004d52: af00 add r7, sp, #0
8004d54: 6078 str r0, [r7, #4]
/* Make sure the list item is not recorded as being on a list. */
pxItem->pxContainer = NULL;
8004d56: 687b ldr r3, [r7, #4]
8004d58: 2200 movs r2, #0
8004d5a: 611a str r2, [r3, #16]
/* Write known values into the list item if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
}
8004d5c: bf00 nop
8004d5e: 370c adds r7, #12
8004d60: 46bd mov sp, r7
8004d62: f85d 7b04 ldr.w r7, [sp], #4
8004d66: 4770 bx lr
08004d68 <vListInsertEnd>:
/*-----------------------------------------------------------*/
void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
{
8004d68: b480 push {r7}
8004d6a: b085 sub sp, #20
8004d6c: af00 add r7, sp, #0
8004d6e: 6078 str r0, [r7, #4]
8004d70: 6039 str r1, [r7, #0]
ListItem_t * const pxIndex = pxList->pxIndex;
8004d72: 687b ldr r3, [r7, #4]
8004d74: 685b ldr r3, [r3, #4]
8004d76: 60fb str r3, [r7, #12]
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
/* Insert a new list item into pxList, but rather than sort the list,
makes the new list item the last item to be removed by a call to
listGET_OWNER_OF_NEXT_ENTRY(). */
pxNewListItem->pxNext = pxIndex;
8004d78: 683b ldr r3, [r7, #0]
8004d7a: 68fa ldr r2, [r7, #12]
8004d7c: 605a str r2, [r3, #4]
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
8004d7e: 68fb ldr r3, [r7, #12]
8004d80: 689a ldr r2, [r3, #8]
8004d82: 683b ldr r3, [r7, #0]
8004d84: 609a str r2, [r3, #8]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
pxIndex->pxPrevious->pxNext = pxNewListItem;
8004d86: 68fb ldr r3, [r7, #12]
8004d88: 689b ldr r3, [r3, #8]
8004d8a: 683a ldr r2, [r7, #0]
8004d8c: 605a str r2, [r3, #4]
pxIndex->pxPrevious = pxNewListItem;
8004d8e: 68fb ldr r3, [r7, #12]
8004d90: 683a ldr r2, [r7, #0]
8004d92: 609a str r2, [r3, #8]
/* Remember which list the item is in. */
pxNewListItem->pxContainer = pxList;
8004d94: 683b ldr r3, [r7, #0]
8004d96: 687a ldr r2, [r7, #4]
8004d98: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
8004d9a: 687b ldr r3, [r7, #4]
8004d9c: 681b ldr r3, [r3, #0]
8004d9e: 1c5a adds r2, r3, #1
8004da0: 687b ldr r3, [r7, #4]
8004da2: 601a str r2, [r3, #0]
}
8004da4: bf00 nop
8004da6: 3714 adds r7, #20
8004da8: 46bd mov sp, r7
8004daa: f85d 7b04 ldr.w r7, [sp], #4
8004dae: 4770 bx lr
08004db0 <vListInsert>:
/*-----------------------------------------------------------*/
void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
{
8004db0: b480 push {r7}
8004db2: b085 sub sp, #20
8004db4: af00 add r7, sp, #0
8004db6: 6078 str r0, [r7, #4]
8004db8: 6039 str r1, [r7, #0]
ListItem_t *pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
8004dba: 683b ldr r3, [r7, #0]
8004dbc: 681b ldr r3, [r3, #0]
8004dbe: 60bb str r3, [r7, #8]
new list item should be placed after it. This ensures that TCBs which are
stored in ready lists (all of which have the same xItemValue value) get a
share of the CPU. However, if the xItemValue is the same as the back marker
the iteration loop below will not end. Therefore the value is checked
first, and the algorithm slightly modified if necessary. */
if( xValueOfInsertion == portMAX_DELAY )
8004dc0: 68bb ldr r3, [r7, #8]
8004dc2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8004dc6: d103 bne.n 8004dd0 <vListInsert+0x20>
{
pxIterator = pxList->xListEnd.pxPrevious;
8004dc8: 687b ldr r3, [r7, #4]
8004dca: 691b ldr r3, [r3, #16]
8004dcc: 60fb str r3, [r7, #12]
8004dce: e00c b.n 8004dea <vListInsert+0x3a>
4) Using a queue or semaphore before it has been initialised or
before the scheduler has been started (are interrupts firing
before vTaskStartScheduler() has been called?).
**********************************************************************/
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
8004dd0: 687b ldr r3, [r7, #4]
8004dd2: 3308 adds r3, #8
8004dd4: 60fb str r3, [r7, #12]
8004dd6: e002 b.n 8004dde <vListInsert+0x2e>
8004dd8: 68fb ldr r3, [r7, #12]
8004dda: 685b ldr r3, [r3, #4]
8004ddc: 60fb str r3, [r7, #12]
8004dde: 68fb ldr r3, [r7, #12]
8004de0: 685b ldr r3, [r3, #4]
8004de2: 681b ldr r3, [r3, #0]
8004de4: 68ba ldr r2, [r7, #8]
8004de6: 429a cmp r2, r3
8004de8: d2f6 bcs.n 8004dd8 <vListInsert+0x28>
/* There is nothing to do here, just iterating to the wanted
insertion position. */
}
}
pxNewListItem->pxNext = pxIterator->pxNext;
8004dea: 68fb ldr r3, [r7, #12]
8004dec: 685a ldr r2, [r3, #4]
8004dee: 683b ldr r3, [r7, #0]
8004df0: 605a str r2, [r3, #4]
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
8004df2: 683b ldr r3, [r7, #0]
8004df4: 685b ldr r3, [r3, #4]
8004df6: 683a ldr r2, [r7, #0]
8004df8: 609a str r2, [r3, #8]
pxNewListItem->pxPrevious = pxIterator;
8004dfa: 683b ldr r3, [r7, #0]
8004dfc: 68fa ldr r2, [r7, #12]
8004dfe: 609a str r2, [r3, #8]
pxIterator->pxNext = pxNewListItem;
8004e00: 68fb ldr r3, [r7, #12]
8004e02: 683a ldr r2, [r7, #0]
8004e04: 605a str r2, [r3, #4]
/* Remember which list the item is in. This allows fast removal of the
item later. */
pxNewListItem->pxContainer = pxList;
8004e06: 683b ldr r3, [r7, #0]
8004e08: 687a ldr r2, [r7, #4]
8004e0a: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
8004e0c: 687b ldr r3, [r7, #4]
8004e0e: 681b ldr r3, [r3, #0]
8004e10: 1c5a adds r2, r3, #1
8004e12: 687b ldr r3, [r7, #4]
8004e14: 601a str r2, [r3, #0]
}
8004e16: bf00 nop
8004e18: 3714 adds r7, #20
8004e1a: 46bd mov sp, r7
8004e1c: f85d 7b04 ldr.w r7, [sp], #4
8004e20: 4770 bx lr
08004e22 <uxListRemove>:
/*-----------------------------------------------------------*/
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
8004e22: b480 push {r7}
8004e24: b085 sub sp, #20
8004e26: af00 add r7, sp, #0
8004e28: 6078 str r0, [r7, #4]
/* The list item knows which list it is in. Obtain the list from the list
item. */
List_t * const pxList = pxItemToRemove->pxContainer;
8004e2a: 687b ldr r3, [r7, #4]
8004e2c: 691b ldr r3, [r3, #16]
8004e2e: 60fb str r3, [r7, #12]
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
8004e30: 687b ldr r3, [r7, #4]
8004e32: 685b ldr r3, [r3, #4]
8004e34: 687a ldr r2, [r7, #4]
8004e36: 6892 ldr r2, [r2, #8]
8004e38: 609a str r2, [r3, #8]
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
8004e3a: 687b ldr r3, [r7, #4]
8004e3c: 689b ldr r3, [r3, #8]
8004e3e: 687a ldr r2, [r7, #4]
8004e40: 6852 ldr r2, [r2, #4]
8004e42: 605a str r2, [r3, #4]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
/* Make sure the index is left pointing to a valid item. */
if( pxList->pxIndex == pxItemToRemove )
8004e44: 68fb ldr r3, [r7, #12]
8004e46: 685b ldr r3, [r3, #4]
8004e48: 687a ldr r2, [r7, #4]
8004e4a: 429a cmp r2, r3
8004e4c: d103 bne.n 8004e56 <uxListRemove+0x34>
{
pxList->pxIndex = pxItemToRemove->pxPrevious;
8004e4e: 687b ldr r3, [r7, #4]
8004e50: 689a ldr r2, [r3, #8]
8004e52: 68fb ldr r3, [r7, #12]
8004e54: 605a str r2, [r3, #4]
else
{
mtCOVERAGE_TEST_MARKER();
}
pxItemToRemove->pxContainer = NULL;
8004e56: 687b ldr r3, [r7, #4]
8004e58: 2200 movs r2, #0
8004e5a: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )--;
8004e5c: 68fb ldr r3, [r7, #12]
8004e5e: 681b ldr r3, [r3, #0]
8004e60: 1e5a subs r2, r3, #1
8004e62: 68fb ldr r3, [r7, #12]
8004e64: 601a str r2, [r3, #0]
return pxList->uxNumberOfItems;
8004e66: 68fb ldr r3, [r7, #12]
8004e68: 681b ldr r3, [r3, #0]
}
8004e6a: 4618 mov r0, r3
8004e6c: 3714 adds r7, #20
8004e6e: 46bd mov sp, r7
8004e70: f85d 7b04 ldr.w r7, [sp], #4
8004e74: 4770 bx lr
...
08004e78 <xQueueGenericReset>:
} \
taskEXIT_CRITICAL()
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
{
8004e78: b580 push {r7, lr}
8004e7a: b084 sub sp, #16
8004e7c: af00 add r7, sp, #0
8004e7e: 6078 str r0, [r7, #4]
8004e80: 6039 str r1, [r7, #0]
Queue_t * const pxQueue = xQueue;
8004e82: 687b ldr r3, [r7, #4]
8004e84: 60fb str r3, [r7, #12]
configASSERT( pxQueue );
8004e86: 68fb ldr r3, [r7, #12]
8004e88: 2b00 cmp r3, #0
8004e8a: d10d bne.n 8004ea8 <xQueueGenericReset+0x30>
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;
__asm volatile
8004e8c: f04f 0350 mov.w r3, #80 @ 0x50
8004e90: b672 cpsid i
8004e92: f383 8811 msr BASEPRI, r3
8004e96: f3bf 8f6f isb sy
8004e9a: f3bf 8f4f dsb sy
8004e9e: b662 cpsie i
8004ea0: 60bb str r3, [r7, #8]
" isb \n" \
" dsb \n" \
" cpsie i \n" \
:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
}
8004ea2: bf00 nop
8004ea4: bf00 nop
8004ea6: e7fd b.n 8004ea4 <xQueueGenericReset+0x2c>
taskENTER_CRITICAL();
8004ea8: f002 f8c0 bl 800702c <vPortEnterCritical>
{
pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
8004eac: 68fb ldr r3, [r7, #12]
8004eae: 681a ldr r2, [r3, #0]
8004eb0: 68fb ldr r3, [r7, #12]
8004eb2: 6bdb ldr r3, [r3, #60] @ 0x3c
8004eb4: 68f9 ldr r1, [r7, #12]
8004eb6: 6c09 ldr r1, [r1, #64] @ 0x40
8004eb8: fb01 f303 mul.w r3, r1, r3
8004ebc: 441a add r2, r3
8004ebe: 68fb ldr r3, [r7, #12]
8004ec0: 609a str r2, [r3, #8]
pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
8004ec2: 68fb ldr r3, [r7, #12]
8004ec4: 2200 movs r2, #0
8004ec6: 639a str r2, [r3, #56] @ 0x38
pxQueue->pcWriteTo = pxQueue->pcHead;
8004ec8: 68fb ldr r3, [r7, #12]
8004eca: 681a ldr r2, [r3, #0]
8004ecc: 68fb ldr r3, [r7, #12]
8004ece: 605a str r2, [r3, #4]
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
8004ed0: 68fb ldr r3, [r7, #12]
8004ed2: 681a ldr r2, [r3, #0]
8004ed4: 68fb ldr r3, [r7, #12]
8004ed6: 6bdb ldr r3, [r3, #60] @ 0x3c
8004ed8: 3b01 subs r3, #1
8004eda: 68f9 ldr r1, [r7, #12]
8004edc: 6c09 ldr r1, [r1, #64] @ 0x40
8004ede: fb01 f303 mul.w r3, r1, r3
8004ee2: 441a add r2, r3
8004ee4: 68fb ldr r3, [r7, #12]
8004ee6: 60da str r2, [r3, #12]
pxQueue->cRxLock = queueUNLOCKED;
8004ee8: 68fb ldr r3, [r7, #12]
8004eea: 22ff movs r2, #255 @ 0xff
8004eec: f883 2044 strb.w r2, [r3, #68] @ 0x44
pxQueue->cTxLock = queueUNLOCKED;
8004ef0: 68fb ldr r3, [r7, #12]
8004ef2: 22ff movs r2, #255 @ 0xff
8004ef4: f883 2045 strb.w r2, [r3, #69] @ 0x45
if( xNewQueue == pdFALSE )
8004ef8: 683b ldr r3, [r7, #0]
8004efa: 2b00 cmp r3, #0
8004efc: d114 bne.n 8004f28 <xQueueGenericReset+0xb0>
/* If there are tasks blocked waiting to read from the queue, then
the tasks will remain blocked as after this function exits the queue
will still be empty. If there are tasks blocked waiting to write to
the queue, then one should be unblocked as after this function exits
it will be possible to write to it. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
8004efe: 68fb ldr r3, [r7, #12]
8004f00: 691b ldr r3, [r3, #16]
8004f02: 2b00 cmp r3, #0
8004f04: d01a beq.n 8004f3c <xQueueGenericReset+0xc4>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
8004f06: 68fb ldr r3, [r7, #12]
8004f08: 3310 adds r3, #16
8004f0a: 4618 mov r0, r3
8004f0c: f001 fa96 bl 800643c <xTaskRemoveFromEventList>
8004f10: 4603 mov r3, r0
8004f12: 2b00 cmp r3, #0
8004f14: d012 beq.n 8004f3c <xQueueGenericReset+0xc4>
{
queueYIELD_IF_USING_PREEMPTION();
8004f16: 4b0d ldr r3, [pc, #52] @ (8004f4c <xQueueGenericReset+0xd4>)
8004f18: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8004f1c: 601a str r2, [r3, #0]
8004f1e: f3bf 8f4f dsb sy
8004f22: f3bf 8f6f isb sy
8004f26: e009 b.n 8004f3c <xQueueGenericReset+0xc4>
}
}
else
{
/* Ensure the event queues start in the correct state. */
vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
8004f28: 68fb ldr r3, [r7, #12]
8004f2a: 3310 adds r3, #16
8004f2c: 4618 mov r0, r3
8004f2e: f7ff feee bl 8004d0e <vListInitialise>
vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
8004f32: 68fb ldr r3, [r7, #12]
8004f34: 3324 adds r3, #36 @ 0x24
8004f36: 4618 mov r0, r3
8004f38: f7ff fee9 bl 8004d0e <vListInitialise>
}
}
taskEXIT_CRITICAL();
8004f3c: f002 f8ac bl 8007098 <vPortExitCritical>
/* A value is returned for calling semantic consistency with previous
versions. */
return pdPASS;
8004f40: 2301 movs r3, #1
}
8004f42: 4618 mov r0, r3
8004f44: 3710 adds r7, #16
8004f46: 46bd mov sp, r7
8004f48: bd80 pop {r7, pc}
8004f4a: bf00 nop
8004f4c: e000ed04 .word 0xe000ed04
08004f50 <xQueueGenericCreate>:
/*-----------------------------------------------------------*/
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
{
8004f50: b580 push {r7, lr}
8004f52: b08a sub sp, #40 @ 0x28
8004f54: af02 add r7, sp, #8
8004f56: 60f8 str r0, [r7, #12]
8004f58: 60b9 str r1, [r7, #8]
8004f5a: 4613 mov r3, r2
8004f5c: 71fb strb r3, [r7, #7]
Queue_t *pxNewQueue;
size_t xQueueSizeInBytes;
uint8_t *pucQueueStorage;
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
8004f5e: 68fb ldr r3, [r7, #12]
8004f60: 2b00 cmp r3, #0
8004f62: d10d bne.n 8004f80 <xQueueGenericCreate+0x30>
__asm volatile
8004f64: f04f 0350 mov.w r3, #80 @ 0x50
8004f68: b672 cpsid i
8004f6a: f383 8811 msr BASEPRI, r3
8004f6e: f3bf 8f6f isb sy
8004f72: f3bf 8f4f dsb sy
8004f76: b662 cpsie i
8004f78: 613b str r3, [r7, #16]
}
8004f7a: bf00 nop
8004f7c: bf00 nop
8004f7e: e7fd b.n 8004f7c <xQueueGenericCreate+0x2c>
if( uxItemSize == ( UBaseType_t ) 0 )
8004f80: 68bb ldr r3, [r7, #8]
8004f82: 2b00 cmp r3, #0
8004f84: d102 bne.n 8004f8c <xQueueGenericCreate+0x3c>
{
/* There is not going to be a queue storage area. */
xQueueSizeInBytes = ( size_t ) 0;
8004f86: 2300 movs r3, #0
8004f88: 61fb str r3, [r7, #28]
8004f8a: e004 b.n 8004f96 <xQueueGenericCreate+0x46>
}
else
{
/* Allocate enough space to hold the maximum number of items that
can be in the queue at any time. */
xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8004f8c: 68fb ldr r3, [r7, #12]
8004f8e: 68ba ldr r2, [r7, #8]
8004f90: fb02 f303 mul.w r3, r2, r3
8004f94: 61fb str r3, [r7, #28]
alignment requirements of the Queue_t structure - which in this case
is an int8_t *. Therefore, whenever the stack alignment requirements
are greater than or equal to the pointer to char requirements the cast
is safe. In other cases alignment requirements are not strict (one or
two bytes). */
pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
8004f96: 69fb ldr r3, [r7, #28]
8004f98: 3350 adds r3, #80 @ 0x50
8004f9a: 4618 mov r0, r3
8004f9c: f002 f92e bl 80071fc <pvPortMalloc>
8004fa0: 61b8 str r0, [r7, #24]
if( pxNewQueue != NULL )
8004fa2: 69bb ldr r3, [r7, #24]
8004fa4: 2b00 cmp r3, #0
8004fa6: d011 beq.n 8004fcc <xQueueGenericCreate+0x7c>
{
/* Jump past the queue structure to find the location of the queue
storage area. */
pucQueueStorage = ( uint8_t * ) pxNewQueue;
8004fa8: 69bb ldr r3, [r7, #24]
8004faa: 617b str r3, [r7, #20]
pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
8004fac: 697b ldr r3, [r7, #20]
8004fae: 3350 adds r3, #80 @ 0x50
8004fb0: 617b str r3, [r7, #20]
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
{
/* Queues can be created either statically or dynamically, so
note this task was created dynamically in case it is later
deleted. */
pxNewQueue->ucStaticallyAllocated = pdFALSE;
8004fb2: 69bb ldr r3, [r7, #24]
8004fb4: 2200 movs r2, #0
8004fb6: f883 2046 strb.w r2, [r3, #70] @ 0x46
}
#endif /* configSUPPORT_STATIC_ALLOCATION */
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
8004fba: 79fa ldrb r2, [r7, #7]
8004fbc: 69bb ldr r3, [r7, #24]
8004fbe: 9300 str r3, [sp, #0]
8004fc0: 4613 mov r3, r2
8004fc2: 697a ldr r2, [r7, #20]
8004fc4: 68b9 ldr r1, [r7, #8]
8004fc6: 68f8 ldr r0, [r7, #12]
8004fc8: f000 f805 bl 8004fd6 <prvInitialiseNewQueue>
{
traceQUEUE_CREATE_FAILED( ucQueueType );
mtCOVERAGE_TEST_MARKER();
}
return pxNewQueue;
8004fcc: 69bb ldr r3, [r7, #24]
}
8004fce: 4618 mov r0, r3
8004fd0: 3720 adds r7, #32
8004fd2: 46bd mov sp, r7
8004fd4: bd80 pop {r7, pc}
08004fd6 <prvInitialiseNewQueue>:
#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
{
8004fd6: b580 push {r7, lr}
8004fd8: b084 sub sp, #16
8004fda: af00 add r7, sp, #0
8004fdc: 60f8 str r0, [r7, #12]
8004fde: 60b9 str r1, [r7, #8]
8004fe0: 607a str r2, [r7, #4]
8004fe2: 70fb strb r3, [r7, #3]
/* Remove compiler warnings about unused parameters should
configUSE_TRACE_FACILITY not be set to 1. */
( void ) ucQueueType;
if( uxItemSize == ( UBaseType_t ) 0 )
8004fe4: 68bb ldr r3, [r7, #8]
8004fe6: 2b00 cmp r3, #0
8004fe8: d103 bne.n 8004ff2 <prvInitialiseNewQueue+0x1c>
{
/* No RAM was allocated for the queue storage area, but PC head cannot
be set to NULL because NULL is used as a key to say the queue is used as
a mutex. Therefore just set pcHead to point to the queue as a benign
value that is known to be within the memory map. */
pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
8004fea: 69bb ldr r3, [r7, #24]
8004fec: 69ba ldr r2, [r7, #24]
8004fee: 601a str r2, [r3, #0]
8004ff0: e002 b.n 8004ff8 <prvInitialiseNewQueue+0x22>
}
else
{
/* Set the head to the start of the queue storage area. */
pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
8004ff2: 69bb ldr r3, [r7, #24]
8004ff4: 687a ldr r2, [r7, #4]
8004ff6: 601a str r2, [r3, #0]
}
/* Initialise the queue members as described where the queue type is
defined. */
pxNewQueue->uxLength = uxQueueLength;
8004ff8: 69bb ldr r3, [r7, #24]
8004ffa: 68fa ldr r2, [r7, #12]
8004ffc: 63da str r2, [r3, #60] @ 0x3c
pxNewQueue->uxItemSize = uxItemSize;
8004ffe: 69bb ldr r3, [r7, #24]
8005000: 68ba ldr r2, [r7, #8]
8005002: 641a str r2, [r3, #64] @ 0x40
( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
8005004: 2101 movs r1, #1
8005006: 69b8 ldr r0, [r7, #24]
8005008: f7ff ff36 bl 8004e78 <xQueueGenericReset>
#if ( configUSE_TRACE_FACILITY == 1 )
{
pxNewQueue->ucQueueType = ucQueueType;
800500c: 69bb ldr r3, [r7, #24]
800500e: 78fa ldrb r2, [r7, #3]
8005010: f883 204c strb.w r2, [r3, #76] @ 0x4c
pxNewQueue->pxQueueSetContainer = NULL;
}
#endif /* configUSE_QUEUE_SETS */
traceQUEUE_CREATE( pxNewQueue );
}
8005014: bf00 nop
8005016: 3710 adds r7, #16
8005018: 46bd mov sp, r7
800501a: bd80 pop {r7, pc}
0800501c <prvInitialiseMutex>:
/*-----------------------------------------------------------*/
#if( configUSE_MUTEXES == 1 )
static void prvInitialiseMutex( Queue_t *pxNewQueue )
{
800501c: b580 push {r7, lr}
800501e: b082 sub sp, #8
8005020: af00 add r7, sp, #0
8005022: 6078 str r0, [r7, #4]
if( pxNewQueue != NULL )
8005024: 687b ldr r3, [r7, #4]
8005026: 2b00 cmp r3, #0
8005028: d00e beq.n 8005048 <prvInitialiseMutex+0x2c>
{
/* The queue create function will set all the queue structure members
correctly for a generic queue, but this function is creating a
mutex. Overwrite those members that need to be set differently -
in particular the information required for priority inheritance. */
pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
800502a: 687b ldr r3, [r7, #4]
800502c: 2200 movs r2, #0
800502e: 609a str r2, [r3, #8]
pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
8005030: 687b ldr r3, [r7, #4]
8005032: 2200 movs r2, #0
8005034: 601a str r2, [r3, #0]
/* In case this is a recursive mutex. */
pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
8005036: 687b ldr r3, [r7, #4]
8005038: 2200 movs r2, #0
800503a: 60da str r2, [r3, #12]
traceCREATE_MUTEX( pxNewQueue );
/* Start with the semaphore in the expected state. */
( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
800503c: 2300 movs r3, #0
800503e: 2200 movs r2, #0
8005040: 2100 movs r1, #0
8005042: 6878 ldr r0, [r7, #4]
8005044: f000 f81c bl 8005080 <xQueueGenericSend>
}
else
{
traceCREATE_MUTEX_FAILED();
}
}
8005048: bf00 nop
800504a: 3708 adds r7, #8
800504c: 46bd mov sp, r7
800504e: bd80 pop {r7, pc}
08005050 <xQueueCreateMutex>:
/*-----------------------------------------------------------*/
#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
{
8005050: b580 push {r7, lr}
8005052: b086 sub sp, #24
8005054: af00 add r7, sp, #0
8005056: 4603 mov r3, r0
8005058: 71fb strb r3, [r7, #7]
QueueHandle_t xNewQueue;
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
800505a: 2301 movs r3, #1
800505c: 617b str r3, [r7, #20]
800505e: 2300 movs r3, #0
8005060: 613b str r3, [r7, #16]
xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
8005062: 79fb ldrb r3, [r7, #7]
8005064: 461a mov r2, r3
8005066: 6939 ldr r1, [r7, #16]
8005068: 6978 ldr r0, [r7, #20]
800506a: f7ff ff71 bl 8004f50 <xQueueGenericCreate>
800506e: 60f8 str r0, [r7, #12]
prvInitialiseMutex( ( Queue_t * ) xNewQueue );
8005070: 68f8 ldr r0, [r7, #12]
8005072: f7ff ffd3 bl 800501c <prvInitialiseMutex>
return xNewQueue;
8005076: 68fb ldr r3, [r7, #12]
}
8005078: 4618 mov r0, r3
800507a: 3718 adds r7, #24
800507c: 46bd mov sp, r7
800507e: bd80 pop {r7, pc}
08005080 <xQueueGenericSend>:
#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
{
8005080: b580 push {r7, lr}
8005082: b08e sub sp, #56 @ 0x38
8005084: af00 add r7, sp, #0
8005086: 60f8 str r0, [r7, #12]
8005088: 60b9 str r1, [r7, #8]
800508a: 607a str r2, [r7, #4]
800508c: 603b str r3, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
800508e: 2300 movs r3, #0
8005090: 637b str r3, [r7, #52] @ 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
8005092: 68fb ldr r3, [r7, #12]
8005094: 633b str r3, [r7, #48] @ 0x30
configASSERT( pxQueue );
8005096: 6b3b ldr r3, [r7, #48] @ 0x30
8005098: 2b00 cmp r3, #0
800509a: d10d bne.n 80050b8 <xQueueGenericSend+0x38>
__asm volatile
800509c: f04f 0350 mov.w r3, #80 @ 0x50
80050a0: b672 cpsid i
80050a2: f383 8811 msr BASEPRI, r3
80050a6: f3bf 8f6f isb sy
80050aa: f3bf 8f4f dsb sy
80050ae: b662 cpsie i
80050b0: 62bb str r3, [r7, #40] @ 0x28
}
80050b2: bf00 nop
80050b4: bf00 nop
80050b6: e7fd b.n 80050b4 <xQueueGenericSend+0x34>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
80050b8: 68bb ldr r3, [r7, #8]
80050ba: 2b00 cmp r3, #0
80050bc: d103 bne.n 80050c6 <xQueueGenericSend+0x46>
80050be: 6b3b ldr r3, [r7, #48] @ 0x30
80050c0: 6c1b ldr r3, [r3, #64] @ 0x40
80050c2: 2b00 cmp r3, #0
80050c4: d101 bne.n 80050ca <xQueueGenericSend+0x4a>
80050c6: 2301 movs r3, #1
80050c8: e000 b.n 80050cc <xQueueGenericSend+0x4c>
80050ca: 2300 movs r3, #0
80050cc: 2b00 cmp r3, #0
80050ce: d10d bne.n 80050ec <xQueueGenericSend+0x6c>
__asm volatile
80050d0: f04f 0350 mov.w r3, #80 @ 0x50
80050d4: b672 cpsid i
80050d6: f383 8811 msr BASEPRI, r3
80050da: f3bf 8f6f isb sy
80050de: f3bf 8f4f dsb sy
80050e2: b662 cpsie i
80050e4: 627b str r3, [r7, #36] @ 0x24
}
80050e6: bf00 nop
80050e8: bf00 nop
80050ea: e7fd b.n 80050e8 <xQueueGenericSend+0x68>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
80050ec: 683b ldr r3, [r7, #0]
80050ee: 2b02 cmp r3, #2
80050f0: d103 bne.n 80050fa <xQueueGenericSend+0x7a>
80050f2: 6b3b ldr r3, [r7, #48] @ 0x30
80050f4: 6bdb ldr r3, [r3, #60] @ 0x3c
80050f6: 2b01 cmp r3, #1
80050f8: d101 bne.n 80050fe <xQueueGenericSend+0x7e>
80050fa: 2301 movs r3, #1
80050fc: e000 b.n 8005100 <xQueueGenericSend+0x80>
80050fe: 2300 movs r3, #0
8005100: 2b00 cmp r3, #0
8005102: d10d bne.n 8005120 <xQueueGenericSend+0xa0>
__asm volatile
8005104: f04f 0350 mov.w r3, #80 @ 0x50
8005108: b672 cpsid i
800510a: f383 8811 msr BASEPRI, r3
800510e: f3bf 8f6f isb sy
8005112: f3bf 8f4f dsb sy
8005116: b662 cpsie i
8005118: 623b str r3, [r7, #32]
}
800511a: bf00 nop
800511c: bf00 nop
800511e: e7fd b.n 800511c <xQueueGenericSend+0x9c>
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
8005120: f001 fc2e bl 8006980 <xTaskGetSchedulerState>
8005124: 4603 mov r3, r0
8005126: 2b00 cmp r3, #0
8005128: d102 bne.n 8005130 <xQueueGenericSend+0xb0>
800512a: 687b ldr r3, [r7, #4]
800512c: 2b00 cmp r3, #0
800512e: d101 bne.n 8005134 <xQueueGenericSend+0xb4>
8005130: 2301 movs r3, #1
8005132: e000 b.n 8005136 <xQueueGenericSend+0xb6>
8005134: 2300 movs r3, #0
8005136: 2b00 cmp r3, #0
8005138: d10d bne.n 8005156 <xQueueGenericSend+0xd6>
__asm volatile
800513a: f04f 0350 mov.w r3, #80 @ 0x50
800513e: b672 cpsid i
8005140: f383 8811 msr BASEPRI, r3
8005144: f3bf 8f6f isb sy
8005148: f3bf 8f4f dsb sy
800514c: b662 cpsie i
800514e: 61fb str r3, [r7, #28]
}
8005150: bf00 nop
8005152: bf00 nop
8005154: e7fd b.n 8005152 <xQueueGenericSend+0xd2>
/*lint -save -e904 This function relaxes the coding standard somewhat to
allow return statements within the function itself. This is done in the
interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
8005156: f001 ff69 bl 800702c <vPortEnterCritical>
{
/* Is there room on the queue now? The running task must be the
highest priority task wanting to access the queue. If the head item
in the queue is to be overwritten then it does not matter if the
queue is full. */
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
800515a: 6b3b ldr r3, [r7, #48] @ 0x30
800515c: 6b9a ldr r2, [r3, #56] @ 0x38
800515e: 6b3b ldr r3, [r7, #48] @ 0x30
8005160: 6bdb ldr r3, [r3, #60] @ 0x3c
8005162: 429a cmp r2, r3
8005164: d302 bcc.n 800516c <xQueueGenericSend+0xec>
8005166: 683b ldr r3, [r7, #0]
8005168: 2b02 cmp r3, #2
800516a: d129 bne.n 80051c0 <xQueueGenericSend+0x140>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
800516c: 683a ldr r2, [r7, #0]
800516e: 68b9 ldr r1, [r7, #8]
8005170: 6b38 ldr r0, [r7, #48] @ 0x30
8005172: f000 faa7 bl 80056c4 <prvCopyDataToQueue>
8005176: 62f8 str r0, [r7, #44] @ 0x2c
/* If there was a task waiting for data to arrive on the
queue then unblock it now. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
8005178: 6b3b ldr r3, [r7, #48] @ 0x30
800517a: 6a5b ldr r3, [r3, #36] @ 0x24
800517c: 2b00 cmp r3, #0
800517e: d010 beq.n 80051a2 <xQueueGenericSend+0x122>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
8005180: 6b3b ldr r3, [r7, #48] @ 0x30
8005182: 3324 adds r3, #36 @ 0x24
8005184: 4618 mov r0, r3
8005186: f001 f959 bl 800643c <xTaskRemoveFromEventList>
800518a: 4603 mov r3, r0
800518c: 2b00 cmp r3, #0
800518e: d013 beq.n 80051b8 <xQueueGenericSend+0x138>
{
/* The unblocked task has a priority higher than
our own so yield immediately. Yes it is ok to do
this from within the critical section - the kernel
takes care of that. */
queueYIELD_IF_USING_PREEMPTION();
8005190: 4b3f ldr r3, [pc, #252] @ (8005290 <xQueueGenericSend+0x210>)
8005192: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8005196: 601a str r2, [r3, #0]
8005198: f3bf 8f4f dsb sy
800519c: f3bf 8f6f isb sy
80051a0: e00a b.n 80051b8 <xQueueGenericSend+0x138>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else if( xYieldRequired != pdFALSE )
80051a2: 6afb ldr r3, [r7, #44] @ 0x2c
80051a4: 2b00 cmp r3, #0
80051a6: d007 beq.n 80051b8 <xQueueGenericSend+0x138>
{
/* This path is a special case that will only get
executed if the task was holding multiple mutexes and
the mutexes were given back in an order that is
different to that in which they were taken. */
queueYIELD_IF_USING_PREEMPTION();
80051a8: 4b39 ldr r3, [pc, #228] @ (8005290 <xQueueGenericSend+0x210>)
80051aa: f04f 5280 mov.w r2, #268435456 @ 0x10000000
80051ae: 601a str r2, [r3, #0]
80051b0: f3bf 8f4f dsb sy
80051b4: f3bf 8f6f isb sy
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_QUEUE_SETS */
taskEXIT_CRITICAL();
80051b8: f001 ff6e bl 8007098 <vPortExitCritical>
return pdPASS;
80051bc: 2301 movs r3, #1
80051be: e063 b.n 8005288 <xQueueGenericSend+0x208>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
80051c0: 687b ldr r3, [r7, #4]
80051c2: 2b00 cmp r3, #0
80051c4: d103 bne.n 80051ce <xQueueGenericSend+0x14e>
{
/* The queue was full and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
80051c6: f001 ff67 bl 8007098 <vPortExitCritical>
/* Return to the original privilege level before exiting
the function. */
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
80051ca: 2300 movs r3, #0
80051cc: e05c b.n 8005288 <xQueueGenericSend+0x208>
}
else if( xEntryTimeSet == pdFALSE )
80051ce: 6b7b ldr r3, [r7, #52] @ 0x34
80051d0: 2b00 cmp r3, #0
80051d2: d106 bne.n 80051e2 <xQueueGenericSend+0x162>
{
/* The queue was full and a block time was specified so
configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
80051d4: f107 0314 add.w r3, r7, #20
80051d8: 4618 mov r0, r3
80051da: f001 f995 bl 8006508 <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
80051de: 2301 movs r3, #1
80051e0: 637b str r3, [r7, #52] @ 0x34
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
80051e2: f001 ff59 bl 8007098 <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
80051e6: f000 fe57 bl 8005e98 <vTaskSuspendAll>
prvLockQueue( pxQueue );
80051ea: f001 ff1f bl 800702c <vPortEnterCritical>
80051ee: 6b3b ldr r3, [r7, #48] @ 0x30
80051f0: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
80051f4: b25b sxtb r3, r3
80051f6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80051fa: d103 bne.n 8005204 <xQueueGenericSend+0x184>
80051fc: 6b3b ldr r3, [r7, #48] @ 0x30
80051fe: 2200 movs r2, #0
8005200: f883 2044 strb.w r2, [r3, #68] @ 0x44
8005204: 6b3b ldr r3, [r7, #48] @ 0x30
8005206: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
800520a: b25b sxtb r3, r3
800520c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8005210: d103 bne.n 800521a <xQueueGenericSend+0x19a>
8005212: 6b3b ldr r3, [r7, #48] @ 0x30
8005214: 2200 movs r2, #0
8005216: f883 2045 strb.w r2, [r3, #69] @ 0x45
800521a: f001 ff3d bl 8007098 <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
800521e: 1d3a adds r2, r7, #4
8005220: f107 0314 add.w r3, r7, #20
8005224: 4611 mov r1, r2
8005226: 4618 mov r0, r3
8005228: f001 f984 bl 8006534 <xTaskCheckForTimeOut>
800522c: 4603 mov r3, r0
800522e: 2b00 cmp r3, #0
8005230: d124 bne.n 800527c <xQueueGenericSend+0x1fc>
{
if( prvIsQueueFull( pxQueue ) != pdFALSE )
8005232: 6b38 ldr r0, [r7, #48] @ 0x30
8005234: f000 fb3e bl 80058b4 <prvIsQueueFull>
8005238: 4603 mov r3, r0
800523a: 2b00 cmp r3, #0
800523c: d018 beq.n 8005270 <xQueueGenericSend+0x1f0>
{
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
800523e: 6b3b ldr r3, [r7, #48] @ 0x30
8005240: 3310 adds r3, #16
8005242: 687a ldr r2, [r7, #4]
8005244: 4611 mov r1, r2
8005246: 4618 mov r0, r3
8005248: f001 f8d0 bl 80063ec <vTaskPlaceOnEventList>
/* Unlocking the queue means queue events can effect the
event list. It is possible that interrupts occurring now
remove this task from the event list again - but as the
scheduler is suspended the task will go onto the pending
ready last instead of the actual ready list. */
prvUnlockQueue( pxQueue );
800524c: 6b38 ldr r0, [r7, #48] @ 0x30
800524e: f000 fac9 bl 80057e4 <prvUnlockQueue>
/* Resuming the scheduler will move tasks from the pending
ready list into the ready list - so it is feasible that this
task is already in a ready list before it yields - in which
case the yield will not cause a context switch unless there
is also a higher priority task in the pending ready list. */
if( xTaskResumeAll() == pdFALSE )
8005252: f000 fe2f bl 8005eb4 <xTaskResumeAll>
8005256: 4603 mov r3, r0
8005258: 2b00 cmp r3, #0
800525a: f47f af7c bne.w 8005156 <xQueueGenericSend+0xd6>
{
portYIELD_WITHIN_API();
800525e: 4b0c ldr r3, [pc, #48] @ (8005290 <xQueueGenericSend+0x210>)
8005260: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8005264: 601a str r2, [r3, #0]
8005266: f3bf 8f4f dsb sy
800526a: f3bf 8f6f isb sy
800526e: e772 b.n 8005156 <xQueueGenericSend+0xd6>
}
}
else
{
/* Try again. */
prvUnlockQueue( pxQueue );
8005270: 6b38 ldr r0, [r7, #48] @ 0x30
8005272: f000 fab7 bl 80057e4 <prvUnlockQueue>
( void ) xTaskResumeAll();
8005276: f000 fe1d bl 8005eb4 <xTaskResumeAll>
800527a: e76c b.n 8005156 <xQueueGenericSend+0xd6>
}
}
else
{
/* The timeout has expired. */
prvUnlockQueue( pxQueue );
800527c: 6b38 ldr r0, [r7, #48] @ 0x30
800527e: f000 fab1 bl 80057e4 <prvUnlockQueue>
( void ) xTaskResumeAll();
8005282: f000 fe17 bl 8005eb4 <xTaskResumeAll>
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
8005286: 2300 movs r3, #0
}
} /*lint -restore */
}
8005288: 4618 mov r0, r3
800528a: 3738 adds r7, #56 @ 0x38
800528c: 46bd mov sp, r7
800528e: bd80 pop {r7, pc}
8005290: e000ed04 .word 0xe000ed04
08005294 <xQueueReceive>:
return xReturn;
}
/*-----------------------------------------------------------*/
BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
{
8005294: b580 push {r7, lr}
8005296: b08c sub sp, #48 @ 0x30
8005298: af00 add r7, sp, #0
800529a: 60f8 str r0, [r7, #12]
800529c: 60b9 str r1, [r7, #8]
800529e: 607a str r2, [r7, #4]
BaseType_t xEntryTimeSet = pdFALSE;
80052a0: 2300 movs r3, #0
80052a2: 62fb str r3, [r7, #44] @ 0x2c
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
80052a4: 68fb ldr r3, [r7, #12]
80052a6: 62bb str r3, [r7, #40] @ 0x28
/* Check the pointer is not NULL. */
configASSERT( ( pxQueue ) );
80052a8: 6abb ldr r3, [r7, #40] @ 0x28
80052aa: 2b00 cmp r3, #0
80052ac: d10d bne.n 80052ca <xQueueReceive+0x36>
__asm volatile
80052ae: f04f 0350 mov.w r3, #80 @ 0x50
80052b2: b672 cpsid i
80052b4: f383 8811 msr BASEPRI, r3
80052b8: f3bf 8f6f isb sy
80052bc: f3bf 8f4f dsb sy
80052c0: b662 cpsie i
80052c2: 623b str r3, [r7, #32]
}
80052c4: bf00 nop
80052c6: bf00 nop
80052c8: e7fd b.n 80052c6 <xQueueReceive+0x32>
/* The buffer into which data is received can only be NULL if the data size
is zero (so no data is copied into the buffer. */
configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
80052ca: 68bb ldr r3, [r7, #8]
80052cc: 2b00 cmp r3, #0
80052ce: d103 bne.n 80052d8 <xQueueReceive+0x44>
80052d0: 6abb ldr r3, [r7, #40] @ 0x28
80052d2: 6c1b ldr r3, [r3, #64] @ 0x40
80052d4: 2b00 cmp r3, #0
80052d6: d101 bne.n 80052dc <xQueueReceive+0x48>
80052d8: 2301 movs r3, #1
80052da: e000 b.n 80052de <xQueueReceive+0x4a>
80052dc: 2300 movs r3, #0
80052de: 2b00 cmp r3, #0
80052e0: d10d bne.n 80052fe <xQueueReceive+0x6a>
__asm volatile
80052e2: f04f 0350 mov.w r3, #80 @ 0x50
80052e6: b672 cpsid i
80052e8: f383 8811 msr BASEPRI, r3
80052ec: f3bf 8f6f isb sy
80052f0: f3bf 8f4f dsb sy
80052f4: b662 cpsie i
80052f6: 61fb str r3, [r7, #28]
}
80052f8: bf00 nop
80052fa: bf00 nop
80052fc: e7fd b.n 80052fa <xQueueReceive+0x66>
/* Cannot block if the scheduler is suspended. */
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
80052fe: f001 fb3f bl 8006980 <xTaskGetSchedulerState>
8005302: 4603 mov r3, r0
8005304: 2b00 cmp r3, #0
8005306: d102 bne.n 800530e <xQueueReceive+0x7a>
8005308: 687b ldr r3, [r7, #4]
800530a: 2b00 cmp r3, #0
800530c: d101 bne.n 8005312 <xQueueReceive+0x7e>
800530e: 2301 movs r3, #1
8005310: e000 b.n 8005314 <xQueueReceive+0x80>
8005312: 2300 movs r3, #0
8005314: 2b00 cmp r3, #0
8005316: d10d bne.n 8005334 <xQueueReceive+0xa0>
__asm volatile
8005318: f04f 0350 mov.w r3, #80 @ 0x50
800531c: b672 cpsid i
800531e: f383 8811 msr BASEPRI, r3
8005322: f3bf 8f6f isb sy
8005326: f3bf 8f4f dsb sy
800532a: b662 cpsie i
800532c: 61bb str r3, [r7, #24]
}
800532e: bf00 nop
8005330: bf00 nop
8005332: e7fd b.n 8005330 <xQueueReceive+0x9c>
/*lint -save -e904 This function relaxes the coding standard somewhat to
allow return statements within the function itself. This is done in the
interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
8005334: f001 fe7a bl 800702c <vPortEnterCritical>
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
8005338: 6abb ldr r3, [r7, #40] @ 0x28
800533a: 6b9b ldr r3, [r3, #56] @ 0x38
800533c: 627b str r3, [r7, #36] @ 0x24
/* Is there data in the queue now? To be running the calling task
must be the highest priority task wanting to access the queue. */
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
800533e: 6a7b ldr r3, [r7, #36] @ 0x24
8005340: 2b00 cmp r3, #0
8005342: d01f beq.n 8005384 <xQueueReceive+0xf0>
{
/* Data available, remove one item. */
prvCopyDataFromQueue( pxQueue, pvBuffer );
8005344: 68b9 ldr r1, [r7, #8]
8005346: 6ab8 ldr r0, [r7, #40] @ 0x28
8005348: f000 fa26 bl 8005798 <prvCopyDataFromQueue>
traceQUEUE_RECEIVE( pxQueue );
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
800534c: 6a7b ldr r3, [r7, #36] @ 0x24
800534e: 1e5a subs r2, r3, #1
8005350: 6abb ldr r3, [r7, #40] @ 0x28
8005352: 639a str r2, [r3, #56] @ 0x38
/* There is now space in the queue, were any tasks waiting to
post to the queue? If so, unblock the highest priority waiting
task. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
8005354: 6abb ldr r3, [r7, #40] @ 0x28
8005356: 691b ldr r3, [r3, #16]
8005358: 2b00 cmp r3, #0
800535a: d00f beq.n 800537c <xQueueReceive+0xe8>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800535c: 6abb ldr r3, [r7, #40] @ 0x28
800535e: 3310 adds r3, #16
8005360: 4618 mov r0, r3
8005362: f001 f86b bl 800643c <xTaskRemoveFromEventList>
8005366: 4603 mov r3, r0
8005368: 2b00 cmp r3, #0
800536a: d007 beq.n 800537c <xQueueReceive+0xe8>
{
queueYIELD_IF_USING_PREEMPTION();
800536c: 4b3c ldr r3, [pc, #240] @ (8005460 <xQueueReceive+0x1cc>)
800536e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8005372: 601a str r2, [r3, #0]
8005374: f3bf 8f4f dsb sy
8005378: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
taskEXIT_CRITICAL();
800537c: f001 fe8c bl 8007098 <vPortExitCritical>
return pdPASS;
8005380: 2301 movs r3, #1
8005382: e069 b.n 8005458 <xQueueReceive+0x1c4>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
8005384: 687b ldr r3, [r7, #4]
8005386: 2b00 cmp r3, #0
8005388: d103 bne.n 8005392 <xQueueReceive+0xfe>
{
/* The queue was empty and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
800538a: f001 fe85 bl 8007098 <vPortExitCritical>
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
800538e: 2300 movs r3, #0
8005390: e062 b.n 8005458 <xQueueReceive+0x1c4>
}
else if( xEntryTimeSet == pdFALSE )
8005392: 6afb ldr r3, [r7, #44] @ 0x2c
8005394: 2b00 cmp r3, #0
8005396: d106 bne.n 80053a6 <xQueueReceive+0x112>
{
/* The queue was empty and a block time was specified so
configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
8005398: f107 0310 add.w r3, r7, #16
800539c: 4618 mov r0, r3
800539e: f001 f8b3 bl 8006508 <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
80053a2: 2301 movs r3, #1
80053a4: 62fb str r3, [r7, #44] @ 0x2c
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
80053a6: f001 fe77 bl 8007098 <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
80053aa: f000 fd75 bl 8005e98 <vTaskSuspendAll>
prvLockQueue( pxQueue );
80053ae: f001 fe3d bl 800702c <vPortEnterCritical>
80053b2: 6abb ldr r3, [r7, #40] @ 0x28
80053b4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
80053b8: b25b sxtb r3, r3
80053ba: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80053be: d103 bne.n 80053c8 <xQueueReceive+0x134>
80053c0: 6abb ldr r3, [r7, #40] @ 0x28
80053c2: 2200 movs r2, #0
80053c4: f883 2044 strb.w r2, [r3, #68] @ 0x44
80053c8: 6abb ldr r3, [r7, #40] @ 0x28
80053ca: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
80053ce: b25b sxtb r3, r3
80053d0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80053d4: d103 bne.n 80053de <xQueueReceive+0x14a>
80053d6: 6abb ldr r3, [r7, #40] @ 0x28
80053d8: 2200 movs r2, #0
80053da: f883 2045 strb.w r2, [r3, #69] @ 0x45
80053de: f001 fe5b bl 8007098 <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
80053e2: 1d3a adds r2, r7, #4
80053e4: f107 0310 add.w r3, r7, #16
80053e8: 4611 mov r1, r2
80053ea: 4618 mov r0, r3
80053ec: f001 f8a2 bl 8006534 <xTaskCheckForTimeOut>
80053f0: 4603 mov r3, r0
80053f2: 2b00 cmp r3, #0
80053f4: d123 bne.n 800543e <xQueueReceive+0x1aa>
{
/* The timeout has not expired. If the queue is still empty place
the task on the list of tasks waiting to receive from the queue. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
80053f6: 6ab8 ldr r0, [r7, #40] @ 0x28
80053f8: f000 fa46 bl 8005888 <prvIsQueueEmpty>
80053fc: 4603 mov r3, r0
80053fe: 2b00 cmp r3, #0
8005400: d017 beq.n 8005432 <xQueueReceive+0x19e>
{
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
8005402: 6abb ldr r3, [r7, #40] @ 0x28
8005404: 3324 adds r3, #36 @ 0x24
8005406: 687a ldr r2, [r7, #4]
8005408: 4611 mov r1, r2
800540a: 4618 mov r0, r3
800540c: f000 ffee bl 80063ec <vTaskPlaceOnEventList>
prvUnlockQueue( pxQueue );
8005410: 6ab8 ldr r0, [r7, #40] @ 0x28
8005412: f000 f9e7 bl 80057e4 <prvUnlockQueue>
if( xTaskResumeAll() == pdFALSE )
8005416: f000 fd4d bl 8005eb4 <xTaskResumeAll>
800541a: 4603 mov r3, r0
800541c: 2b00 cmp r3, #0
800541e: d189 bne.n 8005334 <xQueueReceive+0xa0>
{
portYIELD_WITHIN_API();
8005420: 4b0f ldr r3, [pc, #60] @ (8005460 <xQueueReceive+0x1cc>)
8005422: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8005426: 601a str r2, [r3, #0]
8005428: f3bf 8f4f dsb sy
800542c: f3bf 8f6f isb sy
8005430: e780 b.n 8005334 <xQueueReceive+0xa0>
}
else
{
/* The queue contains data again. Loop back to try and read the
data. */
prvUnlockQueue( pxQueue );
8005432: 6ab8 ldr r0, [r7, #40] @ 0x28
8005434: f000 f9d6 bl 80057e4 <prvUnlockQueue>
( void ) xTaskResumeAll();
8005438: f000 fd3c bl 8005eb4 <xTaskResumeAll>
800543c: e77a b.n 8005334 <xQueueReceive+0xa0>
}
else
{
/* Timed out. If there is no data in the queue exit, otherwise loop
back and attempt to read the data. */
prvUnlockQueue( pxQueue );
800543e: 6ab8 ldr r0, [r7, #40] @ 0x28
8005440: f000 f9d0 bl 80057e4 <prvUnlockQueue>
( void ) xTaskResumeAll();
8005444: f000 fd36 bl 8005eb4 <xTaskResumeAll>
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
8005448: 6ab8 ldr r0, [r7, #40] @ 0x28
800544a: f000 fa1d bl 8005888 <prvIsQueueEmpty>
800544e: 4603 mov r3, r0
8005450: 2b00 cmp r3, #0
8005452: f43f af6f beq.w 8005334 <xQueueReceive+0xa0>
{
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
8005456: 2300 movs r3, #0
{
mtCOVERAGE_TEST_MARKER();
}
}
} /*lint -restore */
}
8005458: 4618 mov r0, r3
800545a: 3730 adds r7, #48 @ 0x30
800545c: 46bd mov sp, r7
800545e: bd80 pop {r7, pc}
8005460: e000ed04 .word 0xe000ed04
08005464 <xQueueSemaphoreTake>:
/*-----------------------------------------------------------*/
BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
{
8005464: b580 push {r7, lr}
8005466: b08e sub sp, #56 @ 0x38
8005468: af00 add r7, sp, #0
800546a: 6078 str r0, [r7, #4]
800546c: 6039 str r1, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE;
800546e: 2300 movs r3, #0
8005470: 637b str r3, [r7, #52] @ 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
8005472: 687b ldr r3, [r7, #4]
8005474: 62fb str r3, [r7, #44] @ 0x2c
#if( configUSE_MUTEXES == 1 )
BaseType_t xInheritanceOccurred = pdFALSE;
8005476: 2300 movs r3, #0
8005478: 633b str r3, [r7, #48] @ 0x30
#endif
/* Check the queue pointer is not NULL. */
configASSERT( ( pxQueue ) );
800547a: 6afb ldr r3, [r7, #44] @ 0x2c
800547c: 2b00 cmp r3, #0
800547e: d10d bne.n 800549c <xQueueSemaphoreTake+0x38>
__asm volatile
8005480: f04f 0350 mov.w r3, #80 @ 0x50
8005484: b672 cpsid i
8005486: f383 8811 msr BASEPRI, r3
800548a: f3bf 8f6f isb sy
800548e: f3bf 8f4f dsb sy
8005492: b662 cpsie i
8005494: 623b str r3, [r7, #32]
}
8005496: bf00 nop
8005498: bf00 nop
800549a: e7fd b.n 8005498 <xQueueSemaphoreTake+0x34>
/* Check this really is a semaphore, in which case the item size will be
0. */
configASSERT( pxQueue->uxItemSize == 0 );
800549c: 6afb ldr r3, [r7, #44] @ 0x2c
800549e: 6c1b ldr r3, [r3, #64] @ 0x40
80054a0: 2b00 cmp r3, #0
80054a2: d00d beq.n 80054c0 <xQueueSemaphoreTake+0x5c>
__asm volatile
80054a4: f04f 0350 mov.w r3, #80 @ 0x50
80054a8: b672 cpsid i
80054aa: f383 8811 msr BASEPRI, r3
80054ae: f3bf 8f6f isb sy
80054b2: f3bf 8f4f dsb sy
80054b6: b662 cpsie i
80054b8: 61fb str r3, [r7, #28]
}
80054ba: bf00 nop
80054bc: bf00 nop
80054be: e7fd b.n 80054bc <xQueueSemaphoreTake+0x58>
/* Cannot block if the scheduler is suspended. */
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
80054c0: f001 fa5e bl 8006980 <xTaskGetSchedulerState>
80054c4: 4603 mov r3, r0
80054c6: 2b00 cmp r3, #0
80054c8: d102 bne.n 80054d0 <xQueueSemaphoreTake+0x6c>
80054ca: 683b ldr r3, [r7, #0]
80054cc: 2b00 cmp r3, #0
80054ce: d101 bne.n 80054d4 <xQueueSemaphoreTake+0x70>
80054d0: 2301 movs r3, #1
80054d2: e000 b.n 80054d6 <xQueueSemaphoreTake+0x72>
80054d4: 2300 movs r3, #0
80054d6: 2b00 cmp r3, #0
80054d8: d10d bne.n 80054f6 <xQueueSemaphoreTake+0x92>
__asm volatile
80054da: f04f 0350 mov.w r3, #80 @ 0x50
80054de: b672 cpsid i
80054e0: f383 8811 msr BASEPRI, r3
80054e4: f3bf 8f6f isb sy
80054e8: f3bf 8f4f dsb sy
80054ec: b662 cpsie i
80054ee: 61bb str r3, [r7, #24]
}
80054f0: bf00 nop
80054f2: bf00 nop
80054f4: e7fd b.n 80054f2 <xQueueSemaphoreTake+0x8e>
/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
statements within the function itself. This is done in the interest
of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
80054f6: f001 fd99 bl 800702c <vPortEnterCritical>
{
/* Semaphores are queues with an item size of 0, and where the
number of messages in the queue is the semaphore's count value. */
const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
80054fa: 6afb ldr r3, [r7, #44] @ 0x2c
80054fc: 6b9b ldr r3, [r3, #56] @ 0x38
80054fe: 62bb str r3, [r7, #40] @ 0x28
/* Is there data in the queue now? To be running the calling task
must be the highest priority task wanting to access the queue. */
if( uxSemaphoreCount > ( UBaseType_t ) 0 )
8005500: 6abb ldr r3, [r7, #40] @ 0x28
8005502: 2b00 cmp r3, #0
8005504: d024 beq.n 8005550 <xQueueSemaphoreTake+0xec>
{
traceQUEUE_RECEIVE( pxQueue );
/* Semaphores are queues with a data size of zero and where the
messages waiting is the semaphore's count. Reduce the count. */
pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
8005506: 6abb ldr r3, [r7, #40] @ 0x28
8005508: 1e5a subs r2, r3, #1
800550a: 6afb ldr r3, [r7, #44] @ 0x2c
800550c: 639a str r2, [r3, #56] @ 0x38
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
800550e: 6afb ldr r3, [r7, #44] @ 0x2c
8005510: 681b ldr r3, [r3, #0]
8005512: 2b00 cmp r3, #0
8005514: d104 bne.n 8005520 <xQueueSemaphoreTake+0xbc>
{
/* Record the information required to implement
priority inheritance should it become necessary. */
pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
8005516: f001 fbfd bl 8006d14 <pvTaskIncrementMutexHeldCount>
800551a: 4602 mov r2, r0
800551c: 6afb ldr r3, [r7, #44] @ 0x2c
800551e: 609a str r2, [r3, #8]
}
#endif /* configUSE_MUTEXES */
/* Check to see if other tasks are blocked waiting to give the
semaphore, and if so, unblock the highest priority such task. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
8005520: 6afb ldr r3, [r7, #44] @ 0x2c
8005522: 691b ldr r3, [r3, #16]
8005524: 2b00 cmp r3, #0
8005526: d00f beq.n 8005548 <xQueueSemaphoreTake+0xe4>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
8005528: 6afb ldr r3, [r7, #44] @ 0x2c
800552a: 3310 adds r3, #16
800552c: 4618 mov r0, r3
800552e: f000 ff85 bl 800643c <xTaskRemoveFromEventList>
8005532: 4603 mov r3, r0
8005534: 2b00 cmp r3, #0
8005536: d007 beq.n 8005548 <xQueueSemaphoreTake+0xe4>
{
queueYIELD_IF_USING_PREEMPTION();
8005538: 4b55 ldr r3, [pc, #340] @ (8005690 <xQueueSemaphoreTake+0x22c>)
800553a: f04f 5280 mov.w r2, #268435456 @ 0x10000000
800553e: 601a str r2, [r3, #0]
8005540: f3bf 8f4f dsb sy
8005544: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
taskEXIT_CRITICAL();
8005548: f001 fda6 bl 8007098 <vPortExitCritical>
return pdPASS;
800554c: 2301 movs r3, #1
800554e: e09a b.n 8005686 <xQueueSemaphoreTake+0x222>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
8005550: 683b ldr r3, [r7, #0]
8005552: 2b00 cmp r3, #0
8005554: d114 bne.n 8005580 <xQueueSemaphoreTake+0x11c>
/* For inheritance to have occurred there must have been an
initial timeout, and an adjusted timeout cannot become 0, as
if it were 0 the function would have exited. */
#if( configUSE_MUTEXES == 1 )
{
configASSERT( xInheritanceOccurred == pdFALSE );
8005556: 6b3b ldr r3, [r7, #48] @ 0x30
8005558: 2b00 cmp r3, #0
800555a: d00d beq.n 8005578 <xQueueSemaphoreTake+0x114>
__asm volatile
800555c: f04f 0350 mov.w r3, #80 @ 0x50
8005560: b672 cpsid i
8005562: f383 8811 msr BASEPRI, r3
8005566: f3bf 8f6f isb sy
800556a: f3bf 8f4f dsb sy
800556e: b662 cpsie i
8005570: 617b str r3, [r7, #20]
}
8005572: bf00 nop
8005574: bf00 nop
8005576: e7fd b.n 8005574 <xQueueSemaphoreTake+0x110>
}
#endif /* configUSE_MUTEXES */
/* The semaphore count was 0 and no block time is specified
(or the block time has expired) so exit now. */
taskEXIT_CRITICAL();
8005578: f001 fd8e bl 8007098 <vPortExitCritical>
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
800557c: 2300 movs r3, #0
800557e: e082 b.n 8005686 <xQueueSemaphoreTake+0x222>
}
else if( xEntryTimeSet == pdFALSE )
8005580: 6b7b ldr r3, [r7, #52] @ 0x34
8005582: 2b00 cmp r3, #0
8005584: d106 bne.n 8005594 <xQueueSemaphoreTake+0x130>
{
/* The semaphore count was 0 and a block time was specified
so configure the timeout structure ready to block. */
vTaskInternalSetTimeOutState( &xTimeOut );
8005586: f107 030c add.w r3, r7, #12
800558a: 4618 mov r0, r3
800558c: f000 ffbc bl 8006508 <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
8005590: 2301 movs r3, #1
8005592: 637b str r3, [r7, #52] @ 0x34
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
8005594: f001 fd80 bl 8007098 <vPortExitCritical>
/* Interrupts and other tasks can give to and take from the semaphore
now the critical section has been exited. */
vTaskSuspendAll();
8005598: f000 fc7e bl 8005e98 <vTaskSuspendAll>
prvLockQueue( pxQueue );
800559c: f001 fd46 bl 800702c <vPortEnterCritical>
80055a0: 6afb ldr r3, [r7, #44] @ 0x2c
80055a2: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
80055a6: b25b sxtb r3, r3
80055a8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80055ac: d103 bne.n 80055b6 <xQueueSemaphoreTake+0x152>
80055ae: 6afb ldr r3, [r7, #44] @ 0x2c
80055b0: 2200 movs r2, #0
80055b2: f883 2044 strb.w r2, [r3, #68] @ 0x44
80055b6: 6afb ldr r3, [r7, #44] @ 0x2c
80055b8: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
80055bc: b25b sxtb r3, r3
80055be: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80055c2: d103 bne.n 80055cc <xQueueSemaphoreTake+0x168>
80055c4: 6afb ldr r3, [r7, #44] @ 0x2c
80055c6: 2200 movs r2, #0
80055c8: f883 2045 strb.w r2, [r3, #69] @ 0x45
80055cc: f001 fd64 bl 8007098 <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
80055d0: 463a mov r2, r7
80055d2: f107 030c add.w r3, r7, #12
80055d6: 4611 mov r1, r2
80055d8: 4618 mov r0, r3
80055da: f000 ffab bl 8006534 <xTaskCheckForTimeOut>
80055de: 4603 mov r3, r0
80055e0: 2b00 cmp r3, #0
80055e2: d132 bne.n 800564a <xQueueSemaphoreTake+0x1e6>
{
/* A block time is specified and not expired. If the semaphore
count is 0 then enter the Blocked state to wait for a semaphore to
become available. As semaphores are implemented with queues the
queue being empty is equivalent to the semaphore count being 0. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
80055e4: 6af8 ldr r0, [r7, #44] @ 0x2c
80055e6: f000 f94f bl 8005888 <prvIsQueueEmpty>
80055ea: 4603 mov r3, r0
80055ec: 2b00 cmp r3, #0
80055ee: d026 beq.n 800563e <xQueueSemaphoreTake+0x1da>
{
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
80055f0: 6afb ldr r3, [r7, #44] @ 0x2c
80055f2: 681b ldr r3, [r3, #0]
80055f4: 2b00 cmp r3, #0
80055f6: d109 bne.n 800560c <xQueueSemaphoreTake+0x1a8>
{
taskENTER_CRITICAL();
80055f8: f001 fd18 bl 800702c <vPortEnterCritical>
{
xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
80055fc: 6afb ldr r3, [r7, #44] @ 0x2c
80055fe: 689b ldr r3, [r3, #8]
8005600: 4618 mov r0, r3
8005602: f001 f9db bl 80069bc <xTaskPriorityInherit>
8005606: 6338 str r0, [r7, #48] @ 0x30
}
taskEXIT_CRITICAL();
8005608: f001 fd46 bl 8007098 <vPortExitCritical>
mtCOVERAGE_TEST_MARKER();
}
}
#endif
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
800560c: 6afb ldr r3, [r7, #44] @ 0x2c
800560e: 3324 adds r3, #36 @ 0x24
8005610: 683a ldr r2, [r7, #0]
8005612: 4611 mov r1, r2
8005614: 4618 mov r0, r3
8005616: f000 fee9 bl 80063ec <vTaskPlaceOnEventList>
prvUnlockQueue( pxQueue );
800561a: 6af8 ldr r0, [r7, #44] @ 0x2c
800561c: f000 f8e2 bl 80057e4 <prvUnlockQueue>
if( xTaskResumeAll() == pdFALSE )
8005620: f000 fc48 bl 8005eb4 <xTaskResumeAll>
8005624: 4603 mov r3, r0
8005626: 2b00 cmp r3, #0
8005628: f47f af65 bne.w 80054f6 <xQueueSemaphoreTake+0x92>
{
portYIELD_WITHIN_API();
800562c: 4b18 ldr r3, [pc, #96] @ (8005690 <xQueueSemaphoreTake+0x22c>)
800562e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8005632: 601a str r2, [r3, #0]
8005634: f3bf 8f4f dsb sy
8005638: f3bf 8f6f isb sy
800563c: e75b b.n 80054f6 <xQueueSemaphoreTake+0x92>
}
else
{
/* There was no timeout and the semaphore count was not 0, so
attempt to take the semaphore again. */
prvUnlockQueue( pxQueue );
800563e: 6af8 ldr r0, [r7, #44] @ 0x2c
8005640: f000 f8d0 bl 80057e4 <prvUnlockQueue>
( void ) xTaskResumeAll();
8005644: f000 fc36 bl 8005eb4 <xTaskResumeAll>
8005648: e755 b.n 80054f6 <xQueueSemaphoreTake+0x92>
}
}
else
{
/* Timed out. */
prvUnlockQueue( pxQueue );
800564a: 6af8 ldr r0, [r7, #44] @ 0x2c
800564c: f000 f8ca bl 80057e4 <prvUnlockQueue>
( void ) xTaskResumeAll();
8005650: f000 fc30 bl 8005eb4 <xTaskResumeAll>
/* If the semaphore count is 0 exit now as the timeout has
expired. Otherwise return to attempt to take the semaphore that is
known to be available. As semaphores are implemented by queues the
queue being empty is equivalent to the semaphore count being 0. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
8005654: 6af8 ldr r0, [r7, #44] @ 0x2c
8005656: f000 f917 bl 8005888 <prvIsQueueEmpty>
800565a: 4603 mov r3, r0
800565c: 2b00 cmp r3, #0
800565e: f43f af4a beq.w 80054f6 <xQueueSemaphoreTake+0x92>
#if ( configUSE_MUTEXES == 1 )
{
/* xInheritanceOccurred could only have be set if
pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
test the mutex type again to check it is actually a mutex. */
if( xInheritanceOccurred != pdFALSE )
8005662: 6b3b ldr r3, [r7, #48] @ 0x30
8005664: 2b00 cmp r3, #0
8005666: d00d beq.n 8005684 <xQueueSemaphoreTake+0x220>
{
taskENTER_CRITICAL();
8005668: f001 fce0 bl 800702c <vPortEnterCritical>
/* This task blocking on the mutex caused another
task to inherit this task's priority. Now this task
has timed out the priority should be disinherited
again, but only as low as the next highest priority
task that is waiting for the same mutex. */
uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
800566c: 6af8 ldr r0, [r7, #44] @ 0x2c
800566e: f000 f811 bl 8005694 <prvGetDisinheritPriorityAfterTimeout>
8005672: 6278 str r0, [r7, #36] @ 0x24
vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
8005674: 6afb ldr r3, [r7, #44] @ 0x2c
8005676: 689b ldr r3, [r3, #8]
8005678: 6a79 ldr r1, [r7, #36] @ 0x24
800567a: 4618 mov r0, r3
800567c: f001 faaa bl 8006bd4 <vTaskPriorityDisinheritAfterTimeout>
}
taskEXIT_CRITICAL();
8005680: f001 fd0a bl 8007098 <vPortExitCritical>
}
}
#endif /* configUSE_MUTEXES */
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
8005684: 2300 movs r3, #0
{
mtCOVERAGE_TEST_MARKER();
}
}
} /*lint -restore */
}
8005686: 4618 mov r0, r3
8005688: 3738 adds r7, #56 @ 0x38
800568a: 46bd mov sp, r7
800568c: bd80 pop {r7, pc}
800568e: bf00 nop
8005690: e000ed04 .word 0xe000ed04
08005694 <prvGetDisinheritPriorityAfterTimeout>:
/*-----------------------------------------------------------*/
#if( configUSE_MUTEXES == 1 )
static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
{
8005694: b480 push {r7}
8005696: b085 sub sp, #20
8005698: af00 add r7, sp, #0
800569a: 6078 str r0, [r7, #4]
priority, but the waiting task times out, then the holder should
disinherit the priority - but only down to the highest priority of any
other tasks that are waiting for the same mutex. For this purpose,
return the priority of the highest priority task that is waiting for the
mutex. */
if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
800569c: 687b ldr r3, [r7, #4]
800569e: 6a5b ldr r3, [r3, #36] @ 0x24
80056a0: 2b00 cmp r3, #0
80056a2: d006 beq.n 80056b2 <prvGetDisinheritPriorityAfterTimeout+0x1e>
{
uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
80056a4: 687b ldr r3, [r7, #4]
80056a6: 6b1b ldr r3, [r3, #48] @ 0x30
80056a8: 681b ldr r3, [r3, #0]
80056aa: f1c3 0307 rsb r3, r3, #7
80056ae: 60fb str r3, [r7, #12]
80056b0: e001 b.n 80056b6 <prvGetDisinheritPriorityAfterTimeout+0x22>
}
else
{
uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
80056b2: 2300 movs r3, #0
80056b4: 60fb str r3, [r7, #12]
}
return uxHighestPriorityOfWaitingTasks;
80056b6: 68fb ldr r3, [r7, #12]
}
80056b8: 4618 mov r0, r3
80056ba: 3714 adds r7, #20
80056bc: 46bd mov sp, r7
80056be: f85d 7b04 ldr.w r7, [sp], #4
80056c2: 4770 bx lr
080056c4 <prvCopyDataToQueue>:
#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/
static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
{
80056c4: b580 push {r7, lr}
80056c6: b086 sub sp, #24
80056c8: af00 add r7, sp, #0
80056ca: 60f8 str r0, [r7, #12]
80056cc: 60b9 str r1, [r7, #8]
80056ce: 607a str r2, [r7, #4]
BaseType_t xReturn = pdFALSE;
80056d0: 2300 movs r3, #0
80056d2: 617b str r3, [r7, #20]
UBaseType_t uxMessagesWaiting;
/* This function is called from a critical section. */
uxMessagesWaiting = pxQueue->uxMessagesWaiting;
80056d4: 68fb ldr r3, [r7, #12]
80056d6: 6b9b ldr r3, [r3, #56] @ 0x38
80056d8: 613b str r3, [r7, #16]
if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
80056da: 68fb ldr r3, [r7, #12]
80056dc: 6c1b ldr r3, [r3, #64] @ 0x40
80056de: 2b00 cmp r3, #0
80056e0: d10d bne.n 80056fe <prvCopyDataToQueue+0x3a>
{
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
80056e2: 68fb ldr r3, [r7, #12]
80056e4: 681b ldr r3, [r3, #0]
80056e6: 2b00 cmp r3, #0
80056e8: d14d bne.n 8005786 <prvCopyDataToQueue+0xc2>
{
/* The mutex is no longer being held. */
xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
80056ea: 68fb ldr r3, [r7, #12]
80056ec: 689b ldr r3, [r3, #8]
80056ee: 4618 mov r0, r3
80056f0: f001 f9e4 bl 8006abc <xTaskPriorityDisinherit>
80056f4: 6178 str r0, [r7, #20]
pxQueue->u.xSemaphore.xMutexHolder = NULL;
80056f6: 68fb ldr r3, [r7, #12]
80056f8: 2200 movs r2, #0
80056fa: 609a str r2, [r3, #8]
80056fc: e043 b.n 8005786 <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_MUTEXES */
}
else if( xPosition == queueSEND_TO_BACK )
80056fe: 687b ldr r3, [r7, #4]
8005700: 2b00 cmp r3, #0
8005702: d119 bne.n 8005738 <prvCopyDataToQueue+0x74>
{
( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
8005704: 68fb ldr r3, [r7, #12]
8005706: 6858 ldr r0, [r3, #4]
8005708: 68fb ldr r3, [r7, #12]
800570a: 6c1b ldr r3, [r3, #64] @ 0x40
800570c: 461a mov r2, r3
800570e: 68b9 ldr r1, [r7, #8]
8005710: f002 fadb bl 8007cca <memcpy>
pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
8005714: 68fb ldr r3, [r7, #12]
8005716: 685a ldr r2, [r3, #4]
8005718: 68fb ldr r3, [r7, #12]
800571a: 6c1b ldr r3, [r3, #64] @ 0x40
800571c: 441a add r2, r3
800571e: 68fb ldr r3, [r7, #12]
8005720: 605a str r2, [r3, #4]
if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
8005722: 68fb ldr r3, [r7, #12]
8005724: 685a ldr r2, [r3, #4]
8005726: 68fb ldr r3, [r7, #12]
8005728: 689b ldr r3, [r3, #8]
800572a: 429a cmp r2, r3
800572c: d32b bcc.n 8005786 <prvCopyDataToQueue+0xc2>
{
pxQueue->pcWriteTo = pxQueue->pcHead;
800572e: 68fb ldr r3, [r7, #12]
8005730: 681a ldr r2, [r3, #0]
8005732: 68fb ldr r3, [r7, #12]
8005734: 605a str r2, [r3, #4]
8005736: e026 b.n 8005786 <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
else
{
( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
8005738: 68fb ldr r3, [r7, #12]
800573a: 68d8 ldr r0, [r3, #12]
800573c: 68fb ldr r3, [r7, #12]
800573e: 6c1b ldr r3, [r3, #64] @ 0x40
8005740: 461a mov r2, r3
8005742: 68b9 ldr r1, [r7, #8]
8005744: f002 fac1 bl 8007cca <memcpy>
pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
8005748: 68fb ldr r3, [r7, #12]
800574a: 68da ldr r2, [r3, #12]
800574c: 68fb ldr r3, [r7, #12]
800574e: 6c1b ldr r3, [r3, #64] @ 0x40
8005750: 425b negs r3, r3
8005752: 441a add r2, r3
8005754: 68fb ldr r3, [r7, #12]
8005756: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
8005758: 68fb ldr r3, [r7, #12]
800575a: 68da ldr r2, [r3, #12]
800575c: 68fb ldr r3, [r7, #12]
800575e: 681b ldr r3, [r3, #0]
8005760: 429a cmp r2, r3
8005762: d207 bcs.n 8005774 <prvCopyDataToQueue+0xb0>
{
pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
8005764: 68fb ldr r3, [r7, #12]
8005766: 689a ldr r2, [r3, #8]
8005768: 68fb ldr r3, [r7, #12]
800576a: 6c1b ldr r3, [r3, #64] @ 0x40
800576c: 425b negs r3, r3
800576e: 441a add r2, r3
8005770: 68fb ldr r3, [r7, #12]
8005772: 60da str r2, [r3, #12]
else
{
mtCOVERAGE_TEST_MARKER();
}
if( xPosition == queueOVERWRITE )
8005774: 687b ldr r3, [r7, #4]
8005776: 2b02 cmp r3, #2
8005778: d105 bne.n 8005786 <prvCopyDataToQueue+0xc2>
{
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
800577a: 693b ldr r3, [r7, #16]
800577c: 2b00 cmp r3, #0
800577e: d002 beq.n 8005786 <prvCopyDataToQueue+0xc2>
{
/* An item is not being added but overwritten, so subtract
one from the recorded number of items in the queue so when
one is added again below the number of recorded items remains
correct. */
--uxMessagesWaiting;
8005780: 693b ldr r3, [r7, #16]
8005782: 3b01 subs r3, #1
8005784: 613b str r3, [r7, #16]
{
mtCOVERAGE_TEST_MARKER();
}
}
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
8005786: 693b ldr r3, [r7, #16]
8005788: 1c5a adds r2, r3, #1
800578a: 68fb ldr r3, [r7, #12]
800578c: 639a str r2, [r3, #56] @ 0x38
return xReturn;
800578e: 697b ldr r3, [r7, #20]
}
8005790: 4618 mov r0, r3
8005792: 3718 adds r7, #24
8005794: 46bd mov sp, r7
8005796: bd80 pop {r7, pc}
08005798 <prvCopyDataFromQueue>:
/*-----------------------------------------------------------*/
static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
{
8005798: b580 push {r7, lr}
800579a: b082 sub sp, #8
800579c: af00 add r7, sp, #0
800579e: 6078 str r0, [r7, #4]
80057a0: 6039 str r1, [r7, #0]
if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
80057a2: 687b ldr r3, [r7, #4]
80057a4: 6c1b ldr r3, [r3, #64] @ 0x40
80057a6: 2b00 cmp r3, #0
80057a8: d018 beq.n 80057dc <prvCopyDataFromQueue+0x44>
{
pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
80057aa: 687b ldr r3, [r7, #4]
80057ac: 68da ldr r2, [r3, #12]
80057ae: 687b ldr r3, [r7, #4]
80057b0: 6c1b ldr r3, [r3, #64] @ 0x40
80057b2: 441a add r2, r3
80057b4: 687b ldr r3, [r7, #4]
80057b6: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
80057b8: 687b ldr r3, [r7, #4]
80057ba: 68da ldr r2, [r3, #12]
80057bc: 687b ldr r3, [r7, #4]
80057be: 689b ldr r3, [r3, #8]
80057c0: 429a cmp r2, r3
80057c2: d303 bcc.n 80057cc <prvCopyDataFromQueue+0x34>
{
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
80057c4: 687b ldr r3, [r7, #4]
80057c6: 681a ldr r2, [r3, #0]
80057c8: 687b ldr r3, [r7, #4]
80057ca: 60da str r2, [r3, #12]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
80057cc: 687b ldr r3, [r7, #4]
80057ce: 68d9 ldr r1, [r3, #12]
80057d0: 687b ldr r3, [r7, #4]
80057d2: 6c1b ldr r3, [r3, #64] @ 0x40
80057d4: 461a mov r2, r3
80057d6: 6838 ldr r0, [r7, #0]
80057d8: f002 fa77 bl 8007cca <memcpy>
}
}
80057dc: bf00 nop
80057de: 3708 adds r7, #8
80057e0: 46bd mov sp, r7
80057e2: bd80 pop {r7, pc}
080057e4 <prvUnlockQueue>:
/*-----------------------------------------------------------*/
static void prvUnlockQueue( Queue_t * const pxQueue )
{
80057e4: b580 push {r7, lr}
80057e6: b084 sub sp, #16
80057e8: af00 add r7, sp, #0
80057ea: 6078 str r0, [r7, #4]
/* The lock counts contains the number of extra data items placed or
removed from the queue while the queue was locked. When a queue is
locked items can be added or removed, but the event lists cannot be
updated. */
taskENTER_CRITICAL();
80057ec: f001 fc1e bl 800702c <vPortEnterCritical>
{
int8_t cTxLock = pxQueue->cTxLock;
80057f0: 687b ldr r3, [r7, #4]
80057f2: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
80057f6: 73fb strb r3, [r7, #15]
/* See if data was added to the queue while it was locked. */
while( cTxLock > queueLOCKED_UNMODIFIED )
80057f8: e011 b.n 800581e <prvUnlockQueue+0x3a>
}
#else /* configUSE_QUEUE_SETS */
{
/* Tasks that are removed from the event list will get added to
the pending ready list as the scheduler is still suspended. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
80057fa: 687b ldr r3, [r7, #4]
80057fc: 6a5b ldr r3, [r3, #36] @ 0x24
80057fe: 2b00 cmp r3, #0
8005800: d012 beq.n 8005828 <prvUnlockQueue+0x44>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
8005802: 687b ldr r3, [r7, #4]
8005804: 3324 adds r3, #36 @ 0x24
8005806: 4618 mov r0, r3
8005808: f000 fe18 bl 800643c <xTaskRemoveFromEventList>
800580c: 4603 mov r3, r0
800580e: 2b00 cmp r3, #0
8005810: d001 beq.n 8005816 <prvUnlockQueue+0x32>
{
/* The task waiting has a higher priority so record that
a context switch is required. */
vTaskMissedYield();
8005812: f000 fef7 bl 8006604 <vTaskMissedYield>
break;
}
}
#endif /* configUSE_QUEUE_SETS */
--cTxLock;
8005816: 7bfb ldrb r3, [r7, #15]
8005818: 3b01 subs r3, #1
800581a: b2db uxtb r3, r3
800581c: 73fb strb r3, [r7, #15]
while( cTxLock > queueLOCKED_UNMODIFIED )
800581e: f997 300f ldrsb.w r3, [r7, #15]
8005822: 2b00 cmp r3, #0
8005824: dce9 bgt.n 80057fa <prvUnlockQueue+0x16>
8005826: e000 b.n 800582a <prvUnlockQueue+0x46>
break;
8005828: bf00 nop
}
pxQueue->cTxLock = queueUNLOCKED;
800582a: 687b ldr r3, [r7, #4]
800582c: 22ff movs r2, #255 @ 0xff
800582e: f883 2045 strb.w r2, [r3, #69] @ 0x45
}
taskEXIT_CRITICAL();
8005832: f001 fc31 bl 8007098 <vPortExitCritical>
/* Do the same for the Rx lock. */
taskENTER_CRITICAL();
8005836: f001 fbf9 bl 800702c <vPortEnterCritical>
{
int8_t cRxLock = pxQueue->cRxLock;
800583a: 687b ldr r3, [r7, #4]
800583c: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
8005840: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
8005842: e011 b.n 8005868 <prvUnlockQueue+0x84>
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
8005844: 687b ldr r3, [r7, #4]
8005846: 691b ldr r3, [r3, #16]
8005848: 2b00 cmp r3, #0
800584a: d012 beq.n 8005872 <prvUnlockQueue+0x8e>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800584c: 687b ldr r3, [r7, #4]
800584e: 3310 adds r3, #16
8005850: 4618 mov r0, r3
8005852: f000 fdf3 bl 800643c <xTaskRemoveFromEventList>
8005856: 4603 mov r3, r0
8005858: 2b00 cmp r3, #0
800585a: d001 beq.n 8005860 <prvUnlockQueue+0x7c>
{
vTaskMissedYield();
800585c: f000 fed2 bl 8006604 <vTaskMissedYield>
else
{
mtCOVERAGE_TEST_MARKER();
}
--cRxLock;
8005860: 7bbb ldrb r3, [r7, #14]
8005862: 3b01 subs r3, #1
8005864: b2db uxtb r3, r3
8005866: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
8005868: f997 300e ldrsb.w r3, [r7, #14]
800586c: 2b00 cmp r3, #0
800586e: dce9 bgt.n 8005844 <prvUnlockQueue+0x60>
8005870: e000 b.n 8005874 <prvUnlockQueue+0x90>
}
else
{
break;
8005872: bf00 nop
}
}
pxQueue->cRxLock = queueUNLOCKED;
8005874: 687b ldr r3, [r7, #4]
8005876: 22ff movs r2, #255 @ 0xff
8005878: f883 2044 strb.w r2, [r3, #68] @ 0x44
}
taskEXIT_CRITICAL();
800587c: f001 fc0c bl 8007098 <vPortExitCritical>
}
8005880: bf00 nop
8005882: 3710 adds r7, #16
8005884: 46bd mov sp, r7
8005886: bd80 pop {r7, pc}
08005888 <prvIsQueueEmpty>:
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
{
8005888: b580 push {r7, lr}
800588a: b084 sub sp, #16
800588c: af00 add r7, sp, #0
800588e: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
8005890: f001 fbcc bl 800702c <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
8005894: 687b ldr r3, [r7, #4]
8005896: 6b9b ldr r3, [r3, #56] @ 0x38
8005898: 2b00 cmp r3, #0
800589a: d102 bne.n 80058a2 <prvIsQueueEmpty+0x1a>
{
xReturn = pdTRUE;
800589c: 2301 movs r3, #1
800589e: 60fb str r3, [r7, #12]
80058a0: e001 b.n 80058a6 <prvIsQueueEmpty+0x1e>
}
else
{
xReturn = pdFALSE;
80058a2: 2300 movs r3, #0
80058a4: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
80058a6: f001 fbf7 bl 8007098 <vPortExitCritical>
return xReturn;
80058aa: 68fb ldr r3, [r7, #12]
}
80058ac: 4618 mov r0, r3
80058ae: 3710 adds r7, #16
80058b0: 46bd mov sp, r7
80058b2: bd80 pop {r7, pc}
080058b4 <prvIsQueueFull>:
return xReturn;
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
{
80058b4: b580 push {r7, lr}
80058b6: b084 sub sp, #16
80058b8: af00 add r7, sp, #0
80058ba: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
80058bc: f001 fbb6 bl 800702c <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
80058c0: 687b ldr r3, [r7, #4]
80058c2: 6b9a ldr r2, [r3, #56] @ 0x38
80058c4: 687b ldr r3, [r7, #4]
80058c6: 6bdb ldr r3, [r3, #60] @ 0x3c
80058c8: 429a cmp r2, r3
80058ca: d102 bne.n 80058d2 <prvIsQueueFull+0x1e>
{
xReturn = pdTRUE;
80058cc: 2301 movs r3, #1
80058ce: 60fb str r3, [r7, #12]
80058d0: e001 b.n 80058d6 <prvIsQueueFull+0x22>
}
else
{
xReturn = pdFALSE;
80058d2: 2300 movs r3, #0
80058d4: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
80058d6: f001 fbdf bl 8007098 <vPortExitCritical>
return xReturn;
80058da: 68fb ldr r3, [r7, #12]
}
80058dc: 4618 mov r0, r3
80058de: 3710 adds r7, #16
80058e0: 46bd mov sp, r7
80058e2: bd80 pop {r7, pc}
080058e4 <xTaskCreateStatic>:
const uint32_t ulStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
StackType_t * const puxStackBuffer,
StaticTask_t * const pxTaskBuffer )
{
80058e4: b580 push {r7, lr}
80058e6: b08e sub sp, #56 @ 0x38
80058e8: af04 add r7, sp, #16
80058ea: 60f8 str r0, [r7, #12]
80058ec: 60b9 str r1, [r7, #8]
80058ee: 607a str r2, [r7, #4]
80058f0: 603b str r3, [r7, #0]
TCB_t *pxNewTCB;
TaskHandle_t xReturn;
configASSERT( puxStackBuffer != NULL );
80058f2: 6b7b ldr r3, [r7, #52] @ 0x34
80058f4: 2b00 cmp r3, #0
80058f6: d10d bne.n 8005914 <xTaskCreateStatic+0x30>
__asm volatile
80058f8: f04f 0350 mov.w r3, #80 @ 0x50
80058fc: b672 cpsid i
80058fe: f383 8811 msr BASEPRI, r3
8005902: f3bf 8f6f isb sy
8005906: f3bf 8f4f dsb sy
800590a: b662 cpsie i
800590c: 623b str r3, [r7, #32]
}
800590e: bf00 nop
8005910: bf00 nop
8005912: e7fd b.n 8005910 <xTaskCreateStatic+0x2c>
configASSERT( pxTaskBuffer != NULL );
8005914: 6bbb ldr r3, [r7, #56] @ 0x38
8005916: 2b00 cmp r3, #0
8005918: d10d bne.n 8005936 <xTaskCreateStatic+0x52>
__asm volatile
800591a: f04f 0350 mov.w r3, #80 @ 0x50
800591e: b672 cpsid i
8005920: f383 8811 msr BASEPRI, r3
8005924: f3bf 8f6f isb sy
8005928: f3bf 8f4f dsb sy
800592c: b662 cpsie i
800592e: 61fb str r3, [r7, #28]
}
8005930: bf00 nop
8005932: bf00 nop
8005934: e7fd b.n 8005932 <xTaskCreateStatic+0x4e>
#if( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
variable of type StaticTask_t equals the size of the real task
structure. */
volatile size_t xSize = sizeof( StaticTask_t );
8005936: 23ac movs r3, #172 @ 0xac
8005938: 613b str r3, [r7, #16]
configASSERT( xSize == sizeof( TCB_t ) );
800593a: 693b ldr r3, [r7, #16]
800593c: 2bac cmp r3, #172 @ 0xac
800593e: d00d beq.n 800595c <xTaskCreateStatic+0x78>
__asm volatile
8005940: f04f 0350 mov.w r3, #80 @ 0x50
8005944: b672 cpsid i
8005946: f383 8811 msr BASEPRI, r3
800594a: f3bf 8f6f isb sy
800594e: f3bf 8f4f dsb sy
8005952: b662 cpsie i
8005954: 61bb str r3, [r7, #24]
}
8005956: bf00 nop
8005958: bf00 nop
800595a: e7fd b.n 8005958 <xTaskCreateStatic+0x74>
( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
800595c: 693b ldr r3, [r7, #16]
}
#endif /* configASSERT_DEFINED */
if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
800595e: 6bbb ldr r3, [r7, #56] @ 0x38
8005960: 2b00 cmp r3, #0
8005962: d01e beq.n 80059a2 <xTaskCreateStatic+0xbe>
8005964: 6b7b ldr r3, [r7, #52] @ 0x34
8005966: 2b00 cmp r3, #0
8005968: d01b beq.n 80059a2 <xTaskCreateStatic+0xbe>
{
/* The memory used for the task's TCB and stack are passed into this
function - use them. */
pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
800596a: 6bbb ldr r3, [r7, #56] @ 0x38
800596c: 627b str r3, [r7, #36] @ 0x24
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
800596e: 6a7b ldr r3, [r7, #36] @ 0x24
8005970: 6b7a ldr r2, [r7, #52] @ 0x34
8005972: 631a str r2, [r3, #48] @ 0x30
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created statically in case the task is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
8005974: 6a7b ldr r3, [r7, #36] @ 0x24
8005976: 2202 movs r2, #2
8005978: f883 20a9 strb.w r2, [r3, #169] @ 0xa9
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
800597c: 2300 movs r3, #0
800597e: 9303 str r3, [sp, #12]
8005980: 6a7b ldr r3, [r7, #36] @ 0x24
8005982: 9302 str r3, [sp, #8]
8005984: f107 0314 add.w r3, r7, #20
8005988: 9301 str r3, [sp, #4]
800598a: 6b3b ldr r3, [r7, #48] @ 0x30
800598c: 9300 str r3, [sp, #0]
800598e: 683b ldr r3, [r7, #0]
8005990: 687a ldr r2, [r7, #4]
8005992: 68b9 ldr r1, [r7, #8]
8005994: 68f8 ldr r0, [r7, #12]
8005996: f000 f851 bl 8005a3c <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
800599a: 6a78 ldr r0, [r7, #36] @ 0x24
800599c: f000 f8fa bl 8005b94 <prvAddNewTaskToReadyList>
80059a0: e001 b.n 80059a6 <xTaskCreateStatic+0xc2>
}
else
{
xReturn = NULL;
80059a2: 2300 movs r3, #0
80059a4: 617b str r3, [r7, #20]
}
return xReturn;
80059a6: 697b ldr r3, [r7, #20]
}
80059a8: 4618 mov r0, r3
80059aa: 3728 adds r7, #40 @ 0x28
80059ac: 46bd mov sp, r7
80059ae: bd80 pop {r7, pc}
080059b0 <xTaskCreate>:
const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
const configSTACK_DEPTH_TYPE usStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask )
{
80059b0: b580 push {r7, lr}
80059b2: b08c sub sp, #48 @ 0x30
80059b4: af04 add r7, sp, #16
80059b6: 60f8 str r0, [r7, #12]
80059b8: 60b9 str r1, [r7, #8]
80059ba: 603b str r3, [r7, #0]
80059bc: 4613 mov r3, r2
80059be: 80fb strh r3, [r7, #6]
#else /* portSTACK_GROWTH */
{
StackType_t *pxStack;
/* Allocate space for the stack used by the task being created. */
pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
80059c0: 88fb ldrh r3, [r7, #6]
80059c2: 009b lsls r3, r3, #2
80059c4: 4618 mov r0, r3
80059c6: f001 fc19 bl 80071fc <pvPortMalloc>
80059ca: 6178 str r0, [r7, #20]
if( pxStack != NULL )
80059cc: 697b ldr r3, [r7, #20]
80059ce: 2b00 cmp r3, #0
80059d0: d00e beq.n 80059f0 <xTaskCreate+0x40>
{
/* Allocate space for the TCB. */
pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
80059d2: 20ac movs r0, #172 @ 0xac
80059d4: f001 fc12 bl 80071fc <pvPortMalloc>
80059d8: 61f8 str r0, [r7, #28]
if( pxNewTCB != NULL )
80059da: 69fb ldr r3, [r7, #28]
80059dc: 2b00 cmp r3, #0
80059de: d003 beq.n 80059e8 <xTaskCreate+0x38>
{
/* Store the stack location in the TCB. */
pxNewTCB->pxStack = pxStack;
80059e0: 69fb ldr r3, [r7, #28]
80059e2: 697a ldr r2, [r7, #20]
80059e4: 631a str r2, [r3, #48] @ 0x30
80059e6: e005 b.n 80059f4 <xTaskCreate+0x44>
}
else
{
/* The stack cannot be used as the TCB was not created. Free
it again. */
vPortFree( pxStack );
80059e8: 6978 ldr r0, [r7, #20]
80059ea: f001 fcd5 bl 8007398 <vPortFree>
80059ee: e001 b.n 80059f4 <xTaskCreate+0x44>
}
}
else
{
pxNewTCB = NULL;
80059f0: 2300 movs r3, #0
80059f2: 61fb str r3, [r7, #28]
}
}
#endif /* portSTACK_GROWTH */
if( pxNewTCB != NULL )
80059f4: 69fb ldr r3, [r7, #28]
80059f6: 2b00 cmp r3, #0
80059f8: d017 beq.n 8005a2a <xTaskCreate+0x7a>
{
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created dynamically in case it is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
80059fa: 69fb ldr r3, [r7, #28]
80059fc: 2200 movs r2, #0
80059fe: f883 20a9 strb.w r2, [r3, #169] @ 0xa9
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
8005a02: 88fa ldrh r2, [r7, #6]
8005a04: 2300 movs r3, #0
8005a06: 9303 str r3, [sp, #12]
8005a08: 69fb ldr r3, [r7, #28]
8005a0a: 9302 str r3, [sp, #8]
8005a0c: 6afb ldr r3, [r7, #44] @ 0x2c
8005a0e: 9301 str r3, [sp, #4]
8005a10: 6abb ldr r3, [r7, #40] @ 0x28
8005a12: 9300 str r3, [sp, #0]
8005a14: 683b ldr r3, [r7, #0]
8005a16: 68b9 ldr r1, [r7, #8]
8005a18: 68f8 ldr r0, [r7, #12]
8005a1a: f000 f80f bl 8005a3c <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
8005a1e: 69f8 ldr r0, [r7, #28]
8005a20: f000 f8b8 bl 8005b94 <prvAddNewTaskToReadyList>
xReturn = pdPASS;
8005a24: 2301 movs r3, #1
8005a26: 61bb str r3, [r7, #24]
8005a28: e002 b.n 8005a30 <xTaskCreate+0x80>
}
else
{
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
8005a2a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
8005a2e: 61bb str r3, [r7, #24]
}
return xReturn;
8005a30: 69bb ldr r3, [r7, #24]
}
8005a32: 4618 mov r0, r3
8005a34: 3720 adds r7, #32
8005a36: 46bd mov sp, r7
8005a38: bd80 pop {r7, pc}
...
08005a3c <prvInitialiseNewTask>:
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask,
TCB_t *pxNewTCB,
const MemoryRegion_t * const xRegions )
{
8005a3c: b580 push {r7, lr}
8005a3e: b088 sub sp, #32
8005a40: af00 add r7, sp, #0
8005a42: 60f8 str r0, [r7, #12]
8005a44: 60b9 str r1, [r7, #8]
8005a46: 607a str r2, [r7, #4]
8005a48: 603b str r3, [r7, #0]
/* Avoid dependency on memset() if it is not required. */
#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
{
/* Fill the stack with a known value to assist debugging. */
( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
8005a4a: 6b3b ldr r3, [r7, #48] @ 0x30
8005a4c: 6b18 ldr r0, [r3, #48] @ 0x30
8005a4e: 687b ldr r3, [r7, #4]
8005a50: 009b lsls r3, r3, #2
8005a52: 461a mov r2, r3
8005a54: 21a5 movs r1, #165 @ 0xa5
8005a56: f002 f85e bl 8007b16 <memset>
grows from high memory to low (as per the 80x86) or vice versa.
portSTACK_GROWTH is used to make the result positive or negative as required
by the port. */
#if( portSTACK_GROWTH < 0 )
{
pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
8005a5a: 6b3b ldr r3, [r7, #48] @ 0x30
8005a5c: 6b1a ldr r2, [r3, #48] @ 0x30
8005a5e: 6879 ldr r1, [r7, #4]
8005a60: f06f 4340 mvn.w r3, #3221225472 @ 0xc0000000
8005a64: 440b add r3, r1
8005a66: 009b lsls r3, r3, #2
8005a68: 4413 add r3, r2
8005a6a: 61bb str r3, [r7, #24]
pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
8005a6c: 69bb ldr r3, [r7, #24]
8005a6e: f023 0307 bic.w r3, r3, #7
8005a72: 61bb str r3, [r7, #24]
/* Check the alignment of the calculated top of stack is correct. */
configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
8005a74: 69bb ldr r3, [r7, #24]
8005a76: f003 0307 and.w r3, r3, #7
8005a7a: 2b00 cmp r3, #0
8005a7c: d00d beq.n 8005a9a <prvInitialiseNewTask+0x5e>
__asm volatile
8005a7e: f04f 0350 mov.w r3, #80 @ 0x50
8005a82: b672 cpsid i
8005a84: f383 8811 msr BASEPRI, r3
8005a88: f3bf 8f6f isb sy
8005a8c: f3bf 8f4f dsb sy
8005a90: b662 cpsie i
8005a92: 617b str r3, [r7, #20]
}
8005a94: bf00 nop
8005a96: bf00 nop
8005a98: e7fd b.n 8005a96 <prvInitialiseNewTask+0x5a>
pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
}
#endif /* portSTACK_GROWTH */
/* Store the task name in the TCB. */
if( pcName != NULL )
8005a9a: 68bb ldr r3, [r7, #8]
8005a9c: 2b00 cmp r3, #0
8005a9e: d01f beq.n 8005ae0 <prvInitialiseNewTask+0xa4>
{
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
8005aa0: 2300 movs r3, #0
8005aa2: 61fb str r3, [r7, #28]
8005aa4: e012 b.n 8005acc <prvInitialiseNewTask+0x90>
{
pxNewTCB->pcTaskName[ x ] = pcName[ x ];
8005aa6: 68ba ldr r2, [r7, #8]
8005aa8: 69fb ldr r3, [r7, #28]
8005aaa: 4413 add r3, r2
8005aac: 7819 ldrb r1, [r3, #0]
8005aae: 6b3a ldr r2, [r7, #48] @ 0x30
8005ab0: 69fb ldr r3, [r7, #28]
8005ab2: 4413 add r3, r2
8005ab4: 3334 adds r3, #52 @ 0x34
8005ab6: 460a mov r2, r1
8005ab8: 701a strb r2, [r3, #0]
/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
configMAX_TASK_NAME_LEN characters just in case the memory after the
string is not accessible (extremely unlikely). */
if( pcName[ x ] == ( char ) 0x00 )
8005aba: 68ba ldr r2, [r7, #8]
8005abc: 69fb ldr r3, [r7, #28]
8005abe: 4413 add r3, r2
8005ac0: 781b ldrb r3, [r3, #0]
8005ac2: 2b00 cmp r3, #0
8005ac4: d006 beq.n 8005ad4 <prvInitialiseNewTask+0x98>
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
8005ac6: 69fb ldr r3, [r7, #28]
8005ac8: 3301 adds r3, #1
8005aca: 61fb str r3, [r7, #28]
8005acc: 69fb ldr r3, [r7, #28]
8005ace: 2b0f cmp r3, #15
8005ad0: d9e9 bls.n 8005aa6 <prvInitialiseNewTask+0x6a>
8005ad2: e000 b.n 8005ad6 <prvInitialiseNewTask+0x9a>
{
break;
8005ad4: bf00 nop
}
}
/* Ensure the name string is terminated in the case that the string length
was greater or equal to configMAX_TASK_NAME_LEN. */
pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
8005ad6: 6b3b ldr r3, [r7, #48] @ 0x30
8005ad8: 2200 movs r2, #0
8005ada: f883 2043 strb.w r2, [r3, #67] @ 0x43
8005ade: e003 b.n 8005ae8 <prvInitialiseNewTask+0xac>
}
else
{
/* The task has not been given a name, so just ensure there is a NULL
terminator when it is read out. */
pxNewTCB->pcTaskName[ 0 ] = 0x00;
8005ae0: 6b3b ldr r3, [r7, #48] @ 0x30
8005ae2: 2200 movs r2, #0
8005ae4: f883 2034 strb.w r2, [r3, #52] @ 0x34
}
/* This is used as an array index so must ensure it's not too large. First
remove the privilege bit if one is present. */
if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
8005ae8: 6abb ldr r3, [r7, #40] @ 0x28
8005aea: 2b06 cmp r3, #6
8005aec: d901 bls.n 8005af2 <prvInitialiseNewTask+0xb6>
{
uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
8005aee: 2306 movs r3, #6
8005af0: 62bb str r3, [r7, #40] @ 0x28
else
{
mtCOVERAGE_TEST_MARKER();
}
pxNewTCB->uxPriority = uxPriority;
8005af2: 6b3b ldr r3, [r7, #48] @ 0x30
8005af4: 6aba ldr r2, [r7, #40] @ 0x28
8005af6: 62da str r2, [r3, #44] @ 0x2c
#if ( configUSE_MUTEXES == 1 )
{
pxNewTCB->uxBasePriority = uxPriority;
8005af8: 6b3b ldr r3, [r7, #48] @ 0x30
8005afa: 6aba ldr r2, [r7, #40] @ 0x28
8005afc: 64da str r2, [r3, #76] @ 0x4c
pxNewTCB->uxMutexesHeld = 0;
8005afe: 6b3b ldr r3, [r7, #48] @ 0x30
8005b00: 2200 movs r2, #0
8005b02: 651a str r2, [r3, #80] @ 0x50
}
#endif /* configUSE_MUTEXES */
vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
8005b04: 6b3b ldr r3, [r7, #48] @ 0x30
8005b06: 3304 adds r3, #4
8005b08: 4618 mov r0, r3
8005b0a: f7ff f920 bl 8004d4e <vListInitialiseItem>
vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
8005b0e: 6b3b ldr r3, [r7, #48] @ 0x30
8005b10: 3318 adds r3, #24
8005b12: 4618 mov r0, r3
8005b14: f7ff f91b bl 8004d4e <vListInitialiseItem>
/* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get
back to the containing TCB from a generic item in a list. */
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
8005b18: 6b3b ldr r3, [r7, #48] @ 0x30
8005b1a: 6b3a ldr r2, [r7, #48] @ 0x30
8005b1c: 611a str r2, [r3, #16]
/* Event lists are always in priority order. */
listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8005b1e: 6abb ldr r3, [r7, #40] @ 0x28
8005b20: f1c3 0207 rsb r2, r3, #7
8005b24: 6b3b ldr r3, [r7, #48] @ 0x30
8005b26: 619a str r2, [r3, #24]
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
8005b28: 6b3b ldr r3, [r7, #48] @ 0x30
8005b2a: 6b3a ldr r2, [r7, #48] @ 0x30
8005b2c: 625a str r2, [r3, #36] @ 0x24
}
#endif /* configUSE_APPLICATION_TASK_TAG */
#if ( configGENERATE_RUN_TIME_STATS == 1 )
{
pxNewTCB->ulRunTimeCounter = 0UL;
8005b2e: 6b3b ldr r3, [r7, #48] @ 0x30
8005b30: 2200 movs r2, #0
8005b32: 655a str r2, [r3, #84] @ 0x54
}
#endif
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
{
pxNewTCB->ulNotifiedValue = 0;
8005b34: 6b3b ldr r3, [r7, #48] @ 0x30
8005b36: 2200 movs r2, #0
8005b38: f8c3 20a4 str.w r2, [r3, #164] @ 0xa4
pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
8005b3c: 6b3b ldr r3, [r7, #48] @ 0x30
8005b3e: 2200 movs r2, #0
8005b40: f883 20a8 strb.w r2, [r3, #168] @ 0xa8
#endif
#if ( configUSE_NEWLIB_REENTRANT == 1 )
{
/* Initialise this task's Newlib reent structure. */
_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
8005b44: 6b3b ldr r3, [r7, #48] @ 0x30
8005b46: 3358 adds r3, #88 @ 0x58
8005b48: 224c movs r2, #76 @ 0x4c
8005b4a: 2100 movs r1, #0
8005b4c: 4618 mov r0, r3
8005b4e: f001 ffe2 bl 8007b16 <memset>
8005b52: 6b3b ldr r3, [r7, #48] @ 0x30
8005b54: 4a0c ldr r2, [pc, #48] @ (8005b88 <prvInitialiseNewTask+0x14c>)
8005b56: 65da str r2, [r3, #92] @ 0x5c
8005b58: 6b3b ldr r3, [r7, #48] @ 0x30
8005b5a: 4a0c ldr r2, [pc, #48] @ (8005b8c <prvInitialiseNewTask+0x150>)
8005b5c: 661a str r2, [r3, #96] @ 0x60
8005b5e: 6b3b ldr r3, [r7, #48] @ 0x30
8005b60: 4a0b ldr r2, [pc, #44] @ (8005b90 <prvInitialiseNewTask+0x154>)
8005b62: 665a str r2, [r3, #100] @ 0x64
}
#endif /* portSTACK_GROWTH */
}
#else /* portHAS_STACK_OVERFLOW_CHECKING */
{
pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
8005b64: 683a ldr r2, [r7, #0]
8005b66: 68f9 ldr r1, [r7, #12]
8005b68: 69b8 ldr r0, [r7, #24]
8005b6a: f001 f94d bl 8006e08 <pxPortInitialiseStack>
8005b6e: 4602 mov r2, r0
8005b70: 6b3b ldr r3, [r7, #48] @ 0x30
8005b72: 601a str r2, [r3, #0]
}
#endif /* portHAS_STACK_OVERFLOW_CHECKING */
}
#endif /* portUSING_MPU_WRAPPERS */
if( pxCreatedTask != NULL )
8005b74: 6afb ldr r3, [r7, #44] @ 0x2c
8005b76: 2b00 cmp r3, #0
8005b78: d002 beq.n 8005b80 <prvInitialiseNewTask+0x144>
{
/* Pass the handle out in an anonymous way. The handle can be used to
change the created task's priority, delete the created task, etc.*/
*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
8005b7a: 6afb ldr r3, [r7, #44] @ 0x2c
8005b7c: 6b3a ldr r2, [r7, #48] @ 0x30
8005b7e: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8005b80: bf00 nop
8005b82: 3720 adds r7, #32
8005b84: 46bd mov sp, r7
8005b86: bd80 pop {r7, pc}
8005b88: 20008cec .word 0x20008cec
8005b8c: 20008d54 .word 0x20008d54
8005b90: 20008dbc .word 0x20008dbc
08005b94 <prvAddNewTaskToReadyList>:
/*-----------------------------------------------------------*/
static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
{
8005b94: b580 push {r7, lr}
8005b96: b082 sub sp, #8
8005b98: af00 add r7, sp, #0
8005b9a: 6078 str r0, [r7, #4]
/* Ensure interrupts don't access the task lists while the lists are being
updated. */
taskENTER_CRITICAL();
8005b9c: f001 fa46 bl 800702c <vPortEnterCritical>
{
uxCurrentNumberOfTasks++;
8005ba0: 4b2c ldr r3, [pc, #176] @ (8005c54 <prvAddNewTaskToReadyList+0xc0>)
8005ba2: 681b ldr r3, [r3, #0]
8005ba4: 3301 adds r3, #1
8005ba6: 4a2b ldr r2, [pc, #172] @ (8005c54 <prvAddNewTaskToReadyList+0xc0>)
8005ba8: 6013 str r3, [r2, #0]
if( pxCurrentTCB == NULL )
8005baa: 4b2b ldr r3, [pc, #172] @ (8005c58 <prvAddNewTaskToReadyList+0xc4>)
8005bac: 681b ldr r3, [r3, #0]
8005bae: 2b00 cmp r3, #0
8005bb0: d109 bne.n 8005bc6 <prvAddNewTaskToReadyList+0x32>
{
/* There are no other tasks, or all the other tasks are in
the suspended state - make this the current task. */
pxCurrentTCB = pxNewTCB;
8005bb2: 4a29 ldr r2, [pc, #164] @ (8005c58 <prvAddNewTaskToReadyList+0xc4>)
8005bb4: 687b ldr r3, [r7, #4]
8005bb6: 6013 str r3, [r2, #0]
if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
8005bb8: 4b26 ldr r3, [pc, #152] @ (8005c54 <prvAddNewTaskToReadyList+0xc0>)
8005bba: 681b ldr r3, [r3, #0]
8005bbc: 2b01 cmp r3, #1
8005bbe: d110 bne.n 8005be2 <prvAddNewTaskToReadyList+0x4e>
{
/* This is the first task to be created so do the preliminary
initialisation required. We will not recover if this call
fails, but we will report the failure. */
prvInitialiseTaskLists();
8005bc0: f000 fd44 bl 800664c <prvInitialiseTaskLists>
8005bc4: e00d b.n 8005be2 <prvAddNewTaskToReadyList+0x4e>
else
{
/* If the scheduler is not already running, make this task the
current task if it is the highest priority task to be created
so far. */
if( xSchedulerRunning == pdFALSE )
8005bc6: 4b25 ldr r3, [pc, #148] @ (8005c5c <prvAddNewTaskToReadyList+0xc8>)
8005bc8: 681b ldr r3, [r3, #0]
8005bca: 2b00 cmp r3, #0
8005bcc: d109 bne.n 8005be2 <prvAddNewTaskToReadyList+0x4e>
{
if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
8005bce: 4b22 ldr r3, [pc, #136] @ (8005c58 <prvAddNewTaskToReadyList+0xc4>)
8005bd0: 681b ldr r3, [r3, #0]
8005bd2: 6ada ldr r2, [r3, #44] @ 0x2c
8005bd4: 687b ldr r3, [r7, #4]
8005bd6: 6adb ldr r3, [r3, #44] @ 0x2c
8005bd8: 429a cmp r2, r3
8005bda: d802 bhi.n 8005be2 <prvAddNewTaskToReadyList+0x4e>
{
pxCurrentTCB = pxNewTCB;
8005bdc: 4a1e ldr r2, [pc, #120] @ (8005c58 <prvAddNewTaskToReadyList+0xc4>)
8005bde: 687b ldr r3, [r7, #4]
8005be0: 6013 str r3, [r2, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
uxTaskNumber++;
8005be2: 4b1f ldr r3, [pc, #124] @ (8005c60 <prvAddNewTaskToReadyList+0xcc>)
8005be4: 681b ldr r3, [r3, #0]
8005be6: 3301 adds r3, #1
8005be8: 4a1d ldr r2, [pc, #116] @ (8005c60 <prvAddNewTaskToReadyList+0xcc>)
8005bea: 6013 str r3, [r2, #0]
#if ( configUSE_TRACE_FACILITY == 1 )
{
/* Add a counter into the TCB for tracing only. */
pxNewTCB->uxTCBNumber = uxTaskNumber;
8005bec: 4b1c ldr r3, [pc, #112] @ (8005c60 <prvAddNewTaskToReadyList+0xcc>)
8005bee: 681a ldr r2, [r3, #0]
8005bf0: 687b ldr r3, [r7, #4]
8005bf2: 645a str r2, [r3, #68] @ 0x44
}
#endif /* configUSE_TRACE_FACILITY */
traceTASK_CREATE( pxNewTCB );
prvAddTaskToReadyList( pxNewTCB );
8005bf4: 687b ldr r3, [r7, #4]
8005bf6: 6adb ldr r3, [r3, #44] @ 0x2c
8005bf8: 2201 movs r2, #1
8005bfa: 409a lsls r2, r3
8005bfc: 4b19 ldr r3, [pc, #100] @ (8005c64 <prvAddNewTaskToReadyList+0xd0>)
8005bfe: 681b ldr r3, [r3, #0]
8005c00: 4313 orrs r3, r2
8005c02: 4a18 ldr r2, [pc, #96] @ (8005c64 <prvAddNewTaskToReadyList+0xd0>)
8005c04: 6013 str r3, [r2, #0]
8005c06: 687b ldr r3, [r7, #4]
8005c08: 6ada ldr r2, [r3, #44] @ 0x2c
8005c0a: 4613 mov r3, r2
8005c0c: 009b lsls r3, r3, #2
8005c0e: 4413 add r3, r2
8005c10: 009b lsls r3, r3, #2
8005c12: 4a15 ldr r2, [pc, #84] @ (8005c68 <prvAddNewTaskToReadyList+0xd4>)
8005c14: 441a add r2, r3
8005c16: 687b ldr r3, [r7, #4]
8005c18: 3304 adds r3, #4
8005c1a: 4619 mov r1, r3
8005c1c: 4610 mov r0, r2
8005c1e: f7ff f8a3 bl 8004d68 <vListInsertEnd>
portSETUP_TCB( pxNewTCB );
}
taskEXIT_CRITICAL();
8005c22: f001 fa39 bl 8007098 <vPortExitCritical>
if( xSchedulerRunning != pdFALSE )
8005c26: 4b0d ldr r3, [pc, #52] @ (8005c5c <prvAddNewTaskToReadyList+0xc8>)
8005c28: 681b ldr r3, [r3, #0]
8005c2a: 2b00 cmp r3, #0
8005c2c: d00e beq.n 8005c4c <prvAddNewTaskToReadyList+0xb8>
{
/* If the created task is of a higher priority than the current task
then it should run now. */
if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
8005c2e: 4b0a ldr r3, [pc, #40] @ (8005c58 <prvAddNewTaskToReadyList+0xc4>)
8005c30: 681b ldr r3, [r3, #0]
8005c32: 6ada ldr r2, [r3, #44] @ 0x2c
8005c34: 687b ldr r3, [r7, #4]
8005c36: 6adb ldr r3, [r3, #44] @ 0x2c
8005c38: 429a cmp r2, r3
8005c3a: d207 bcs.n 8005c4c <prvAddNewTaskToReadyList+0xb8>
{
taskYIELD_IF_USING_PREEMPTION();
8005c3c: 4b0b ldr r3, [pc, #44] @ (8005c6c <prvAddNewTaskToReadyList+0xd8>)
8005c3e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8005c42: 601a str r2, [r3, #0]
8005c44: f3bf 8f4f dsb sy
8005c48: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8005c4c: bf00 nop
8005c4e: 3708 adds r7, #8
8005c50: 46bd mov sp, r7
8005c52: bd80 pop {r7, pc}
8005c54: 20000c98 .word 0x20000c98
8005c58: 20000b98 .word 0x20000b98
8005c5c: 20000ca4 .word 0x20000ca4
8005c60: 20000cb4 .word 0x20000cb4
8005c64: 20000ca0 .word 0x20000ca0
8005c68: 20000b9c .word 0x20000b9c
8005c6c: e000ed04 .word 0xe000ed04
08005c70 <vTaskDelay>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelay == 1 )
void vTaskDelay( const TickType_t xTicksToDelay )
{
8005c70: b580 push {r7, lr}
8005c72: b084 sub sp, #16
8005c74: af00 add r7, sp, #0
8005c76: 6078 str r0, [r7, #4]
BaseType_t xAlreadyYielded = pdFALSE;
8005c78: 2300 movs r3, #0
8005c7a: 60fb str r3, [r7, #12]
/* A delay time of zero just forces a reschedule. */
if( xTicksToDelay > ( TickType_t ) 0U )
8005c7c: 687b ldr r3, [r7, #4]
8005c7e: 2b00 cmp r3, #0
8005c80: d01a beq.n 8005cb8 <vTaskDelay+0x48>
{
configASSERT( uxSchedulerSuspended == 0 );
8005c82: 4b15 ldr r3, [pc, #84] @ (8005cd8 <vTaskDelay+0x68>)
8005c84: 681b ldr r3, [r3, #0]
8005c86: 2b00 cmp r3, #0
8005c88: d00d beq.n 8005ca6 <vTaskDelay+0x36>
__asm volatile
8005c8a: f04f 0350 mov.w r3, #80 @ 0x50
8005c8e: b672 cpsid i
8005c90: f383 8811 msr BASEPRI, r3
8005c94: f3bf 8f6f isb sy
8005c98: f3bf 8f4f dsb sy
8005c9c: b662 cpsie i
8005c9e: 60bb str r3, [r7, #8]
}
8005ca0: bf00 nop
8005ca2: bf00 nop
8005ca4: e7fd b.n 8005ca2 <vTaskDelay+0x32>
vTaskSuspendAll();
8005ca6: f000 f8f7 bl 8005e98 <vTaskSuspendAll>
list or removed from the blocked list until the scheduler
is resumed.
This task cannot be in an event list as it is the currently
executing task. */
prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
8005caa: 2100 movs r1, #0
8005cac: 6878 ldr r0, [r7, #4]
8005cae: f001 f845 bl 8006d3c <prvAddCurrentTaskToDelayedList>
}
xAlreadyYielded = xTaskResumeAll();
8005cb2: f000 f8ff bl 8005eb4 <xTaskResumeAll>
8005cb6: 60f8 str r0, [r7, #12]
mtCOVERAGE_TEST_MARKER();
}
/* Force a reschedule if xTaskResumeAll has not already done so, we may
have put ourselves to sleep. */
if( xAlreadyYielded == pdFALSE )
8005cb8: 68fb ldr r3, [r7, #12]
8005cba: 2b00 cmp r3, #0
8005cbc: d107 bne.n 8005cce <vTaskDelay+0x5e>
{
portYIELD_WITHIN_API();
8005cbe: 4b07 ldr r3, [pc, #28] @ (8005cdc <vTaskDelay+0x6c>)
8005cc0: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8005cc4: 601a str r2, [r3, #0]
8005cc6: f3bf 8f4f dsb sy
8005cca: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8005cce: bf00 nop
8005cd0: 3710 adds r7, #16
8005cd2: 46bd mov sp, r7
8005cd4: bd80 pop {r7, pc}
8005cd6: bf00 nop
8005cd8: 20000cc0 .word 0x20000cc0
8005cdc: e000ed04 .word 0xe000ed04
08005ce0 <eTaskGetState>:
/*-----------------------------------------------------------*/
#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
eTaskState eTaskGetState( TaskHandle_t xTask )
{
8005ce0: b580 push {r7, lr}
8005ce2: b088 sub sp, #32
8005ce4: af00 add r7, sp, #0
8005ce6: 6078 str r0, [r7, #4]
eTaskState eReturn;
List_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;
const TCB_t * const pxTCB = xTask;
8005ce8: 687b ldr r3, [r7, #4]
8005cea: 61bb str r3, [r7, #24]
configASSERT( pxTCB );
8005cec: 69bb ldr r3, [r7, #24]
8005cee: 2b00 cmp r3, #0
8005cf0: d10d bne.n 8005d0e <eTaskGetState+0x2e>
__asm volatile
8005cf2: f04f 0350 mov.w r3, #80 @ 0x50
8005cf6: b672 cpsid i
8005cf8: f383 8811 msr BASEPRI, r3
8005cfc: f3bf 8f6f isb sy
8005d00: f3bf 8f4f dsb sy
8005d04: b662 cpsie i
8005d06: 60bb str r3, [r7, #8]
}
8005d08: bf00 nop
8005d0a: bf00 nop
8005d0c: e7fd b.n 8005d0a <eTaskGetState+0x2a>
if( pxTCB == pxCurrentTCB )
8005d0e: 4b24 ldr r3, [pc, #144] @ (8005da0 <eTaskGetState+0xc0>)
8005d10: 681b ldr r3, [r3, #0]
8005d12: 69ba ldr r2, [r7, #24]
8005d14: 429a cmp r2, r3
8005d16: d102 bne.n 8005d1e <eTaskGetState+0x3e>
{
/* The task calling this function is querying its own state. */
eReturn = eRunning;
8005d18: 2300 movs r3, #0
8005d1a: 77fb strb r3, [r7, #31]
8005d1c: e03a b.n 8005d94 <eTaskGetState+0xb4>
}
else
{
taskENTER_CRITICAL();
8005d1e: f001 f985 bl 800702c <vPortEnterCritical>
{
pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
8005d22: 69bb ldr r3, [r7, #24]
8005d24: 695b ldr r3, [r3, #20]
8005d26: 617b str r3, [r7, #20]
pxDelayedList = pxDelayedTaskList;
8005d28: 4b1e ldr r3, [pc, #120] @ (8005da4 <eTaskGetState+0xc4>)
8005d2a: 681b ldr r3, [r3, #0]
8005d2c: 613b str r3, [r7, #16]
pxOverflowedDelayedList = pxOverflowDelayedTaskList;
8005d2e: 4b1e ldr r3, [pc, #120] @ (8005da8 <eTaskGetState+0xc8>)
8005d30: 681b ldr r3, [r3, #0]
8005d32: 60fb str r3, [r7, #12]
}
taskEXIT_CRITICAL();
8005d34: f001 f9b0 bl 8007098 <vPortExitCritical>
if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
8005d38: 697a ldr r2, [r7, #20]
8005d3a: 693b ldr r3, [r7, #16]
8005d3c: 429a cmp r2, r3
8005d3e: d003 beq.n 8005d48 <eTaskGetState+0x68>
8005d40: 697a ldr r2, [r7, #20]
8005d42: 68fb ldr r3, [r7, #12]
8005d44: 429a cmp r2, r3
8005d46: d102 bne.n 8005d4e <eTaskGetState+0x6e>
{
/* The task being queried is referenced from one of the Blocked
lists. */
eReturn = eBlocked;
8005d48: 2302 movs r3, #2
8005d4a: 77fb strb r3, [r7, #31]
8005d4c: e022 b.n 8005d94 <eTaskGetState+0xb4>
}
#if ( INCLUDE_vTaskSuspend == 1 )
else if( pxStateList == &xSuspendedTaskList )
8005d4e: 697b ldr r3, [r7, #20]
8005d50: 4a16 ldr r2, [pc, #88] @ (8005dac <eTaskGetState+0xcc>)
8005d52: 4293 cmp r3, r2
8005d54: d112 bne.n 8005d7c <eTaskGetState+0x9c>
{
/* The task being queried is referenced from the suspended
list. Is it genuinely suspended or is it blocked
indefinitely? */
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
8005d56: 69bb ldr r3, [r7, #24]
8005d58: 6a9b ldr r3, [r3, #40] @ 0x28
8005d5a: 2b00 cmp r3, #0
8005d5c: d10b bne.n 8005d76 <eTaskGetState+0x96>
{
/* The task does not appear on the event list item of
and of the RTOS objects, but could still be in the
blocked state if it is waiting on its notification
rather than waiting on an object. */
if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
8005d5e: 69bb ldr r3, [r7, #24]
8005d60: f893 30a8 ldrb.w r3, [r3, #168] @ 0xa8
8005d64: b2db uxtb r3, r3
8005d66: 2b01 cmp r3, #1
8005d68: d102 bne.n 8005d70 <eTaskGetState+0x90>
{
eReturn = eBlocked;
8005d6a: 2302 movs r3, #2
8005d6c: 77fb strb r3, [r7, #31]
8005d6e: e011 b.n 8005d94 <eTaskGetState+0xb4>
}
else
{
eReturn = eSuspended;
8005d70: 2303 movs r3, #3
8005d72: 77fb strb r3, [r7, #31]
8005d74: e00e b.n 8005d94 <eTaskGetState+0xb4>
}
#endif
}
else
{
eReturn = eBlocked;
8005d76: 2302 movs r3, #2
8005d78: 77fb strb r3, [r7, #31]
8005d7a: e00b b.n 8005d94 <eTaskGetState+0xb4>
}
}
#endif
#if ( INCLUDE_vTaskDelete == 1 )
else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
8005d7c: 697b ldr r3, [r7, #20]
8005d7e: 4a0c ldr r2, [pc, #48] @ (8005db0 <eTaskGetState+0xd0>)
8005d80: 4293 cmp r3, r2
8005d82: d002 beq.n 8005d8a <eTaskGetState+0xaa>
8005d84: 697b ldr r3, [r7, #20]
8005d86: 2b00 cmp r3, #0
8005d88: d102 bne.n 8005d90 <eTaskGetState+0xb0>
{
/* The task being queried is referenced from the deleted
tasks list, or it is not referenced from any lists at
all. */
eReturn = eDeleted;
8005d8a: 2304 movs r3, #4
8005d8c: 77fb strb r3, [r7, #31]
8005d8e: e001 b.n 8005d94 <eTaskGetState+0xb4>
else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
{
/* If the task is not in any other state, it must be in the
Ready (including pending ready) state. */
eReturn = eReady;
8005d90: 2301 movs r3, #1
8005d92: 77fb strb r3, [r7, #31]
}
}
return eReturn;
8005d94: 7ffb ldrb r3, [r7, #31]
} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
8005d96: 4618 mov r0, r3
8005d98: 3720 adds r7, #32
8005d9a: 46bd mov sp, r7
8005d9c: bd80 pop {r7, pc}
8005d9e: bf00 nop
8005da0: 20000b98 .word 0x20000b98
8005da4: 20000c50 .word 0x20000c50
8005da8: 20000c54 .word 0x20000c54
8005dac: 20000c84 .word 0x20000c84
8005db0: 20000c6c .word 0x20000c6c
08005db4 <vTaskStartScheduler>:
#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
/*-----------------------------------------------------------*/
void vTaskStartScheduler( void )
{
8005db4: b580 push {r7, lr}
8005db6: b08a sub sp, #40 @ 0x28
8005db8: af04 add r7, sp, #16
BaseType_t xReturn;
/* Add the idle task at the lowest priority. */
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
{
StaticTask_t *pxIdleTaskTCBBuffer = NULL;
8005dba: 2300 movs r3, #0
8005dbc: 60bb str r3, [r7, #8]
StackType_t *pxIdleTaskStackBuffer = NULL;
8005dbe: 2300 movs r3, #0
8005dc0: 607b str r3, [r7, #4]
uint32_t ulIdleTaskStackSize;
/* The Idle task is created using user provided RAM - obtain the
address of the RAM then create the idle task. */
vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
8005dc2: 463a mov r2, r7
8005dc4: 1d39 adds r1, r7, #4
8005dc6: f107 0308 add.w r3, r7, #8
8005dca: 4618 mov r0, r3
8005dcc: f7fa fdf0 bl 80009b0 <vApplicationGetIdleTaskMemory>
xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
8005dd0: 6839 ldr r1, [r7, #0]
8005dd2: 687b ldr r3, [r7, #4]
8005dd4: 68ba ldr r2, [r7, #8]
8005dd6: 9202 str r2, [sp, #8]
8005dd8: 9301 str r3, [sp, #4]
8005dda: 2300 movs r3, #0
8005ddc: 9300 str r3, [sp, #0]
8005dde: 2300 movs r3, #0
8005de0: 460a mov r2, r1
8005de2: 4925 ldr r1, [pc, #148] @ (8005e78 <vTaskStartScheduler+0xc4>)
8005de4: 4825 ldr r0, [pc, #148] @ (8005e7c <vTaskStartScheduler+0xc8>)
8005de6: f7ff fd7d bl 80058e4 <xTaskCreateStatic>
8005dea: 4603 mov r3, r0
8005dec: 4a24 ldr r2, [pc, #144] @ (8005e80 <vTaskStartScheduler+0xcc>)
8005dee: 6013 str r3, [r2, #0]
( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
pxIdleTaskStackBuffer,
pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
if( xIdleTaskHandle != NULL )
8005df0: 4b23 ldr r3, [pc, #140] @ (8005e80 <vTaskStartScheduler+0xcc>)
8005df2: 681b ldr r3, [r3, #0]
8005df4: 2b00 cmp r3, #0
8005df6: d002 beq.n 8005dfe <vTaskStartScheduler+0x4a>
{
xReturn = pdPASS;
8005df8: 2301 movs r3, #1
8005dfa: 617b str r3, [r7, #20]
8005dfc: e001 b.n 8005e02 <vTaskStartScheduler+0x4e>
}
else
{
xReturn = pdFAIL;
8005dfe: 2300 movs r3, #0
8005e00: 617b str r3, [r7, #20]
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_TIMERS */
if( xReturn == pdPASS )
8005e02: 697b ldr r3, [r7, #20]
8005e04: 2b01 cmp r3, #1
8005e06: d121 bne.n 8005e4c <vTaskStartScheduler+0x98>
__asm volatile
8005e08: f04f 0350 mov.w r3, #80 @ 0x50
8005e0c: b672 cpsid i
8005e0e: f383 8811 msr BASEPRI, r3
8005e12: f3bf 8f6f isb sy
8005e16: f3bf 8f4f dsb sy
8005e1a: b662 cpsie i
8005e1c: 613b str r3, [r7, #16]
}
8005e1e: bf00 nop
#if ( configUSE_NEWLIB_REENTRANT == 1 )
{
/* Switch Newlib's _impure_ptr variable to point to the _reent
structure specific to the task that will run first. */
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
8005e20: 4b18 ldr r3, [pc, #96] @ (8005e84 <vTaskStartScheduler+0xd0>)
8005e22: 681b ldr r3, [r3, #0]
8005e24: 3358 adds r3, #88 @ 0x58
8005e26: 4a18 ldr r2, [pc, #96] @ (8005e88 <vTaskStartScheduler+0xd4>)
8005e28: 6013 str r3, [r2, #0]
}
#endif /* configUSE_NEWLIB_REENTRANT */
xNextTaskUnblockTime = portMAX_DELAY;
8005e2a: 4b18 ldr r3, [pc, #96] @ (8005e8c <vTaskStartScheduler+0xd8>)
8005e2c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8005e30: 601a str r2, [r3, #0]
xSchedulerRunning = pdTRUE;
8005e32: 4b17 ldr r3, [pc, #92] @ (8005e90 <vTaskStartScheduler+0xdc>)
8005e34: 2201 movs r2, #1
8005e36: 601a str r2, [r3, #0]
xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
8005e38: 4b16 ldr r3, [pc, #88] @ (8005e94 <vTaskStartScheduler+0xe0>)
8005e3a: 2200 movs r2, #0
8005e3c: 601a str r2, [r3, #0]
macro must be defined to configure the timer/counter used to generate
the run time counter time base. NOTE: If configGENERATE_RUN_TIME_STATS
is set to 0 and the following line fails to build then ensure you do not
have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
FreeRTOSConfig.h file. */
portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
8005e3e: f7fa fda9 bl 8000994 <configureTimerForRunTimeStats>
traceTASK_SWITCHED_IN();
8005e42: f7fb ff59 bl 8001cf8 <Usage_TaskSwitchedIn>
/* Setting up the timer tick is hardware specific and thus in the
portable interface. */
if( xPortStartScheduler() != pdFALSE )
8005e46: f001 f873 bl 8006f30 <xPortStartScheduler>
}
/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
meaning xIdleTaskHandle is not used anywhere else. */
( void ) xIdleTaskHandle;
}
8005e4a: e011 b.n 8005e70 <vTaskStartScheduler+0xbc>
configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
8005e4c: 697b ldr r3, [r7, #20]
8005e4e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8005e52: d10d bne.n 8005e70 <vTaskStartScheduler+0xbc>
__asm volatile
8005e54: f04f 0350 mov.w r3, #80 @ 0x50
8005e58: b672 cpsid i
8005e5a: f383 8811 msr BASEPRI, r3
8005e5e: f3bf 8f6f isb sy
8005e62: f3bf 8f4f dsb sy
8005e66: b662 cpsie i
8005e68: 60fb str r3, [r7, #12]
}
8005e6a: bf00 nop
8005e6c: bf00 nop
8005e6e: e7fd b.n 8005e6c <vTaskStartScheduler+0xb8>
}
8005e70: bf00 nop
8005e72: 3718 adds r7, #24
8005e74: 46bd mov sp, r7
8005e76: bd80 pop {r7, pc}
8005e78: 080089bc .word 0x080089bc
8005e7c: 0800661d .word 0x0800661d
8005e80: 20000cbc .word 0x20000cbc
8005e84: 20000b98 .word 0x20000b98
8005e88: 2000001c .word 0x2000001c
8005e8c: 20000cb8 .word 0x20000cb8
8005e90: 20000ca4 .word 0x20000ca4
8005e94: 20000c9c .word 0x20000c9c
08005e98 <vTaskSuspendAll>:
vPortEndScheduler();
}
/*----------------------------------------------------------*/
void vTaskSuspendAll( void )
{
8005e98: b480 push {r7}
8005e9a: af00 add r7, sp, #0
/* A critical section is not required as the variable is of type
BaseType_t. Please read Richard Barry's reply in the following link to a
post in the FreeRTOS support forum before reporting this as a bug! -
http://goo.gl/wu4acr */
++uxSchedulerSuspended;
8005e9c: 4b04 ldr r3, [pc, #16] @ (8005eb0 <vTaskSuspendAll+0x18>)
8005e9e: 681b ldr r3, [r3, #0]
8005ea0: 3301 adds r3, #1
8005ea2: 4a03 ldr r2, [pc, #12] @ (8005eb0 <vTaskSuspendAll+0x18>)
8005ea4: 6013 str r3, [r2, #0]
portMEMORY_BARRIER();
}
8005ea6: bf00 nop
8005ea8: 46bd mov sp, r7
8005eaa: f85d 7b04 ldr.w r7, [sp], #4
8005eae: 4770 bx lr
8005eb0: 20000cc0 .word 0x20000cc0
08005eb4 <xTaskResumeAll>:
#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/
BaseType_t xTaskResumeAll( void )
{
8005eb4: b580 push {r7, lr}
8005eb6: b084 sub sp, #16
8005eb8: af00 add r7, sp, #0
TCB_t *pxTCB = NULL;
8005eba: 2300 movs r3, #0
8005ebc: 60fb str r3, [r7, #12]
BaseType_t xAlreadyYielded = pdFALSE;
8005ebe: 2300 movs r3, #0
8005ec0: 60bb str r3, [r7, #8]
/* If uxSchedulerSuspended is zero then this function does not match a
previous call to vTaskSuspendAll(). */
configASSERT( uxSchedulerSuspended );
8005ec2: 4b43 ldr r3, [pc, #268] @ (8005fd0 <xTaskResumeAll+0x11c>)
8005ec4: 681b ldr r3, [r3, #0]
8005ec6: 2b00 cmp r3, #0
8005ec8: d10d bne.n 8005ee6 <xTaskResumeAll+0x32>
__asm volatile
8005eca: f04f 0350 mov.w r3, #80 @ 0x50
8005ece: b672 cpsid i
8005ed0: f383 8811 msr BASEPRI, r3
8005ed4: f3bf 8f6f isb sy
8005ed8: f3bf 8f4f dsb sy
8005edc: b662 cpsie i
8005ede: 603b str r3, [r7, #0]
}
8005ee0: bf00 nop
8005ee2: bf00 nop
8005ee4: e7fd b.n 8005ee2 <xTaskResumeAll+0x2e>
/* It is possible that an ISR caused a task to be removed from an event
list while the scheduler was suspended. If this was the case then the
removed task will have been added to the xPendingReadyList. Once the
scheduler has been resumed it is safe to move all the pending ready
tasks from this list into their appropriate ready list. */
taskENTER_CRITICAL();
8005ee6: f001 f8a1 bl 800702c <vPortEnterCritical>
{
--uxSchedulerSuspended;
8005eea: 4b39 ldr r3, [pc, #228] @ (8005fd0 <xTaskResumeAll+0x11c>)
8005eec: 681b ldr r3, [r3, #0]
8005eee: 3b01 subs r3, #1
8005ef0: 4a37 ldr r2, [pc, #220] @ (8005fd0 <xTaskResumeAll+0x11c>)
8005ef2: 6013 str r3, [r2, #0]
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8005ef4: 4b36 ldr r3, [pc, #216] @ (8005fd0 <xTaskResumeAll+0x11c>)
8005ef6: 681b ldr r3, [r3, #0]
8005ef8: 2b00 cmp r3, #0
8005efa: d161 bne.n 8005fc0 <xTaskResumeAll+0x10c>
{
if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
8005efc: 4b35 ldr r3, [pc, #212] @ (8005fd4 <xTaskResumeAll+0x120>)
8005efe: 681b ldr r3, [r3, #0]
8005f00: 2b00 cmp r3, #0
8005f02: d05d beq.n 8005fc0 <xTaskResumeAll+0x10c>
{
/* Move any readied tasks from the pending list into the
appropriate ready list. */
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
8005f04: e02e b.n 8005f64 <xTaskResumeAll+0xb0>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8005f06: 4b34 ldr r3, [pc, #208] @ (8005fd8 <xTaskResumeAll+0x124>)
8005f08: 68db ldr r3, [r3, #12]
8005f0a: 68db ldr r3, [r3, #12]
8005f0c: 60fb str r3, [r7, #12]
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
8005f0e: 68fb ldr r3, [r7, #12]
8005f10: 3318 adds r3, #24
8005f12: 4618 mov r0, r3
8005f14: f7fe ff85 bl 8004e22 <uxListRemove>
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
8005f18: 68fb ldr r3, [r7, #12]
8005f1a: 3304 adds r3, #4
8005f1c: 4618 mov r0, r3
8005f1e: f7fe ff80 bl 8004e22 <uxListRemove>
prvAddTaskToReadyList( pxTCB );
8005f22: 68fb ldr r3, [r7, #12]
8005f24: 6adb ldr r3, [r3, #44] @ 0x2c
8005f26: 2201 movs r2, #1
8005f28: 409a lsls r2, r3
8005f2a: 4b2c ldr r3, [pc, #176] @ (8005fdc <xTaskResumeAll+0x128>)
8005f2c: 681b ldr r3, [r3, #0]
8005f2e: 4313 orrs r3, r2
8005f30: 4a2a ldr r2, [pc, #168] @ (8005fdc <xTaskResumeAll+0x128>)
8005f32: 6013 str r3, [r2, #0]
8005f34: 68fb ldr r3, [r7, #12]
8005f36: 6ada ldr r2, [r3, #44] @ 0x2c
8005f38: 4613 mov r3, r2
8005f3a: 009b lsls r3, r3, #2
8005f3c: 4413 add r3, r2
8005f3e: 009b lsls r3, r3, #2
8005f40: 4a27 ldr r2, [pc, #156] @ (8005fe0 <xTaskResumeAll+0x12c>)
8005f42: 441a add r2, r3
8005f44: 68fb ldr r3, [r7, #12]
8005f46: 3304 adds r3, #4
8005f48: 4619 mov r1, r3
8005f4a: 4610 mov r0, r2
8005f4c: f7fe ff0c bl 8004d68 <vListInsertEnd>
/* If the moved task has a priority higher than the current
task then a yield must be performed. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
8005f50: 68fb ldr r3, [r7, #12]
8005f52: 6ada ldr r2, [r3, #44] @ 0x2c
8005f54: 4b23 ldr r3, [pc, #140] @ (8005fe4 <xTaskResumeAll+0x130>)
8005f56: 681b ldr r3, [r3, #0]
8005f58: 6adb ldr r3, [r3, #44] @ 0x2c
8005f5a: 429a cmp r2, r3
8005f5c: d302 bcc.n 8005f64 <xTaskResumeAll+0xb0>
{
xYieldPending = pdTRUE;
8005f5e: 4b22 ldr r3, [pc, #136] @ (8005fe8 <xTaskResumeAll+0x134>)
8005f60: 2201 movs r2, #1
8005f62: 601a str r2, [r3, #0]
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
8005f64: 4b1c ldr r3, [pc, #112] @ (8005fd8 <xTaskResumeAll+0x124>)
8005f66: 681b ldr r3, [r3, #0]
8005f68: 2b00 cmp r3, #0
8005f6a: d1cc bne.n 8005f06 <xTaskResumeAll+0x52>
{
mtCOVERAGE_TEST_MARKER();
}
}
if( pxTCB != NULL )
8005f6c: 68fb ldr r3, [r7, #12]
8005f6e: 2b00 cmp r3, #0
8005f70: d001 beq.n 8005f76 <xTaskResumeAll+0xc2>
which may have prevented the next unblock time from being
re-calculated, in which case re-calculate it now. Mainly
important for low power tickless implementations, where
this can prevent an unnecessary exit from low power
state. */
prvResetNextTaskUnblockTime();
8005f72: f000 fce5 bl 8006940 <prvResetNextTaskUnblockTime>
/* If any ticks occurred while the scheduler was suspended then
they should be processed now. This ensures the tick count does
not slip, and that any delayed tasks are resumed at the correct
time. */
{
UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */
8005f76: 4b1d ldr r3, [pc, #116] @ (8005fec <xTaskResumeAll+0x138>)
8005f78: 681b ldr r3, [r3, #0]
8005f7a: 607b str r3, [r7, #4]
if( uxPendedCounts > ( UBaseType_t ) 0U )
8005f7c: 687b ldr r3, [r7, #4]
8005f7e: 2b00 cmp r3, #0
8005f80: d010 beq.n 8005fa4 <xTaskResumeAll+0xf0>
{
do
{
if( xTaskIncrementTick() != pdFALSE )
8005f82: f000 f8f3 bl 800616c <xTaskIncrementTick>
8005f86: 4603 mov r3, r0
8005f88: 2b00 cmp r3, #0
8005f8a: d002 beq.n 8005f92 <xTaskResumeAll+0xde>
{
xYieldPending = pdTRUE;
8005f8c: 4b16 ldr r3, [pc, #88] @ (8005fe8 <xTaskResumeAll+0x134>)
8005f8e: 2201 movs r2, #1
8005f90: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
--uxPendedCounts;
8005f92: 687b ldr r3, [r7, #4]
8005f94: 3b01 subs r3, #1
8005f96: 607b str r3, [r7, #4]
} while( uxPendedCounts > ( UBaseType_t ) 0U );
8005f98: 687b ldr r3, [r7, #4]
8005f9a: 2b00 cmp r3, #0
8005f9c: d1f1 bne.n 8005f82 <xTaskResumeAll+0xce>
uxPendedTicks = 0;
8005f9e: 4b13 ldr r3, [pc, #76] @ (8005fec <xTaskResumeAll+0x138>)
8005fa0: 2200 movs r2, #0
8005fa2: 601a str r2, [r3, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
if( xYieldPending != pdFALSE )
8005fa4: 4b10 ldr r3, [pc, #64] @ (8005fe8 <xTaskResumeAll+0x134>)
8005fa6: 681b ldr r3, [r3, #0]
8005fa8: 2b00 cmp r3, #0
8005faa: d009 beq.n 8005fc0 <xTaskResumeAll+0x10c>
{
#if( configUSE_PREEMPTION != 0 )
{
xAlreadyYielded = pdTRUE;
8005fac: 2301 movs r3, #1
8005fae: 60bb str r3, [r7, #8]
}
#endif
taskYIELD_IF_USING_PREEMPTION();
8005fb0: 4b0f ldr r3, [pc, #60] @ (8005ff0 <xTaskResumeAll+0x13c>)
8005fb2: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8005fb6: 601a str r2, [r3, #0]
8005fb8: f3bf 8f4f dsb sy
8005fbc: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
8005fc0: f001 f86a bl 8007098 <vPortExitCritical>
return xAlreadyYielded;
8005fc4: 68bb ldr r3, [r7, #8]
}
8005fc6: 4618 mov r0, r3
8005fc8: 3710 adds r7, #16
8005fca: 46bd mov sp, r7
8005fcc: bd80 pop {r7, pc}
8005fce: bf00 nop
8005fd0: 20000cc0 .word 0x20000cc0
8005fd4: 20000c98 .word 0x20000c98
8005fd8: 20000c58 .word 0x20000c58
8005fdc: 20000ca0 .word 0x20000ca0
8005fe0: 20000b9c .word 0x20000b9c
8005fe4: 20000b98 .word 0x20000b98
8005fe8: 20000cac .word 0x20000cac
8005fec: 20000ca8 .word 0x20000ca8
8005ff0: e000ed04 .word 0xe000ed04
08005ff4 <uxTaskGetNumberOfTasks>:
return xReturn;
}
/*-----------------------------------------------------------*/
UBaseType_t uxTaskGetNumberOfTasks( void )
{
8005ff4: b480 push {r7}
8005ff6: af00 add r7, sp, #0
/* A critical section is not required because the variables are of type
BaseType_t. */
return uxCurrentNumberOfTasks;
8005ff8: 4b03 ldr r3, [pc, #12] @ (8006008 <uxTaskGetNumberOfTasks+0x14>)
8005ffa: 681b ldr r3, [r3, #0]
}
8005ffc: 4618 mov r0, r3
8005ffe: 46bd mov sp, r7
8006000: f85d 7b04 ldr.w r7, [sp], #4
8006004: 4770 bx lr
8006006: bf00 nop
8006008: 20000c98 .word 0x20000c98
0800600c <uxTaskGetSystemState>:
/*-----------------------------------------------------------*/
#if ( configUSE_TRACE_FACILITY == 1 )
UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
{
800600c: b580 push {r7, lr}
800600e: b086 sub sp, #24
8006010: af00 add r7, sp, #0
8006012: 60f8 str r0, [r7, #12]
8006014: 60b9 str r1, [r7, #8]
8006016: 607a str r2, [r7, #4]
UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
8006018: 2300 movs r3, #0
800601a: 617b str r3, [r7, #20]
800601c: 2307 movs r3, #7
800601e: 613b str r3, [r7, #16]
vTaskSuspendAll();
8006020: f7ff ff3a bl 8005e98 <vTaskSuspendAll>
{
/* Is there a space in the array for each task in the system? */
if( uxArraySize >= uxCurrentNumberOfTasks )
8006024: 4b3b ldr r3, [pc, #236] @ (8006114 <uxTaskGetSystemState+0x108>)
8006026: 681b ldr r3, [r3, #0]
8006028: 68ba ldr r2, [r7, #8]
800602a: 429a cmp r2, r3
800602c: d36a bcc.n 8006104 <uxTaskGetSystemState+0xf8>
{
/* Fill in an TaskStatus_t structure with information on each
task in the Ready state. */
do
{
uxQueue--;
800602e: 693b ldr r3, [r7, #16]
8006030: 3b01 subs r3, #1
8006032: 613b str r3, [r7, #16]
uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
8006034: 697a ldr r2, [r7, #20]
8006036: 4613 mov r3, r2
8006038: 00db lsls r3, r3, #3
800603a: 4413 add r3, r2
800603c: 009b lsls r3, r3, #2
800603e: 461a mov r2, r3
8006040: 68fb ldr r3, [r7, #12]
8006042: 1898 adds r0, r3, r2
8006044: 693a ldr r2, [r7, #16]
8006046: 4613 mov r3, r2
8006048: 009b lsls r3, r3, #2
800604a: 4413 add r3, r2
800604c: 009b lsls r3, r3, #2
800604e: 4a32 ldr r2, [pc, #200] @ (8006118 <uxTaskGetSystemState+0x10c>)
8006050: 4413 add r3, r2
8006052: 2201 movs r2, #1
8006054: 4619 mov r1, r3
8006056: f000 fbcd bl 80067f4 <prvListTasksWithinSingleList>
800605a: 4602 mov r2, r0
800605c: 697b ldr r3, [r7, #20]
800605e: 4413 add r3, r2
8006060: 617b str r3, [r7, #20]
} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8006062: 693b ldr r3, [r7, #16]
8006064: 2b00 cmp r3, #0
8006066: d1e2 bne.n 800602e <uxTaskGetSystemState+0x22>
/* Fill in an TaskStatus_t structure with information on each
task in the Blocked state. */
uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
8006068: 697a ldr r2, [r7, #20]
800606a: 4613 mov r3, r2
800606c: 00db lsls r3, r3, #3
800606e: 4413 add r3, r2
8006070: 009b lsls r3, r3, #2
8006072: 461a mov r2, r3
8006074: 68fb ldr r3, [r7, #12]
8006076: 4413 add r3, r2
8006078: 4a28 ldr r2, [pc, #160] @ (800611c <uxTaskGetSystemState+0x110>)
800607a: 6811 ldr r1, [r2, #0]
800607c: 2202 movs r2, #2
800607e: 4618 mov r0, r3
8006080: f000 fbb8 bl 80067f4 <prvListTasksWithinSingleList>
8006084: 4602 mov r2, r0
8006086: 697b ldr r3, [r7, #20]
8006088: 4413 add r3, r2
800608a: 617b str r3, [r7, #20]
uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
800608c: 697a ldr r2, [r7, #20]
800608e: 4613 mov r3, r2
8006090: 00db lsls r3, r3, #3
8006092: 4413 add r3, r2
8006094: 009b lsls r3, r3, #2
8006096: 461a mov r2, r3
8006098: 68fb ldr r3, [r7, #12]
800609a: 4413 add r3, r2
800609c: 4a20 ldr r2, [pc, #128] @ (8006120 <uxTaskGetSystemState+0x114>)
800609e: 6811 ldr r1, [r2, #0]
80060a0: 2202 movs r2, #2
80060a2: 4618 mov r0, r3
80060a4: f000 fba6 bl 80067f4 <prvListTasksWithinSingleList>
80060a8: 4602 mov r2, r0
80060aa: 697b ldr r3, [r7, #20]
80060ac: 4413 add r3, r2
80060ae: 617b str r3, [r7, #20]
#if( INCLUDE_vTaskDelete == 1 )
{
/* Fill in an TaskStatus_t structure with information on
each task that has been deleted but not yet cleaned up. */
uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
80060b0: 697a ldr r2, [r7, #20]
80060b2: 4613 mov r3, r2
80060b4: 00db lsls r3, r3, #3
80060b6: 4413 add r3, r2
80060b8: 009b lsls r3, r3, #2
80060ba: 461a mov r2, r3
80060bc: 68fb ldr r3, [r7, #12]
80060be: 4413 add r3, r2
80060c0: 2204 movs r2, #4
80060c2: 4918 ldr r1, [pc, #96] @ (8006124 <uxTaskGetSystemState+0x118>)
80060c4: 4618 mov r0, r3
80060c6: f000 fb95 bl 80067f4 <prvListTasksWithinSingleList>
80060ca: 4602 mov r2, r0
80060cc: 697b ldr r3, [r7, #20]
80060ce: 4413 add r3, r2
80060d0: 617b str r3, [r7, #20]
#if ( INCLUDE_vTaskSuspend == 1 )
{
/* Fill in an TaskStatus_t structure with information on
each task in the Suspended state. */
uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
80060d2: 697a ldr r2, [r7, #20]
80060d4: 4613 mov r3, r2
80060d6: 00db lsls r3, r3, #3
80060d8: 4413 add r3, r2
80060da: 009b lsls r3, r3, #2
80060dc: 461a mov r2, r3
80060de: 68fb ldr r3, [r7, #12]
80060e0: 4413 add r3, r2
80060e2: 2203 movs r2, #3
80060e4: 4910 ldr r1, [pc, #64] @ (8006128 <uxTaskGetSystemState+0x11c>)
80060e6: 4618 mov r0, r3
80060e8: f000 fb84 bl 80067f4 <prvListTasksWithinSingleList>
80060ec: 4602 mov r2, r0
80060ee: 697b ldr r3, [r7, #20]
80060f0: 4413 add r3, r2
80060f2: 617b str r3, [r7, #20]
}
#endif
#if ( configGENERATE_RUN_TIME_STATS == 1)
{
if( pulTotalRunTime != NULL )
80060f4: 687b ldr r3, [r7, #4]
80060f6: 2b00 cmp r3, #0
80060f8: d004 beq.n 8006104 <uxTaskGetSystemState+0xf8>
{
#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
#else
*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
80060fa: f7fa fc52 bl 80009a2 <getRunTimeCounterValue>
80060fe: 4602 mov r2, r0
8006100: 687b ldr r3, [r7, #4]
8006102: 601a str r2, [r3, #0]
else
{
mtCOVERAGE_TEST_MARKER();
}
}
( void ) xTaskResumeAll();
8006104: f7ff fed6 bl 8005eb4 <xTaskResumeAll>
return uxTask;
8006108: 697b ldr r3, [r7, #20]
}
800610a: 4618 mov r0, r3
800610c: 3718 adds r7, #24
800610e: 46bd mov sp, r7
8006110: bd80 pop {r7, pc}
8006112: bf00 nop
8006114: 20000c98 .word 0x20000c98
8006118: 20000b9c .word 0x20000b9c
800611c: 20000c50 .word 0x20000c50
8006120: 20000c54 .word 0x20000c54
8006124: 20000c6c .word 0x20000c6c
8006128: 20000c84 .word 0x20000c84
0800612c <xTaskGetIdleTaskHandle>:
/*----------------------------------------------------------*/
#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
TaskHandle_t xTaskGetIdleTaskHandle( void )
{
800612c: b480 push {r7}
800612e: b083 sub sp, #12
8006130: af00 add r7, sp, #0
/* If xTaskGetIdleTaskHandle() is called before the scheduler has been
started, then xIdleTaskHandle will be NULL. */
configASSERT( ( xIdleTaskHandle != NULL ) );
8006132: 4b0d ldr r3, [pc, #52] @ (8006168 <xTaskGetIdleTaskHandle+0x3c>)
8006134: 681b ldr r3, [r3, #0]
8006136: 2b00 cmp r3, #0
8006138: d10d bne.n 8006156 <xTaskGetIdleTaskHandle+0x2a>
__asm volatile
800613a: f04f 0350 mov.w r3, #80 @ 0x50
800613e: b672 cpsid i
8006140: f383 8811 msr BASEPRI, r3
8006144: f3bf 8f6f isb sy
8006148: f3bf 8f4f dsb sy
800614c: b662 cpsie i
800614e: 607b str r3, [r7, #4]
}
8006150: bf00 nop
8006152: bf00 nop
8006154: e7fd b.n 8006152 <xTaskGetIdleTaskHandle+0x26>
return xIdleTaskHandle;
8006156: 4b04 ldr r3, [pc, #16] @ (8006168 <xTaskGetIdleTaskHandle+0x3c>)
8006158: 681b ldr r3, [r3, #0]
}
800615a: 4618 mov r0, r3
800615c: 370c adds r7, #12
800615e: 46bd mov sp, r7
8006160: f85d 7b04 ldr.w r7, [sp], #4
8006164: 4770 bx lr
8006166: bf00 nop
8006168: 20000cbc .word 0x20000cbc
0800616c <xTaskIncrementTick>:
#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/
BaseType_t xTaskIncrementTick( void )
{
800616c: b580 push {r7, lr}
800616e: b086 sub sp, #24
8006170: af00 add r7, sp, #0
TCB_t * pxTCB;
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
8006172: 2300 movs r3, #0
8006174: 617b str r3, [r7, #20]
/* Called by the portable layer each time a tick interrupt occurs.
Increments the tick then checks to see if the new tick value will cause any
tasks to be unblocked. */
traceTASK_INCREMENT_TICK( xTickCount );
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8006176: 4b50 ldr r3, [pc, #320] @ (80062b8 <xTaskIncrementTick+0x14c>)
8006178: 681b ldr r3, [r3, #0]
800617a: 2b00 cmp r3, #0
800617c: f040 808b bne.w 8006296 <xTaskIncrementTick+0x12a>
{
/* Minor optimisation. The tick count cannot change in this
block. */
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
8006180: 4b4e ldr r3, [pc, #312] @ (80062bc <xTaskIncrementTick+0x150>)
8006182: 681b ldr r3, [r3, #0]
8006184: 3301 adds r3, #1
8006186: 613b str r3, [r7, #16]
/* Increment the RTOS tick, switching the delayed and overflowed
delayed lists if it wraps to 0. */
xTickCount = xConstTickCount;
8006188: 4a4c ldr r2, [pc, #304] @ (80062bc <xTaskIncrementTick+0x150>)
800618a: 693b ldr r3, [r7, #16]
800618c: 6013 str r3, [r2, #0]
if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
800618e: 693b ldr r3, [r7, #16]
8006190: 2b00 cmp r3, #0
8006192: d123 bne.n 80061dc <xTaskIncrementTick+0x70>
{
taskSWITCH_DELAYED_LISTS();
8006194: 4b4a ldr r3, [pc, #296] @ (80062c0 <xTaskIncrementTick+0x154>)
8006196: 681b ldr r3, [r3, #0]
8006198: 681b ldr r3, [r3, #0]
800619a: 2b00 cmp r3, #0
800619c: d00d beq.n 80061ba <xTaskIncrementTick+0x4e>
__asm volatile
800619e: f04f 0350 mov.w r3, #80 @ 0x50
80061a2: b672 cpsid i
80061a4: f383 8811 msr BASEPRI, r3
80061a8: f3bf 8f6f isb sy
80061ac: f3bf 8f4f dsb sy
80061b0: b662 cpsie i
80061b2: 603b str r3, [r7, #0]
}
80061b4: bf00 nop
80061b6: bf00 nop
80061b8: e7fd b.n 80061b6 <xTaskIncrementTick+0x4a>
80061ba: 4b41 ldr r3, [pc, #260] @ (80062c0 <xTaskIncrementTick+0x154>)
80061bc: 681b ldr r3, [r3, #0]
80061be: 60fb str r3, [r7, #12]
80061c0: 4b40 ldr r3, [pc, #256] @ (80062c4 <xTaskIncrementTick+0x158>)
80061c2: 681b ldr r3, [r3, #0]
80061c4: 4a3e ldr r2, [pc, #248] @ (80062c0 <xTaskIncrementTick+0x154>)
80061c6: 6013 str r3, [r2, #0]
80061c8: 4a3e ldr r2, [pc, #248] @ (80062c4 <xTaskIncrementTick+0x158>)
80061ca: 68fb ldr r3, [r7, #12]
80061cc: 6013 str r3, [r2, #0]
80061ce: 4b3e ldr r3, [pc, #248] @ (80062c8 <xTaskIncrementTick+0x15c>)
80061d0: 681b ldr r3, [r3, #0]
80061d2: 3301 adds r3, #1
80061d4: 4a3c ldr r2, [pc, #240] @ (80062c8 <xTaskIncrementTick+0x15c>)
80061d6: 6013 str r3, [r2, #0]
80061d8: f000 fbb2 bl 8006940 <prvResetNextTaskUnblockTime>
/* See if this tick has made a timeout expire. Tasks are stored in
the queue in the order of their wake time - meaning once one task
has been found whose block time has not expired there is no need to
look any further down the list. */
if( xConstTickCount >= xNextTaskUnblockTime )
80061dc: 4b3b ldr r3, [pc, #236] @ (80062cc <xTaskIncrementTick+0x160>)
80061de: 681b ldr r3, [r3, #0]
80061e0: 693a ldr r2, [r7, #16]
80061e2: 429a cmp r2, r3
80061e4: d348 bcc.n 8006278 <xTaskIncrementTick+0x10c>
{
for( ;; )
{
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
80061e6: 4b36 ldr r3, [pc, #216] @ (80062c0 <xTaskIncrementTick+0x154>)
80061e8: 681b ldr r3, [r3, #0]
80061ea: 681b ldr r3, [r3, #0]
80061ec: 2b00 cmp r3, #0
80061ee: d104 bne.n 80061fa <xTaskIncrementTick+0x8e>
/* The delayed list is empty. Set xNextTaskUnblockTime
to the maximum possible value so it is extremely
unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass
next time through. */
xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
80061f0: 4b36 ldr r3, [pc, #216] @ (80062cc <xTaskIncrementTick+0x160>)
80061f2: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
80061f6: 601a str r2, [r3, #0]
break;
80061f8: e03e b.n 8006278 <xTaskIncrementTick+0x10c>
{
/* The delayed list is not empty, get the value of the
item at the head of the delayed list. This is the time
at which the task at the head of the delayed list must
be removed from the Blocked state. */
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
80061fa: 4b31 ldr r3, [pc, #196] @ (80062c0 <xTaskIncrementTick+0x154>)
80061fc: 681b ldr r3, [r3, #0]
80061fe: 68db ldr r3, [r3, #12]
8006200: 68db ldr r3, [r3, #12]
8006202: 60bb str r3, [r7, #8]
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
8006204: 68bb ldr r3, [r7, #8]
8006206: 685b ldr r3, [r3, #4]
8006208: 607b str r3, [r7, #4]
if( xConstTickCount < xItemValue )
800620a: 693a ldr r2, [r7, #16]
800620c: 687b ldr r3, [r7, #4]
800620e: 429a cmp r2, r3
8006210: d203 bcs.n 800621a <xTaskIncrementTick+0xae>
/* It is not time to unblock this item yet, but the
item value is the time at which the task at the head
of the blocked list must be removed from the Blocked
state - so record the item value in
xNextTaskUnblockTime. */
xNextTaskUnblockTime = xItemValue;
8006212: 4a2e ldr r2, [pc, #184] @ (80062cc <xTaskIncrementTick+0x160>)
8006214: 687b ldr r3, [r7, #4]
8006216: 6013 str r3, [r2, #0]
break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
8006218: e02e b.n 8006278 <xTaskIncrementTick+0x10c>
{
mtCOVERAGE_TEST_MARKER();
}
/* It is time to remove the item from the Blocked state. */
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
800621a: 68bb ldr r3, [r7, #8]
800621c: 3304 adds r3, #4
800621e: 4618 mov r0, r3
8006220: f7fe fdff bl 8004e22 <uxListRemove>
/* Is the task waiting on an event also? If so remove
it from the event list. */
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
8006224: 68bb ldr r3, [r7, #8]
8006226: 6a9b ldr r3, [r3, #40] @ 0x28
8006228: 2b00 cmp r3, #0
800622a: d004 beq.n 8006236 <xTaskIncrementTick+0xca>
{
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
800622c: 68bb ldr r3, [r7, #8]
800622e: 3318 adds r3, #24
8006230: 4618 mov r0, r3
8006232: f7fe fdf6 bl 8004e22 <uxListRemove>
mtCOVERAGE_TEST_MARKER();
}
/* Place the unblocked task into the appropriate ready
list. */
prvAddTaskToReadyList( pxTCB );
8006236: 68bb ldr r3, [r7, #8]
8006238: 6adb ldr r3, [r3, #44] @ 0x2c
800623a: 2201 movs r2, #1
800623c: 409a lsls r2, r3
800623e: 4b24 ldr r3, [pc, #144] @ (80062d0 <xTaskIncrementTick+0x164>)
8006240: 681b ldr r3, [r3, #0]
8006242: 4313 orrs r3, r2
8006244: 4a22 ldr r2, [pc, #136] @ (80062d0 <xTaskIncrementTick+0x164>)
8006246: 6013 str r3, [r2, #0]
8006248: 68bb ldr r3, [r7, #8]
800624a: 6ada ldr r2, [r3, #44] @ 0x2c
800624c: 4613 mov r3, r2
800624e: 009b lsls r3, r3, #2
8006250: 4413 add r3, r2
8006252: 009b lsls r3, r3, #2
8006254: 4a1f ldr r2, [pc, #124] @ (80062d4 <xTaskIncrementTick+0x168>)
8006256: 441a add r2, r3
8006258: 68bb ldr r3, [r7, #8]
800625a: 3304 adds r3, #4
800625c: 4619 mov r1, r3
800625e: 4610 mov r0, r2
8006260: f7fe fd82 bl 8004d68 <vListInsertEnd>
{
/* Preemption is on, but a context switch should
only be performed if the unblocked task has a
priority that is equal to or higher than the
currently executing task. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
8006264: 68bb ldr r3, [r7, #8]
8006266: 6ada ldr r2, [r3, #44] @ 0x2c
8006268: 4b1b ldr r3, [pc, #108] @ (80062d8 <xTaskIncrementTick+0x16c>)
800626a: 681b ldr r3, [r3, #0]
800626c: 6adb ldr r3, [r3, #44] @ 0x2c
800626e: 429a cmp r2, r3
8006270: d3b9 bcc.n 80061e6 <xTaskIncrementTick+0x7a>
{
xSwitchRequired = pdTRUE;
8006272: 2301 movs r3, #1
8006274: 617b str r3, [r7, #20]
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
8006276: e7b6 b.n 80061e6 <xTaskIncrementTick+0x7a>
/* Tasks of equal priority to the currently running task will share
processing time (time slice) if preemption is on, and the application
writer has not explicitly turned time slicing off. */
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
{
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
8006278: 4b17 ldr r3, [pc, #92] @ (80062d8 <xTaskIncrementTick+0x16c>)
800627a: 681b ldr r3, [r3, #0]
800627c: 6ada ldr r2, [r3, #44] @ 0x2c
800627e: 4915 ldr r1, [pc, #84] @ (80062d4 <xTaskIncrementTick+0x168>)
8006280: 4613 mov r3, r2
8006282: 009b lsls r3, r3, #2
8006284: 4413 add r3, r2
8006286: 009b lsls r3, r3, #2
8006288: 440b add r3, r1
800628a: 681b ldr r3, [r3, #0]
800628c: 2b01 cmp r3, #1
800628e: d907 bls.n 80062a0 <xTaskIncrementTick+0x134>
{
xSwitchRequired = pdTRUE;
8006290: 2301 movs r3, #1
8006292: 617b str r3, [r7, #20]
8006294: e004 b.n 80062a0 <xTaskIncrementTick+0x134>
}
#endif /* configUSE_TICK_HOOK */
}
else
{
++uxPendedTicks;
8006296: 4b11 ldr r3, [pc, #68] @ (80062dc <xTaskIncrementTick+0x170>)
8006298: 681b ldr r3, [r3, #0]
800629a: 3301 adds r3, #1
800629c: 4a0f ldr r2, [pc, #60] @ (80062dc <xTaskIncrementTick+0x170>)
800629e: 6013 str r3, [r2, #0]
#endif
}
#if ( configUSE_PREEMPTION == 1 )
{
if( xYieldPending != pdFALSE )
80062a0: 4b0f ldr r3, [pc, #60] @ (80062e0 <xTaskIncrementTick+0x174>)
80062a2: 681b ldr r3, [r3, #0]
80062a4: 2b00 cmp r3, #0
80062a6: d001 beq.n 80062ac <xTaskIncrementTick+0x140>
{
xSwitchRequired = pdTRUE;
80062a8: 2301 movs r3, #1
80062aa: 617b str r3, [r7, #20]
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_PREEMPTION */
return xSwitchRequired;
80062ac: 697b ldr r3, [r7, #20]
}
80062ae: 4618 mov r0, r3
80062b0: 3718 adds r7, #24
80062b2: 46bd mov sp, r7
80062b4: bd80 pop {r7, pc}
80062b6: bf00 nop
80062b8: 20000cc0 .word 0x20000cc0
80062bc: 20000c9c .word 0x20000c9c
80062c0: 20000c50 .word 0x20000c50
80062c4: 20000c54 .word 0x20000c54
80062c8: 20000cb0 .word 0x20000cb0
80062cc: 20000cb8 .word 0x20000cb8
80062d0: 20000ca0 .word 0x20000ca0
80062d4: 20000b9c .word 0x20000b9c
80062d8: 20000b98 .word 0x20000b98
80062dc: 20000ca8 .word 0x20000ca8
80062e0: 20000cac .word 0x20000cac
080062e4 <vTaskSwitchContext>:
#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/
void vTaskSwitchContext( void )
{
80062e4: b580 push {r7, lr}
80062e6: b086 sub sp, #24
80062e8: af00 add r7, sp, #0
if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
80062ea: 4b38 ldr r3, [pc, #224] @ (80063cc <vTaskSwitchContext+0xe8>)
80062ec: 681b ldr r3, [r3, #0]
80062ee: 2b00 cmp r3, #0
80062f0: d003 beq.n 80062fa <vTaskSwitchContext+0x16>
{
/* The scheduler is currently suspended - do not allow a context
switch. */
xYieldPending = pdTRUE;
80062f2: 4b37 ldr r3, [pc, #220] @ (80063d0 <vTaskSwitchContext+0xec>)
80062f4: 2201 movs r2, #1
80062f6: 601a str r2, [r3, #0]
structure specific to this task. */
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
}
#endif /* configUSE_NEWLIB_REENTRANT */
}
}
80062f8: e064 b.n 80063c4 <vTaskSwitchContext+0xe0>
xYieldPending = pdFALSE;
80062fa: 4b35 ldr r3, [pc, #212] @ (80063d0 <vTaskSwitchContext+0xec>)
80062fc: 2200 movs r2, #0
80062fe: 601a str r2, [r3, #0]
traceTASK_SWITCHED_OUT();
8006300: f7fb fd0e bl 8001d20 <Usage_TaskSwitchedOut>
ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
8006304: f7fa fb4d bl 80009a2 <getRunTimeCounterValue>
8006308: 4603 mov r3, r0
800630a: 4a32 ldr r2, [pc, #200] @ (80063d4 <vTaskSwitchContext+0xf0>)
800630c: 6013 str r3, [r2, #0]
if( ulTotalRunTime > ulTaskSwitchedInTime )
800630e: 4b31 ldr r3, [pc, #196] @ (80063d4 <vTaskSwitchContext+0xf0>)
8006310: 681a ldr r2, [r3, #0]
8006312: 4b31 ldr r3, [pc, #196] @ (80063d8 <vTaskSwitchContext+0xf4>)
8006314: 681b ldr r3, [r3, #0]
8006316: 429a cmp r2, r3
8006318: d909 bls.n 800632e <vTaskSwitchContext+0x4a>
pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
800631a: 4b30 ldr r3, [pc, #192] @ (80063dc <vTaskSwitchContext+0xf8>)
800631c: 681b ldr r3, [r3, #0]
800631e: 6d59 ldr r1, [r3, #84] @ 0x54
8006320: 4a2c ldr r2, [pc, #176] @ (80063d4 <vTaskSwitchContext+0xf0>)
8006322: 6810 ldr r0, [r2, #0]
8006324: 4a2c ldr r2, [pc, #176] @ (80063d8 <vTaskSwitchContext+0xf4>)
8006326: 6812 ldr r2, [r2, #0]
8006328: 1a82 subs r2, r0, r2
800632a: 440a add r2, r1
800632c: 655a str r2, [r3, #84] @ 0x54
ulTaskSwitchedInTime = ulTotalRunTime;
800632e: 4b29 ldr r3, [pc, #164] @ (80063d4 <vTaskSwitchContext+0xf0>)
8006330: 681b ldr r3, [r3, #0]
8006332: 4a29 ldr r2, [pc, #164] @ (80063d8 <vTaskSwitchContext+0xf4>)
8006334: 6013 str r3, [r2, #0]
taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8006336: 4b2a ldr r3, [pc, #168] @ (80063e0 <vTaskSwitchContext+0xfc>)
8006338: 681b ldr r3, [r3, #0]
800633a: 60fb str r3, [r7, #12]
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
800633c: 68fb ldr r3, [r7, #12]
800633e: fab3 f383 clz r3, r3
8006342: 72fb strb r3, [r7, #11]
return ucReturn;
8006344: 7afb ldrb r3, [r7, #11]
8006346: f1c3 031f rsb r3, r3, #31
800634a: 617b str r3, [r7, #20]
800634c: 4925 ldr r1, [pc, #148] @ (80063e4 <vTaskSwitchContext+0x100>)
800634e: 697a ldr r2, [r7, #20]
8006350: 4613 mov r3, r2
8006352: 009b lsls r3, r3, #2
8006354: 4413 add r3, r2
8006356: 009b lsls r3, r3, #2
8006358: 440b add r3, r1
800635a: 681b ldr r3, [r3, #0]
800635c: 2b00 cmp r3, #0
800635e: d10d bne.n 800637c <vTaskSwitchContext+0x98>
__asm volatile
8006360: f04f 0350 mov.w r3, #80 @ 0x50
8006364: b672 cpsid i
8006366: f383 8811 msr BASEPRI, r3
800636a: f3bf 8f6f isb sy
800636e: f3bf 8f4f dsb sy
8006372: b662 cpsie i
8006374: 607b str r3, [r7, #4]
}
8006376: bf00 nop
8006378: bf00 nop
800637a: e7fd b.n 8006378 <vTaskSwitchContext+0x94>
800637c: 697a ldr r2, [r7, #20]
800637e: 4613 mov r3, r2
8006380: 009b lsls r3, r3, #2
8006382: 4413 add r3, r2
8006384: 009b lsls r3, r3, #2
8006386: 4a17 ldr r2, [pc, #92] @ (80063e4 <vTaskSwitchContext+0x100>)
8006388: 4413 add r3, r2
800638a: 613b str r3, [r7, #16]
800638c: 693b ldr r3, [r7, #16]
800638e: 685b ldr r3, [r3, #4]
8006390: 685a ldr r2, [r3, #4]
8006392: 693b ldr r3, [r7, #16]
8006394: 605a str r2, [r3, #4]
8006396: 693b ldr r3, [r7, #16]
8006398: 685a ldr r2, [r3, #4]
800639a: 693b ldr r3, [r7, #16]
800639c: 3308 adds r3, #8
800639e: 429a cmp r2, r3
80063a0: d104 bne.n 80063ac <vTaskSwitchContext+0xc8>
80063a2: 693b ldr r3, [r7, #16]
80063a4: 685b ldr r3, [r3, #4]
80063a6: 685a ldr r2, [r3, #4]
80063a8: 693b ldr r3, [r7, #16]
80063aa: 605a str r2, [r3, #4]
80063ac: 693b ldr r3, [r7, #16]
80063ae: 685b ldr r3, [r3, #4]
80063b0: 68db ldr r3, [r3, #12]
80063b2: 4a0a ldr r2, [pc, #40] @ (80063dc <vTaskSwitchContext+0xf8>)
80063b4: 6013 str r3, [r2, #0]
traceTASK_SWITCHED_IN();
80063b6: f7fb fc9f bl 8001cf8 <Usage_TaskSwitchedIn>
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
80063ba: 4b08 ldr r3, [pc, #32] @ (80063dc <vTaskSwitchContext+0xf8>)
80063bc: 681b ldr r3, [r3, #0]
80063be: 3358 adds r3, #88 @ 0x58
80063c0: 4a09 ldr r2, [pc, #36] @ (80063e8 <vTaskSwitchContext+0x104>)
80063c2: 6013 str r3, [r2, #0]
}
80063c4: bf00 nop
80063c6: 3718 adds r7, #24
80063c8: 46bd mov sp, r7
80063ca: bd80 pop {r7, pc}
80063cc: 20000cc0 .word 0x20000cc0
80063d0: 20000cac .word 0x20000cac
80063d4: 20000cc8 .word 0x20000cc8
80063d8: 20000cc4 .word 0x20000cc4
80063dc: 20000b98 .word 0x20000b98
80063e0: 20000ca0 .word 0x20000ca0
80063e4: 20000b9c .word 0x20000b9c
80063e8: 2000001c .word 0x2000001c
080063ec <vTaskPlaceOnEventList>:
/*-----------------------------------------------------------*/
void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
{
80063ec: b580 push {r7, lr}
80063ee: b084 sub sp, #16
80063f0: af00 add r7, sp, #0
80063f2: 6078 str r0, [r7, #4]
80063f4: 6039 str r1, [r7, #0]
configASSERT( pxEventList );
80063f6: 687b ldr r3, [r7, #4]
80063f8: 2b00 cmp r3, #0
80063fa: d10d bne.n 8006418 <vTaskPlaceOnEventList+0x2c>
__asm volatile
80063fc: f04f 0350 mov.w r3, #80 @ 0x50
8006400: b672 cpsid i
8006402: f383 8811 msr BASEPRI, r3
8006406: f3bf 8f6f isb sy
800640a: f3bf 8f4f dsb sy
800640e: b662 cpsie i
8006410: 60fb str r3, [r7, #12]
}
8006412: bf00 nop
8006414: bf00 nop
8006416: e7fd b.n 8006414 <vTaskPlaceOnEventList+0x28>
/* Place the event list item of the TCB in the appropriate event list.
This is placed in the list in priority order so the highest priority task
is the first to be woken by the event. The queue that contains the event
list is locked, preventing simultaneous access from interrupts. */
vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
8006418: 4b07 ldr r3, [pc, #28] @ (8006438 <vTaskPlaceOnEventList+0x4c>)
800641a: 681b ldr r3, [r3, #0]
800641c: 3318 adds r3, #24
800641e: 4619 mov r1, r3
8006420: 6878 ldr r0, [r7, #4]
8006422: f7fe fcc5 bl 8004db0 <vListInsert>
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
8006426: 2101 movs r1, #1
8006428: 6838 ldr r0, [r7, #0]
800642a: f000 fc87 bl 8006d3c <prvAddCurrentTaskToDelayedList>
}
800642e: bf00 nop
8006430: 3710 adds r7, #16
8006432: 46bd mov sp, r7
8006434: bd80 pop {r7, pc}
8006436: bf00 nop
8006438: 20000b98 .word 0x20000b98
0800643c <xTaskRemoveFromEventList>:
#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/
BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
{
800643c: b580 push {r7, lr}
800643e: b086 sub sp, #24
8006440: af00 add r7, sp, #0
8006442: 6078 str r0, [r7, #4]
get called - the lock count on the queue will get modified instead. This
means exclusive access to the event list is guaranteed here.
This function assumes that a check has already been made to ensure that
pxEventList is not empty. */
pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8006444: 687b ldr r3, [r7, #4]
8006446: 68db ldr r3, [r3, #12]
8006448: 68db ldr r3, [r3, #12]
800644a: 613b str r3, [r7, #16]
configASSERT( pxUnblockedTCB );
800644c: 693b ldr r3, [r7, #16]
800644e: 2b00 cmp r3, #0
8006450: d10d bne.n 800646e <xTaskRemoveFromEventList+0x32>
__asm volatile
8006452: f04f 0350 mov.w r3, #80 @ 0x50
8006456: b672 cpsid i
8006458: f383 8811 msr BASEPRI, r3
800645c: f3bf 8f6f isb sy
8006460: f3bf 8f4f dsb sy
8006464: b662 cpsie i
8006466: 60fb str r3, [r7, #12]
}
8006468: bf00 nop
800646a: bf00 nop
800646c: e7fd b.n 800646a <xTaskRemoveFromEventList+0x2e>
( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
800646e: 693b ldr r3, [r7, #16]
8006470: 3318 adds r3, #24
8006472: 4618 mov r0, r3
8006474: f7fe fcd5 bl 8004e22 <uxListRemove>
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8006478: 4b1d ldr r3, [pc, #116] @ (80064f0 <xTaskRemoveFromEventList+0xb4>)
800647a: 681b ldr r3, [r3, #0]
800647c: 2b00 cmp r3, #0
800647e: d11c bne.n 80064ba <xTaskRemoveFromEventList+0x7e>
{
( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
8006480: 693b ldr r3, [r7, #16]
8006482: 3304 adds r3, #4
8006484: 4618 mov r0, r3
8006486: f7fe fccc bl 8004e22 <uxListRemove>
prvAddTaskToReadyList( pxUnblockedTCB );
800648a: 693b ldr r3, [r7, #16]
800648c: 6adb ldr r3, [r3, #44] @ 0x2c
800648e: 2201 movs r2, #1
8006490: 409a lsls r2, r3
8006492: 4b18 ldr r3, [pc, #96] @ (80064f4 <xTaskRemoveFromEventList+0xb8>)
8006494: 681b ldr r3, [r3, #0]
8006496: 4313 orrs r3, r2
8006498: 4a16 ldr r2, [pc, #88] @ (80064f4 <xTaskRemoveFromEventList+0xb8>)
800649a: 6013 str r3, [r2, #0]
800649c: 693b ldr r3, [r7, #16]
800649e: 6ada ldr r2, [r3, #44] @ 0x2c
80064a0: 4613 mov r3, r2
80064a2: 009b lsls r3, r3, #2
80064a4: 4413 add r3, r2
80064a6: 009b lsls r3, r3, #2
80064a8: 4a13 ldr r2, [pc, #76] @ (80064f8 <xTaskRemoveFromEventList+0xbc>)
80064aa: 441a add r2, r3
80064ac: 693b ldr r3, [r7, #16]
80064ae: 3304 adds r3, #4
80064b0: 4619 mov r1, r3
80064b2: 4610 mov r0, r2
80064b4: f7fe fc58 bl 8004d68 <vListInsertEnd>
80064b8: e005 b.n 80064c6 <xTaskRemoveFromEventList+0x8a>
}
else
{
/* The delayed and ready lists cannot be accessed, so hold this task
pending until the scheduler is resumed. */
vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
80064ba: 693b ldr r3, [r7, #16]
80064bc: 3318 adds r3, #24
80064be: 4619 mov r1, r3
80064c0: 480e ldr r0, [pc, #56] @ (80064fc <xTaskRemoveFromEventList+0xc0>)
80064c2: f7fe fc51 bl 8004d68 <vListInsertEnd>
}
if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
80064c6: 693b ldr r3, [r7, #16]
80064c8: 6ada ldr r2, [r3, #44] @ 0x2c
80064ca: 4b0d ldr r3, [pc, #52] @ (8006500 <xTaskRemoveFromEventList+0xc4>)
80064cc: 681b ldr r3, [r3, #0]
80064ce: 6adb ldr r3, [r3, #44] @ 0x2c
80064d0: 429a cmp r2, r3
80064d2: d905 bls.n 80064e0 <xTaskRemoveFromEventList+0xa4>
{
/* Return true if the task removed from the event list has a higher
priority than the calling task. This allows the calling task to know if
it should force a context switch now. */
xReturn = pdTRUE;
80064d4: 2301 movs r3, #1
80064d6: 617b str r3, [r7, #20]
/* Mark that a yield is pending in case the user is not using the
"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
xYieldPending = pdTRUE;
80064d8: 4b0a ldr r3, [pc, #40] @ (8006504 <xTaskRemoveFromEventList+0xc8>)
80064da: 2201 movs r2, #1
80064dc: 601a str r2, [r3, #0]
80064de: e001 b.n 80064e4 <xTaskRemoveFromEventList+0xa8>
}
else
{
xReturn = pdFALSE;
80064e0: 2300 movs r3, #0
80064e2: 617b str r3, [r7, #20]
}
return xReturn;
80064e4: 697b ldr r3, [r7, #20]
}
80064e6: 4618 mov r0, r3
80064e8: 3718 adds r7, #24
80064ea: 46bd mov sp, r7
80064ec: bd80 pop {r7, pc}
80064ee: bf00 nop
80064f0: 20000cc0 .word 0x20000cc0
80064f4: 20000ca0 .word 0x20000ca0
80064f8: 20000b9c .word 0x20000b9c
80064fc: 20000c58 .word 0x20000c58
8006500: 20000b98 .word 0x20000b98
8006504: 20000cac .word 0x20000cac
08006508 <vTaskInternalSetTimeOutState>:
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
8006508: b480 push {r7}
800650a: b083 sub sp, #12
800650c: af00 add r7, sp, #0
800650e: 6078 str r0, [r7, #4]
/* For internal use only as it does not use a critical section. */
pxTimeOut->xOverflowCount = xNumOfOverflows;
8006510: 4b06 ldr r3, [pc, #24] @ (800652c <vTaskInternalSetTimeOutState+0x24>)
8006512: 681a ldr r2, [r3, #0]
8006514: 687b ldr r3, [r7, #4]
8006516: 601a str r2, [r3, #0]
pxTimeOut->xTimeOnEntering = xTickCount;
8006518: 4b05 ldr r3, [pc, #20] @ (8006530 <vTaskInternalSetTimeOutState+0x28>)
800651a: 681a ldr r2, [r3, #0]
800651c: 687b ldr r3, [r7, #4]
800651e: 605a str r2, [r3, #4]
}
8006520: bf00 nop
8006522: 370c adds r7, #12
8006524: 46bd mov sp, r7
8006526: f85d 7b04 ldr.w r7, [sp], #4
800652a: 4770 bx lr
800652c: 20000cb0 .word 0x20000cb0
8006530: 20000c9c .word 0x20000c9c
08006534 <xTaskCheckForTimeOut>:
/*-----------------------------------------------------------*/
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
{
8006534: b580 push {r7, lr}
8006536: b088 sub sp, #32
8006538: af00 add r7, sp, #0
800653a: 6078 str r0, [r7, #4]
800653c: 6039 str r1, [r7, #0]
BaseType_t xReturn;
configASSERT( pxTimeOut );
800653e: 687b ldr r3, [r7, #4]
8006540: 2b00 cmp r3, #0
8006542: d10d bne.n 8006560 <xTaskCheckForTimeOut+0x2c>
__asm volatile
8006544: f04f 0350 mov.w r3, #80 @ 0x50
8006548: b672 cpsid i
800654a: f383 8811 msr BASEPRI, r3
800654e: f3bf 8f6f isb sy
8006552: f3bf 8f4f dsb sy
8006556: b662 cpsie i
8006558: 613b str r3, [r7, #16]
}
800655a: bf00 nop
800655c: bf00 nop
800655e: e7fd b.n 800655c <xTaskCheckForTimeOut+0x28>
configASSERT( pxTicksToWait );
8006560: 683b ldr r3, [r7, #0]
8006562: 2b00 cmp r3, #0
8006564: d10d bne.n 8006582 <xTaskCheckForTimeOut+0x4e>
__asm volatile
8006566: f04f 0350 mov.w r3, #80 @ 0x50
800656a: b672 cpsid i
800656c: f383 8811 msr BASEPRI, r3
8006570: f3bf 8f6f isb sy
8006574: f3bf 8f4f dsb sy
8006578: b662 cpsie i
800657a: 60fb str r3, [r7, #12]
}
800657c: bf00 nop
800657e: bf00 nop
8006580: e7fd b.n 800657e <xTaskCheckForTimeOut+0x4a>
taskENTER_CRITICAL();
8006582: f000 fd53 bl 800702c <vPortEnterCritical>
{
/* Minor optimisation. The tick count cannot change in this block. */
const TickType_t xConstTickCount = xTickCount;
8006586: 4b1d ldr r3, [pc, #116] @ (80065fc <xTaskCheckForTimeOut+0xc8>)
8006588: 681b ldr r3, [r3, #0]
800658a: 61bb str r3, [r7, #24]
const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
800658c: 687b ldr r3, [r7, #4]
800658e: 685b ldr r3, [r3, #4]
8006590: 69ba ldr r2, [r7, #24]
8006592: 1ad3 subs r3, r2, r3
8006594: 617b str r3, [r7, #20]
}
else
#endif
#if ( INCLUDE_vTaskSuspend == 1 )
if( *pxTicksToWait == portMAX_DELAY )
8006596: 683b ldr r3, [r7, #0]
8006598: 681b ldr r3, [r3, #0]
800659a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
800659e: d102 bne.n 80065a6 <xTaskCheckForTimeOut+0x72>
{
/* If INCLUDE_vTaskSuspend is set to 1 and the block time
specified is the maximum block time then the task should block
indefinitely, and therefore never time out. */
xReturn = pdFALSE;
80065a0: 2300 movs r3, #0
80065a2: 61fb str r3, [r7, #28]
80065a4: e023 b.n 80065ee <xTaskCheckForTimeOut+0xba>
}
else
#endif
if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
80065a6: 687b ldr r3, [r7, #4]
80065a8: 681a ldr r2, [r3, #0]
80065aa: 4b15 ldr r3, [pc, #84] @ (8006600 <xTaskCheckForTimeOut+0xcc>)
80065ac: 681b ldr r3, [r3, #0]
80065ae: 429a cmp r2, r3
80065b0: d007 beq.n 80065c2 <xTaskCheckForTimeOut+0x8e>
80065b2: 687b ldr r3, [r7, #4]
80065b4: 685b ldr r3, [r3, #4]
80065b6: 69ba ldr r2, [r7, #24]
80065b8: 429a cmp r2, r3
80065ba: d302 bcc.n 80065c2 <xTaskCheckForTimeOut+0x8e>
/* The tick count is greater than the time at which
vTaskSetTimeout() was called, but has also overflowed since
vTaskSetTimeOut() was called. It must have wrapped all the way
around and gone past again. This passed since vTaskSetTimeout()
was called. */
xReturn = pdTRUE;
80065bc: 2301 movs r3, #1
80065be: 61fb str r3, [r7, #28]
80065c0: e015 b.n 80065ee <xTaskCheckForTimeOut+0xba>
}
else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
80065c2: 683b ldr r3, [r7, #0]
80065c4: 681b ldr r3, [r3, #0]
80065c6: 697a ldr r2, [r7, #20]
80065c8: 429a cmp r2, r3
80065ca: d20b bcs.n 80065e4 <xTaskCheckForTimeOut+0xb0>
{
/* Not a genuine timeout. Adjust parameters for time remaining. */
*pxTicksToWait -= xElapsedTime;
80065cc: 683b ldr r3, [r7, #0]
80065ce: 681a ldr r2, [r3, #0]
80065d0: 697b ldr r3, [r7, #20]
80065d2: 1ad2 subs r2, r2, r3
80065d4: 683b ldr r3, [r7, #0]
80065d6: 601a str r2, [r3, #0]
vTaskInternalSetTimeOutState( pxTimeOut );
80065d8: 6878 ldr r0, [r7, #4]
80065da: f7ff ff95 bl 8006508 <vTaskInternalSetTimeOutState>
xReturn = pdFALSE;
80065de: 2300 movs r3, #0
80065e0: 61fb str r3, [r7, #28]
80065e2: e004 b.n 80065ee <xTaskCheckForTimeOut+0xba>
}
else
{
*pxTicksToWait = 0;
80065e4: 683b ldr r3, [r7, #0]
80065e6: 2200 movs r2, #0
80065e8: 601a str r2, [r3, #0]
xReturn = pdTRUE;
80065ea: 2301 movs r3, #1
80065ec: 61fb str r3, [r7, #28]
}
}
taskEXIT_CRITICAL();
80065ee: f000 fd53 bl 8007098 <vPortExitCritical>
return xReturn;
80065f2: 69fb ldr r3, [r7, #28]
}
80065f4: 4618 mov r0, r3
80065f6: 3720 adds r7, #32
80065f8: 46bd mov sp, r7
80065fa: bd80 pop {r7, pc}
80065fc: 20000c9c .word 0x20000c9c
8006600: 20000cb0 .word 0x20000cb0
08006604 <vTaskMissedYield>:
/*-----------------------------------------------------------*/
void vTaskMissedYield( void )
{
8006604: b480 push {r7}
8006606: af00 add r7, sp, #0
xYieldPending = pdTRUE;
8006608: 4b03 ldr r3, [pc, #12] @ (8006618 <vTaskMissedYield+0x14>)
800660a: 2201 movs r2, #1
800660c: 601a str r2, [r3, #0]
}
800660e: bf00 nop
8006610: 46bd mov sp, r7
8006612: f85d 7b04 ldr.w r7, [sp], #4
8006616: 4770 bx lr
8006618: 20000cac .word 0x20000cac
0800661c <prvIdleTask>:
*
* void prvIdleTask( void *pvParameters );
*
*/
static portTASK_FUNCTION( prvIdleTask, pvParameters )
{
800661c: b580 push {r7, lr}
800661e: b082 sub sp, #8
8006620: af00 add r7, sp, #0
8006622: 6078 str r0, [r7, #4]
for( ;; )
{
/* See if any tasks have deleted themselves - if so then the idle task
is responsible for freeing the deleted task's TCB and stack. */
prvCheckTasksWaitingTermination();
8006624: f000 f852 bl 80066cc <prvCheckTasksWaitingTermination>
A critical region is not required here as we are just reading from
the list, and an occasional incorrect value will not matter. If
the ready list at the idle priority contains more than one task
then a task other than the idle task is ready to execute. */
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
8006628: 4b06 ldr r3, [pc, #24] @ (8006644 <prvIdleTask+0x28>)
800662a: 681b ldr r3, [r3, #0]
800662c: 2b01 cmp r3, #1
800662e: d9f9 bls.n 8006624 <prvIdleTask+0x8>
{
taskYIELD();
8006630: 4b05 ldr r3, [pc, #20] @ (8006648 <prvIdleTask+0x2c>)
8006632: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8006636: 601a str r2, [r3, #0]
8006638: f3bf 8f4f dsb sy
800663c: f3bf 8f6f isb sy
prvCheckTasksWaitingTermination();
8006640: e7f0 b.n 8006624 <prvIdleTask+0x8>
8006642: bf00 nop
8006644: 20000b9c .word 0x20000b9c
8006648: e000ed04 .word 0xe000ed04
0800664c <prvInitialiseTaskLists>:
#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/
static void prvInitialiseTaskLists( void )
{
800664c: b580 push {r7, lr}
800664e: b082 sub sp, #8
8006650: af00 add r7, sp, #0
UBaseType_t uxPriority;
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
8006652: 2300 movs r3, #0
8006654: 607b str r3, [r7, #4]
8006656: e00c b.n 8006672 <prvInitialiseTaskLists+0x26>
{
vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
8006658: 687a ldr r2, [r7, #4]
800665a: 4613 mov r3, r2
800665c: 009b lsls r3, r3, #2
800665e: 4413 add r3, r2
8006660: 009b lsls r3, r3, #2
8006662: 4a12 ldr r2, [pc, #72] @ (80066ac <prvInitialiseTaskLists+0x60>)
8006664: 4413 add r3, r2
8006666: 4618 mov r0, r3
8006668: f7fe fb51 bl 8004d0e <vListInitialise>
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
800666c: 687b ldr r3, [r7, #4]
800666e: 3301 adds r3, #1
8006670: 607b str r3, [r7, #4]
8006672: 687b ldr r3, [r7, #4]
8006674: 2b06 cmp r3, #6
8006676: d9ef bls.n 8006658 <prvInitialiseTaskLists+0xc>
}
vListInitialise( &xDelayedTaskList1 );
8006678: 480d ldr r0, [pc, #52] @ (80066b0 <prvInitialiseTaskLists+0x64>)
800667a: f7fe fb48 bl 8004d0e <vListInitialise>
vListInitialise( &xDelayedTaskList2 );
800667e: 480d ldr r0, [pc, #52] @ (80066b4 <prvInitialiseTaskLists+0x68>)
8006680: f7fe fb45 bl 8004d0e <vListInitialise>
vListInitialise( &xPendingReadyList );
8006684: 480c ldr r0, [pc, #48] @ (80066b8 <prvInitialiseTaskLists+0x6c>)
8006686: f7fe fb42 bl 8004d0e <vListInitialise>
#if ( INCLUDE_vTaskDelete == 1 )
{
vListInitialise( &xTasksWaitingTermination );
800668a: 480c ldr r0, [pc, #48] @ (80066bc <prvInitialiseTaskLists+0x70>)
800668c: f7fe fb3f bl 8004d0e <vListInitialise>
}
#endif /* INCLUDE_vTaskDelete */
#if ( INCLUDE_vTaskSuspend == 1 )
{
vListInitialise( &xSuspendedTaskList );
8006690: 480b ldr r0, [pc, #44] @ (80066c0 <prvInitialiseTaskLists+0x74>)
8006692: f7fe fb3c bl 8004d0e <vListInitialise>
}
#endif /* INCLUDE_vTaskSuspend */
/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
using list2. */
pxDelayedTaskList = &xDelayedTaskList1;
8006696: 4b0b ldr r3, [pc, #44] @ (80066c4 <prvInitialiseTaskLists+0x78>)
8006698: 4a05 ldr r2, [pc, #20] @ (80066b0 <prvInitialiseTaskLists+0x64>)
800669a: 601a str r2, [r3, #0]
pxOverflowDelayedTaskList = &xDelayedTaskList2;
800669c: 4b0a ldr r3, [pc, #40] @ (80066c8 <prvInitialiseTaskLists+0x7c>)
800669e: 4a05 ldr r2, [pc, #20] @ (80066b4 <prvInitialiseTaskLists+0x68>)
80066a0: 601a str r2, [r3, #0]
}
80066a2: bf00 nop
80066a4: 3708 adds r7, #8
80066a6: 46bd mov sp, r7
80066a8: bd80 pop {r7, pc}
80066aa: bf00 nop
80066ac: 20000b9c .word 0x20000b9c
80066b0: 20000c28 .word 0x20000c28
80066b4: 20000c3c .word 0x20000c3c
80066b8: 20000c58 .word 0x20000c58
80066bc: 20000c6c .word 0x20000c6c
80066c0: 20000c84 .word 0x20000c84
80066c4: 20000c50 .word 0x20000c50
80066c8: 20000c54 .word 0x20000c54
080066cc <prvCheckTasksWaitingTermination>:
/*-----------------------------------------------------------*/
static void prvCheckTasksWaitingTermination( void )
{
80066cc: b580 push {r7, lr}
80066ce: b082 sub sp, #8
80066d0: af00 add r7, sp, #0
{
TCB_t *pxTCB;
/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
being called too often in the idle task. */
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
80066d2: e019 b.n 8006708 <prvCheckTasksWaitingTermination+0x3c>
{
taskENTER_CRITICAL();
80066d4: f000 fcaa bl 800702c <vPortEnterCritical>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
80066d8: 4b10 ldr r3, [pc, #64] @ (800671c <prvCheckTasksWaitingTermination+0x50>)
80066da: 68db ldr r3, [r3, #12]
80066dc: 68db ldr r3, [r3, #12]
80066de: 607b str r3, [r7, #4]
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
80066e0: 687b ldr r3, [r7, #4]
80066e2: 3304 adds r3, #4
80066e4: 4618 mov r0, r3
80066e6: f7fe fb9c bl 8004e22 <uxListRemove>
--uxCurrentNumberOfTasks;
80066ea: 4b0d ldr r3, [pc, #52] @ (8006720 <prvCheckTasksWaitingTermination+0x54>)
80066ec: 681b ldr r3, [r3, #0]
80066ee: 3b01 subs r3, #1
80066f0: 4a0b ldr r2, [pc, #44] @ (8006720 <prvCheckTasksWaitingTermination+0x54>)
80066f2: 6013 str r3, [r2, #0]
--uxDeletedTasksWaitingCleanUp;
80066f4: 4b0b ldr r3, [pc, #44] @ (8006724 <prvCheckTasksWaitingTermination+0x58>)
80066f6: 681b ldr r3, [r3, #0]
80066f8: 3b01 subs r3, #1
80066fa: 4a0a ldr r2, [pc, #40] @ (8006724 <prvCheckTasksWaitingTermination+0x58>)
80066fc: 6013 str r3, [r2, #0]
}
taskEXIT_CRITICAL();
80066fe: f000 fccb bl 8007098 <vPortExitCritical>
prvDeleteTCB( pxTCB );
8006702: 6878 ldr r0, [r7, #4]
8006704: f000 f8e4 bl 80068d0 <prvDeleteTCB>
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
8006708: 4b06 ldr r3, [pc, #24] @ (8006724 <prvCheckTasksWaitingTermination+0x58>)
800670a: 681b ldr r3, [r3, #0]
800670c: 2b00 cmp r3, #0
800670e: d1e1 bne.n 80066d4 <prvCheckTasksWaitingTermination+0x8>
}
}
#endif /* INCLUDE_vTaskDelete */
}
8006710: bf00 nop
8006712: bf00 nop
8006714: 3708 adds r7, #8
8006716: 46bd mov sp, r7
8006718: bd80 pop {r7, pc}
800671a: bf00 nop
800671c: 20000c6c .word 0x20000c6c
8006720: 20000c98 .word 0x20000c98
8006724: 20000c80 .word 0x20000c80
08006728 <vTaskGetInfo>:
/*-----------------------------------------------------------*/
#if( configUSE_TRACE_FACILITY == 1 )
void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
{
8006728: b580 push {r7, lr}
800672a: b086 sub sp, #24
800672c: af00 add r7, sp, #0
800672e: 60f8 str r0, [r7, #12]
8006730: 60b9 str r1, [r7, #8]
8006732: 607a str r2, [r7, #4]
8006734: 70fb strb r3, [r7, #3]
TCB_t *pxTCB;
/* xTask is NULL then get the state of the calling task. */
pxTCB = prvGetTCBFromHandle( xTask );
8006736: 68fb ldr r3, [r7, #12]
8006738: 2b00 cmp r3, #0
800673a: d102 bne.n 8006742 <vTaskGetInfo+0x1a>
800673c: 4b2c ldr r3, [pc, #176] @ (80067f0 <vTaskGetInfo+0xc8>)
800673e: 681b ldr r3, [r3, #0]
8006740: e000 b.n 8006744 <vTaskGetInfo+0x1c>
8006742: 68fb ldr r3, [r7, #12]
8006744: 617b str r3, [r7, #20]
pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
8006746: 68bb ldr r3, [r7, #8]
8006748: 697a ldr r2, [r7, #20]
800674a: 601a str r2, [r3, #0]
pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );
800674c: 697b ldr r3, [r7, #20]
800674e: f103 0234 add.w r2, r3, #52 @ 0x34
8006752: 68bb ldr r3, [r7, #8]
8006754: 605a str r2, [r3, #4]
pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
8006756: 697b ldr r3, [r7, #20]
8006758: 6ada ldr r2, [r3, #44] @ 0x2c
800675a: 68bb ldr r3, [r7, #8]
800675c: 611a str r2, [r3, #16]
pxTaskStatus->pxStackBase = pxTCB->pxStack;
800675e: 697b ldr r3, [r7, #20]
8006760: 6b1a ldr r2, [r3, #48] @ 0x30
8006762: 68bb ldr r3, [r7, #8]
8006764: 61da str r2, [r3, #28]
pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
8006766: 697b ldr r3, [r7, #20]
8006768: 6c5a ldr r2, [r3, #68] @ 0x44
800676a: 68bb ldr r3, [r7, #8]
800676c: 609a str r2, [r3, #8]
#if ( configUSE_MUTEXES == 1 )
{
pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
800676e: 697b ldr r3, [r7, #20]
8006770: 6cda ldr r2, [r3, #76] @ 0x4c
8006772: 68bb ldr r3, [r7, #8]
8006774: 615a str r2, [r3, #20]
}
#endif
#if ( configGENERATE_RUN_TIME_STATS == 1 )
{
pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
8006776: 697b ldr r3, [r7, #20]
8006778: 6d5a ldr r2, [r3, #84] @ 0x54
800677a: 68bb ldr r3, [r7, #8]
800677c: 619a str r2, [r3, #24]
#endif
/* Obtaining the task state is a little fiddly, so is only done if the
value of eState passed into this function is eInvalid - otherwise the
state is just set to whatever is passed in. */
if( eState != eInvalid )
800677e: 78fb ldrb r3, [r7, #3]
8006780: 2b05 cmp r3, #5
8006782: d01a beq.n 80067ba <vTaskGetInfo+0x92>
{
if( pxTCB == pxCurrentTCB )
8006784: 4b1a ldr r3, [pc, #104] @ (80067f0 <vTaskGetInfo+0xc8>)
8006786: 681b ldr r3, [r3, #0]
8006788: 697a ldr r2, [r7, #20]
800678a: 429a cmp r2, r3
800678c: d103 bne.n 8006796 <vTaskGetInfo+0x6e>
{
pxTaskStatus->eCurrentState = eRunning;
800678e: 68bb ldr r3, [r7, #8]
8006790: 2200 movs r2, #0
8006792: 731a strb r2, [r3, #12]
8006794: e018 b.n 80067c8 <vTaskGetInfo+0xa0>
}
else
{
pxTaskStatus->eCurrentState = eState;
8006796: 68bb ldr r3, [r7, #8]
8006798: 78fa ldrb r2, [r7, #3]
800679a: 731a strb r2, [r3, #12]
#if ( INCLUDE_vTaskSuspend == 1 )
{
/* If the task is in the suspended list then there is a
chance it is actually just blocked indefinitely - so really
it should be reported as being in the Blocked state. */
if( eState == eSuspended )
800679c: 78fb ldrb r3, [r7, #3]
800679e: 2b03 cmp r3, #3
80067a0: d112 bne.n 80067c8 <vTaskGetInfo+0xa0>
{
vTaskSuspendAll();
80067a2: f7ff fb79 bl 8005e98 <vTaskSuspendAll>
{
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
80067a6: 697b ldr r3, [r7, #20]
80067a8: 6a9b ldr r3, [r3, #40] @ 0x28
80067aa: 2b00 cmp r3, #0
80067ac: d002 beq.n 80067b4 <vTaskGetInfo+0x8c>
{
pxTaskStatus->eCurrentState = eBlocked;
80067ae: 68bb ldr r3, [r7, #8]
80067b0: 2202 movs r2, #2
80067b2: 731a strb r2, [r3, #12]
}
}
( void ) xTaskResumeAll();
80067b4: f7ff fb7e bl 8005eb4 <xTaskResumeAll>
80067b8: e006 b.n 80067c8 <vTaskGetInfo+0xa0>
#endif /* INCLUDE_vTaskSuspend */
}
}
else
{
pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
80067ba: 6978 ldr r0, [r7, #20]
80067bc: f7ff fa90 bl 8005ce0 <eTaskGetState>
80067c0: 4603 mov r3, r0
80067c2: 461a mov r2, r3
80067c4: 68bb ldr r3, [r7, #8]
80067c6: 731a strb r2, [r3, #12]
}
/* Obtaining the stack space takes some time, so the xGetFreeStackSpace
parameter is provided to allow it to be skipped. */
if( xGetFreeStackSpace != pdFALSE )
80067c8: 687b ldr r3, [r7, #4]
80067ca: 2b00 cmp r3, #0
80067cc: d009 beq.n 80067e2 <vTaskGetInfo+0xba>
{
pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
}
#else
{
pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
80067ce: 697b ldr r3, [r7, #20]
80067d0: 6b1b ldr r3, [r3, #48] @ 0x30
80067d2: 4618 mov r0, r3
80067d4: f000 f860 bl 8006898 <prvTaskCheckFreeStackSpace>
80067d8: 4603 mov r3, r0
80067da: 461a mov r2, r3
80067dc: 68bb ldr r3, [r7, #8]
80067de: 841a strh r2, [r3, #32]
}
else
{
pxTaskStatus->usStackHighWaterMark = 0;
}
}
80067e0: e002 b.n 80067e8 <vTaskGetInfo+0xc0>
pxTaskStatus->usStackHighWaterMark = 0;
80067e2: 68bb ldr r3, [r7, #8]
80067e4: 2200 movs r2, #0
80067e6: 841a strh r2, [r3, #32]
}
80067e8: bf00 nop
80067ea: 3718 adds r7, #24
80067ec: 46bd mov sp, r7
80067ee: bd80 pop {r7, pc}
80067f0: 20000b98 .word 0x20000b98
080067f4 <prvListTasksWithinSingleList>:
/*-----------------------------------------------------------*/
#if ( configUSE_TRACE_FACILITY == 1 )
static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
{
80067f4: b580 push {r7, lr}
80067f6: b08a sub sp, #40 @ 0x28
80067f8: af00 add r7, sp, #0
80067fa: 60f8 str r0, [r7, #12]
80067fc: 60b9 str r1, [r7, #8]
80067fe: 4613 mov r3, r2
8006800: 71fb strb r3, [r7, #7]
configLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;
UBaseType_t uxTask = 0;
8006802: 2300 movs r3, #0
8006804: 627b str r3, [r7, #36] @ 0x24
if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
8006806: 68bb ldr r3, [r7, #8]
8006808: 681b ldr r3, [r3, #0]
800680a: 2b00 cmp r3, #0
800680c: d03f beq.n 800688e <prvListTasksWithinSingleList+0x9a>
{
listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800680e: 68bb ldr r3, [r7, #8]
8006810: 623b str r3, [r7, #32]
8006812: 6a3b ldr r3, [r7, #32]
8006814: 685b ldr r3, [r3, #4]
8006816: 685a ldr r2, [r3, #4]
8006818: 6a3b ldr r3, [r7, #32]
800681a: 605a str r2, [r3, #4]
800681c: 6a3b ldr r3, [r7, #32]
800681e: 685a ldr r2, [r3, #4]
8006820: 6a3b ldr r3, [r7, #32]
8006822: 3308 adds r3, #8
8006824: 429a cmp r2, r3
8006826: d104 bne.n 8006832 <prvListTasksWithinSingleList+0x3e>
8006828: 6a3b ldr r3, [r7, #32]
800682a: 685b ldr r3, [r3, #4]
800682c: 685a ldr r2, [r3, #4]
800682e: 6a3b ldr r3, [r7, #32]
8006830: 605a str r2, [r3, #4]
8006832: 6a3b ldr r3, [r7, #32]
8006834: 685b ldr r3, [r3, #4]
8006836: 68db ldr r3, [r3, #12]
8006838: 61fb str r3, [r7, #28]
pxTaskStatusArray array for each task that is referenced from
pxList. See the definition of TaskStatus_t in task.h for the
meaning of each TaskStatus_t structure member. */
do
{
listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800683a: 68bb ldr r3, [r7, #8]
800683c: 61bb str r3, [r7, #24]
800683e: 69bb ldr r3, [r7, #24]
8006840: 685b ldr r3, [r3, #4]
8006842: 685a ldr r2, [r3, #4]
8006844: 69bb ldr r3, [r7, #24]
8006846: 605a str r2, [r3, #4]
8006848: 69bb ldr r3, [r7, #24]
800684a: 685a ldr r2, [r3, #4]
800684c: 69bb ldr r3, [r7, #24]
800684e: 3308 adds r3, #8
8006850: 429a cmp r2, r3
8006852: d104 bne.n 800685e <prvListTasksWithinSingleList+0x6a>
8006854: 69bb ldr r3, [r7, #24]
8006856: 685b ldr r3, [r3, #4]
8006858: 685a ldr r2, [r3, #4]
800685a: 69bb ldr r3, [r7, #24]
800685c: 605a str r2, [r3, #4]
800685e: 69bb ldr r3, [r7, #24]
8006860: 685b ldr r3, [r3, #4]
8006862: 68db ldr r3, [r3, #12]
8006864: 617b str r3, [r7, #20]
vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
8006866: 6a7a ldr r2, [r7, #36] @ 0x24
8006868: 4613 mov r3, r2
800686a: 00db lsls r3, r3, #3
800686c: 4413 add r3, r2
800686e: 009b lsls r3, r3, #2
8006870: 461a mov r2, r3
8006872: 68fb ldr r3, [r7, #12]
8006874: 1899 adds r1, r3, r2
8006876: 79fb ldrb r3, [r7, #7]
8006878: 2201 movs r2, #1
800687a: 6978 ldr r0, [r7, #20]
800687c: f7ff ff54 bl 8006728 <vTaskGetInfo>
uxTask++;
8006880: 6a7b ldr r3, [r7, #36] @ 0x24
8006882: 3301 adds r3, #1
8006884: 627b str r3, [r7, #36] @ 0x24
} while( pxNextTCB != pxFirstTCB );
8006886: 697a ldr r2, [r7, #20]
8006888: 69fb ldr r3, [r7, #28]
800688a: 429a cmp r2, r3
800688c: d1d5 bne.n 800683a <prvListTasksWithinSingleList+0x46>
else
{
mtCOVERAGE_TEST_MARKER();
}
return uxTask;
800688e: 6a7b ldr r3, [r7, #36] @ 0x24
}
8006890: 4618 mov r0, r3
8006892: 3728 adds r7, #40 @ 0x28
8006894: 46bd mov sp, r7
8006896: bd80 pop {r7, pc}
08006898 <prvTaskCheckFreeStackSpace>:
/*-----------------------------------------------------------*/
#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
{
8006898: b480 push {r7}
800689a: b085 sub sp, #20
800689c: af00 add r7, sp, #0
800689e: 6078 str r0, [r7, #4]
uint32_t ulCount = 0U;
80068a0: 2300 movs r3, #0
80068a2: 60fb str r3, [r7, #12]
while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
80068a4: e005 b.n 80068b2 <prvTaskCheckFreeStackSpace+0x1a>
{
pucStackByte -= portSTACK_GROWTH;
80068a6: 687b ldr r3, [r7, #4]
80068a8: 3301 adds r3, #1
80068aa: 607b str r3, [r7, #4]
ulCount++;
80068ac: 68fb ldr r3, [r7, #12]
80068ae: 3301 adds r3, #1
80068b0: 60fb str r3, [r7, #12]
while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
80068b2: 687b ldr r3, [r7, #4]
80068b4: 781b ldrb r3, [r3, #0]
80068b6: 2ba5 cmp r3, #165 @ 0xa5
80068b8: d0f5 beq.n 80068a6 <prvTaskCheckFreeStackSpace+0xe>
}
ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
80068ba: 68fb ldr r3, [r7, #12]
80068bc: 089b lsrs r3, r3, #2
80068be: 60fb str r3, [r7, #12]
return ( configSTACK_DEPTH_TYPE ) ulCount;
80068c0: 68fb ldr r3, [r7, #12]
80068c2: b29b uxth r3, r3
}
80068c4: 4618 mov r0, r3
80068c6: 3714 adds r7, #20
80068c8: 46bd mov sp, r7
80068ca: f85d 7b04 ldr.w r7, [sp], #4
80068ce: 4770 bx lr
080068d0 <prvDeleteTCB>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelete == 1 )
static void prvDeleteTCB( TCB_t *pxTCB )
{
80068d0: b580 push {r7, lr}
80068d2: b084 sub sp, #16
80068d4: af00 add r7, sp, #0
80068d6: 6078 str r0, [r7, #4]
/* Free up the memory allocated by the scheduler for the task. It is up
to the task to free any memory allocated at the application level. */
#if ( configUSE_NEWLIB_REENTRANT == 1 )
{
_reclaim_reent( &( pxTCB->xNewLib_reent ) );
80068d8: 687b ldr r3, [r7, #4]
80068da: 3358 adds r3, #88 @ 0x58
80068dc: 4618 mov r0, r3
80068de: f001 f933 bl 8007b48 <_reclaim_reent>
#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* The task could have been allocated statically or dynamically, so
check what was statically allocated before trying to free the
memory. */
if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
80068e2: 687b ldr r3, [r7, #4]
80068e4: f893 30a9 ldrb.w r3, [r3, #169] @ 0xa9
80068e8: 2b00 cmp r3, #0
80068ea: d108 bne.n 80068fe <prvDeleteTCB+0x2e>
{
/* Both the stack and TCB were allocated dynamically, so both
must be freed. */
vPortFree( pxTCB->pxStack );
80068ec: 687b ldr r3, [r7, #4]
80068ee: 6b1b ldr r3, [r3, #48] @ 0x30
80068f0: 4618 mov r0, r3
80068f2: f000 fd51 bl 8007398 <vPortFree>
vPortFree( pxTCB );
80068f6: 6878 ldr r0, [r7, #4]
80068f8: f000 fd4e bl 8007398 <vPortFree>
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
}
80068fc: e01b b.n 8006936 <prvDeleteTCB+0x66>
else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
80068fe: 687b ldr r3, [r7, #4]
8006900: f893 30a9 ldrb.w r3, [r3, #169] @ 0xa9
8006904: 2b01 cmp r3, #1
8006906: d103 bne.n 8006910 <prvDeleteTCB+0x40>
vPortFree( pxTCB );
8006908: 6878 ldr r0, [r7, #4]
800690a: f000 fd45 bl 8007398 <vPortFree>
}
800690e: e012 b.n 8006936 <prvDeleteTCB+0x66>
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
8006910: 687b ldr r3, [r7, #4]
8006912: f893 30a9 ldrb.w r3, [r3, #169] @ 0xa9
8006916: 2b02 cmp r3, #2
8006918: d00d beq.n 8006936 <prvDeleteTCB+0x66>
__asm volatile
800691a: f04f 0350 mov.w r3, #80 @ 0x50
800691e: b672 cpsid i
8006920: f383 8811 msr BASEPRI, r3
8006924: f3bf 8f6f isb sy
8006928: f3bf 8f4f dsb sy
800692c: b662 cpsie i
800692e: 60fb str r3, [r7, #12]
}
8006930: bf00 nop
8006932: bf00 nop
8006934: e7fd b.n 8006932 <prvDeleteTCB+0x62>
}
8006936: bf00 nop
8006938: 3710 adds r7, #16
800693a: 46bd mov sp, r7
800693c: bd80 pop {r7, pc}
...
08006940 <prvResetNextTaskUnblockTime>:
#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/
static void prvResetNextTaskUnblockTime( void )
{
8006940: b480 push {r7}
8006942: b083 sub sp, #12
8006944: af00 add r7, sp, #0
TCB_t *pxTCB;
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
8006946: 4b0c ldr r3, [pc, #48] @ (8006978 <prvResetNextTaskUnblockTime+0x38>)
8006948: 681b ldr r3, [r3, #0]
800694a: 681b ldr r3, [r3, #0]
800694c: 2b00 cmp r3, #0
800694e: d104 bne.n 800695a <prvResetNextTaskUnblockTime+0x1a>
{
/* The new current delayed list is empty. Set xNextTaskUnblockTime to
the maximum possible value so it is extremely unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass until
there is an item in the delayed list. */
xNextTaskUnblockTime = portMAX_DELAY;
8006950: 4b0a ldr r3, [pc, #40] @ (800697c <prvResetNextTaskUnblockTime+0x3c>)
8006952: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8006956: 601a str r2, [r3, #0]
which the task at the head of the delayed list should be removed
from the Blocked state. */
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
}
}
8006958: e008 b.n 800696c <prvResetNextTaskUnblockTime+0x2c>
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800695a: 4b07 ldr r3, [pc, #28] @ (8006978 <prvResetNextTaskUnblockTime+0x38>)
800695c: 681b ldr r3, [r3, #0]
800695e: 68db ldr r3, [r3, #12]
8006960: 68db ldr r3, [r3, #12]
8006962: 607b str r3, [r7, #4]
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
8006964: 687b ldr r3, [r7, #4]
8006966: 685b ldr r3, [r3, #4]
8006968: 4a04 ldr r2, [pc, #16] @ (800697c <prvResetNextTaskUnblockTime+0x3c>)
800696a: 6013 str r3, [r2, #0]
}
800696c: bf00 nop
800696e: 370c adds r7, #12
8006970: 46bd mov sp, r7
8006972: f85d 7b04 ldr.w r7, [sp], #4
8006976: 4770 bx lr
8006978: 20000c50 .word 0x20000c50
800697c: 20000cb8 .word 0x20000cb8
08006980 <xTaskGetSchedulerState>:
/*-----------------------------------------------------------*/
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
BaseType_t xTaskGetSchedulerState( void )
{
8006980: b480 push {r7}
8006982: b083 sub sp, #12
8006984: af00 add r7, sp, #0
BaseType_t xReturn;
if( xSchedulerRunning == pdFALSE )
8006986: 4b0b ldr r3, [pc, #44] @ (80069b4 <xTaskGetSchedulerState+0x34>)
8006988: 681b ldr r3, [r3, #0]
800698a: 2b00 cmp r3, #0
800698c: d102 bne.n 8006994 <xTaskGetSchedulerState+0x14>
{
xReturn = taskSCHEDULER_NOT_STARTED;
800698e: 2301 movs r3, #1
8006990: 607b str r3, [r7, #4]
8006992: e008 b.n 80069a6 <xTaskGetSchedulerState+0x26>
}
else
{
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8006994: 4b08 ldr r3, [pc, #32] @ (80069b8 <xTaskGetSchedulerState+0x38>)
8006996: 681b ldr r3, [r3, #0]
8006998: 2b00 cmp r3, #0
800699a: d102 bne.n 80069a2 <xTaskGetSchedulerState+0x22>
{
xReturn = taskSCHEDULER_RUNNING;
800699c: 2302 movs r3, #2
800699e: 607b str r3, [r7, #4]
80069a0: e001 b.n 80069a6 <xTaskGetSchedulerState+0x26>
}
else
{
xReturn = taskSCHEDULER_SUSPENDED;
80069a2: 2300 movs r3, #0
80069a4: 607b str r3, [r7, #4]
}
}
return xReturn;
80069a6: 687b ldr r3, [r7, #4]
}
80069a8: 4618 mov r0, r3
80069aa: 370c adds r7, #12
80069ac: 46bd mov sp, r7
80069ae: f85d 7b04 ldr.w r7, [sp], #4
80069b2: 4770 bx lr
80069b4: 20000ca4 .word 0x20000ca4
80069b8: 20000cc0 .word 0x20000cc0
080069bc <xTaskPriorityInherit>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
{
80069bc: b580 push {r7, lr}
80069be: b084 sub sp, #16
80069c0: af00 add r7, sp, #0
80069c2: 6078 str r0, [r7, #4]
TCB_t * const pxMutexHolderTCB = pxMutexHolder;
80069c4: 687b ldr r3, [r7, #4]
80069c6: 60bb str r3, [r7, #8]
BaseType_t xReturn = pdFALSE;
80069c8: 2300 movs r3, #0
80069ca: 60fb str r3, [r7, #12]
/* If the mutex was given back by an interrupt while the queue was
locked then the mutex holder might now be NULL. _RB_ Is this still
needed as interrupts can no longer use mutexes? */
if( pxMutexHolder != NULL )
80069cc: 687b ldr r3, [r7, #4]
80069ce: 2b00 cmp r3, #0
80069d0: d069 beq.n 8006aa6 <xTaskPriorityInherit+0xea>
{
/* If the holder of the mutex has a priority below the priority of
the task attempting to obtain the mutex then it will temporarily
inherit the priority of the task attempting to obtain the mutex. */
if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
80069d2: 68bb ldr r3, [r7, #8]
80069d4: 6ada ldr r2, [r3, #44] @ 0x2c
80069d6: 4b36 ldr r3, [pc, #216] @ (8006ab0 <xTaskPriorityInherit+0xf4>)
80069d8: 681b ldr r3, [r3, #0]
80069da: 6adb ldr r3, [r3, #44] @ 0x2c
80069dc: 429a cmp r2, r3
80069de: d259 bcs.n 8006a94 <xTaskPriorityInherit+0xd8>
{
/* Adjust the mutex holder state to account for its new
priority. Only reset the event list item value if the value is
not being used for anything else. */
if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
80069e0: 68bb ldr r3, [r7, #8]
80069e2: 699b ldr r3, [r3, #24]
80069e4: 2b00 cmp r3, #0
80069e6: db06 blt.n 80069f6 <xTaskPriorityInherit+0x3a>
{
listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
80069e8: 4b31 ldr r3, [pc, #196] @ (8006ab0 <xTaskPriorityInherit+0xf4>)
80069ea: 681b ldr r3, [r3, #0]
80069ec: 6adb ldr r3, [r3, #44] @ 0x2c
80069ee: f1c3 0207 rsb r2, r3, #7
80069f2: 68bb ldr r3, [r7, #8]
80069f4: 619a str r2, [r3, #24]
mtCOVERAGE_TEST_MARKER();
}
/* If the task being modified is in the ready state it will need
to be moved into a new list. */
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
80069f6: 68bb ldr r3, [r7, #8]
80069f8: 6959 ldr r1, [r3, #20]
80069fa: 68bb ldr r3, [r7, #8]
80069fc: 6ada ldr r2, [r3, #44] @ 0x2c
80069fe: 4613 mov r3, r2
8006a00: 009b lsls r3, r3, #2
8006a02: 4413 add r3, r2
8006a04: 009b lsls r3, r3, #2
8006a06: 4a2b ldr r2, [pc, #172] @ (8006ab4 <xTaskPriorityInherit+0xf8>)
8006a08: 4413 add r3, r2
8006a0a: 4299 cmp r1, r3
8006a0c: d13a bne.n 8006a84 <xTaskPriorityInherit+0xc8>
{
if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
8006a0e: 68bb ldr r3, [r7, #8]
8006a10: 3304 adds r3, #4
8006a12: 4618 mov r0, r3
8006a14: f7fe fa05 bl 8004e22 <uxListRemove>
8006a18: 4603 mov r3, r0
8006a1a: 2b00 cmp r3, #0
8006a1c: d115 bne.n 8006a4a <xTaskPriorityInherit+0x8e>
{
taskRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority );
8006a1e: 68bb ldr r3, [r7, #8]
8006a20: 6ada ldr r2, [r3, #44] @ 0x2c
8006a22: 4924 ldr r1, [pc, #144] @ (8006ab4 <xTaskPriorityInherit+0xf8>)
8006a24: 4613 mov r3, r2
8006a26: 009b lsls r3, r3, #2
8006a28: 4413 add r3, r2
8006a2a: 009b lsls r3, r3, #2
8006a2c: 440b add r3, r1
8006a2e: 681b ldr r3, [r3, #0]
8006a30: 2b00 cmp r3, #0
8006a32: d10a bne.n 8006a4a <xTaskPriorityInherit+0x8e>
8006a34: 68bb ldr r3, [r7, #8]
8006a36: 6adb ldr r3, [r3, #44] @ 0x2c
8006a38: 2201 movs r2, #1
8006a3a: fa02 f303 lsl.w r3, r2, r3
8006a3e: 43da mvns r2, r3
8006a40: 4b1d ldr r3, [pc, #116] @ (8006ab8 <xTaskPriorityInherit+0xfc>)
8006a42: 681b ldr r3, [r3, #0]
8006a44: 4013 ands r3, r2
8006a46: 4a1c ldr r2, [pc, #112] @ (8006ab8 <xTaskPriorityInherit+0xfc>)
8006a48: 6013 str r3, [r2, #0]
{
mtCOVERAGE_TEST_MARKER();
}
/* Inherit the priority before being moved into the new list. */
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
8006a4a: 4b19 ldr r3, [pc, #100] @ (8006ab0 <xTaskPriorityInherit+0xf4>)
8006a4c: 681b ldr r3, [r3, #0]
8006a4e: 6ada ldr r2, [r3, #44] @ 0x2c
8006a50: 68bb ldr r3, [r7, #8]
8006a52: 62da str r2, [r3, #44] @ 0x2c
prvAddTaskToReadyList( pxMutexHolderTCB );
8006a54: 68bb ldr r3, [r7, #8]
8006a56: 6adb ldr r3, [r3, #44] @ 0x2c
8006a58: 2201 movs r2, #1
8006a5a: 409a lsls r2, r3
8006a5c: 4b16 ldr r3, [pc, #88] @ (8006ab8 <xTaskPriorityInherit+0xfc>)
8006a5e: 681b ldr r3, [r3, #0]
8006a60: 4313 orrs r3, r2
8006a62: 4a15 ldr r2, [pc, #84] @ (8006ab8 <xTaskPriorityInherit+0xfc>)
8006a64: 6013 str r3, [r2, #0]
8006a66: 68bb ldr r3, [r7, #8]
8006a68: 6ada ldr r2, [r3, #44] @ 0x2c
8006a6a: 4613 mov r3, r2
8006a6c: 009b lsls r3, r3, #2
8006a6e: 4413 add r3, r2
8006a70: 009b lsls r3, r3, #2
8006a72: 4a10 ldr r2, [pc, #64] @ (8006ab4 <xTaskPriorityInherit+0xf8>)
8006a74: 441a add r2, r3
8006a76: 68bb ldr r3, [r7, #8]
8006a78: 3304 adds r3, #4
8006a7a: 4619 mov r1, r3
8006a7c: 4610 mov r0, r2
8006a7e: f7fe f973 bl 8004d68 <vListInsertEnd>
8006a82: e004 b.n 8006a8e <xTaskPriorityInherit+0xd2>
}
else
{
/* Just inherit the priority. */
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
8006a84: 4b0a ldr r3, [pc, #40] @ (8006ab0 <xTaskPriorityInherit+0xf4>)
8006a86: 681b ldr r3, [r3, #0]
8006a88: 6ada ldr r2, [r3, #44] @ 0x2c
8006a8a: 68bb ldr r3, [r7, #8]
8006a8c: 62da str r2, [r3, #44] @ 0x2c
}
traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
/* Inheritance occurred. */
xReturn = pdTRUE;
8006a8e: 2301 movs r3, #1
8006a90: 60fb str r3, [r7, #12]
8006a92: e008 b.n 8006aa6 <xTaskPriorityInherit+0xea>
}
else
{
if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
8006a94: 68bb ldr r3, [r7, #8]
8006a96: 6cda ldr r2, [r3, #76] @ 0x4c
8006a98: 4b05 ldr r3, [pc, #20] @ (8006ab0 <xTaskPriorityInherit+0xf4>)
8006a9a: 681b ldr r3, [r3, #0]
8006a9c: 6adb ldr r3, [r3, #44] @ 0x2c
8006a9e: 429a cmp r2, r3
8006aa0: d201 bcs.n 8006aa6 <xTaskPriorityInherit+0xea>
current priority of the mutex holder is not lower than the
priority of the task attempting to take the mutex.
Therefore the mutex holder must have already inherited a
priority, but inheritance would have occurred if that had
not been the case. */
xReturn = pdTRUE;
8006aa2: 2301 movs r3, #1
8006aa4: 60fb str r3, [r7, #12]
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
8006aa6: 68fb ldr r3, [r7, #12]
}
8006aa8: 4618 mov r0, r3
8006aaa: 3710 adds r7, #16
8006aac: 46bd mov sp, r7
8006aae: bd80 pop {r7, pc}
8006ab0: 20000b98 .word 0x20000b98
8006ab4: 20000b9c .word 0x20000b9c
8006ab8: 20000ca0 .word 0x20000ca0
08006abc <xTaskPriorityDisinherit>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
{
8006abc: b580 push {r7, lr}
8006abe: b086 sub sp, #24
8006ac0: af00 add r7, sp, #0
8006ac2: 6078 str r0, [r7, #4]
TCB_t * const pxTCB = pxMutexHolder;
8006ac4: 687b ldr r3, [r7, #4]
8006ac6: 613b str r3, [r7, #16]
BaseType_t xReturn = pdFALSE;
8006ac8: 2300 movs r3, #0
8006aca: 617b str r3, [r7, #20]
if( pxMutexHolder != NULL )
8006acc: 687b ldr r3, [r7, #4]
8006ace: 2b00 cmp r3, #0
8006ad0: d074 beq.n 8006bbc <xTaskPriorityDisinherit+0x100>
{
/* A task can only have an inherited priority if it holds the mutex.
If the mutex is held by a task then it cannot be given from an
interrupt, and if a mutex is given by the holding task then it must
be the running state task. */
configASSERT( pxTCB == pxCurrentTCB );
8006ad2: 4b3d ldr r3, [pc, #244] @ (8006bc8 <xTaskPriorityDisinherit+0x10c>)
8006ad4: 681b ldr r3, [r3, #0]
8006ad6: 693a ldr r2, [r7, #16]
8006ad8: 429a cmp r2, r3
8006ada: d00d beq.n 8006af8 <xTaskPriorityDisinherit+0x3c>
__asm volatile
8006adc: f04f 0350 mov.w r3, #80 @ 0x50
8006ae0: b672 cpsid i
8006ae2: f383 8811 msr BASEPRI, r3
8006ae6: f3bf 8f6f isb sy
8006aea: f3bf 8f4f dsb sy
8006aee: b662 cpsie i
8006af0: 60fb str r3, [r7, #12]
}
8006af2: bf00 nop
8006af4: bf00 nop
8006af6: e7fd b.n 8006af4 <xTaskPriorityDisinherit+0x38>
configASSERT( pxTCB->uxMutexesHeld );
8006af8: 693b ldr r3, [r7, #16]
8006afa: 6d1b ldr r3, [r3, #80] @ 0x50
8006afc: 2b00 cmp r3, #0
8006afe: d10d bne.n 8006b1c <xTaskPriorityDisinherit+0x60>
__asm volatile
8006b00: f04f 0350 mov.w r3, #80 @ 0x50
8006b04: b672 cpsid i
8006b06: f383 8811 msr BASEPRI, r3
8006b0a: f3bf 8f6f isb sy
8006b0e: f3bf 8f4f dsb sy
8006b12: b662 cpsie i
8006b14: 60bb str r3, [r7, #8]
}
8006b16: bf00 nop
8006b18: bf00 nop
8006b1a: e7fd b.n 8006b18 <xTaskPriorityDisinherit+0x5c>
( pxTCB->uxMutexesHeld )--;
8006b1c: 693b ldr r3, [r7, #16]
8006b1e: 6d1b ldr r3, [r3, #80] @ 0x50
8006b20: 1e5a subs r2, r3, #1
8006b22: 693b ldr r3, [r7, #16]
8006b24: 651a str r2, [r3, #80] @ 0x50
/* Has the holder of the mutex inherited the priority of another
task? */
if( pxTCB->uxPriority != pxTCB->uxBasePriority )
8006b26: 693b ldr r3, [r7, #16]
8006b28: 6ada ldr r2, [r3, #44] @ 0x2c
8006b2a: 693b ldr r3, [r7, #16]
8006b2c: 6cdb ldr r3, [r3, #76] @ 0x4c
8006b2e: 429a cmp r2, r3
8006b30: d044 beq.n 8006bbc <xTaskPriorityDisinherit+0x100>
{
/* Only disinherit if no other mutexes are held. */
if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
8006b32: 693b ldr r3, [r7, #16]
8006b34: 6d1b ldr r3, [r3, #80] @ 0x50
8006b36: 2b00 cmp r3, #0
8006b38: d140 bne.n 8006bbc <xTaskPriorityDisinherit+0x100>
/* A task can only have an inherited priority if it holds
the mutex. If the mutex is held by a task then it cannot be
given from an interrupt, and if a mutex is given by the
holding task then it must be the running state task. Remove
the holding task from the ready list. */
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
8006b3a: 693b ldr r3, [r7, #16]
8006b3c: 3304 adds r3, #4
8006b3e: 4618 mov r0, r3
8006b40: f7fe f96f bl 8004e22 <uxListRemove>
8006b44: 4603 mov r3, r0
8006b46: 2b00 cmp r3, #0
8006b48: d115 bne.n 8006b76 <xTaskPriorityDisinherit+0xba>
{
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
8006b4a: 693b ldr r3, [r7, #16]
8006b4c: 6ada ldr r2, [r3, #44] @ 0x2c
8006b4e: 491f ldr r1, [pc, #124] @ (8006bcc <xTaskPriorityDisinherit+0x110>)
8006b50: 4613 mov r3, r2
8006b52: 009b lsls r3, r3, #2
8006b54: 4413 add r3, r2
8006b56: 009b lsls r3, r3, #2
8006b58: 440b add r3, r1
8006b5a: 681b ldr r3, [r3, #0]
8006b5c: 2b00 cmp r3, #0
8006b5e: d10a bne.n 8006b76 <xTaskPriorityDisinherit+0xba>
8006b60: 693b ldr r3, [r7, #16]
8006b62: 6adb ldr r3, [r3, #44] @ 0x2c
8006b64: 2201 movs r2, #1
8006b66: fa02 f303 lsl.w r3, r2, r3
8006b6a: 43da mvns r2, r3
8006b6c: 4b18 ldr r3, [pc, #96] @ (8006bd0 <xTaskPriorityDisinherit+0x114>)
8006b6e: 681b ldr r3, [r3, #0]
8006b70: 4013 ands r3, r2
8006b72: 4a17 ldr r2, [pc, #92] @ (8006bd0 <xTaskPriorityDisinherit+0x114>)
8006b74: 6013 str r3, [r2, #0]
}
/* Disinherit the priority before adding the task into the
new ready list. */
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
pxTCB->uxPriority = pxTCB->uxBasePriority;
8006b76: 693b ldr r3, [r7, #16]
8006b78: 6cda ldr r2, [r3, #76] @ 0x4c
8006b7a: 693b ldr r3, [r7, #16]
8006b7c: 62da str r2, [r3, #44] @ 0x2c
/* Reset the event list item value. It cannot be in use for
any other purpose if this task is running, and it must be
running to give back the mutex. */
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8006b7e: 693b ldr r3, [r7, #16]
8006b80: 6adb ldr r3, [r3, #44] @ 0x2c
8006b82: f1c3 0207 rsb r2, r3, #7
8006b86: 693b ldr r3, [r7, #16]
8006b88: 619a str r2, [r3, #24]
prvAddTaskToReadyList( pxTCB );
8006b8a: 693b ldr r3, [r7, #16]
8006b8c: 6adb ldr r3, [r3, #44] @ 0x2c
8006b8e: 2201 movs r2, #1
8006b90: 409a lsls r2, r3
8006b92: 4b0f ldr r3, [pc, #60] @ (8006bd0 <xTaskPriorityDisinherit+0x114>)
8006b94: 681b ldr r3, [r3, #0]
8006b96: 4313 orrs r3, r2
8006b98: 4a0d ldr r2, [pc, #52] @ (8006bd0 <xTaskPriorityDisinherit+0x114>)
8006b9a: 6013 str r3, [r2, #0]
8006b9c: 693b ldr r3, [r7, #16]
8006b9e: 6ada ldr r2, [r3, #44] @ 0x2c
8006ba0: 4613 mov r3, r2
8006ba2: 009b lsls r3, r3, #2
8006ba4: 4413 add r3, r2
8006ba6: 009b lsls r3, r3, #2
8006ba8: 4a08 ldr r2, [pc, #32] @ (8006bcc <xTaskPriorityDisinherit+0x110>)
8006baa: 441a add r2, r3
8006bac: 693b ldr r3, [r7, #16]
8006bae: 3304 adds r3, #4
8006bb0: 4619 mov r1, r3
8006bb2: 4610 mov r0, r2
8006bb4: f7fe f8d8 bl 8004d68 <vListInsertEnd>
in an order different to that in which they were taken.
If a context switch did not occur when the first mutex was
returned, even if a task was waiting on it, then a context
switch should occur when the last mutex is returned whether
a task is waiting on it or not. */
xReturn = pdTRUE;
8006bb8: 2301 movs r3, #1
8006bba: 617b str r3, [r7, #20]
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
8006bbc: 697b ldr r3, [r7, #20]
}
8006bbe: 4618 mov r0, r3
8006bc0: 3718 adds r7, #24
8006bc2: 46bd mov sp, r7
8006bc4: bd80 pop {r7, pc}
8006bc6: bf00 nop
8006bc8: 20000b98 .word 0x20000b98
8006bcc: 20000b9c .word 0x20000b9c
8006bd0: 20000ca0 .word 0x20000ca0
08006bd4 <vTaskPriorityDisinheritAfterTimeout>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
{
8006bd4: b580 push {r7, lr}
8006bd6: b088 sub sp, #32
8006bd8: af00 add r7, sp, #0
8006bda: 6078 str r0, [r7, #4]
8006bdc: 6039 str r1, [r7, #0]
TCB_t * const pxTCB = pxMutexHolder;
8006bde: 687b ldr r3, [r7, #4]
8006be0: 61bb str r3, [r7, #24]
UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
8006be2: 2301 movs r3, #1
8006be4: 617b str r3, [r7, #20]
if( pxMutexHolder != NULL )
8006be6: 687b ldr r3, [r7, #4]
8006be8: 2b00 cmp r3, #0
8006bea: f000 8089 beq.w 8006d00 <vTaskPriorityDisinheritAfterTimeout+0x12c>
{
/* If pxMutexHolder is not NULL then the holder must hold at least
one mutex. */
configASSERT( pxTCB->uxMutexesHeld );
8006bee: 69bb ldr r3, [r7, #24]
8006bf0: 6d1b ldr r3, [r3, #80] @ 0x50
8006bf2: 2b00 cmp r3, #0
8006bf4: d10d bne.n 8006c12 <vTaskPriorityDisinheritAfterTimeout+0x3e>
__asm volatile
8006bf6: f04f 0350 mov.w r3, #80 @ 0x50
8006bfa: b672 cpsid i
8006bfc: f383 8811 msr BASEPRI, r3
8006c00: f3bf 8f6f isb sy
8006c04: f3bf 8f4f dsb sy
8006c08: b662 cpsie i
8006c0a: 60fb str r3, [r7, #12]
}
8006c0c: bf00 nop
8006c0e: bf00 nop
8006c10: e7fd b.n 8006c0e <vTaskPriorityDisinheritAfterTimeout+0x3a>
/* Determine the priority to which the priority of the task that
holds the mutex should be set. This will be the greater of the
holding task's base priority and the priority of the highest
priority task that is waiting to obtain the mutex. */
if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
8006c12: 69bb ldr r3, [r7, #24]
8006c14: 6cdb ldr r3, [r3, #76] @ 0x4c
8006c16: 683a ldr r2, [r7, #0]
8006c18: 429a cmp r2, r3
8006c1a: d902 bls.n 8006c22 <vTaskPriorityDisinheritAfterTimeout+0x4e>
{
uxPriorityToUse = uxHighestPriorityWaitingTask;
8006c1c: 683b ldr r3, [r7, #0]
8006c1e: 61fb str r3, [r7, #28]
8006c20: e002 b.n 8006c28 <vTaskPriorityDisinheritAfterTimeout+0x54>
}
else
{
uxPriorityToUse = pxTCB->uxBasePriority;
8006c22: 69bb ldr r3, [r7, #24]
8006c24: 6cdb ldr r3, [r3, #76] @ 0x4c
8006c26: 61fb str r3, [r7, #28]
}
/* Does the priority need to change? */
if( pxTCB->uxPriority != uxPriorityToUse )
8006c28: 69bb ldr r3, [r7, #24]
8006c2a: 6adb ldr r3, [r3, #44] @ 0x2c
8006c2c: 69fa ldr r2, [r7, #28]
8006c2e: 429a cmp r2, r3
8006c30: d066 beq.n 8006d00 <vTaskPriorityDisinheritAfterTimeout+0x12c>
{
/* Only disinherit if no other mutexes are held. This is a
simplification in the priority inheritance implementation. If
the task that holds the mutex is also holding other mutexes then
the other mutexes may have caused the priority inheritance. */
if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
8006c32: 69bb ldr r3, [r7, #24]
8006c34: 6d1b ldr r3, [r3, #80] @ 0x50
8006c36: 697a ldr r2, [r7, #20]
8006c38: 429a cmp r2, r3
8006c3a: d161 bne.n 8006d00 <vTaskPriorityDisinheritAfterTimeout+0x12c>
{
/* If a task has timed out because it already holds the
mutex it was trying to obtain then it cannot of inherited
its own priority. */
configASSERT( pxTCB != pxCurrentTCB );
8006c3c: 4b32 ldr r3, [pc, #200] @ (8006d08 <vTaskPriorityDisinheritAfterTimeout+0x134>)
8006c3e: 681b ldr r3, [r3, #0]
8006c40: 69ba ldr r2, [r7, #24]
8006c42: 429a cmp r2, r3
8006c44: d10d bne.n 8006c62 <vTaskPriorityDisinheritAfterTimeout+0x8e>
__asm volatile
8006c46: f04f 0350 mov.w r3, #80 @ 0x50
8006c4a: b672 cpsid i
8006c4c: f383 8811 msr BASEPRI, r3
8006c50: f3bf 8f6f isb sy
8006c54: f3bf 8f4f dsb sy
8006c58: b662 cpsie i
8006c5a: 60bb str r3, [r7, #8]
}
8006c5c: bf00 nop
8006c5e: bf00 nop
8006c60: e7fd b.n 8006c5e <vTaskPriorityDisinheritAfterTimeout+0x8a>
/* Disinherit the priority, remembering the previous
priority to facilitate determining the subject task's
state. */
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
uxPriorityUsedOnEntry = pxTCB->uxPriority;
8006c62: 69bb ldr r3, [r7, #24]
8006c64: 6adb ldr r3, [r3, #44] @ 0x2c
8006c66: 613b str r3, [r7, #16]
pxTCB->uxPriority = uxPriorityToUse;
8006c68: 69bb ldr r3, [r7, #24]
8006c6a: 69fa ldr r2, [r7, #28]
8006c6c: 62da str r2, [r3, #44] @ 0x2c
/* Only reset the event list item value if the value is not
being used for anything else. */
if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
8006c6e: 69bb ldr r3, [r7, #24]
8006c70: 699b ldr r3, [r3, #24]
8006c72: 2b00 cmp r3, #0
8006c74: db04 blt.n 8006c80 <vTaskPriorityDisinheritAfterTimeout+0xac>
{
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8006c76: 69fb ldr r3, [r7, #28]
8006c78: f1c3 0207 rsb r2, r3, #7
8006c7c: 69bb ldr r3, [r7, #24]
8006c7e: 619a str r2, [r3, #24]
then the task that holds the mutex could be in either the
Ready, Blocked or Suspended states. Only remove the task
from its current state list if it is in the Ready state as
the task's priority is going to change and there is one
Ready list per priority. */
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
8006c80: 69bb ldr r3, [r7, #24]
8006c82: 6959 ldr r1, [r3, #20]
8006c84: 693a ldr r2, [r7, #16]
8006c86: 4613 mov r3, r2
8006c88: 009b lsls r3, r3, #2
8006c8a: 4413 add r3, r2
8006c8c: 009b lsls r3, r3, #2
8006c8e: 4a1f ldr r2, [pc, #124] @ (8006d0c <vTaskPriorityDisinheritAfterTimeout+0x138>)
8006c90: 4413 add r3, r2
8006c92: 4299 cmp r1, r3
8006c94: d134 bne.n 8006d00 <vTaskPriorityDisinheritAfterTimeout+0x12c>
{
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
8006c96: 69bb ldr r3, [r7, #24]
8006c98: 3304 adds r3, #4
8006c9a: 4618 mov r0, r3
8006c9c: f7fe f8c1 bl 8004e22 <uxListRemove>
8006ca0: 4603 mov r3, r0
8006ca2: 2b00 cmp r3, #0
8006ca4: d115 bne.n 8006cd2 <vTaskPriorityDisinheritAfterTimeout+0xfe>
{
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
8006ca6: 69bb ldr r3, [r7, #24]
8006ca8: 6ada ldr r2, [r3, #44] @ 0x2c
8006caa: 4918 ldr r1, [pc, #96] @ (8006d0c <vTaskPriorityDisinheritAfterTimeout+0x138>)
8006cac: 4613 mov r3, r2
8006cae: 009b lsls r3, r3, #2
8006cb0: 4413 add r3, r2
8006cb2: 009b lsls r3, r3, #2
8006cb4: 440b add r3, r1
8006cb6: 681b ldr r3, [r3, #0]
8006cb8: 2b00 cmp r3, #0
8006cba: d10a bne.n 8006cd2 <vTaskPriorityDisinheritAfterTimeout+0xfe>
8006cbc: 69bb ldr r3, [r7, #24]
8006cbe: 6adb ldr r3, [r3, #44] @ 0x2c
8006cc0: 2201 movs r2, #1
8006cc2: fa02 f303 lsl.w r3, r2, r3
8006cc6: 43da mvns r2, r3
8006cc8: 4b11 ldr r3, [pc, #68] @ (8006d10 <vTaskPriorityDisinheritAfterTimeout+0x13c>)
8006cca: 681b ldr r3, [r3, #0]
8006ccc: 4013 ands r3, r2
8006cce: 4a10 ldr r2, [pc, #64] @ (8006d10 <vTaskPriorityDisinheritAfterTimeout+0x13c>)
8006cd0: 6013 str r3, [r2, #0]
else
{
mtCOVERAGE_TEST_MARKER();
}
prvAddTaskToReadyList( pxTCB );
8006cd2: 69bb ldr r3, [r7, #24]
8006cd4: 6adb ldr r3, [r3, #44] @ 0x2c
8006cd6: 2201 movs r2, #1
8006cd8: 409a lsls r2, r3
8006cda: 4b0d ldr r3, [pc, #52] @ (8006d10 <vTaskPriorityDisinheritAfterTimeout+0x13c>)
8006cdc: 681b ldr r3, [r3, #0]
8006cde: 4313 orrs r3, r2
8006ce0: 4a0b ldr r2, [pc, #44] @ (8006d10 <vTaskPriorityDisinheritAfterTimeout+0x13c>)
8006ce2: 6013 str r3, [r2, #0]
8006ce4: 69bb ldr r3, [r7, #24]
8006ce6: 6ada ldr r2, [r3, #44] @ 0x2c
8006ce8: 4613 mov r3, r2
8006cea: 009b lsls r3, r3, #2
8006cec: 4413 add r3, r2
8006cee: 009b lsls r3, r3, #2
8006cf0: 4a06 ldr r2, [pc, #24] @ (8006d0c <vTaskPriorityDisinheritAfterTimeout+0x138>)
8006cf2: 441a add r2, r3
8006cf4: 69bb ldr r3, [r7, #24]
8006cf6: 3304 adds r3, #4
8006cf8: 4619 mov r1, r3
8006cfa: 4610 mov r0, r2
8006cfc: f7fe f834 bl 8004d68 <vListInsertEnd>
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8006d00: bf00 nop
8006d02: 3720 adds r7, #32
8006d04: 46bd mov sp, r7
8006d06: bd80 pop {r7, pc}
8006d08: 20000b98 .word 0x20000b98
8006d0c: 20000b9c .word 0x20000b9c
8006d10: 20000ca0 .word 0x20000ca0
08006d14 <pvTaskIncrementMutexHeldCount>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
TaskHandle_t pvTaskIncrementMutexHeldCount( void )
{
8006d14: b480 push {r7}
8006d16: af00 add r7, sp, #0
/* If xSemaphoreCreateMutex() is called before any tasks have been created
then pxCurrentTCB will be NULL. */
if( pxCurrentTCB != NULL )
8006d18: 4b07 ldr r3, [pc, #28] @ (8006d38 <pvTaskIncrementMutexHeldCount+0x24>)
8006d1a: 681b ldr r3, [r3, #0]
8006d1c: 2b00 cmp r3, #0
8006d1e: d004 beq.n 8006d2a <pvTaskIncrementMutexHeldCount+0x16>
{
( pxCurrentTCB->uxMutexesHeld )++;
8006d20: 4b05 ldr r3, [pc, #20] @ (8006d38 <pvTaskIncrementMutexHeldCount+0x24>)
8006d22: 681b ldr r3, [r3, #0]
8006d24: 6d1a ldr r2, [r3, #80] @ 0x50
8006d26: 3201 adds r2, #1
8006d28: 651a str r2, [r3, #80] @ 0x50
}
return pxCurrentTCB;
8006d2a: 4b03 ldr r3, [pc, #12] @ (8006d38 <pvTaskIncrementMutexHeldCount+0x24>)
8006d2c: 681b ldr r3, [r3, #0]
}
8006d2e: 4618 mov r0, r3
8006d30: 46bd mov sp, r7
8006d32: f85d 7b04 ldr.w r7, [sp], #4
8006d36: 4770 bx lr
8006d38: 20000b98 .word 0x20000b98
08006d3c <prvAddCurrentTaskToDelayedList>:
}
#endif
/*-----------------------------------------------------------*/
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
{
8006d3c: b580 push {r7, lr}
8006d3e: b084 sub sp, #16
8006d40: af00 add r7, sp, #0
8006d42: 6078 str r0, [r7, #4]
8006d44: 6039 str r1, [r7, #0]
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
8006d46: 4b29 ldr r3, [pc, #164] @ (8006dec <prvAddCurrentTaskToDelayedList+0xb0>)
8006d48: 681b ldr r3, [r3, #0]
8006d4a: 60fb str r3, [r7, #12]
}
#endif
/* Remove the task from the ready list before adding it to the blocked list
as the same list item is used for both lists. */
if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
8006d4c: 4b28 ldr r3, [pc, #160] @ (8006df0 <prvAddCurrentTaskToDelayedList+0xb4>)
8006d4e: 681b ldr r3, [r3, #0]
8006d50: 3304 adds r3, #4
8006d52: 4618 mov r0, r3
8006d54: f7fe f865 bl 8004e22 <uxListRemove>
8006d58: 4603 mov r3, r0
8006d5a: 2b00 cmp r3, #0
8006d5c: d10b bne.n 8006d76 <prvAddCurrentTaskToDelayedList+0x3a>
{
/* The current task must be in a ready list, so there is no need to
check, and the port reset macro can be called directly. */
portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
8006d5e: 4b24 ldr r3, [pc, #144] @ (8006df0 <prvAddCurrentTaskToDelayedList+0xb4>)
8006d60: 681b ldr r3, [r3, #0]
8006d62: 6adb ldr r3, [r3, #44] @ 0x2c
8006d64: 2201 movs r2, #1
8006d66: fa02 f303 lsl.w r3, r2, r3
8006d6a: 43da mvns r2, r3
8006d6c: 4b21 ldr r3, [pc, #132] @ (8006df4 <prvAddCurrentTaskToDelayedList+0xb8>)
8006d6e: 681b ldr r3, [r3, #0]
8006d70: 4013 ands r3, r2
8006d72: 4a20 ldr r2, [pc, #128] @ (8006df4 <prvAddCurrentTaskToDelayedList+0xb8>)
8006d74: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
#if ( INCLUDE_vTaskSuspend == 1 )
{
if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
8006d76: 687b ldr r3, [r7, #4]
8006d78: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8006d7c: d10a bne.n 8006d94 <prvAddCurrentTaskToDelayedList+0x58>
8006d7e: 683b ldr r3, [r7, #0]
8006d80: 2b00 cmp r3, #0
8006d82: d007 beq.n 8006d94 <prvAddCurrentTaskToDelayedList+0x58>
{
/* Add the task to the suspended task list instead of a delayed task
list to ensure it is not woken by a timing event. It will block
indefinitely. */
vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
8006d84: 4b1a ldr r3, [pc, #104] @ (8006df0 <prvAddCurrentTaskToDelayedList+0xb4>)
8006d86: 681b ldr r3, [r3, #0]
8006d88: 3304 adds r3, #4
8006d8a: 4619 mov r1, r3
8006d8c: 481a ldr r0, [pc, #104] @ (8006df8 <prvAddCurrentTaskToDelayedList+0xbc>)
8006d8e: f7fd ffeb bl 8004d68 <vListInsertEnd>
/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
( void ) xCanBlockIndefinitely;
}
#endif /* INCLUDE_vTaskSuspend */
}
8006d92: e026 b.n 8006de2 <prvAddCurrentTaskToDelayedList+0xa6>
xTimeToWake = xConstTickCount + xTicksToWait;
8006d94: 68fa ldr r2, [r7, #12]
8006d96: 687b ldr r3, [r7, #4]
8006d98: 4413 add r3, r2
8006d9a: 60bb str r3, [r7, #8]
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
8006d9c: 4b14 ldr r3, [pc, #80] @ (8006df0 <prvAddCurrentTaskToDelayedList+0xb4>)
8006d9e: 681b ldr r3, [r3, #0]
8006da0: 68ba ldr r2, [r7, #8]
8006da2: 605a str r2, [r3, #4]
if( xTimeToWake < xConstTickCount )
8006da4: 68ba ldr r2, [r7, #8]
8006da6: 68fb ldr r3, [r7, #12]
8006da8: 429a cmp r2, r3
8006daa: d209 bcs.n 8006dc0 <prvAddCurrentTaskToDelayedList+0x84>
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
8006dac: 4b13 ldr r3, [pc, #76] @ (8006dfc <prvAddCurrentTaskToDelayedList+0xc0>)
8006dae: 681a ldr r2, [r3, #0]
8006db0: 4b0f ldr r3, [pc, #60] @ (8006df0 <prvAddCurrentTaskToDelayedList+0xb4>)
8006db2: 681b ldr r3, [r3, #0]
8006db4: 3304 adds r3, #4
8006db6: 4619 mov r1, r3
8006db8: 4610 mov r0, r2
8006dba: f7fd fff9 bl 8004db0 <vListInsert>
}
8006dbe: e010 b.n 8006de2 <prvAddCurrentTaskToDelayedList+0xa6>
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
8006dc0: 4b0f ldr r3, [pc, #60] @ (8006e00 <prvAddCurrentTaskToDelayedList+0xc4>)
8006dc2: 681a ldr r2, [r3, #0]
8006dc4: 4b0a ldr r3, [pc, #40] @ (8006df0 <prvAddCurrentTaskToDelayedList+0xb4>)
8006dc6: 681b ldr r3, [r3, #0]
8006dc8: 3304 adds r3, #4
8006dca: 4619 mov r1, r3
8006dcc: 4610 mov r0, r2
8006dce: f7fd ffef bl 8004db0 <vListInsert>
if( xTimeToWake < xNextTaskUnblockTime )
8006dd2: 4b0c ldr r3, [pc, #48] @ (8006e04 <prvAddCurrentTaskToDelayedList+0xc8>)
8006dd4: 681b ldr r3, [r3, #0]
8006dd6: 68ba ldr r2, [r7, #8]
8006dd8: 429a cmp r2, r3
8006dda: d202 bcs.n 8006de2 <prvAddCurrentTaskToDelayedList+0xa6>
xNextTaskUnblockTime = xTimeToWake;
8006ddc: 4a09 ldr r2, [pc, #36] @ (8006e04 <prvAddCurrentTaskToDelayedList+0xc8>)
8006dde: 68bb ldr r3, [r7, #8]
8006de0: 6013 str r3, [r2, #0]
}
8006de2: bf00 nop
8006de4: 3710 adds r7, #16
8006de6: 46bd mov sp, r7
8006de8: bd80 pop {r7, pc}
8006dea: bf00 nop
8006dec: 20000c9c .word 0x20000c9c
8006df0: 20000b98 .word 0x20000b98
8006df4: 20000ca0 .word 0x20000ca0
8006df8: 20000c84 .word 0x20000c84
8006dfc: 20000c54 .word 0x20000c54
8006e00: 20000c50 .word 0x20000c50
8006e04: 20000cb8 .word 0x20000cb8
08006e08 <pxPortInitialiseStack>:
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
8006e08: b480 push {r7}
8006e0a: b085 sub sp, #20
8006e0c: af00 add r7, sp, #0
8006e0e: 60f8 str r0, [r7, #12]
8006e10: 60b9 str r1, [r7, #8]
8006e12: 607a str r2, [r7, #4]
/* Simulate the stack frame as it would be created by a context switch
interrupt. */
/* Offset added to account for the way the MCU uses the stack on entry/exit
of interrupts, and to ensure alignment. */
pxTopOfStack--;
8006e14: 68fb ldr r3, [r7, #12]
8006e16: 3b04 subs r3, #4
8006e18: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
8006e1a: 68fb ldr r3, [r7, #12]
8006e1c: f04f 7280 mov.w r2, #16777216 @ 0x1000000
8006e20: 601a str r2, [r3, #0]
pxTopOfStack--;
8006e22: 68fb ldr r3, [r7, #12]
8006e24: 3b04 subs r3, #4
8006e26: 60fb str r3, [r7, #12]
*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
8006e28: 68bb ldr r3, [r7, #8]
8006e2a: f023 0201 bic.w r2, r3, #1
8006e2e: 68fb ldr r3, [r7, #12]
8006e30: 601a str r2, [r3, #0]
pxTopOfStack--;
8006e32: 68fb ldr r3, [r7, #12]
8006e34: 3b04 subs r3, #4
8006e36: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
8006e38: 4a0c ldr r2, [pc, #48] @ (8006e6c <pxPortInitialiseStack+0x64>)
8006e3a: 68fb ldr r3, [r7, #12]
8006e3c: 601a str r2, [r3, #0]
/* Save code space by skipping register initialisation. */
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
8006e3e: 68fb ldr r3, [r7, #12]
8006e40: 3b14 subs r3, #20
8006e42: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
8006e44: 687a ldr r2, [r7, #4]
8006e46: 68fb ldr r3, [r7, #12]
8006e48: 601a str r2, [r3, #0]
/* A save method is being used that requires each task to maintain its
own exec return value. */
pxTopOfStack--;
8006e4a: 68fb ldr r3, [r7, #12]
8006e4c: 3b04 subs r3, #4
8006e4e: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_EXC_RETURN;
8006e50: 68fb ldr r3, [r7, #12]
8006e52: f06f 0202 mvn.w r2, #2
8006e56: 601a str r2, [r3, #0]
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
8006e58: 68fb ldr r3, [r7, #12]
8006e5a: 3b20 subs r3, #32
8006e5c: 60fb str r3, [r7, #12]
return pxTopOfStack;
8006e5e: 68fb ldr r3, [r7, #12]
}
8006e60: 4618 mov r0, r3
8006e62: 3714 adds r7, #20
8006e64: 46bd mov sp, r7
8006e66: f85d 7b04 ldr.w r7, [sp], #4
8006e6a: 4770 bx lr
8006e6c: 08006e71 .word 0x08006e71
08006e70 <prvTaskExitError>:
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
8006e70: b480 push {r7}
8006e72: b085 sub sp, #20
8006e74: af00 add r7, sp, #0
volatile uint32_t ulDummy = 0;
8006e76: 2300 movs r3, #0
8006e78: 607b str r3, [r7, #4]
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
configASSERT( uxCriticalNesting == ~0UL );
8006e7a: 4b15 ldr r3, [pc, #84] @ (8006ed0 <prvTaskExitError+0x60>)
8006e7c: 681b ldr r3, [r3, #0]
8006e7e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8006e82: d00d beq.n 8006ea0 <prvTaskExitError+0x30>
__asm volatile
8006e84: f04f 0350 mov.w r3, #80 @ 0x50
8006e88: b672 cpsid i
8006e8a: f383 8811 msr BASEPRI, r3
8006e8e: f3bf 8f6f isb sy
8006e92: f3bf 8f4f dsb sy
8006e96: b662 cpsie i
8006e98: 60fb str r3, [r7, #12]
}
8006e9a: bf00 nop
8006e9c: bf00 nop
8006e9e: e7fd b.n 8006e9c <prvTaskExitError+0x2c>
__asm volatile
8006ea0: f04f 0350 mov.w r3, #80 @ 0x50
8006ea4: b672 cpsid i
8006ea6: f383 8811 msr BASEPRI, r3
8006eaa: f3bf 8f6f isb sy
8006eae: f3bf 8f4f dsb sy
8006eb2: b662 cpsie i
8006eb4: 60bb str r3, [r7, #8]
}
8006eb6: bf00 nop
portDISABLE_INTERRUPTS();
while( ulDummy == 0 )
8006eb8: bf00 nop
8006eba: 687b ldr r3, [r7, #4]
8006ebc: 2b00 cmp r3, #0
8006ebe: d0fc beq.n 8006eba <prvTaskExitError+0x4a>
about code appearing after this function is called - making ulDummy
volatile makes the compiler think the function could return and
therefore not output an 'unreachable code' warning for code that appears
after it. */
}
}
8006ec0: bf00 nop
8006ec2: bf00 nop
8006ec4: 3714 adds r7, #20
8006ec6: 46bd mov sp, r7
8006ec8: f85d 7b04 ldr.w r7, [sp], #4
8006ecc: 4770 bx lr
8006ece: bf00 nop
8006ed0: 2000000c .word 0x2000000c
...
08006ee0 <SVC_Handler>:
/*-----------------------------------------------------------*/
void vPortSVCHandler( void )
{
__asm volatile (
8006ee0: 4b07 ldr r3, [pc, #28] @ (8006f00 <pxCurrentTCBConst2>)
8006ee2: 6819 ldr r1, [r3, #0]
8006ee4: 6808 ldr r0, [r1, #0]
8006ee6: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8006eea: f380 8809 msr PSP, r0
8006eee: f3bf 8f6f isb sy
8006ef2: f04f 0000 mov.w r0, #0
8006ef6: f380 8811 msr BASEPRI, r0
8006efa: 4770 bx lr
8006efc: f3af 8000 nop.w
08006f00 <pxCurrentTCBConst2>:
8006f00: 20000b98 .word 0x20000b98
" bx r14 \n"
" \n"
" .align 4 \n"
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
}
8006f04: bf00 nop
8006f06: bf00 nop
08006f08 <prvPortStartFirstTask>:
{
/* Start the first task. This also clears the bit that indicates the FPU is
in use in case the FPU was used before the scheduler was started - which
would otherwise result in the unnecessary leaving of space in the SVC stack
for lazy saving of FPU registers. */
__asm volatile(
8006f08: 4808 ldr r0, [pc, #32] @ (8006f2c <prvPortStartFirstTask+0x24>)
8006f0a: 6800 ldr r0, [r0, #0]
8006f0c: 6800 ldr r0, [r0, #0]
8006f0e: f380 8808 msr MSP, r0
8006f12: f04f 0000 mov.w r0, #0
8006f16: f380 8814 msr CONTROL, r0
8006f1a: b662 cpsie i
8006f1c: b661 cpsie f
8006f1e: f3bf 8f4f dsb sy
8006f22: f3bf 8f6f isb sy
8006f26: df00 svc 0
8006f28: bf00 nop
" dsb \n"
" isb \n"
" svc 0 \n" /* System call to start first task. */
" nop \n"
);
}
8006f2a: bf00 nop
8006f2c: e000ed08 .word 0xe000ed08
08006f30 <xPortStartScheduler>:
/*
* See header file for description.
*/
BaseType_t xPortStartScheduler( void )
{
8006f30: b580 push {r7, lr}
8006f32: b084 sub sp, #16
8006f34: af00 add r7, sp, #0
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
#if( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
8006f36: 4b37 ldr r3, [pc, #220] @ (8007014 <xPortStartScheduler+0xe4>)
8006f38: 60fb str r3, [r7, #12]
functions can be called. ISR safe functions are those that end in
"FromISR". FreeRTOS maintains separate thread and ISR API functions to
ensure interrupt entry is as fast and simple as possible.
Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
8006f3a: 68fb ldr r3, [r7, #12]
8006f3c: 781b ldrb r3, [r3, #0]
8006f3e: b2db uxtb r3, r3
8006f40: 607b str r3, [r7, #4]
/* Determine the number of priority bits available. First write to all
possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
8006f42: 68fb ldr r3, [r7, #12]
8006f44: 22ff movs r2, #255 @ 0xff
8006f46: 701a strb r2, [r3, #0]
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
8006f48: 68fb ldr r3, [r7, #12]
8006f4a: 781b ldrb r3, [r3, #0]
8006f4c: b2db uxtb r3, r3
8006f4e: 70fb strb r3, [r7, #3]
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
8006f50: 78fb ldrb r3, [r7, #3]
8006f52: b2db uxtb r3, r3
8006f54: f003 0350 and.w r3, r3, #80 @ 0x50
8006f58: b2da uxtb r2, r3
8006f5a: 4b2f ldr r3, [pc, #188] @ (8007018 <xPortStartScheduler+0xe8>)
8006f5c: 701a strb r2, [r3, #0]
/* Calculate the maximum acceptable priority group value for the number
of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
8006f5e: 4b2f ldr r3, [pc, #188] @ (800701c <xPortStartScheduler+0xec>)
8006f60: 2207 movs r2, #7
8006f62: 601a str r2, [r3, #0]
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
8006f64: e009 b.n 8006f7a <xPortStartScheduler+0x4a>
{
ulMaxPRIGROUPValue--;
8006f66: 4b2d ldr r3, [pc, #180] @ (800701c <xPortStartScheduler+0xec>)
8006f68: 681b ldr r3, [r3, #0]
8006f6a: 3b01 subs r3, #1
8006f6c: 4a2b ldr r2, [pc, #172] @ (800701c <xPortStartScheduler+0xec>)
8006f6e: 6013 str r3, [r2, #0]
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
8006f70: 78fb ldrb r3, [r7, #3]
8006f72: b2db uxtb r3, r3
8006f74: 005b lsls r3, r3, #1
8006f76: b2db uxtb r3, r3
8006f78: 70fb strb r3, [r7, #3]
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
8006f7a: 78fb ldrb r3, [r7, #3]
8006f7c: b2db uxtb r3, r3
8006f7e: f003 0380 and.w r3, r3, #128 @ 0x80
8006f82: 2b80 cmp r3, #128 @ 0x80
8006f84: d0ef beq.n 8006f66 <xPortStartScheduler+0x36>
#ifdef configPRIO_BITS
{
/* Check the FreeRTOS configuration that defines the number of
priority bits matches the number of priority bits actually queried
from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
8006f86: 4b25 ldr r3, [pc, #148] @ (800701c <xPortStartScheduler+0xec>)
8006f88: 681b ldr r3, [r3, #0]
8006f8a: f1c3 0307 rsb r3, r3, #7
8006f8e: 2b04 cmp r3, #4
8006f90: d00d beq.n 8006fae <xPortStartScheduler+0x7e>
__asm volatile
8006f92: f04f 0350 mov.w r3, #80 @ 0x50
8006f96: b672 cpsid i
8006f98: f383 8811 msr BASEPRI, r3
8006f9c: f3bf 8f6f isb sy
8006fa0: f3bf 8f4f dsb sy
8006fa4: b662 cpsie i
8006fa6: 60bb str r3, [r7, #8]
}
8006fa8: bf00 nop
8006faa: bf00 nop
8006fac: e7fd b.n 8006faa <xPortStartScheduler+0x7a>
}
#endif
/* Shift the priority group value back to its position within the AIRCR
register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
8006fae: 4b1b ldr r3, [pc, #108] @ (800701c <xPortStartScheduler+0xec>)
8006fb0: 681b ldr r3, [r3, #0]
8006fb2: 021b lsls r3, r3, #8
8006fb4: 4a19 ldr r2, [pc, #100] @ (800701c <xPortStartScheduler+0xec>)
8006fb6: 6013 str r3, [r2, #0]
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
8006fb8: 4b18 ldr r3, [pc, #96] @ (800701c <xPortStartScheduler+0xec>)
8006fba: 681b ldr r3, [r3, #0]
8006fbc: f403 63e0 and.w r3, r3, #1792 @ 0x700
8006fc0: 4a16 ldr r2, [pc, #88] @ (800701c <xPortStartScheduler+0xec>)
8006fc2: 6013 str r3, [r2, #0]
/* Restore the clobbered interrupt priority register to its original
value. */
*pucFirstUserPriorityRegister = ulOriginalPriority;
8006fc4: 687b ldr r3, [r7, #4]
8006fc6: b2da uxtb r2, r3
8006fc8: 68fb ldr r3, [r7, #12]
8006fca: 701a strb r2, [r3, #0]
}
#endif /* conifgASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
8006fcc: 4b14 ldr r3, [pc, #80] @ (8007020 <xPortStartScheduler+0xf0>)
8006fce: 681b ldr r3, [r3, #0]
8006fd0: 4a13 ldr r2, [pc, #76] @ (8007020 <xPortStartScheduler+0xf0>)
8006fd2: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
8006fd6: 6013 str r3, [r2, #0]
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
8006fd8: 4b11 ldr r3, [pc, #68] @ (8007020 <xPortStartScheduler+0xf0>)
8006fda: 681b ldr r3, [r3, #0]
8006fdc: 4a10 ldr r2, [pc, #64] @ (8007020 <xPortStartScheduler+0xf0>)
8006fde: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000
8006fe2: 6013 str r3, [r2, #0]
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
vPortSetupTimerInterrupt();
8006fe4: f000 f8dc bl 80071a0 <vPortSetupTimerInterrupt>
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
8006fe8: 4b0e ldr r3, [pc, #56] @ (8007024 <xPortStartScheduler+0xf4>)
8006fea: 2200 movs r2, #0
8006fec: 601a str r2, [r3, #0]
/* Ensure the VFP is enabled - it should be anyway. */
vPortEnableVFP();
8006fee: f000 f8fb bl 80071e8 <vPortEnableVFP>
/* Lazy save always. */
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
8006ff2: 4b0d ldr r3, [pc, #52] @ (8007028 <xPortStartScheduler+0xf8>)
8006ff4: 681b ldr r3, [r3, #0]
8006ff6: 4a0c ldr r2, [pc, #48] @ (8007028 <xPortStartScheduler+0xf8>)
8006ff8: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000
8006ffc: 6013 str r3, [r2, #0]
/* Start the first task. */
prvPortStartFirstTask();
8006ffe: f7ff ff83 bl 8006f08 <prvPortStartFirstTask>
exit error function to prevent compiler warnings about a static function
not being called in the case that the application writer overrides this
functionality by defining configTASK_RETURN_ADDRESS. Call
vTaskSwitchContext() so link time optimisation does not remove the
symbol. */
vTaskSwitchContext();
8007002: f7ff f96f bl 80062e4 <vTaskSwitchContext>
prvTaskExitError();
8007006: f7ff ff33 bl 8006e70 <prvTaskExitError>
/* Should not get here! */
return 0;
800700a: 2300 movs r3, #0
}
800700c: 4618 mov r0, r3
800700e: 3710 adds r7, #16
8007010: 46bd mov sp, r7
8007012: bd80 pop {r7, pc}
8007014: e000e400 .word 0xe000e400
8007018: 20000ccc .word 0x20000ccc
800701c: 20000cd0 .word 0x20000cd0
8007020: e000ed20 .word 0xe000ed20
8007024: 2000000c .word 0x2000000c
8007028: e000ef34 .word 0xe000ef34
0800702c <vPortEnterCritical>:
configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
800702c: b480 push {r7}
800702e: b083 sub sp, #12
8007030: af00 add r7, sp, #0
__asm volatile
8007032: f04f 0350 mov.w r3, #80 @ 0x50
8007036: b672 cpsid i
8007038: f383 8811 msr BASEPRI, r3
800703c: f3bf 8f6f isb sy
8007040: f3bf 8f4f dsb sy
8007044: b662 cpsie i
8007046: 607b str r3, [r7, #4]
}
8007048: bf00 nop
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
800704a: 4b11 ldr r3, [pc, #68] @ (8007090 <vPortEnterCritical+0x64>)
800704c: 681b ldr r3, [r3, #0]
800704e: 3301 adds r3, #1
8007050: 4a0f ldr r2, [pc, #60] @ (8007090 <vPortEnterCritical+0x64>)
8007052: 6013 str r3, [r2, #0]
/* This is not the interrupt safe version of the enter critical function so
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
if( uxCriticalNesting == 1 )
8007054: 4b0e ldr r3, [pc, #56] @ (8007090 <vPortEnterCritical+0x64>)
8007056: 681b ldr r3, [r3, #0]
8007058: 2b01 cmp r3, #1
800705a: d112 bne.n 8007082 <vPortEnterCritical+0x56>
{
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
800705c: 4b0d ldr r3, [pc, #52] @ (8007094 <vPortEnterCritical+0x68>)
800705e: 681b ldr r3, [r3, #0]
8007060: b2db uxtb r3, r3
8007062: 2b00 cmp r3, #0
8007064: d00d beq.n 8007082 <vPortEnterCritical+0x56>
__asm volatile
8007066: f04f 0350 mov.w r3, #80 @ 0x50
800706a: b672 cpsid i
800706c: f383 8811 msr BASEPRI, r3
8007070: f3bf 8f6f isb sy
8007074: f3bf 8f4f dsb sy
8007078: b662 cpsie i
800707a: 603b str r3, [r7, #0]
}
800707c: bf00 nop
800707e: bf00 nop
8007080: e7fd b.n 800707e <vPortEnterCritical+0x52>
}
}
8007082: bf00 nop
8007084: 370c adds r7, #12
8007086: 46bd mov sp, r7
8007088: f85d 7b04 ldr.w r7, [sp], #4
800708c: 4770 bx lr
800708e: bf00 nop
8007090: 2000000c .word 0x2000000c
8007094: e000ed04 .word 0xe000ed04
08007098 <vPortExitCritical>:
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
8007098: b480 push {r7}
800709a: b083 sub sp, #12
800709c: af00 add r7, sp, #0
configASSERT( uxCriticalNesting );
800709e: 4b13 ldr r3, [pc, #76] @ (80070ec <vPortExitCritical+0x54>)
80070a0: 681b ldr r3, [r3, #0]
80070a2: 2b00 cmp r3, #0
80070a4: d10d bne.n 80070c2 <vPortExitCritical+0x2a>
__asm volatile
80070a6: f04f 0350 mov.w r3, #80 @ 0x50
80070aa: b672 cpsid i
80070ac: f383 8811 msr BASEPRI, r3
80070b0: f3bf 8f6f isb sy
80070b4: f3bf 8f4f dsb sy
80070b8: b662 cpsie i
80070ba: 607b str r3, [r7, #4]
}
80070bc: bf00 nop
80070be: bf00 nop
80070c0: e7fd b.n 80070be <vPortExitCritical+0x26>
uxCriticalNesting--;
80070c2: 4b0a ldr r3, [pc, #40] @ (80070ec <vPortExitCritical+0x54>)
80070c4: 681b ldr r3, [r3, #0]
80070c6: 3b01 subs r3, #1
80070c8: 4a08 ldr r2, [pc, #32] @ (80070ec <vPortExitCritical+0x54>)
80070ca: 6013 str r3, [r2, #0]
if( uxCriticalNesting == 0 )
80070cc: 4b07 ldr r3, [pc, #28] @ (80070ec <vPortExitCritical+0x54>)
80070ce: 681b ldr r3, [r3, #0]
80070d0: 2b00 cmp r3, #0
80070d2: d105 bne.n 80070e0 <vPortExitCritical+0x48>
80070d4: 2300 movs r3, #0
80070d6: 603b str r3, [r7, #0]
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
__asm volatile
80070d8: 683b ldr r3, [r7, #0]
80070da: f383 8811 msr BASEPRI, r3
(
" msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"
);
}
80070de: bf00 nop
{
portENABLE_INTERRUPTS();
}
}
80070e0: bf00 nop
80070e2: 370c adds r7, #12
80070e4: 46bd mov sp, r7
80070e6: f85d 7b04 ldr.w r7, [sp], #4
80070ea: 4770 bx lr
80070ec: 2000000c .word 0x2000000c
080070f0 <PendSV_Handler>:
void xPortPendSVHandler( void )
{
/* This is a naked function. */
__asm volatile
80070f0: f3ef 8009 mrs r0, PSP
80070f4: f3bf 8f6f isb sy
80070f8: 4b15 ldr r3, [pc, #84] @ (8007150 <pxCurrentTCBConst>)
80070fa: 681a ldr r2, [r3, #0]
80070fc: f01e 0f10 tst.w lr, #16
8007100: bf08 it eq
8007102: ed20 8a10 vstmdbeq r0!, {s16-s31}
8007106: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800710a: 6010 str r0, [r2, #0]
800710c: e92d 0009 stmdb sp!, {r0, r3}
8007110: f04f 0050 mov.w r0, #80 @ 0x50
8007114: b672 cpsid i
8007116: f380 8811 msr BASEPRI, r0
800711a: f3bf 8f4f dsb sy
800711e: f3bf 8f6f isb sy
8007122: b662 cpsie i
8007124: f7ff f8de bl 80062e4 <vTaskSwitchContext>
8007128: f04f 0000 mov.w r0, #0
800712c: f380 8811 msr BASEPRI, r0
8007130: bc09 pop {r0, r3}
8007132: 6819 ldr r1, [r3, #0]
8007134: 6808 ldr r0, [r1, #0]
8007136: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800713a: f01e 0f10 tst.w lr, #16
800713e: bf08 it eq
8007140: ecb0 8a10 vldmiaeq r0!, {s16-s31}
8007144: f380 8809 msr PSP, r0
8007148: f3bf 8f6f isb sy
800714c: 4770 bx lr
800714e: bf00 nop
08007150 <pxCurrentTCBConst>:
8007150: 20000b98 .word 0x20000b98
" \n"
" .align 4 \n"
"pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
);
}
8007154: bf00 nop
8007156: bf00 nop
08007158 <SysTick_Handler>:
/*-----------------------------------------------------------*/
void xPortSysTickHandler( void )
{
8007158: b580 push {r7, lr}
800715a: b082 sub sp, #8
800715c: af00 add r7, sp, #0
__asm volatile
800715e: f04f 0350 mov.w r3, #80 @ 0x50
8007162: b672 cpsid i
8007164: f383 8811 msr BASEPRI, r3
8007168: f3bf 8f6f isb sy
800716c: f3bf 8f4f dsb sy
8007170: b662 cpsie i
8007172: 607b str r3, [r7, #4]
}
8007174: bf00 nop
save and then restore the interrupt mask value as its value is already
known. */
portDISABLE_INTERRUPTS();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
8007176: f7fe fff9 bl 800616c <xTaskIncrementTick>
800717a: 4603 mov r3, r0
800717c: 2b00 cmp r3, #0
800717e: d003 beq.n 8007188 <SysTick_Handler+0x30>
{
/* A context switch is required. Context switching is performed in
the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
8007180: 4b06 ldr r3, [pc, #24] @ (800719c <SysTick_Handler+0x44>)
8007182: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8007186: 601a str r2, [r3, #0]
8007188: 2300 movs r3, #0
800718a: 603b str r3, [r7, #0]
__asm volatile
800718c: 683b ldr r3, [r7, #0]
800718e: f383 8811 msr BASEPRI, r3
}
8007192: bf00 nop
}
}
portENABLE_INTERRUPTS();
}
8007194: bf00 nop
8007196: 3708 adds r7, #8
8007198: 46bd mov sp, r7
800719a: bd80 pop {r7, pc}
800719c: e000ed04 .word 0xe000ed04
080071a0 <vPortSetupTimerInterrupt>:
/*
* Setup the systick timer to generate the tick interrupts at the required
* frequency.
*/
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
80071a0: b480 push {r7}
80071a2: af00 add r7, sp, #0
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
80071a4: 4b0b ldr r3, [pc, #44] @ (80071d4 <vPortSetupTimerInterrupt+0x34>)
80071a6: 2200 movs r2, #0
80071a8: 601a str r2, [r3, #0]
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
80071aa: 4b0b ldr r3, [pc, #44] @ (80071d8 <vPortSetupTimerInterrupt+0x38>)
80071ac: 2200 movs r2, #0
80071ae: 601a str r2, [r3, #0]
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
80071b0: 4b0a ldr r3, [pc, #40] @ (80071dc <vPortSetupTimerInterrupt+0x3c>)
80071b2: 681b ldr r3, [r3, #0]
80071b4: 4a0a ldr r2, [pc, #40] @ (80071e0 <vPortSetupTimerInterrupt+0x40>)
80071b6: fba2 2303 umull r2, r3, r2, r3
80071ba: 099b lsrs r3, r3, #6
80071bc: 4a09 ldr r2, [pc, #36] @ (80071e4 <vPortSetupTimerInterrupt+0x44>)
80071be: 3b01 subs r3, #1
80071c0: 6013 str r3, [r2, #0]
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
80071c2: 4b04 ldr r3, [pc, #16] @ (80071d4 <vPortSetupTimerInterrupt+0x34>)
80071c4: 2207 movs r2, #7
80071c6: 601a str r2, [r3, #0]
}
80071c8: bf00 nop
80071ca: 46bd mov sp, r7
80071cc: f85d 7b04 ldr.w r7, [sp], #4
80071d0: 4770 bx lr
80071d2: bf00 nop
80071d4: e000e010 .word 0xe000e010
80071d8: e000e018 .word 0xe000e018
80071dc: 20000000 .word 0x20000000
80071e0: 10624dd3 .word 0x10624dd3
80071e4: e000e014 .word 0xe000e014
080071e8 <vPortEnableVFP>:
/*-----------------------------------------------------------*/
/* This is a naked function. */
static void vPortEnableVFP( void )
{
__asm volatile
80071e8: f8df 000c ldr.w r0, [pc, #12] @ 80071f8 <vPortEnableVFP+0x10>
80071ec: 6801 ldr r1, [r0, #0]
80071ee: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
80071f2: 6001 str r1, [r0, #0]
80071f4: 4770 bx lr
" \n"
" orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
" str r1, [r0] \n"
" bx r14 "
);
}
80071f6: bf00 nop
80071f8: e000ed88 .word 0xe000ed88
080071fc <pvPortMalloc>:
static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
void *pvPortMalloc( size_t xWantedSize )
{
80071fc: b580 push {r7, lr}
80071fe: b08a sub sp, #40 @ 0x28
8007200: af00 add r7, sp, #0
8007202: 6078 str r0, [r7, #4]
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
void *pvReturn = NULL;
8007204: 2300 movs r3, #0
8007206: 61fb str r3, [r7, #28]
vTaskSuspendAll();
8007208: f7fe fe46 bl 8005e98 <vTaskSuspendAll>
{
/* If this is the first call to malloc then the heap will require
initialisation to setup the list of free blocks. */
if( pxEnd == NULL )
800720c: 4b5d ldr r3, [pc, #372] @ (8007384 <pvPortMalloc+0x188>)
800720e: 681b ldr r3, [r3, #0]
8007210: 2b00 cmp r3, #0
8007212: d101 bne.n 8007218 <pvPortMalloc+0x1c>
{
prvHeapInit();
8007214: f000 f92c bl 8007470 <prvHeapInit>
/* Check the requested block size is not so large that the top bit is
set. The top bit of the block size member of the BlockLink_t structure
is used to determine who owns the block - the application or the
kernel, so it must be free. */
if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
8007218: 4b5b ldr r3, [pc, #364] @ (8007388 <pvPortMalloc+0x18c>)
800721a: 681a ldr r2, [r3, #0]
800721c: 687b ldr r3, [r7, #4]
800721e: 4013 ands r3, r2
8007220: 2b00 cmp r3, #0
8007222: f040 8094 bne.w 800734e <pvPortMalloc+0x152>
{
/* The wanted size is increased so it can contain a BlockLink_t
structure in addition to the requested amount of bytes. */
if( xWantedSize > 0 )
8007226: 687b ldr r3, [r7, #4]
8007228: 2b00 cmp r3, #0
800722a: d020 beq.n 800726e <pvPortMalloc+0x72>
{
xWantedSize += xHeapStructSize;
800722c: 2208 movs r2, #8
800722e: 687b ldr r3, [r7, #4]
8007230: 4413 add r3, r2
8007232: 607b str r3, [r7, #4]
/* Ensure that blocks are always aligned to the required number
of bytes. */
if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
8007234: 687b ldr r3, [r7, #4]
8007236: f003 0307 and.w r3, r3, #7
800723a: 2b00 cmp r3, #0
800723c: d017 beq.n 800726e <pvPortMalloc+0x72>
{
/* Byte alignment required. */
xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
800723e: 687b ldr r3, [r7, #4]
8007240: f023 0307 bic.w r3, r3, #7
8007244: 3308 adds r3, #8
8007246: 607b str r3, [r7, #4]
configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
8007248: 687b ldr r3, [r7, #4]
800724a: f003 0307 and.w r3, r3, #7
800724e: 2b00 cmp r3, #0
8007250: d00d beq.n 800726e <pvPortMalloc+0x72>
__asm volatile
8007252: f04f 0350 mov.w r3, #80 @ 0x50
8007256: b672 cpsid i
8007258: f383 8811 msr BASEPRI, r3
800725c: f3bf 8f6f isb sy
8007260: f3bf 8f4f dsb sy
8007264: b662 cpsie i
8007266: 617b str r3, [r7, #20]
}
8007268: bf00 nop
800726a: bf00 nop
800726c: e7fd b.n 800726a <pvPortMalloc+0x6e>
else
{
mtCOVERAGE_TEST_MARKER();
}
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
800726e: 687b ldr r3, [r7, #4]
8007270: 2b00 cmp r3, #0
8007272: d06c beq.n 800734e <pvPortMalloc+0x152>
8007274: 4b45 ldr r3, [pc, #276] @ (800738c <pvPortMalloc+0x190>)
8007276: 681b ldr r3, [r3, #0]
8007278: 687a ldr r2, [r7, #4]
800727a: 429a cmp r2, r3
800727c: d867 bhi.n 800734e <pvPortMalloc+0x152>
{
/* Traverse the list from the start (lowest address) block until
one of adequate size is found. */
pxPreviousBlock = &xStart;
800727e: 4b44 ldr r3, [pc, #272] @ (8007390 <pvPortMalloc+0x194>)
8007280: 623b str r3, [r7, #32]
pxBlock = xStart.pxNextFreeBlock;
8007282: 4b43 ldr r3, [pc, #268] @ (8007390 <pvPortMalloc+0x194>)
8007284: 681b ldr r3, [r3, #0]
8007286: 627b str r3, [r7, #36] @ 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
8007288: e004 b.n 8007294 <pvPortMalloc+0x98>
{
pxPreviousBlock = pxBlock;
800728a: 6a7b ldr r3, [r7, #36] @ 0x24
800728c: 623b str r3, [r7, #32]
pxBlock = pxBlock->pxNextFreeBlock;
800728e: 6a7b ldr r3, [r7, #36] @ 0x24
8007290: 681b ldr r3, [r3, #0]
8007292: 627b str r3, [r7, #36] @ 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
8007294: 6a7b ldr r3, [r7, #36] @ 0x24
8007296: 685b ldr r3, [r3, #4]
8007298: 687a ldr r2, [r7, #4]
800729a: 429a cmp r2, r3
800729c: d903 bls.n 80072a6 <pvPortMalloc+0xaa>
800729e: 6a7b ldr r3, [r7, #36] @ 0x24
80072a0: 681b ldr r3, [r3, #0]
80072a2: 2b00 cmp r3, #0
80072a4: d1f1 bne.n 800728a <pvPortMalloc+0x8e>
}
/* If the end marker was reached then a block of adequate size
was not found. */
if( pxBlock != pxEnd )
80072a6: 4b37 ldr r3, [pc, #220] @ (8007384 <pvPortMalloc+0x188>)
80072a8: 681b ldr r3, [r3, #0]
80072aa: 6a7a ldr r2, [r7, #36] @ 0x24
80072ac: 429a cmp r2, r3
80072ae: d04e beq.n 800734e <pvPortMalloc+0x152>
{
/* Return the memory space pointed to - jumping over the
BlockLink_t structure at its start. */
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
80072b0: 6a3b ldr r3, [r7, #32]
80072b2: 681b ldr r3, [r3, #0]
80072b4: 2208 movs r2, #8
80072b6: 4413 add r3, r2
80072b8: 61fb str r3, [r7, #28]
/* This block is being returned for use so must be taken out
of the list of free blocks. */
pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
80072ba: 6a7b ldr r3, [r7, #36] @ 0x24
80072bc: 681a ldr r2, [r3, #0]
80072be: 6a3b ldr r3, [r7, #32]
80072c0: 601a str r2, [r3, #0]
/* If the block is larger than required it can be split into
two. */
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
80072c2: 6a7b ldr r3, [r7, #36] @ 0x24
80072c4: 685a ldr r2, [r3, #4]
80072c6: 687b ldr r3, [r7, #4]
80072c8: 1ad2 subs r2, r2, r3
80072ca: 2308 movs r3, #8
80072cc: 005b lsls r3, r3, #1
80072ce: 429a cmp r2, r3
80072d0: d922 bls.n 8007318 <pvPortMalloc+0x11c>
{
/* This block is to be split into two. Create a new
block following the number of bytes requested. The void
cast is used to prevent byte alignment warnings from the
compiler. */
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
80072d2: 6a7a ldr r2, [r7, #36] @ 0x24
80072d4: 687b ldr r3, [r7, #4]
80072d6: 4413 add r3, r2
80072d8: 61bb str r3, [r7, #24]
configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
80072da: 69bb ldr r3, [r7, #24]
80072dc: f003 0307 and.w r3, r3, #7
80072e0: 2b00 cmp r3, #0
80072e2: d00d beq.n 8007300 <pvPortMalloc+0x104>
__asm volatile
80072e4: f04f 0350 mov.w r3, #80 @ 0x50
80072e8: b672 cpsid i
80072ea: f383 8811 msr BASEPRI, r3
80072ee: f3bf 8f6f isb sy
80072f2: f3bf 8f4f dsb sy
80072f6: b662 cpsie i
80072f8: 613b str r3, [r7, #16]
}
80072fa: bf00 nop
80072fc: bf00 nop
80072fe: e7fd b.n 80072fc <pvPortMalloc+0x100>
/* Calculate the sizes of two blocks split from the
single block. */
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
8007300: 6a7b ldr r3, [r7, #36] @ 0x24
8007302: 685a ldr r2, [r3, #4]
8007304: 687b ldr r3, [r7, #4]
8007306: 1ad2 subs r2, r2, r3
8007308: 69bb ldr r3, [r7, #24]
800730a: 605a str r2, [r3, #4]
pxBlock->xBlockSize = xWantedSize;
800730c: 6a7b ldr r3, [r7, #36] @ 0x24
800730e: 687a ldr r2, [r7, #4]
8007310: 605a str r2, [r3, #4]
/* Insert the new block into the list of free blocks. */
prvInsertBlockIntoFreeList( pxNewBlockLink );
8007312: 69b8 ldr r0, [r7, #24]
8007314: f000 f90e bl 8007534 <prvInsertBlockIntoFreeList>
else
{
mtCOVERAGE_TEST_MARKER();
}
xFreeBytesRemaining -= pxBlock->xBlockSize;
8007318: 4b1c ldr r3, [pc, #112] @ (800738c <pvPortMalloc+0x190>)
800731a: 681a ldr r2, [r3, #0]
800731c: 6a7b ldr r3, [r7, #36] @ 0x24
800731e: 685b ldr r3, [r3, #4]
8007320: 1ad3 subs r3, r2, r3
8007322: 4a1a ldr r2, [pc, #104] @ (800738c <pvPortMalloc+0x190>)
8007324: 6013 str r3, [r2, #0]
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
8007326: 4b19 ldr r3, [pc, #100] @ (800738c <pvPortMalloc+0x190>)
8007328: 681a ldr r2, [r3, #0]
800732a: 4b1a ldr r3, [pc, #104] @ (8007394 <pvPortMalloc+0x198>)
800732c: 681b ldr r3, [r3, #0]
800732e: 429a cmp r2, r3
8007330: d203 bcs.n 800733a <pvPortMalloc+0x13e>
{
xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
8007332: 4b16 ldr r3, [pc, #88] @ (800738c <pvPortMalloc+0x190>)
8007334: 681b ldr r3, [r3, #0]
8007336: 4a17 ldr r2, [pc, #92] @ (8007394 <pvPortMalloc+0x198>)
8007338: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
/* The block is being returned - it is allocated and owned
by the application and has no "next" block. */
pxBlock->xBlockSize |= xBlockAllocatedBit;
800733a: 6a7b ldr r3, [r7, #36] @ 0x24
800733c: 685a ldr r2, [r3, #4]
800733e: 4b12 ldr r3, [pc, #72] @ (8007388 <pvPortMalloc+0x18c>)
8007340: 681b ldr r3, [r3, #0]
8007342: 431a orrs r2, r3
8007344: 6a7b ldr r3, [r7, #36] @ 0x24
8007346: 605a str r2, [r3, #4]
pxBlock->pxNextFreeBlock = NULL;
8007348: 6a7b ldr r3, [r7, #36] @ 0x24
800734a: 2200 movs r2, #0
800734c: 601a str r2, [r3, #0]
mtCOVERAGE_TEST_MARKER();
}
traceMALLOC( pvReturn, xWantedSize );
}
( void ) xTaskResumeAll();
800734e: f7fe fdb1 bl 8005eb4 <xTaskResumeAll>
mtCOVERAGE_TEST_MARKER();
}
}
#endif
configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
8007352: 69fb ldr r3, [r7, #28]
8007354: f003 0307 and.w r3, r3, #7
8007358: 2b00 cmp r3, #0
800735a: d00d beq.n 8007378 <pvPortMalloc+0x17c>
__asm volatile
800735c: f04f 0350 mov.w r3, #80 @ 0x50
8007360: b672 cpsid i
8007362: f383 8811 msr BASEPRI, r3
8007366: f3bf 8f6f isb sy
800736a: f3bf 8f4f dsb sy
800736e: b662 cpsie i
8007370: 60fb str r3, [r7, #12]
}
8007372: bf00 nop
8007374: bf00 nop
8007376: e7fd b.n 8007374 <pvPortMalloc+0x178>
return pvReturn;
8007378: 69fb ldr r3, [r7, #28]
}
800737a: 4618 mov r0, r3
800737c: 3728 adds r7, #40 @ 0x28
800737e: 46bd mov sp, r7
8007380: bd80 pop {r7, pc}
8007382: bf00 nop
8007384: 20008cdc .word 0x20008cdc
8007388: 20008ce8 .word 0x20008ce8
800738c: 20008ce0 .word 0x20008ce0
8007390: 20008cd4 .word 0x20008cd4
8007394: 20008ce4 .word 0x20008ce4
08007398 <vPortFree>:
/*-----------------------------------------------------------*/
void vPortFree( void *pv )
{
8007398: b580 push {r7, lr}
800739a: b086 sub sp, #24
800739c: af00 add r7, sp, #0
800739e: 6078 str r0, [r7, #4]
uint8_t *puc = ( uint8_t * ) pv;
80073a0: 687b ldr r3, [r7, #4]
80073a2: 617b str r3, [r7, #20]
BlockLink_t *pxLink;
if( pv != NULL )
80073a4: 687b ldr r3, [r7, #4]
80073a6: 2b00 cmp r3, #0
80073a8: d04e beq.n 8007448 <vPortFree+0xb0>
{
/* The memory being freed will have an BlockLink_t structure immediately
before it. */
puc -= xHeapStructSize;
80073aa: 2308 movs r3, #8
80073ac: 425b negs r3, r3
80073ae: 697a ldr r2, [r7, #20]
80073b0: 4413 add r3, r2
80073b2: 617b str r3, [r7, #20]
/* This casting is to keep the compiler from issuing warnings. */
pxLink = ( void * ) puc;
80073b4: 697b ldr r3, [r7, #20]
80073b6: 613b str r3, [r7, #16]
/* Check the block is actually allocated. */
configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
80073b8: 693b ldr r3, [r7, #16]
80073ba: 685a ldr r2, [r3, #4]
80073bc: 4b24 ldr r3, [pc, #144] @ (8007450 <vPortFree+0xb8>)
80073be: 681b ldr r3, [r3, #0]
80073c0: 4013 ands r3, r2
80073c2: 2b00 cmp r3, #0
80073c4: d10d bne.n 80073e2 <vPortFree+0x4a>
__asm volatile
80073c6: f04f 0350 mov.w r3, #80 @ 0x50
80073ca: b672 cpsid i
80073cc: f383 8811 msr BASEPRI, r3
80073d0: f3bf 8f6f isb sy
80073d4: f3bf 8f4f dsb sy
80073d8: b662 cpsie i
80073da: 60fb str r3, [r7, #12]
}
80073dc: bf00 nop
80073de: bf00 nop
80073e0: e7fd b.n 80073de <vPortFree+0x46>
configASSERT( pxLink->pxNextFreeBlock == NULL );
80073e2: 693b ldr r3, [r7, #16]
80073e4: 681b ldr r3, [r3, #0]
80073e6: 2b00 cmp r3, #0
80073e8: d00d beq.n 8007406 <vPortFree+0x6e>
__asm volatile
80073ea: f04f 0350 mov.w r3, #80 @ 0x50
80073ee: b672 cpsid i
80073f0: f383 8811 msr BASEPRI, r3
80073f4: f3bf 8f6f isb sy
80073f8: f3bf 8f4f dsb sy
80073fc: b662 cpsie i
80073fe: 60bb str r3, [r7, #8]
}
8007400: bf00 nop
8007402: bf00 nop
8007404: e7fd b.n 8007402 <vPortFree+0x6a>
if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
8007406: 693b ldr r3, [r7, #16]
8007408: 685a ldr r2, [r3, #4]
800740a: 4b11 ldr r3, [pc, #68] @ (8007450 <vPortFree+0xb8>)
800740c: 681b ldr r3, [r3, #0]
800740e: 4013 ands r3, r2
8007410: 2b00 cmp r3, #0
8007412: d019 beq.n 8007448 <vPortFree+0xb0>
{
if( pxLink->pxNextFreeBlock == NULL )
8007414: 693b ldr r3, [r7, #16]
8007416: 681b ldr r3, [r3, #0]
8007418: 2b00 cmp r3, #0
800741a: d115 bne.n 8007448 <vPortFree+0xb0>
{
/* The block is being returned to the heap - it is no longer
allocated. */
pxLink->xBlockSize &= ~xBlockAllocatedBit;
800741c: 693b ldr r3, [r7, #16]
800741e: 685a ldr r2, [r3, #4]
8007420: 4b0b ldr r3, [pc, #44] @ (8007450 <vPortFree+0xb8>)
8007422: 681b ldr r3, [r3, #0]
8007424: 43db mvns r3, r3
8007426: 401a ands r2, r3
8007428: 693b ldr r3, [r7, #16]
800742a: 605a str r2, [r3, #4]
vTaskSuspendAll();
800742c: f7fe fd34 bl 8005e98 <vTaskSuspendAll>
{
/* Add this block to the list of free blocks. */
xFreeBytesRemaining += pxLink->xBlockSize;
8007430: 693b ldr r3, [r7, #16]
8007432: 685a ldr r2, [r3, #4]
8007434: 4b07 ldr r3, [pc, #28] @ (8007454 <vPortFree+0xbc>)
8007436: 681b ldr r3, [r3, #0]
8007438: 4413 add r3, r2
800743a: 4a06 ldr r2, [pc, #24] @ (8007454 <vPortFree+0xbc>)
800743c: 6013 str r3, [r2, #0]
traceFREE( pv, pxLink->xBlockSize );
prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
800743e: 6938 ldr r0, [r7, #16]
8007440: f000 f878 bl 8007534 <prvInsertBlockIntoFreeList>
}
( void ) xTaskResumeAll();
8007444: f7fe fd36 bl 8005eb4 <xTaskResumeAll>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
}
8007448: bf00 nop
800744a: 3718 adds r7, #24
800744c: 46bd mov sp, r7
800744e: bd80 pop {r7, pc}
8007450: 20008ce8 .word 0x20008ce8
8007454: 20008ce0 .word 0x20008ce0
08007458 <xPortGetFreeHeapSize>:
/*-----------------------------------------------------------*/
size_t xPortGetFreeHeapSize( void )
{
8007458: b480 push {r7}
800745a: af00 add r7, sp, #0
return xFreeBytesRemaining;
800745c: 4b03 ldr r3, [pc, #12] @ (800746c <xPortGetFreeHeapSize+0x14>)
800745e: 681b ldr r3, [r3, #0]
}
8007460: 4618 mov r0, r3
8007462: 46bd mov sp, r7
8007464: f85d 7b04 ldr.w r7, [sp], #4
8007468: 4770 bx lr
800746a: bf00 nop
800746c: 20008ce0 .word 0x20008ce0
08007470 <prvHeapInit>:
/* This just exists to keep the linker quiet. */
}
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
{
8007470: b480 push {r7}
8007472: b085 sub sp, #20
8007474: af00 add r7, sp, #0
BlockLink_t *pxFirstFreeBlock;
uint8_t *pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
8007476: f44f 4300 mov.w r3, #32768 @ 0x8000
800747a: 60bb str r3, [r7, #8]
/* Ensure the heap starts on a correctly aligned boundary. */
uxAddress = ( size_t ) ucHeap;
800747c: 4b27 ldr r3, [pc, #156] @ (800751c <prvHeapInit+0xac>)
800747e: 60fb str r3, [r7, #12]
if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
8007480: 68fb ldr r3, [r7, #12]
8007482: f003 0307 and.w r3, r3, #7
8007486: 2b00 cmp r3, #0
8007488: d00c beq.n 80074a4 <prvHeapInit+0x34>
{
uxAddress += ( portBYTE_ALIGNMENT - 1 );
800748a: 68fb ldr r3, [r7, #12]
800748c: 3307 adds r3, #7
800748e: 60fb str r3, [r7, #12]
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
8007490: 68fb ldr r3, [r7, #12]
8007492: f023 0307 bic.w r3, r3, #7
8007496: 60fb str r3, [r7, #12]
xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
8007498: 68ba ldr r2, [r7, #8]
800749a: 68fb ldr r3, [r7, #12]
800749c: 1ad3 subs r3, r2, r3
800749e: 4a1f ldr r2, [pc, #124] @ (800751c <prvHeapInit+0xac>)
80074a0: 4413 add r3, r2
80074a2: 60bb str r3, [r7, #8]
}
pucAlignedHeap = ( uint8_t * ) uxAddress;
80074a4: 68fb ldr r3, [r7, #12]
80074a6: 607b str r3, [r7, #4]
/* xStart is used to hold a pointer to the first item in the list of free
blocks. The void cast is used to prevent compiler warnings. */
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
80074a8: 4a1d ldr r2, [pc, #116] @ (8007520 <prvHeapInit+0xb0>)
80074aa: 687b ldr r3, [r7, #4]
80074ac: 6013 str r3, [r2, #0]
xStart.xBlockSize = ( size_t ) 0;
80074ae: 4b1c ldr r3, [pc, #112] @ (8007520 <prvHeapInit+0xb0>)
80074b0: 2200 movs r2, #0
80074b2: 605a str r2, [r3, #4]
/* pxEnd is used to mark the end of the list of free blocks and is inserted
at the end of the heap space. */
uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
80074b4: 687b ldr r3, [r7, #4]
80074b6: 68ba ldr r2, [r7, #8]
80074b8: 4413 add r3, r2
80074ba: 60fb str r3, [r7, #12]
uxAddress -= xHeapStructSize;
80074bc: 2208 movs r2, #8
80074be: 68fb ldr r3, [r7, #12]
80074c0: 1a9b subs r3, r3, r2
80074c2: 60fb str r3, [r7, #12]
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
80074c4: 68fb ldr r3, [r7, #12]
80074c6: f023 0307 bic.w r3, r3, #7
80074ca: 60fb str r3, [r7, #12]
pxEnd = ( void * ) uxAddress;
80074cc: 68fb ldr r3, [r7, #12]
80074ce: 4a15 ldr r2, [pc, #84] @ (8007524 <prvHeapInit+0xb4>)
80074d0: 6013 str r3, [r2, #0]
pxEnd->xBlockSize = 0;
80074d2: 4b14 ldr r3, [pc, #80] @ (8007524 <prvHeapInit+0xb4>)
80074d4: 681b ldr r3, [r3, #0]
80074d6: 2200 movs r2, #0
80074d8: 605a str r2, [r3, #4]
pxEnd->pxNextFreeBlock = NULL;
80074da: 4b12 ldr r3, [pc, #72] @ (8007524 <prvHeapInit+0xb4>)
80074dc: 681b ldr r3, [r3, #0]
80074de: 2200 movs r2, #0
80074e0: 601a str r2, [r3, #0]
/* To start with there is a single free block that is sized to take up the
entire heap space, minus the space taken by pxEnd. */
pxFirstFreeBlock = ( void * ) pucAlignedHeap;
80074e2: 687b ldr r3, [r7, #4]
80074e4: 603b str r3, [r7, #0]
pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
80074e6: 683b ldr r3, [r7, #0]
80074e8: 68fa ldr r2, [r7, #12]
80074ea: 1ad2 subs r2, r2, r3
80074ec: 683b ldr r3, [r7, #0]
80074ee: 605a str r2, [r3, #4]
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
80074f0: 4b0c ldr r3, [pc, #48] @ (8007524 <prvHeapInit+0xb4>)
80074f2: 681a ldr r2, [r3, #0]
80074f4: 683b ldr r3, [r7, #0]
80074f6: 601a str r2, [r3, #0]
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
80074f8: 683b ldr r3, [r7, #0]
80074fa: 685b ldr r3, [r3, #4]
80074fc: 4a0a ldr r2, [pc, #40] @ (8007528 <prvHeapInit+0xb8>)
80074fe: 6013 str r3, [r2, #0]
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
8007500: 683b ldr r3, [r7, #0]
8007502: 685b ldr r3, [r3, #4]
8007504: 4a09 ldr r2, [pc, #36] @ (800752c <prvHeapInit+0xbc>)
8007506: 6013 str r3, [r2, #0]
/* Work out the position of the top bit in a size_t variable. */
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
8007508: 4b09 ldr r3, [pc, #36] @ (8007530 <prvHeapInit+0xc0>)
800750a: f04f 4200 mov.w r2, #2147483648 @ 0x80000000
800750e: 601a str r2, [r3, #0]
}
8007510: bf00 nop
8007512: 3714 adds r7, #20
8007514: 46bd mov sp, r7
8007516: f85d 7b04 ldr.w r7, [sp], #4
800751a: 4770 bx lr
800751c: 20000cd4 .word 0x20000cd4
8007520: 20008cd4 .word 0x20008cd4
8007524: 20008cdc .word 0x20008cdc
8007528: 20008ce4 .word 0x20008ce4
800752c: 20008ce0 .word 0x20008ce0
8007530: 20008ce8 .word 0x20008ce8
08007534 <prvInsertBlockIntoFreeList>:
/*-----------------------------------------------------------*/
static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
{
8007534: b480 push {r7}
8007536: b085 sub sp, #20
8007538: af00 add r7, sp, #0
800753a: 6078 str r0, [r7, #4]
BlockLink_t *pxIterator;
uint8_t *puc;
/* Iterate through the list until a block is found that has a higher address
than the block being inserted. */
for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
800753c: 4b28 ldr r3, [pc, #160] @ (80075e0 <prvInsertBlockIntoFreeList+0xac>)
800753e: 60fb str r3, [r7, #12]
8007540: e002 b.n 8007548 <prvInsertBlockIntoFreeList+0x14>
8007542: 68fb ldr r3, [r7, #12]
8007544: 681b ldr r3, [r3, #0]
8007546: 60fb str r3, [r7, #12]
8007548: 68fb ldr r3, [r7, #12]
800754a: 681b ldr r3, [r3, #0]
800754c: 687a ldr r2, [r7, #4]
800754e: 429a cmp r2, r3
8007550: d8f7 bhi.n 8007542 <prvInsertBlockIntoFreeList+0xe>
/* Nothing to do here, just iterate to the right position. */
}
/* Do the block being inserted, and the block it is being inserted after
make a contiguous block of memory? */
puc = ( uint8_t * ) pxIterator;
8007552: 68fb ldr r3, [r7, #12]
8007554: 60bb str r3, [r7, #8]
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
8007556: 68fb ldr r3, [r7, #12]
8007558: 685b ldr r3, [r3, #4]
800755a: 68ba ldr r2, [r7, #8]
800755c: 4413 add r3, r2
800755e: 687a ldr r2, [r7, #4]
8007560: 429a cmp r2, r3
8007562: d108 bne.n 8007576 <prvInsertBlockIntoFreeList+0x42>
{
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
8007564: 68fb ldr r3, [r7, #12]
8007566: 685a ldr r2, [r3, #4]
8007568: 687b ldr r3, [r7, #4]
800756a: 685b ldr r3, [r3, #4]
800756c: 441a add r2, r3
800756e: 68fb ldr r3, [r7, #12]
8007570: 605a str r2, [r3, #4]
pxBlockToInsert = pxIterator;
8007572: 68fb ldr r3, [r7, #12]
8007574: 607b str r3, [r7, #4]
mtCOVERAGE_TEST_MARKER();
}
/* Do the block being inserted, and the block it is being inserted before
make a contiguous block of memory? */
puc = ( uint8_t * ) pxBlockToInsert;
8007576: 687b ldr r3, [r7, #4]
8007578: 60bb str r3, [r7, #8]
if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
800757a: 687b ldr r3, [r7, #4]
800757c: 685b ldr r3, [r3, #4]
800757e: 68ba ldr r2, [r7, #8]
8007580: 441a add r2, r3
8007582: 68fb ldr r3, [r7, #12]
8007584: 681b ldr r3, [r3, #0]
8007586: 429a cmp r2, r3
8007588: d118 bne.n 80075bc <prvInsertBlockIntoFreeList+0x88>
{
if( pxIterator->pxNextFreeBlock != pxEnd )
800758a: 68fb ldr r3, [r7, #12]
800758c: 681a ldr r2, [r3, #0]
800758e: 4b15 ldr r3, [pc, #84] @ (80075e4 <prvInsertBlockIntoFreeList+0xb0>)
8007590: 681b ldr r3, [r3, #0]
8007592: 429a cmp r2, r3
8007594: d00d beq.n 80075b2 <prvInsertBlockIntoFreeList+0x7e>
{
/* Form one big block from the two blocks. */
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
8007596: 687b ldr r3, [r7, #4]
8007598: 685a ldr r2, [r3, #4]
800759a: 68fb ldr r3, [r7, #12]
800759c: 681b ldr r3, [r3, #0]
800759e: 685b ldr r3, [r3, #4]
80075a0: 441a add r2, r3
80075a2: 687b ldr r3, [r7, #4]
80075a4: 605a str r2, [r3, #4]
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
80075a6: 68fb ldr r3, [r7, #12]
80075a8: 681b ldr r3, [r3, #0]
80075aa: 681a ldr r2, [r3, #0]
80075ac: 687b ldr r3, [r7, #4]
80075ae: 601a str r2, [r3, #0]
80075b0: e008 b.n 80075c4 <prvInsertBlockIntoFreeList+0x90>
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxEnd;
80075b2: 4b0c ldr r3, [pc, #48] @ (80075e4 <prvInsertBlockIntoFreeList+0xb0>)
80075b4: 681a ldr r2, [r3, #0]
80075b6: 687b ldr r3, [r7, #4]
80075b8: 601a str r2, [r3, #0]
80075ba: e003 b.n 80075c4 <prvInsertBlockIntoFreeList+0x90>
}
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
80075bc: 68fb ldr r3, [r7, #12]
80075be: 681a ldr r2, [r3, #0]
80075c0: 687b ldr r3, [r7, #4]
80075c2: 601a str r2, [r3, #0]
/* If the block being inserted plugged a gab, so was merged with the block
before and the block after, then it's pxNextFreeBlock pointer will have
already been set, and should not be set here as that would make it point
to itself. */
if( pxIterator != pxBlockToInsert )
80075c4: 68fa ldr r2, [r7, #12]
80075c6: 687b ldr r3, [r7, #4]
80075c8: 429a cmp r2, r3
80075ca: d002 beq.n 80075d2 <prvInsertBlockIntoFreeList+0x9e>
{
pxIterator->pxNextFreeBlock = pxBlockToInsert;
80075cc: 68fb ldr r3, [r7, #12]
80075ce: 687a ldr r2, [r7, #4]
80075d0: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
80075d2: bf00 nop
80075d4: 3714 adds r7, #20
80075d6: 46bd mov sp, r7
80075d8: f85d 7b04 ldr.w r7, [sp], #4
80075dc: 4770 bx lr
80075de: bf00 nop
80075e0: 20008cd4 .word 0x20008cd4
80075e4: 20008cdc .word 0x20008cdc
080075e8 <swapfunc>:
80075e8: 2b02 cmp r3, #2
80075ea: b510 push {r4, lr}
80075ec: d00a beq.n 8007604 <swapfunc+0x1c>
80075ee: 0892 lsrs r2, r2, #2
80075f0: 3a01 subs r2, #1
80075f2: 6803 ldr r3, [r0, #0]
80075f4: 680c ldr r4, [r1, #0]
80075f6: f840 4b04 str.w r4, [r0], #4
80075fa: 2a00 cmp r2, #0
80075fc: f841 3b04 str.w r3, [r1], #4
8007600: dcf6 bgt.n 80075f0 <swapfunc+0x8>
8007602: bd10 pop {r4, pc}
8007604: 4402 add r2, r0
8007606: 780c ldrb r4, [r1, #0]
8007608: 7803 ldrb r3, [r0, #0]
800760a: f800 4b01 strb.w r4, [r0], #1
800760e: f801 3b01 strb.w r3, [r1], #1
8007612: 1a13 subs r3, r2, r0
8007614: 2b00 cmp r3, #0
8007616: dcf6 bgt.n 8007606 <swapfunc+0x1e>
8007618: e7f3 b.n 8007602 <swapfunc+0x1a>
0800761a <med3.constprop.0>:
800761a: b5f8 push {r3, r4, r5, r6, r7, lr}
800761c: 460f mov r7, r1
800761e: 4616 mov r6, r2
8007620: 4604 mov r4, r0
8007622: 461d mov r5, r3
8007624: 4798 blx r3
8007626: 2800 cmp r0, #0
8007628: 4631 mov r1, r6
800762a: 4638 mov r0, r7
800762c: da0c bge.n 8007648 <med3.constprop.0+0x2e>
800762e: 47a8 blx r5
8007630: 2800 cmp r0, #0
8007632: da02 bge.n 800763a <med3.constprop.0+0x20>
8007634: 463c mov r4, r7
8007636: 4620 mov r0, r4
8007638: bdf8 pop {r3, r4, r5, r6, r7, pc}
800763a: 4631 mov r1, r6
800763c: 4620 mov r0, r4
800763e: 47a8 blx r5
8007640: 2800 cmp r0, #0
8007642: daf8 bge.n 8007636 <med3.constprop.0+0x1c>
8007644: 4634 mov r4, r6
8007646: e7f6 b.n 8007636 <med3.constprop.0+0x1c>
8007648: 47a8 blx r5
800764a: 2800 cmp r0, #0
800764c: dcf2 bgt.n 8007634 <med3.constprop.0+0x1a>
800764e: 4631 mov r1, r6
8007650: 4620 mov r0, r4
8007652: 47a8 blx r5
8007654: 2800 cmp r0, #0
8007656: daf5 bge.n 8007644 <med3.constprop.0+0x2a>
8007658: e7ed b.n 8007636 <med3.constprop.0+0x1c>
0800765a <qsort>:
800765a: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800765e: b095 sub sp, #84 @ 0x54
8007660: 4607 mov r7, r0
8007662: 9300 str r3, [sp, #0]
8007664: ea40 0302 orr.w r3, r0, r2
8007668: 079b lsls r3, r3, #30
800766a: 4615 mov r5, r2
800766c: d118 bne.n 80076a0 <qsort+0x46>
800766e: f1b2 0804 subs.w r8, r2, #4
8007672: bf18 it ne
8007674: f04f 0801 movne.w r8, #1
8007678: 2300 movs r3, #0
800767a: 9301 str r3, [sp, #4]
800767c: fb05 f401 mul.w r4, r5, r1
8007680: 193b adds r3, r7, r4
8007682: 2906 cmp r1, #6
8007684: eb07 0b05 add.w fp, r7, r5
8007688: 9302 str r3, [sp, #8]
800768a: d828 bhi.n 80076de <qsort+0x84>
800768c: 9b02 ldr r3, [sp, #8]
800768e: 459b cmp fp, r3
8007690: d310 bcc.n 80076b4 <qsort+0x5a>
8007692: 9b01 ldr r3, [sp, #4]
8007694: 2b00 cmp r3, #0
8007696: f040 8117 bne.w 80078c8 <qsort+0x26e>
800769a: b015 add sp, #84 @ 0x54
800769c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
80076a0: f04f 0802 mov.w r8, #2
80076a4: e7e8 b.n 8007678 <qsort+0x1e>
80076a6: 4643 mov r3, r8
80076a8: 462a mov r2, r5
80076aa: 4631 mov r1, r6
80076ac: 4620 mov r0, r4
80076ae: f7ff ff9b bl 80075e8 <swapfunc>
80076b2: e00f b.n 80076d4 <qsort+0x7a>
80076b4: 465c mov r4, fp
80076b6: e00e b.n 80076d6 <qsort+0x7c>
80076b8: 1b66 subs r6, r4, r5
80076ba: 9b00 ldr r3, [sp, #0]
80076bc: 4621 mov r1, r4
80076be: 4630 mov r0, r6
80076c0: 4798 blx r3
80076c2: 2800 cmp r0, #0
80076c4: dd09 ble.n 80076da <qsort+0x80>
80076c6: f1b8 0f00 cmp.w r8, #0
80076ca: d1ec bne.n 80076a6 <qsort+0x4c>
80076cc: 6823 ldr r3, [r4, #0]
80076ce: 6832 ldr r2, [r6, #0]
80076d0: 6022 str r2, [r4, #0]
80076d2: 6033 str r3, [r6, #0]
80076d4: 4634 mov r4, r6
80076d6: 42a7 cmp r7, r4
80076d8: d3ee bcc.n 80076b8 <qsort+0x5e>
80076da: 44ab add fp, r5
80076dc: e7d6 b.n 800768c <qsort+0x32>
80076de: ea4f 0951 mov.w r9, r1, lsr #1
80076e2: 1b64 subs r4, r4, r5
80076e4: 2907 cmp r1, #7
80076e6: fb05 7909 mla r9, r5, r9, r7
80076ea: 443c add r4, r7
80076ec: d021 beq.n 8007732 <qsort+0xd8>
80076ee: 2928 cmp r1, #40 @ 0x28
80076f0: d944 bls.n 800777c <qsort+0x122>
80076f2: 08ce lsrs r6, r1, #3
80076f4: 436e muls r6, r5
80076f6: 9b00 ldr r3, [sp, #0]
80076f8: eb07 0246 add.w r2, r7, r6, lsl #1
80076fc: 19b9 adds r1, r7, r6
80076fe: 4638 mov r0, r7
8007700: f7ff ff8b bl 800761a <med3.constprop.0>
8007704: 4649 mov r1, r9
8007706: eb09 0206 add.w r2, r9, r6
800770a: 9b00 ldr r3, [sp, #0]
800770c: 4682 mov sl, r0
800770e: 1b88 subs r0, r1, r6
8007710: f7ff ff83 bl 800761a <med3.constprop.0>
8007714: 4622 mov r2, r4
8007716: 9b00 ldr r3, [sp, #0]
8007718: 4681 mov r9, r0
800771a: 1ba1 subs r1, r4, r6
800771c: eba4 0046 sub.w r0, r4, r6, lsl #1
8007720: f7ff ff7b bl 800761a <med3.constprop.0>
8007724: 4602 mov r2, r0
8007726: 4649 mov r1, r9
8007728: 9b00 ldr r3, [sp, #0]
800772a: 4650 mov r0, sl
800772c: f7ff ff75 bl 800761a <med3.constprop.0>
8007730: 4681 mov r9, r0
8007732: f1b8 0f00 cmp.w r8, #0
8007736: d124 bne.n 8007782 <qsort+0x128>
8007738: 683b ldr r3, [r7, #0]
800773a: f8d9 2000 ldr.w r2, [r9]
800773e: 603a str r2, [r7, #0]
8007740: f8c9 3000 str.w r3, [r9]
8007744: 46d9 mov r9, fp
8007746: 46a2 mov sl, r4
8007748: 465e mov r6, fp
800774a: 2300 movs r3, #0
800774c: 45a1 cmp r9, r4
800774e: d836 bhi.n 80077be <qsort+0x164>
8007750: 9303 str r3, [sp, #12]
8007752: 4639 mov r1, r7
8007754: 9b00 ldr r3, [sp, #0]
8007756: 4648 mov r0, r9
8007758: 4798 blx r3
800775a: 2800 cmp r0, #0
800775c: 9b03 ldr r3, [sp, #12]
800775e: dc2c bgt.n 80077ba <qsort+0x160>
8007760: d10a bne.n 8007778 <qsort+0x11e>
8007762: f1b8 0f00 cmp.w r8, #0
8007766: d113 bne.n 8007790 <qsort+0x136>
8007768: 6833 ldr r3, [r6, #0]
800776a: f8d9 2000 ldr.w r2, [r9]
800776e: 6032 str r2, [r6, #0]
8007770: f8c9 3000 str.w r3, [r9]
8007774: 442e add r6, r5
8007776: 2301 movs r3, #1
8007778: 44a9 add r9, r5
800777a: e7e7 b.n 800774c <qsort+0xf2>
800777c: 4622 mov r2, r4
800777e: 46ba mov sl, r7
8007780: e7d1 b.n 8007726 <qsort+0xcc>
8007782: 4643 mov r3, r8
8007784: 462a mov r2, r5
8007786: 4649 mov r1, r9
8007788: 4638 mov r0, r7
800778a: f7ff ff2d bl 80075e8 <swapfunc>
800778e: e7d9 b.n 8007744 <qsort+0xea>
8007790: 4643 mov r3, r8
8007792: 462a mov r2, r5
8007794: 4649 mov r1, r9
8007796: 4630 mov r0, r6
8007798: f7ff ff26 bl 80075e8 <swapfunc>
800779c: e7ea b.n 8007774 <qsort+0x11a>
800779e: d10b bne.n 80077b8 <qsort+0x15e>
80077a0: f1b8 0f00 cmp.w r8, #0
80077a4: d113 bne.n 80077ce <qsort+0x174>
80077a6: 6823 ldr r3, [r4, #0]
80077a8: f8da 2000 ldr.w r2, [sl]
80077ac: 6022 str r2, [r4, #0]
80077ae: f8ca 3000 str.w r3, [sl]
80077b2: ebaa 0a05 sub.w sl, sl, r5
80077b6: 2301 movs r3, #1
80077b8: 1b64 subs r4, r4, r5
80077ba: 45a1 cmp r9, r4
80077bc: d90e bls.n 80077dc <qsort+0x182>
80077be: 2b00 cmp r3, #0
80077c0: d140 bne.n 8007844 <qsort+0x1ea>
80077c2: 9b02 ldr r3, [sp, #8]
80077c4: 459b cmp fp, r3
80077c6: f4bf af64 bcs.w 8007692 <qsort+0x38>
80077ca: 465c mov r4, fp
80077cc: e036 b.n 800783c <qsort+0x1e2>
80077ce: 4643 mov r3, r8
80077d0: 462a mov r2, r5
80077d2: 4651 mov r1, sl
80077d4: 4620 mov r0, r4
80077d6: f7ff ff07 bl 80075e8 <swapfunc>
80077da: e7ea b.n 80077b2 <qsort+0x158>
80077dc: 9303 str r3, [sp, #12]
80077de: 4639 mov r1, r7
80077e0: 9b00 ldr r3, [sp, #0]
80077e2: 4620 mov r0, r4
80077e4: 4798 blx r3
80077e6: 2800 cmp r0, #0
80077e8: 9b03 ldr r3, [sp, #12]
80077ea: dad8 bge.n 800779e <qsort+0x144>
80077ec: f1b8 0f00 cmp.w r8, #0
80077f0: d107 bne.n 8007802 <qsort+0x1a8>
80077f2: f8d9 3000 ldr.w r3, [r9]
80077f6: 6822 ldr r2, [r4, #0]
80077f8: f8c9 2000 str.w r2, [r9]
80077fc: 6023 str r3, [r4, #0]
80077fe: 1b64 subs r4, r4, r5
8007800: e7b9 b.n 8007776 <qsort+0x11c>
8007802: 4643 mov r3, r8
8007804: 462a mov r2, r5
8007806: 4621 mov r1, r4
8007808: 4648 mov r0, r9
800780a: f7ff feed bl 80075e8 <swapfunc>
800780e: e7f6 b.n 80077fe <qsort+0x1a4>
8007810: 4643 mov r3, r8
8007812: 462a mov r2, r5
8007814: 4631 mov r1, r6
8007816: 4620 mov r0, r4
8007818: f7ff fee6 bl 80075e8 <swapfunc>
800781c: e00d b.n 800783a <qsort+0x1e0>
800781e: 1b66 subs r6, r4, r5
8007820: 9b00 ldr r3, [sp, #0]
8007822: 4621 mov r1, r4
8007824: 4630 mov r0, r6
8007826: 4798 blx r3
8007828: 2800 cmp r0, #0
800782a: dd09 ble.n 8007840 <qsort+0x1e6>
800782c: f1b8 0f00 cmp.w r8, #0
8007830: d1ee bne.n 8007810 <qsort+0x1b6>
8007832: 6823 ldr r3, [r4, #0]
8007834: 6832 ldr r2, [r6, #0]
8007836: 6022 str r2, [r4, #0]
8007838: 6033 str r3, [r6, #0]
800783a: 4634 mov r4, r6
800783c: 42a7 cmp r7, r4
800783e: d3ee bcc.n 800781e <qsort+0x1c4>
8007840: 44ab add fp, r5
8007842: e7be b.n 80077c2 <qsort+0x168>
8007844: eba9 0b06 sub.w fp, r9, r6
8007848: 1bf2 subs r2, r6, r7
800784a: 455a cmp r2, fp
800784c: bfa8 it ge
800784e: 465a movge r2, fp
8007850: b12a cbz r2, 800785e <qsort+0x204>
8007852: 4643 mov r3, r8
8007854: eba9 0102 sub.w r1, r9, r2
8007858: 4638 mov r0, r7
800785a: f7ff fec5 bl 80075e8 <swapfunc>
800785e: 9b02 ldr r3, [sp, #8]
8007860: eba3 020a sub.w r2, r3, sl
8007864: ebaa 0404 sub.w r4, sl, r4
8007868: 1b52 subs r2, r2, r5
800786a: 42a2 cmp r2, r4
800786c: bf28 it cs
800786e: 4622 movcs r2, r4
8007870: b12a cbz r2, 800787e <qsort+0x224>
8007872: 9902 ldr r1, [sp, #8]
8007874: 4643 mov r3, r8
8007876: 1a89 subs r1, r1, r2
8007878: 4648 mov r0, r9
800787a: f7ff feb5 bl 80075e8 <swapfunc>
800787e: 9b02 ldr r3, [sp, #8]
8007880: 455c cmp r4, fp
8007882: eba3 0604 sub.w r6, r3, r4
8007886: d805 bhi.n 8007894 <qsort+0x23a>
8007888: 4623 mov r3, r4
800788a: 465c mov r4, fp
800788c: 469b mov fp, r3
800788e: 4633 mov r3, r6
8007890: 463e mov r6, r7
8007892: 461f mov r7, r3
8007894: 45ab cmp fp, r5
8007896: d920 bls.n 80078da <qsort+0x280>
8007898: fbbb f1f5 udiv r1, fp, r5
800789c: 9b01 ldr r3, [sp, #4]
800789e: 2b07 cmp r3, #7
80078a0: d80b bhi.n 80078ba <qsort+0x260>
80078a2: fbb4 f4f5 udiv r4, r4, r5
80078a6: aa14 add r2, sp, #80 @ 0x50
80078a8: eb02 03c3 add.w r3, r2, r3, lsl #3
80078ac: f843 6c40 str.w r6, [r3, #-64]
80078b0: f843 4c3c str.w r4, [r3, #-60]
80078b4: 9b01 ldr r3, [sp, #4]
80078b6: 3301 adds r3, #1
80078b8: e6df b.n 800767a <qsort+0x20>
80078ba: 9b00 ldr r3, [sp, #0]
80078bc: 462a mov r2, r5
80078be: 4638 mov r0, r7
80078c0: f7ff fecb bl 800765a <qsort>
80078c4: 42ac cmp r4, r5
80078c6: d80b bhi.n 80078e0 <qsort+0x286>
80078c8: 9b01 ldr r3, [sp, #4]
80078ca: aa14 add r2, sp, #80 @ 0x50
80078cc: 3b01 subs r3, #1
80078ce: 9301 str r3, [sp, #4]
80078d0: eb02 03c3 add.w r3, r2, r3, lsl #3
80078d4: e953 7110 ldrd r7, r1, [r3, #-64] @ 0x40
80078d8: e6d0 b.n 800767c <qsort+0x22>
80078da: 42ac cmp r4, r5
80078dc: f67f aed9 bls.w 8007692 <qsort+0x38>
80078e0: fbb4 f1f5 udiv r1, r4, r5
80078e4: 4637 mov r7, r6
80078e6: e6c9 b.n 800767c <qsort+0x22>
080078e8 <std>:
80078e8: 2300 movs r3, #0
80078ea: b510 push {r4, lr}
80078ec: 4604 mov r4, r0
80078ee: e9c0 3300 strd r3, r3, [r0]
80078f2: e9c0 3304 strd r3, r3, [r0, #16]
80078f6: 6083 str r3, [r0, #8]
80078f8: 8181 strh r1, [r0, #12]
80078fa: 6643 str r3, [r0, #100] @ 0x64
80078fc: 81c2 strh r2, [r0, #14]
80078fe: 6183 str r3, [r0, #24]
8007900: 4619 mov r1, r3
8007902: 2208 movs r2, #8
8007904: 305c adds r0, #92 @ 0x5c
8007906: f000 f906 bl 8007b16 <memset>
800790a: 4b0d ldr r3, [pc, #52] @ (8007940 <std+0x58>)
800790c: 6263 str r3, [r4, #36] @ 0x24
800790e: 4b0d ldr r3, [pc, #52] @ (8007944 <std+0x5c>)
8007910: 62a3 str r3, [r4, #40] @ 0x28
8007912: 4b0d ldr r3, [pc, #52] @ (8007948 <std+0x60>)
8007914: 62e3 str r3, [r4, #44] @ 0x2c
8007916: 4b0d ldr r3, [pc, #52] @ (800794c <std+0x64>)
8007918: 6323 str r3, [r4, #48] @ 0x30
800791a: 4b0d ldr r3, [pc, #52] @ (8007950 <std+0x68>)
800791c: 6224 str r4, [r4, #32]
800791e: 429c cmp r4, r3
8007920: d006 beq.n 8007930 <std+0x48>
8007922: f103 0268 add.w r2, r3, #104 @ 0x68
8007926: 4294 cmp r4, r2
8007928: d002 beq.n 8007930 <std+0x48>
800792a: 33d0 adds r3, #208 @ 0xd0
800792c: 429c cmp r4, r3
800792e: d105 bne.n 800793c <std+0x54>
8007930: f104 0058 add.w r0, r4, #88 @ 0x58
8007934: e8bd 4010 ldmia.w sp!, {r4, lr}
8007938: f000 b9c4 b.w 8007cc4 <__retarget_lock_init_recursive>
800793c: bd10 pop {r4, pc}
800793e: bf00 nop
8007940: 08007a91 .word 0x08007a91
8007944: 08007ab3 .word 0x08007ab3
8007948: 08007aeb .word 0x08007aeb
800794c: 08007b0f .word 0x08007b0f
8007950: 20008cec .word 0x20008cec
08007954 <stdio_exit_handler>:
8007954: 4a02 ldr r2, [pc, #8] @ (8007960 <stdio_exit_handler+0xc>)
8007956: 4903 ldr r1, [pc, #12] @ (8007964 <stdio_exit_handler+0x10>)
8007958: 4803 ldr r0, [pc, #12] @ (8007968 <stdio_exit_handler+0x14>)
800795a: f000 b869 b.w 8007a30 <_fwalk_sglue>
800795e: bf00 nop
8007960: 20000010 .word 0x20000010
8007964: 0800857d .word 0x0800857d
8007968: 20000020 .word 0x20000020
0800796c <cleanup_stdio>:
800796c: 6841 ldr r1, [r0, #4]
800796e: 4b0c ldr r3, [pc, #48] @ (80079a0 <cleanup_stdio+0x34>)
8007970: 4299 cmp r1, r3
8007972: b510 push {r4, lr}
8007974: 4604 mov r4, r0
8007976: d001 beq.n 800797c <cleanup_stdio+0x10>
8007978: f000 fe00 bl 800857c <_fflush_r>
800797c: 68a1 ldr r1, [r4, #8]
800797e: 4b09 ldr r3, [pc, #36] @ (80079a4 <cleanup_stdio+0x38>)
8007980: 4299 cmp r1, r3
8007982: d002 beq.n 800798a <cleanup_stdio+0x1e>
8007984: 4620 mov r0, r4
8007986: f000 fdf9 bl 800857c <_fflush_r>
800798a: 68e1 ldr r1, [r4, #12]
800798c: 4b06 ldr r3, [pc, #24] @ (80079a8 <cleanup_stdio+0x3c>)
800798e: 4299 cmp r1, r3
8007990: d004 beq.n 800799c <cleanup_stdio+0x30>
8007992: 4620 mov r0, r4
8007994: e8bd 4010 ldmia.w sp!, {r4, lr}
8007998: f000 bdf0 b.w 800857c <_fflush_r>
800799c: bd10 pop {r4, pc}
800799e: bf00 nop
80079a0: 20008cec .word 0x20008cec
80079a4: 20008d54 .word 0x20008d54
80079a8: 20008dbc .word 0x20008dbc
080079ac <global_stdio_init.part.0>:
80079ac: b510 push {r4, lr}
80079ae: 4b0b ldr r3, [pc, #44] @ (80079dc <global_stdio_init.part.0+0x30>)
80079b0: 4c0b ldr r4, [pc, #44] @ (80079e0 <global_stdio_init.part.0+0x34>)
80079b2: 4a0c ldr r2, [pc, #48] @ (80079e4 <global_stdio_init.part.0+0x38>)
80079b4: 601a str r2, [r3, #0]
80079b6: 4620 mov r0, r4
80079b8: 2200 movs r2, #0
80079ba: 2104 movs r1, #4
80079bc: f7ff ff94 bl 80078e8 <std>
80079c0: f104 0068 add.w r0, r4, #104 @ 0x68
80079c4: 2201 movs r2, #1
80079c6: 2109 movs r1, #9
80079c8: f7ff ff8e bl 80078e8 <std>
80079cc: f104 00d0 add.w r0, r4, #208 @ 0xd0
80079d0: 2202 movs r2, #2
80079d2: e8bd 4010 ldmia.w sp!, {r4, lr}
80079d6: 2112 movs r1, #18
80079d8: f7ff bf86 b.w 80078e8 <std>
80079dc: 20008e24 .word 0x20008e24
80079e0: 20008cec .word 0x20008cec
80079e4: 08007955 .word 0x08007955
080079e8 <__sfp_lock_acquire>:
80079e8: 4801 ldr r0, [pc, #4] @ (80079f0 <__sfp_lock_acquire+0x8>)
80079ea: f000 b96c b.w 8007cc6 <__retarget_lock_acquire_recursive>
80079ee: bf00 nop
80079f0: 20008e2d .word 0x20008e2d
080079f4 <__sfp_lock_release>:
80079f4: 4801 ldr r0, [pc, #4] @ (80079fc <__sfp_lock_release+0x8>)
80079f6: f000 b967 b.w 8007cc8 <__retarget_lock_release_recursive>
80079fa: bf00 nop
80079fc: 20008e2d .word 0x20008e2d
08007a00 <__sinit>:
8007a00: b510 push {r4, lr}
8007a02: 4604 mov r4, r0
8007a04: f7ff fff0 bl 80079e8 <__sfp_lock_acquire>
8007a08: 6a23 ldr r3, [r4, #32]
8007a0a: b11b cbz r3, 8007a14 <__sinit+0x14>
8007a0c: e8bd 4010 ldmia.w sp!, {r4, lr}
8007a10: f7ff bff0 b.w 80079f4 <__sfp_lock_release>
8007a14: 4b04 ldr r3, [pc, #16] @ (8007a28 <__sinit+0x28>)
8007a16: 6223 str r3, [r4, #32]
8007a18: 4b04 ldr r3, [pc, #16] @ (8007a2c <__sinit+0x2c>)
8007a1a: 681b ldr r3, [r3, #0]
8007a1c: 2b00 cmp r3, #0
8007a1e: d1f5 bne.n 8007a0c <__sinit+0xc>
8007a20: f7ff ffc4 bl 80079ac <global_stdio_init.part.0>
8007a24: e7f2 b.n 8007a0c <__sinit+0xc>
8007a26: bf00 nop
8007a28: 0800796d .word 0x0800796d
8007a2c: 20008e24 .word 0x20008e24
08007a30 <_fwalk_sglue>:
8007a30: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
8007a34: 4607 mov r7, r0
8007a36: 4688 mov r8, r1
8007a38: 4614 mov r4, r2
8007a3a: 2600 movs r6, #0
8007a3c: e9d4 9501 ldrd r9, r5, [r4, #4]
8007a40: f1b9 0901 subs.w r9, r9, #1
8007a44: d505 bpl.n 8007a52 <_fwalk_sglue+0x22>
8007a46: 6824 ldr r4, [r4, #0]
8007a48: 2c00 cmp r4, #0
8007a4a: d1f7 bne.n 8007a3c <_fwalk_sglue+0xc>
8007a4c: 4630 mov r0, r6
8007a4e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
8007a52: 89ab ldrh r3, [r5, #12]
8007a54: 2b01 cmp r3, #1
8007a56: d907 bls.n 8007a68 <_fwalk_sglue+0x38>
8007a58: f9b5 300e ldrsh.w r3, [r5, #14]
8007a5c: 3301 adds r3, #1
8007a5e: d003 beq.n 8007a68 <_fwalk_sglue+0x38>
8007a60: 4629 mov r1, r5
8007a62: 4638 mov r0, r7
8007a64: 47c0 blx r8
8007a66: 4306 orrs r6, r0
8007a68: 3568 adds r5, #104 @ 0x68
8007a6a: e7e9 b.n 8007a40 <_fwalk_sglue+0x10>
08007a6c <iprintf>:
8007a6c: b40f push {r0, r1, r2, r3}
8007a6e: b507 push {r0, r1, r2, lr}
8007a70: 4906 ldr r1, [pc, #24] @ (8007a8c <iprintf+0x20>)
8007a72: ab04 add r3, sp, #16
8007a74: 6808 ldr r0, [r1, #0]
8007a76: f853 2b04 ldr.w r2, [r3], #4
8007a7a: 6881 ldr r1, [r0, #8]
8007a7c: 9301 str r3, [sp, #4]
8007a7e: f000 fa55 bl 8007f2c <_vfiprintf_r>
8007a82: b003 add sp, #12
8007a84: f85d eb04 ldr.w lr, [sp], #4
8007a88: b004 add sp, #16
8007a8a: 4770 bx lr
8007a8c: 2000001c .word 0x2000001c
08007a90 <__sread>:
8007a90: b510 push {r4, lr}
8007a92: 460c mov r4, r1
8007a94: f9b1 100e ldrsh.w r1, [r1, #14]
8007a98: f000 f8c6 bl 8007c28 <_read_r>
8007a9c: 2800 cmp r0, #0
8007a9e: bfab itete ge
8007aa0: 6d63 ldrge r3, [r4, #84] @ 0x54
8007aa2: 89a3 ldrhlt r3, [r4, #12]
8007aa4: 181b addge r3, r3, r0
8007aa6: f423 5380 biclt.w r3, r3, #4096 @ 0x1000
8007aaa: bfac ite ge
8007aac: 6563 strge r3, [r4, #84] @ 0x54
8007aae: 81a3 strhlt r3, [r4, #12]
8007ab0: bd10 pop {r4, pc}
08007ab2 <__swrite>:
8007ab2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8007ab6: 461f mov r7, r3
8007ab8: 898b ldrh r3, [r1, #12]
8007aba: 05db lsls r3, r3, #23
8007abc: 4605 mov r5, r0
8007abe: 460c mov r4, r1
8007ac0: 4616 mov r6, r2
8007ac2: d505 bpl.n 8007ad0 <__swrite+0x1e>
8007ac4: f9b1 100e ldrsh.w r1, [r1, #14]
8007ac8: 2302 movs r3, #2
8007aca: 2200 movs r2, #0
8007acc: f000 f89a bl 8007c04 <_lseek_r>
8007ad0: 89a3 ldrh r3, [r4, #12]
8007ad2: f9b4 100e ldrsh.w r1, [r4, #14]
8007ad6: f423 5380 bic.w r3, r3, #4096 @ 0x1000
8007ada: 81a3 strh r3, [r4, #12]
8007adc: 4632 mov r2, r6
8007ade: 463b mov r3, r7
8007ae0: 4628 mov r0, r5
8007ae2: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
8007ae6: f000 b8b1 b.w 8007c4c <_write_r>
08007aea <__sseek>:
8007aea: b510 push {r4, lr}
8007aec: 460c mov r4, r1
8007aee: f9b1 100e ldrsh.w r1, [r1, #14]
8007af2: f000 f887 bl 8007c04 <_lseek_r>
8007af6: 1c43 adds r3, r0, #1
8007af8: 89a3 ldrh r3, [r4, #12]
8007afa: bf15 itete ne
8007afc: 6560 strne r0, [r4, #84] @ 0x54
8007afe: f423 5380 biceq.w r3, r3, #4096 @ 0x1000
8007b02: f443 5380 orrne.w r3, r3, #4096 @ 0x1000
8007b06: 81a3 strheq r3, [r4, #12]
8007b08: bf18 it ne
8007b0a: 81a3 strhne r3, [r4, #12]
8007b0c: bd10 pop {r4, pc}
08007b0e <__sclose>:
8007b0e: f9b1 100e ldrsh.w r1, [r1, #14]
8007b12: f000 b809 b.w 8007b28 <_close_r>
08007b16 <memset>:
8007b16: 4402 add r2, r0
8007b18: 4603 mov r3, r0
8007b1a: 4293 cmp r3, r2
8007b1c: d100 bne.n 8007b20 <memset+0xa>
8007b1e: 4770 bx lr
8007b20: f803 1b01 strb.w r1, [r3], #1
8007b24: e7f9 b.n 8007b1a <memset+0x4>
...
08007b28 <_close_r>:
8007b28: b538 push {r3, r4, r5, lr}
8007b2a: 4d06 ldr r5, [pc, #24] @ (8007b44 <_close_r+0x1c>)
8007b2c: 2300 movs r3, #0
8007b2e: 4604 mov r4, r0
8007b30: 4608 mov r0, r1
8007b32: 602b str r3, [r5, #0]
8007b34: f7fa f857 bl 8001be6 <_close>
8007b38: 1c43 adds r3, r0, #1
8007b3a: d102 bne.n 8007b42 <_close_r+0x1a>
8007b3c: 682b ldr r3, [r5, #0]
8007b3e: b103 cbz r3, 8007b42 <_close_r+0x1a>
8007b40: 6023 str r3, [r4, #0]
8007b42: bd38 pop {r3, r4, r5, pc}
8007b44: 20008e28 .word 0x20008e28
08007b48 <_reclaim_reent>:
8007b48: 4b2d ldr r3, [pc, #180] @ (8007c00 <_reclaim_reent+0xb8>)
8007b4a: 681b ldr r3, [r3, #0]
8007b4c: 4283 cmp r3, r0
8007b4e: b570 push {r4, r5, r6, lr}
8007b50: 4604 mov r4, r0
8007b52: d053 beq.n 8007bfc <_reclaim_reent+0xb4>
8007b54: 69c3 ldr r3, [r0, #28]
8007b56: b31b cbz r3, 8007ba0 <_reclaim_reent+0x58>
8007b58: 68db ldr r3, [r3, #12]
8007b5a: b163 cbz r3, 8007b76 <_reclaim_reent+0x2e>
8007b5c: 2500 movs r5, #0
8007b5e: 69e3 ldr r3, [r4, #28]
8007b60: 68db ldr r3, [r3, #12]
8007b62: 5959 ldr r1, [r3, r5]
8007b64: b9b1 cbnz r1, 8007b94 <_reclaim_reent+0x4c>
8007b66: 3504 adds r5, #4
8007b68: 2d80 cmp r5, #128 @ 0x80
8007b6a: d1f8 bne.n 8007b5e <_reclaim_reent+0x16>
8007b6c: 69e3 ldr r3, [r4, #28]
8007b6e: 4620 mov r0, r4
8007b70: 68d9 ldr r1, [r3, #12]
8007b72: f000 f8b9 bl 8007ce8 <_free_r>
8007b76: 69e3 ldr r3, [r4, #28]
8007b78: 6819 ldr r1, [r3, #0]
8007b7a: b111 cbz r1, 8007b82 <_reclaim_reent+0x3a>
8007b7c: 4620 mov r0, r4
8007b7e: f000 f8b3 bl 8007ce8 <_free_r>
8007b82: 69e3 ldr r3, [r4, #28]
8007b84: 689d ldr r5, [r3, #8]
8007b86: b15d cbz r5, 8007ba0 <_reclaim_reent+0x58>
8007b88: 4629 mov r1, r5
8007b8a: 4620 mov r0, r4
8007b8c: 682d ldr r5, [r5, #0]
8007b8e: f000 f8ab bl 8007ce8 <_free_r>
8007b92: e7f8 b.n 8007b86 <_reclaim_reent+0x3e>
8007b94: 680e ldr r6, [r1, #0]
8007b96: 4620 mov r0, r4
8007b98: f000 f8a6 bl 8007ce8 <_free_r>
8007b9c: 4631 mov r1, r6
8007b9e: e7e1 b.n 8007b64 <_reclaim_reent+0x1c>
8007ba0: 6961 ldr r1, [r4, #20]
8007ba2: b111 cbz r1, 8007baa <_reclaim_reent+0x62>
8007ba4: 4620 mov r0, r4
8007ba6: f000 f89f bl 8007ce8 <_free_r>
8007baa: 69e1 ldr r1, [r4, #28]
8007bac: b111 cbz r1, 8007bb4 <_reclaim_reent+0x6c>
8007bae: 4620 mov r0, r4
8007bb0: f000 f89a bl 8007ce8 <_free_r>
8007bb4: 6b21 ldr r1, [r4, #48] @ 0x30
8007bb6: b111 cbz r1, 8007bbe <_reclaim_reent+0x76>
8007bb8: 4620 mov r0, r4
8007bba: f000 f895 bl 8007ce8 <_free_r>
8007bbe: 6b61 ldr r1, [r4, #52] @ 0x34
8007bc0: b111 cbz r1, 8007bc8 <_reclaim_reent+0x80>
8007bc2: 4620 mov r0, r4
8007bc4: f000 f890 bl 8007ce8 <_free_r>
8007bc8: 6ba1 ldr r1, [r4, #56] @ 0x38
8007bca: b111 cbz r1, 8007bd2 <_reclaim_reent+0x8a>
8007bcc: 4620 mov r0, r4
8007bce: f000 f88b bl 8007ce8 <_free_r>
8007bd2: 6ca1 ldr r1, [r4, #72] @ 0x48
8007bd4: b111 cbz r1, 8007bdc <_reclaim_reent+0x94>
8007bd6: 4620 mov r0, r4
8007bd8: f000 f886 bl 8007ce8 <_free_r>
8007bdc: 6c61 ldr r1, [r4, #68] @ 0x44
8007bde: b111 cbz r1, 8007be6 <_reclaim_reent+0x9e>
8007be0: 4620 mov r0, r4
8007be2: f000 f881 bl 8007ce8 <_free_r>
8007be6: 6ae1 ldr r1, [r4, #44] @ 0x2c
8007be8: b111 cbz r1, 8007bf0 <_reclaim_reent+0xa8>
8007bea: 4620 mov r0, r4
8007bec: f000 f87c bl 8007ce8 <_free_r>
8007bf0: 6a23 ldr r3, [r4, #32]
8007bf2: b11b cbz r3, 8007bfc <_reclaim_reent+0xb4>
8007bf4: 4620 mov r0, r4
8007bf6: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
8007bfa: 4718 bx r3
8007bfc: bd70 pop {r4, r5, r6, pc}
8007bfe: bf00 nop
8007c00: 2000001c .word 0x2000001c
08007c04 <_lseek_r>:
8007c04: b538 push {r3, r4, r5, lr}
8007c06: 4d07 ldr r5, [pc, #28] @ (8007c24 <_lseek_r+0x20>)
8007c08: 4604 mov r4, r0
8007c0a: 4608 mov r0, r1
8007c0c: 4611 mov r1, r2
8007c0e: 2200 movs r2, #0
8007c10: 602a str r2, [r5, #0]
8007c12: 461a mov r2, r3
8007c14: f7fa f80e bl 8001c34 <_lseek>
8007c18: 1c43 adds r3, r0, #1
8007c1a: d102 bne.n 8007c22 <_lseek_r+0x1e>
8007c1c: 682b ldr r3, [r5, #0]
8007c1e: b103 cbz r3, 8007c22 <_lseek_r+0x1e>
8007c20: 6023 str r3, [r4, #0]
8007c22: bd38 pop {r3, r4, r5, pc}
8007c24: 20008e28 .word 0x20008e28
08007c28 <_read_r>:
8007c28: b538 push {r3, r4, r5, lr}
8007c2a: 4d07 ldr r5, [pc, #28] @ (8007c48 <_read_r+0x20>)
8007c2c: 4604 mov r4, r0
8007c2e: 4608 mov r0, r1
8007c30: 4611 mov r1, r2
8007c32: 2200 movs r2, #0
8007c34: 602a str r2, [r5, #0]
8007c36: 461a mov r2, r3
8007c38: f7f9 ffb8 bl 8001bac <_read>
8007c3c: 1c43 adds r3, r0, #1
8007c3e: d102 bne.n 8007c46 <_read_r+0x1e>
8007c40: 682b ldr r3, [r5, #0]
8007c42: b103 cbz r3, 8007c46 <_read_r+0x1e>
8007c44: 6023 str r3, [r4, #0]
8007c46: bd38 pop {r3, r4, r5, pc}
8007c48: 20008e28 .word 0x20008e28
08007c4c <_write_r>:
8007c4c: b538 push {r3, r4, r5, lr}
8007c4e: 4d07 ldr r5, [pc, #28] @ (8007c6c <_write_r+0x20>)
8007c50: 4604 mov r4, r0
8007c52: 4608 mov r0, r1
8007c54: 4611 mov r1, r2
8007c56: 2200 movs r2, #0
8007c58: 602a str r2, [r5, #0]
8007c5a: 461a mov r2, r3
8007c5c: f7f8 fec2 bl 80009e4 <_write>
8007c60: 1c43 adds r3, r0, #1
8007c62: d102 bne.n 8007c6a <_write_r+0x1e>
8007c64: 682b ldr r3, [r5, #0]
8007c66: b103 cbz r3, 8007c6a <_write_r+0x1e>
8007c68: 6023 str r3, [r4, #0]
8007c6a: bd38 pop {r3, r4, r5, pc}
8007c6c: 20008e28 .word 0x20008e28
08007c70 <__errno>:
8007c70: 4b01 ldr r3, [pc, #4] @ (8007c78 <__errno+0x8>)
8007c72: 6818 ldr r0, [r3, #0]
8007c74: 4770 bx lr
8007c76: bf00 nop
8007c78: 2000001c .word 0x2000001c
08007c7c <__libc_init_array>:
8007c7c: b570 push {r4, r5, r6, lr}
8007c7e: 4d0d ldr r5, [pc, #52] @ (8007cb4 <__libc_init_array+0x38>)
8007c80: 4c0d ldr r4, [pc, #52] @ (8007cb8 <__libc_init_array+0x3c>)
8007c82: 1b64 subs r4, r4, r5
8007c84: 10a4 asrs r4, r4, #2
8007c86: 2600 movs r6, #0
8007c88: 42a6 cmp r6, r4
8007c8a: d109 bne.n 8007ca0 <__libc_init_array+0x24>
8007c8c: 4d0b ldr r5, [pc, #44] @ (8007cbc <__libc_init_array+0x40>)
8007c8e: 4c0c ldr r4, [pc, #48] @ (8007cc0 <__libc_init_array+0x44>)
8007c90: f000 fdc4 bl 800881c <_init>
8007c94: 1b64 subs r4, r4, r5
8007c96: 10a4 asrs r4, r4, #2
8007c98: 2600 movs r6, #0
8007c9a: 42a6 cmp r6, r4
8007c9c: d105 bne.n 8007caa <__libc_init_array+0x2e>
8007c9e: bd70 pop {r4, r5, r6, pc}
8007ca0: f855 3b04 ldr.w r3, [r5], #4
8007ca4: 4798 blx r3
8007ca6: 3601 adds r6, #1
8007ca8: e7ee b.n 8007c88 <__libc_init_array+0xc>
8007caa: f855 3b04 ldr.w r3, [r5], #4
8007cae: 4798 blx r3
8007cb0: 3601 adds r6, #1
8007cb2: e7f2 b.n 8007c9a <__libc_init_array+0x1e>
8007cb4: 08008a7c .word 0x08008a7c
8007cb8: 08008a7c .word 0x08008a7c
8007cbc: 08008a7c .word 0x08008a7c
8007cc0: 08008a80 .word 0x08008a80
08007cc4 <__retarget_lock_init_recursive>:
8007cc4: 4770 bx lr
08007cc6 <__retarget_lock_acquire_recursive>:
8007cc6: 4770 bx lr
08007cc8 <__retarget_lock_release_recursive>:
8007cc8: 4770 bx lr
08007cca <memcpy>:
8007cca: 440a add r2, r1
8007ccc: 4291 cmp r1, r2
8007cce: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff
8007cd2: d100 bne.n 8007cd6 <memcpy+0xc>
8007cd4: 4770 bx lr
8007cd6: b510 push {r4, lr}
8007cd8: f811 4b01 ldrb.w r4, [r1], #1
8007cdc: f803 4f01 strb.w r4, [r3, #1]!
8007ce0: 4291 cmp r1, r2
8007ce2: d1f9 bne.n 8007cd8 <memcpy+0xe>
8007ce4: bd10 pop {r4, pc}
...
08007ce8 <_free_r>:
8007ce8: b538 push {r3, r4, r5, lr}
8007cea: 4605 mov r5, r0
8007cec: 2900 cmp r1, #0
8007cee: d041 beq.n 8007d74 <_free_r+0x8c>
8007cf0: f851 3c04 ldr.w r3, [r1, #-4]
8007cf4: 1f0c subs r4, r1, #4
8007cf6: 2b00 cmp r3, #0
8007cf8: bfb8 it lt
8007cfa: 18e4 addlt r4, r4, r3
8007cfc: f000 f8e0 bl 8007ec0 <__malloc_lock>
8007d00: 4a1d ldr r2, [pc, #116] @ (8007d78 <_free_r+0x90>)
8007d02: 6813 ldr r3, [r2, #0]
8007d04: b933 cbnz r3, 8007d14 <_free_r+0x2c>
8007d06: 6063 str r3, [r4, #4]
8007d08: 6014 str r4, [r2, #0]
8007d0a: 4628 mov r0, r5
8007d0c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
8007d10: f000 b8dc b.w 8007ecc <__malloc_unlock>
8007d14: 42a3 cmp r3, r4
8007d16: d908 bls.n 8007d2a <_free_r+0x42>
8007d18: 6820 ldr r0, [r4, #0]
8007d1a: 1821 adds r1, r4, r0
8007d1c: 428b cmp r3, r1
8007d1e: bf01 itttt eq
8007d20: 6819 ldreq r1, [r3, #0]
8007d22: 685b ldreq r3, [r3, #4]
8007d24: 1809 addeq r1, r1, r0
8007d26: 6021 streq r1, [r4, #0]
8007d28: e7ed b.n 8007d06 <_free_r+0x1e>
8007d2a: 461a mov r2, r3
8007d2c: 685b ldr r3, [r3, #4]
8007d2e: b10b cbz r3, 8007d34 <_free_r+0x4c>
8007d30: 42a3 cmp r3, r4
8007d32: d9fa bls.n 8007d2a <_free_r+0x42>
8007d34: 6811 ldr r1, [r2, #0]
8007d36: 1850 adds r0, r2, r1
8007d38: 42a0 cmp r0, r4
8007d3a: d10b bne.n 8007d54 <_free_r+0x6c>
8007d3c: 6820 ldr r0, [r4, #0]
8007d3e: 4401 add r1, r0
8007d40: 1850 adds r0, r2, r1
8007d42: 4283 cmp r3, r0
8007d44: 6011 str r1, [r2, #0]
8007d46: d1e0 bne.n 8007d0a <_free_r+0x22>
8007d48: 6818 ldr r0, [r3, #0]
8007d4a: 685b ldr r3, [r3, #4]
8007d4c: 6053 str r3, [r2, #4]
8007d4e: 4408 add r0, r1
8007d50: 6010 str r0, [r2, #0]
8007d52: e7da b.n 8007d0a <_free_r+0x22>
8007d54: d902 bls.n 8007d5c <_free_r+0x74>
8007d56: 230c movs r3, #12
8007d58: 602b str r3, [r5, #0]
8007d5a: e7d6 b.n 8007d0a <_free_r+0x22>
8007d5c: 6820 ldr r0, [r4, #0]
8007d5e: 1821 adds r1, r4, r0
8007d60: 428b cmp r3, r1
8007d62: bf04 itt eq
8007d64: 6819 ldreq r1, [r3, #0]
8007d66: 685b ldreq r3, [r3, #4]
8007d68: 6063 str r3, [r4, #4]
8007d6a: bf04 itt eq
8007d6c: 1809 addeq r1, r1, r0
8007d6e: 6021 streq r1, [r4, #0]
8007d70: 6054 str r4, [r2, #4]
8007d72: e7ca b.n 8007d0a <_free_r+0x22>
8007d74: bd38 pop {r3, r4, r5, pc}
8007d76: bf00 nop
8007d78: 20008e34 .word 0x20008e34
08007d7c <sbrk_aligned>:
8007d7c: b570 push {r4, r5, r6, lr}
8007d7e: 4e0f ldr r6, [pc, #60] @ (8007dbc <sbrk_aligned+0x40>)
8007d80: 460c mov r4, r1
8007d82: 6831 ldr r1, [r6, #0]
8007d84: 4605 mov r5, r0
8007d86: b911 cbnz r1, 8007d8e <sbrk_aligned+0x12>
8007d88: f000 fcb4 bl 80086f4 <_sbrk_r>
8007d8c: 6030 str r0, [r6, #0]
8007d8e: 4621 mov r1, r4
8007d90: 4628 mov r0, r5
8007d92: f000 fcaf bl 80086f4 <_sbrk_r>
8007d96: 1c43 adds r3, r0, #1
8007d98: d103 bne.n 8007da2 <sbrk_aligned+0x26>
8007d9a: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff
8007d9e: 4620 mov r0, r4
8007da0: bd70 pop {r4, r5, r6, pc}
8007da2: 1cc4 adds r4, r0, #3
8007da4: f024 0403 bic.w r4, r4, #3
8007da8: 42a0 cmp r0, r4
8007daa: d0f8 beq.n 8007d9e <sbrk_aligned+0x22>
8007dac: 1a21 subs r1, r4, r0
8007dae: 4628 mov r0, r5
8007db0: f000 fca0 bl 80086f4 <_sbrk_r>
8007db4: 3001 adds r0, #1
8007db6: d1f2 bne.n 8007d9e <sbrk_aligned+0x22>
8007db8: e7ef b.n 8007d9a <sbrk_aligned+0x1e>
8007dba: bf00 nop
8007dbc: 20008e30 .word 0x20008e30
08007dc0 <_malloc_r>:
8007dc0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
8007dc4: 1ccd adds r5, r1, #3
8007dc6: f025 0503 bic.w r5, r5, #3
8007dca: 3508 adds r5, #8
8007dcc: 2d0c cmp r5, #12
8007dce: bf38 it cc
8007dd0: 250c movcc r5, #12
8007dd2: 2d00 cmp r5, #0
8007dd4: 4606 mov r6, r0
8007dd6: db01 blt.n 8007ddc <_malloc_r+0x1c>
8007dd8: 42a9 cmp r1, r5
8007dda: d904 bls.n 8007de6 <_malloc_r+0x26>
8007ddc: 230c movs r3, #12
8007dde: 6033 str r3, [r6, #0]
8007de0: 2000 movs r0, #0
8007de2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
8007de6: f8df 80d4 ldr.w r8, [pc, #212] @ 8007ebc <_malloc_r+0xfc>
8007dea: f000 f869 bl 8007ec0 <__malloc_lock>
8007dee: f8d8 3000 ldr.w r3, [r8]
8007df2: 461c mov r4, r3
8007df4: bb44 cbnz r4, 8007e48 <_malloc_r+0x88>
8007df6: 4629 mov r1, r5
8007df8: 4630 mov r0, r6
8007dfa: f7ff ffbf bl 8007d7c <sbrk_aligned>
8007dfe: 1c43 adds r3, r0, #1
8007e00: 4604 mov r4, r0
8007e02: d158 bne.n 8007eb6 <_malloc_r+0xf6>
8007e04: f8d8 4000 ldr.w r4, [r8]
8007e08: 4627 mov r7, r4
8007e0a: 2f00 cmp r7, #0
8007e0c: d143 bne.n 8007e96 <_malloc_r+0xd6>
8007e0e: 2c00 cmp r4, #0
8007e10: d04b beq.n 8007eaa <_malloc_r+0xea>
8007e12: 6823 ldr r3, [r4, #0]
8007e14: 4639 mov r1, r7
8007e16: 4630 mov r0, r6
8007e18: eb04 0903 add.w r9, r4, r3
8007e1c: f000 fc6a bl 80086f4 <_sbrk_r>
8007e20: 4581 cmp r9, r0
8007e22: d142 bne.n 8007eaa <_malloc_r+0xea>
8007e24: 6821 ldr r1, [r4, #0]
8007e26: 1a6d subs r5, r5, r1
8007e28: 4629 mov r1, r5
8007e2a: 4630 mov r0, r6
8007e2c: f7ff ffa6 bl 8007d7c <sbrk_aligned>
8007e30: 3001 adds r0, #1
8007e32: d03a beq.n 8007eaa <_malloc_r+0xea>
8007e34: 6823 ldr r3, [r4, #0]
8007e36: 442b add r3, r5
8007e38: 6023 str r3, [r4, #0]
8007e3a: f8d8 3000 ldr.w r3, [r8]
8007e3e: 685a ldr r2, [r3, #4]
8007e40: bb62 cbnz r2, 8007e9c <_malloc_r+0xdc>
8007e42: f8c8 7000 str.w r7, [r8]
8007e46: e00f b.n 8007e68 <_malloc_r+0xa8>
8007e48: 6822 ldr r2, [r4, #0]
8007e4a: 1b52 subs r2, r2, r5
8007e4c: d420 bmi.n 8007e90 <_malloc_r+0xd0>
8007e4e: 2a0b cmp r2, #11
8007e50: d917 bls.n 8007e82 <_malloc_r+0xc2>
8007e52: 1961 adds r1, r4, r5
8007e54: 42a3 cmp r3, r4
8007e56: 6025 str r5, [r4, #0]
8007e58: bf18 it ne
8007e5a: 6059 strne r1, [r3, #4]
8007e5c: 6863 ldr r3, [r4, #4]
8007e5e: bf08 it eq
8007e60: f8c8 1000 streq.w r1, [r8]
8007e64: 5162 str r2, [r4, r5]
8007e66: 604b str r3, [r1, #4]
8007e68: 4630 mov r0, r6
8007e6a: f000 f82f bl 8007ecc <__malloc_unlock>
8007e6e: f104 000b add.w r0, r4, #11
8007e72: 1d23 adds r3, r4, #4
8007e74: f020 0007 bic.w r0, r0, #7
8007e78: 1ac2 subs r2, r0, r3
8007e7a: bf1c itt ne
8007e7c: 1a1b subne r3, r3, r0
8007e7e: 50a3 strne r3, [r4, r2]
8007e80: e7af b.n 8007de2 <_malloc_r+0x22>
8007e82: 6862 ldr r2, [r4, #4]
8007e84: 42a3 cmp r3, r4
8007e86: bf0c ite eq
8007e88: f8c8 2000 streq.w r2, [r8]
8007e8c: 605a strne r2, [r3, #4]
8007e8e: e7eb b.n 8007e68 <_malloc_r+0xa8>
8007e90: 4623 mov r3, r4
8007e92: 6864 ldr r4, [r4, #4]
8007e94: e7ae b.n 8007df4 <_malloc_r+0x34>
8007e96: 463c mov r4, r7
8007e98: 687f ldr r7, [r7, #4]
8007e9a: e7b6 b.n 8007e0a <_malloc_r+0x4a>
8007e9c: 461a mov r2, r3
8007e9e: 685b ldr r3, [r3, #4]
8007ea0: 42a3 cmp r3, r4
8007ea2: d1fb bne.n 8007e9c <_malloc_r+0xdc>
8007ea4: 2300 movs r3, #0
8007ea6: 6053 str r3, [r2, #4]
8007ea8: e7de b.n 8007e68 <_malloc_r+0xa8>
8007eaa: 230c movs r3, #12
8007eac: 6033 str r3, [r6, #0]
8007eae: 4630 mov r0, r6
8007eb0: f000 f80c bl 8007ecc <__malloc_unlock>
8007eb4: e794 b.n 8007de0 <_malloc_r+0x20>
8007eb6: 6005 str r5, [r0, #0]
8007eb8: e7d6 b.n 8007e68 <_malloc_r+0xa8>
8007eba: bf00 nop
8007ebc: 20008e34 .word 0x20008e34
08007ec0 <__malloc_lock>:
8007ec0: 4801 ldr r0, [pc, #4] @ (8007ec8 <__malloc_lock+0x8>)
8007ec2: f7ff bf00 b.w 8007cc6 <__retarget_lock_acquire_recursive>
8007ec6: bf00 nop
8007ec8: 20008e2c .word 0x20008e2c
08007ecc <__malloc_unlock>:
8007ecc: 4801 ldr r0, [pc, #4] @ (8007ed4 <__malloc_unlock+0x8>)
8007ece: f7ff befb b.w 8007cc8 <__retarget_lock_release_recursive>
8007ed2: bf00 nop
8007ed4: 20008e2c .word 0x20008e2c
08007ed8 <__sfputc_r>:
8007ed8: 6893 ldr r3, [r2, #8]
8007eda: 3b01 subs r3, #1
8007edc: 2b00 cmp r3, #0
8007ede: b410 push {r4}
8007ee0: 6093 str r3, [r2, #8]
8007ee2: da08 bge.n 8007ef6 <__sfputc_r+0x1e>
8007ee4: 6994 ldr r4, [r2, #24]
8007ee6: 42a3 cmp r3, r4
8007ee8: db01 blt.n 8007eee <__sfputc_r+0x16>
8007eea: 290a cmp r1, #10
8007eec: d103 bne.n 8007ef6 <__sfputc_r+0x1e>
8007eee: f85d 4b04 ldr.w r4, [sp], #4
8007ef2: f000 bb6b b.w 80085cc <__swbuf_r>
8007ef6: 6813 ldr r3, [r2, #0]
8007ef8: 1c58 adds r0, r3, #1
8007efa: 6010 str r0, [r2, #0]
8007efc: 7019 strb r1, [r3, #0]
8007efe: 4608 mov r0, r1
8007f00: f85d 4b04 ldr.w r4, [sp], #4
8007f04: 4770 bx lr
08007f06 <__sfputs_r>:
8007f06: b5f8 push {r3, r4, r5, r6, r7, lr}
8007f08: 4606 mov r6, r0
8007f0a: 460f mov r7, r1
8007f0c: 4614 mov r4, r2
8007f0e: 18d5 adds r5, r2, r3
8007f10: 42ac cmp r4, r5
8007f12: d101 bne.n 8007f18 <__sfputs_r+0x12>
8007f14: 2000 movs r0, #0
8007f16: e007 b.n 8007f28 <__sfputs_r+0x22>
8007f18: f814 1b01 ldrb.w r1, [r4], #1
8007f1c: 463a mov r2, r7
8007f1e: 4630 mov r0, r6
8007f20: f7ff ffda bl 8007ed8 <__sfputc_r>
8007f24: 1c43 adds r3, r0, #1
8007f26: d1f3 bne.n 8007f10 <__sfputs_r+0xa>
8007f28: bdf8 pop {r3, r4, r5, r6, r7, pc}
...
08007f2c <_vfiprintf_r>:
8007f2c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8007f30: 460d mov r5, r1
8007f32: b09d sub sp, #116 @ 0x74
8007f34: 4614 mov r4, r2
8007f36: 4698 mov r8, r3
8007f38: 4606 mov r6, r0
8007f3a: b118 cbz r0, 8007f44 <_vfiprintf_r+0x18>
8007f3c: 6a03 ldr r3, [r0, #32]
8007f3e: b90b cbnz r3, 8007f44 <_vfiprintf_r+0x18>
8007f40: f7ff fd5e bl 8007a00 <__sinit>
8007f44: 6e6b ldr r3, [r5, #100] @ 0x64
8007f46: 07d9 lsls r1, r3, #31
8007f48: d405 bmi.n 8007f56 <_vfiprintf_r+0x2a>
8007f4a: 89ab ldrh r3, [r5, #12]
8007f4c: 059a lsls r2, r3, #22
8007f4e: d402 bmi.n 8007f56 <_vfiprintf_r+0x2a>
8007f50: 6da8 ldr r0, [r5, #88] @ 0x58
8007f52: f7ff feb8 bl 8007cc6 <__retarget_lock_acquire_recursive>
8007f56: 89ab ldrh r3, [r5, #12]
8007f58: 071b lsls r3, r3, #28
8007f5a: d501 bpl.n 8007f60 <_vfiprintf_r+0x34>
8007f5c: 692b ldr r3, [r5, #16]
8007f5e: b99b cbnz r3, 8007f88 <_vfiprintf_r+0x5c>
8007f60: 4629 mov r1, r5
8007f62: 4630 mov r0, r6
8007f64: f000 fb70 bl 8008648 <__swsetup_r>
8007f68: b170 cbz r0, 8007f88 <_vfiprintf_r+0x5c>
8007f6a: 6e6b ldr r3, [r5, #100] @ 0x64
8007f6c: 07dc lsls r4, r3, #31
8007f6e: d504 bpl.n 8007f7a <_vfiprintf_r+0x4e>
8007f70: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8007f74: b01d add sp, #116 @ 0x74
8007f76: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8007f7a: 89ab ldrh r3, [r5, #12]
8007f7c: 0598 lsls r0, r3, #22
8007f7e: d4f7 bmi.n 8007f70 <_vfiprintf_r+0x44>
8007f80: 6da8 ldr r0, [r5, #88] @ 0x58
8007f82: f7ff fea1 bl 8007cc8 <__retarget_lock_release_recursive>
8007f86: e7f3 b.n 8007f70 <_vfiprintf_r+0x44>
8007f88: 2300 movs r3, #0
8007f8a: 9309 str r3, [sp, #36] @ 0x24
8007f8c: 2320 movs r3, #32
8007f8e: f88d 3029 strb.w r3, [sp, #41] @ 0x29
8007f92: f8cd 800c str.w r8, [sp, #12]
8007f96: 2330 movs r3, #48 @ 0x30
8007f98: f8df 81ac ldr.w r8, [pc, #428] @ 8008148 <_vfiprintf_r+0x21c>
8007f9c: f88d 302a strb.w r3, [sp, #42] @ 0x2a
8007fa0: f04f 0901 mov.w r9, #1
8007fa4: 4623 mov r3, r4
8007fa6: 469a mov sl, r3
8007fa8: f813 2b01 ldrb.w r2, [r3], #1
8007fac: b10a cbz r2, 8007fb2 <_vfiprintf_r+0x86>
8007fae: 2a25 cmp r2, #37 @ 0x25
8007fb0: d1f9 bne.n 8007fa6 <_vfiprintf_r+0x7a>
8007fb2: ebba 0b04 subs.w fp, sl, r4
8007fb6: d00b beq.n 8007fd0 <_vfiprintf_r+0xa4>
8007fb8: 465b mov r3, fp
8007fba: 4622 mov r2, r4
8007fbc: 4629 mov r1, r5
8007fbe: 4630 mov r0, r6
8007fc0: f7ff ffa1 bl 8007f06 <__sfputs_r>
8007fc4: 3001 adds r0, #1
8007fc6: f000 80a7 beq.w 8008118 <_vfiprintf_r+0x1ec>
8007fca: 9a09 ldr r2, [sp, #36] @ 0x24
8007fcc: 445a add r2, fp
8007fce: 9209 str r2, [sp, #36] @ 0x24
8007fd0: f89a 3000 ldrb.w r3, [sl]
8007fd4: 2b00 cmp r3, #0
8007fd6: f000 809f beq.w 8008118 <_vfiprintf_r+0x1ec>
8007fda: 2300 movs r3, #0
8007fdc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8007fe0: e9cd 2305 strd r2, r3, [sp, #20]
8007fe4: f10a 0a01 add.w sl, sl, #1
8007fe8: 9304 str r3, [sp, #16]
8007fea: 9307 str r3, [sp, #28]
8007fec: f88d 3053 strb.w r3, [sp, #83] @ 0x53
8007ff0: 931a str r3, [sp, #104] @ 0x68
8007ff2: 4654 mov r4, sl
8007ff4: 2205 movs r2, #5
8007ff6: f814 1b01 ldrb.w r1, [r4], #1
8007ffa: 4853 ldr r0, [pc, #332] @ (8008148 <_vfiprintf_r+0x21c>)
8007ffc: f7f8 f910 bl 8000220 <memchr>
8008000: 9a04 ldr r2, [sp, #16]
8008002: b9d8 cbnz r0, 800803c <_vfiprintf_r+0x110>
8008004: 06d1 lsls r1, r2, #27
8008006: bf44 itt mi
8008008: 2320 movmi r3, #32
800800a: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
800800e: 0713 lsls r3, r2, #28
8008010: bf44 itt mi
8008012: 232b movmi r3, #43 @ 0x2b
8008014: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
8008018: f89a 3000 ldrb.w r3, [sl]
800801c: 2b2a cmp r3, #42 @ 0x2a
800801e: d015 beq.n 800804c <_vfiprintf_r+0x120>
8008020: 9a07 ldr r2, [sp, #28]
8008022: 4654 mov r4, sl
8008024: 2000 movs r0, #0
8008026: f04f 0c0a mov.w ip, #10
800802a: 4621 mov r1, r4
800802c: f811 3b01 ldrb.w r3, [r1], #1
8008030: 3b30 subs r3, #48 @ 0x30
8008032: 2b09 cmp r3, #9
8008034: d94b bls.n 80080ce <_vfiprintf_r+0x1a2>
8008036: b1b0 cbz r0, 8008066 <_vfiprintf_r+0x13a>
8008038: 9207 str r2, [sp, #28]
800803a: e014 b.n 8008066 <_vfiprintf_r+0x13a>
800803c: eba0 0308 sub.w r3, r0, r8
8008040: fa09 f303 lsl.w r3, r9, r3
8008044: 4313 orrs r3, r2
8008046: 9304 str r3, [sp, #16]
8008048: 46a2 mov sl, r4
800804a: e7d2 b.n 8007ff2 <_vfiprintf_r+0xc6>
800804c: 9b03 ldr r3, [sp, #12]
800804e: 1d19 adds r1, r3, #4
8008050: 681b ldr r3, [r3, #0]
8008052: 9103 str r1, [sp, #12]
8008054: 2b00 cmp r3, #0
8008056: bfbb ittet lt
8008058: 425b neglt r3, r3
800805a: f042 0202 orrlt.w r2, r2, #2
800805e: 9307 strge r3, [sp, #28]
8008060: 9307 strlt r3, [sp, #28]
8008062: bfb8 it lt
8008064: 9204 strlt r2, [sp, #16]
8008066: 7823 ldrb r3, [r4, #0]
8008068: 2b2e cmp r3, #46 @ 0x2e
800806a: d10a bne.n 8008082 <_vfiprintf_r+0x156>
800806c: 7863 ldrb r3, [r4, #1]
800806e: 2b2a cmp r3, #42 @ 0x2a
8008070: d132 bne.n 80080d8 <_vfiprintf_r+0x1ac>
8008072: 9b03 ldr r3, [sp, #12]
8008074: 1d1a adds r2, r3, #4
8008076: 681b ldr r3, [r3, #0]
8008078: 9203 str r2, [sp, #12]
800807a: ea43 73e3 orr.w r3, r3, r3, asr #31
800807e: 3402 adds r4, #2
8008080: 9305 str r3, [sp, #20]
8008082: f8df a0d4 ldr.w sl, [pc, #212] @ 8008158 <_vfiprintf_r+0x22c>
8008086: 7821 ldrb r1, [r4, #0]
8008088: 2203 movs r2, #3
800808a: 4650 mov r0, sl
800808c: f7f8 f8c8 bl 8000220 <memchr>
8008090: b138 cbz r0, 80080a2 <_vfiprintf_r+0x176>
8008092: 9b04 ldr r3, [sp, #16]
8008094: eba0 000a sub.w r0, r0, sl
8008098: 2240 movs r2, #64 @ 0x40
800809a: 4082 lsls r2, r0
800809c: 4313 orrs r3, r2
800809e: 3401 adds r4, #1
80080a0: 9304 str r3, [sp, #16]
80080a2: f814 1b01 ldrb.w r1, [r4], #1
80080a6: 4829 ldr r0, [pc, #164] @ (800814c <_vfiprintf_r+0x220>)
80080a8: f88d 1028 strb.w r1, [sp, #40] @ 0x28
80080ac: 2206 movs r2, #6
80080ae: f7f8 f8b7 bl 8000220 <memchr>
80080b2: 2800 cmp r0, #0
80080b4: d03f beq.n 8008136 <_vfiprintf_r+0x20a>
80080b6: 4b26 ldr r3, [pc, #152] @ (8008150 <_vfiprintf_r+0x224>)
80080b8: bb1b cbnz r3, 8008102 <_vfiprintf_r+0x1d6>
80080ba: 9b03 ldr r3, [sp, #12]
80080bc: 3307 adds r3, #7
80080be: f023 0307 bic.w r3, r3, #7
80080c2: 3308 adds r3, #8
80080c4: 9303 str r3, [sp, #12]
80080c6: 9b09 ldr r3, [sp, #36] @ 0x24
80080c8: 443b add r3, r7
80080ca: 9309 str r3, [sp, #36] @ 0x24
80080cc: e76a b.n 8007fa4 <_vfiprintf_r+0x78>
80080ce: fb0c 3202 mla r2, ip, r2, r3
80080d2: 460c mov r4, r1
80080d4: 2001 movs r0, #1
80080d6: e7a8 b.n 800802a <_vfiprintf_r+0xfe>
80080d8: 2300 movs r3, #0
80080da: 3401 adds r4, #1
80080dc: 9305 str r3, [sp, #20]
80080de: 4619 mov r1, r3
80080e0: f04f 0c0a mov.w ip, #10
80080e4: 4620 mov r0, r4
80080e6: f810 2b01 ldrb.w r2, [r0], #1
80080ea: 3a30 subs r2, #48 @ 0x30
80080ec: 2a09 cmp r2, #9
80080ee: d903 bls.n 80080f8 <_vfiprintf_r+0x1cc>
80080f0: 2b00 cmp r3, #0
80080f2: d0c6 beq.n 8008082 <_vfiprintf_r+0x156>
80080f4: 9105 str r1, [sp, #20]
80080f6: e7c4 b.n 8008082 <_vfiprintf_r+0x156>
80080f8: fb0c 2101 mla r1, ip, r1, r2
80080fc: 4604 mov r4, r0
80080fe: 2301 movs r3, #1
8008100: e7f0 b.n 80080e4 <_vfiprintf_r+0x1b8>
8008102: ab03 add r3, sp, #12
8008104: 9300 str r3, [sp, #0]
8008106: 462a mov r2, r5
8008108: 4b12 ldr r3, [pc, #72] @ (8008154 <_vfiprintf_r+0x228>)
800810a: a904 add r1, sp, #16
800810c: 4630 mov r0, r6
800810e: f3af 8000 nop.w
8008112: 4607 mov r7, r0
8008114: 1c78 adds r0, r7, #1
8008116: d1d6 bne.n 80080c6 <_vfiprintf_r+0x19a>
8008118: 6e6b ldr r3, [r5, #100] @ 0x64
800811a: 07d9 lsls r1, r3, #31
800811c: d405 bmi.n 800812a <_vfiprintf_r+0x1fe>
800811e: 89ab ldrh r3, [r5, #12]
8008120: 059a lsls r2, r3, #22
8008122: d402 bmi.n 800812a <_vfiprintf_r+0x1fe>
8008124: 6da8 ldr r0, [r5, #88] @ 0x58
8008126: f7ff fdcf bl 8007cc8 <__retarget_lock_release_recursive>
800812a: 89ab ldrh r3, [r5, #12]
800812c: 065b lsls r3, r3, #25
800812e: f53f af1f bmi.w 8007f70 <_vfiprintf_r+0x44>
8008132: 9809 ldr r0, [sp, #36] @ 0x24
8008134: e71e b.n 8007f74 <_vfiprintf_r+0x48>
8008136: ab03 add r3, sp, #12
8008138: 9300 str r3, [sp, #0]
800813a: 462a mov r2, r5
800813c: 4b05 ldr r3, [pc, #20] @ (8008154 <_vfiprintf_r+0x228>)
800813e: a904 add r1, sp, #16
8008140: 4630 mov r0, r6
8008142: f000 f879 bl 8008238 <_printf_i>
8008146: e7e4 b.n 8008112 <_vfiprintf_r+0x1e6>
8008148: 08008a40 .word 0x08008a40
800814c: 08008a4a .word 0x08008a4a
8008150: 00000000 .word 0x00000000
8008154: 08007f07 .word 0x08007f07
8008158: 08008a46 .word 0x08008a46
0800815c <_printf_common>:
800815c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8008160: 4616 mov r6, r2
8008162: 4698 mov r8, r3
8008164: 688a ldr r2, [r1, #8]
8008166: 690b ldr r3, [r1, #16]
8008168: f8dd 9020 ldr.w r9, [sp, #32]
800816c: 4293 cmp r3, r2
800816e: bfb8 it lt
8008170: 4613 movlt r3, r2
8008172: 6033 str r3, [r6, #0]
8008174: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
8008178: 4607 mov r7, r0
800817a: 460c mov r4, r1
800817c: b10a cbz r2, 8008182 <_printf_common+0x26>
800817e: 3301 adds r3, #1
8008180: 6033 str r3, [r6, #0]
8008182: 6823 ldr r3, [r4, #0]
8008184: 0699 lsls r1, r3, #26
8008186: bf42 ittt mi
8008188: 6833 ldrmi r3, [r6, #0]
800818a: 3302 addmi r3, #2
800818c: 6033 strmi r3, [r6, #0]
800818e: 6825 ldr r5, [r4, #0]
8008190: f015 0506 ands.w r5, r5, #6
8008194: d106 bne.n 80081a4 <_printf_common+0x48>
8008196: f104 0a19 add.w sl, r4, #25
800819a: 68e3 ldr r3, [r4, #12]
800819c: 6832 ldr r2, [r6, #0]
800819e: 1a9b subs r3, r3, r2
80081a0: 42ab cmp r3, r5
80081a2: dc26 bgt.n 80081f2 <_printf_common+0x96>
80081a4: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
80081a8: 6822 ldr r2, [r4, #0]
80081aa: 3b00 subs r3, #0
80081ac: bf18 it ne
80081ae: 2301 movne r3, #1
80081b0: 0692 lsls r2, r2, #26
80081b2: d42b bmi.n 800820c <_printf_common+0xb0>
80081b4: f104 0243 add.w r2, r4, #67 @ 0x43
80081b8: 4641 mov r1, r8
80081ba: 4638 mov r0, r7
80081bc: 47c8 blx r9
80081be: 3001 adds r0, #1
80081c0: d01e beq.n 8008200 <_printf_common+0xa4>
80081c2: 6823 ldr r3, [r4, #0]
80081c4: 6922 ldr r2, [r4, #16]
80081c6: f003 0306 and.w r3, r3, #6
80081ca: 2b04 cmp r3, #4
80081cc: bf02 ittt eq
80081ce: 68e5 ldreq r5, [r4, #12]
80081d0: 6833 ldreq r3, [r6, #0]
80081d2: 1aed subeq r5, r5, r3
80081d4: 68a3 ldr r3, [r4, #8]
80081d6: bf0c ite eq
80081d8: ea25 75e5 biceq.w r5, r5, r5, asr #31
80081dc: 2500 movne r5, #0
80081de: 4293 cmp r3, r2
80081e0: bfc4 itt gt
80081e2: 1a9b subgt r3, r3, r2
80081e4: 18ed addgt r5, r5, r3
80081e6: 2600 movs r6, #0
80081e8: 341a adds r4, #26
80081ea: 42b5 cmp r5, r6
80081ec: d11a bne.n 8008224 <_printf_common+0xc8>
80081ee: 2000 movs r0, #0
80081f0: e008 b.n 8008204 <_printf_common+0xa8>
80081f2: 2301 movs r3, #1
80081f4: 4652 mov r2, sl
80081f6: 4641 mov r1, r8
80081f8: 4638 mov r0, r7
80081fa: 47c8 blx r9
80081fc: 3001 adds r0, #1
80081fe: d103 bne.n 8008208 <_printf_common+0xac>
8008200: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8008204: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8008208: 3501 adds r5, #1
800820a: e7c6 b.n 800819a <_printf_common+0x3e>
800820c: 18e1 adds r1, r4, r3
800820e: 1c5a adds r2, r3, #1
8008210: 2030 movs r0, #48 @ 0x30
8008212: f881 0043 strb.w r0, [r1, #67] @ 0x43
8008216: 4422 add r2, r4
8008218: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
800821c: f882 1043 strb.w r1, [r2, #67] @ 0x43
8008220: 3302 adds r3, #2
8008222: e7c7 b.n 80081b4 <_printf_common+0x58>
8008224: 2301 movs r3, #1
8008226: 4622 mov r2, r4
8008228: 4641 mov r1, r8
800822a: 4638 mov r0, r7
800822c: 47c8 blx r9
800822e: 3001 adds r0, #1
8008230: d0e6 beq.n 8008200 <_printf_common+0xa4>
8008232: 3601 adds r6, #1
8008234: e7d9 b.n 80081ea <_printf_common+0x8e>
...
08008238 <_printf_i>:
8008238: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
800823c: 7e0f ldrb r7, [r1, #24]
800823e: 9e0c ldr r6, [sp, #48] @ 0x30
8008240: 2f78 cmp r7, #120 @ 0x78
8008242: 4691 mov r9, r2
8008244: 4680 mov r8, r0
8008246: 460c mov r4, r1
8008248: 469a mov sl, r3
800824a: f101 0243 add.w r2, r1, #67 @ 0x43
800824e: d807 bhi.n 8008260 <_printf_i+0x28>
8008250: 2f62 cmp r7, #98 @ 0x62
8008252: d80a bhi.n 800826a <_printf_i+0x32>
8008254: 2f00 cmp r7, #0
8008256: f000 80d1 beq.w 80083fc <_printf_i+0x1c4>
800825a: 2f58 cmp r7, #88 @ 0x58
800825c: f000 80b8 beq.w 80083d0 <_printf_i+0x198>
8008260: f104 0642 add.w r6, r4, #66 @ 0x42
8008264: f884 7042 strb.w r7, [r4, #66] @ 0x42
8008268: e03a b.n 80082e0 <_printf_i+0xa8>
800826a: f1a7 0363 sub.w r3, r7, #99 @ 0x63
800826e: 2b15 cmp r3, #21
8008270: d8f6 bhi.n 8008260 <_printf_i+0x28>
8008272: a101 add r1, pc, #4 @ (adr r1, 8008278 <_printf_i+0x40>)
8008274: f851 f023 ldr.w pc, [r1, r3, lsl #2]
8008278: 080082d1 .word 0x080082d1
800827c: 080082e5 .word 0x080082e5
8008280: 08008261 .word 0x08008261
8008284: 08008261 .word 0x08008261
8008288: 08008261 .word 0x08008261
800828c: 08008261 .word 0x08008261
8008290: 080082e5 .word 0x080082e5
8008294: 08008261 .word 0x08008261
8008298: 08008261 .word 0x08008261
800829c: 08008261 .word 0x08008261
80082a0: 08008261 .word 0x08008261
80082a4: 080083e3 .word 0x080083e3
80082a8: 0800830f .word 0x0800830f
80082ac: 0800839d .word 0x0800839d
80082b0: 08008261 .word 0x08008261
80082b4: 08008261 .word 0x08008261
80082b8: 08008405 .word 0x08008405
80082bc: 08008261 .word 0x08008261
80082c0: 0800830f .word 0x0800830f
80082c4: 08008261 .word 0x08008261
80082c8: 08008261 .word 0x08008261
80082cc: 080083a5 .word 0x080083a5
80082d0: 6833 ldr r3, [r6, #0]
80082d2: 1d1a adds r2, r3, #4
80082d4: 681b ldr r3, [r3, #0]
80082d6: 6032 str r2, [r6, #0]
80082d8: f104 0642 add.w r6, r4, #66 @ 0x42
80082dc: f884 3042 strb.w r3, [r4, #66] @ 0x42
80082e0: 2301 movs r3, #1
80082e2: e09c b.n 800841e <_printf_i+0x1e6>
80082e4: 6833 ldr r3, [r6, #0]
80082e6: 6820 ldr r0, [r4, #0]
80082e8: 1d19 adds r1, r3, #4
80082ea: 6031 str r1, [r6, #0]
80082ec: 0606 lsls r6, r0, #24
80082ee: d501 bpl.n 80082f4 <_printf_i+0xbc>
80082f0: 681d ldr r5, [r3, #0]
80082f2: e003 b.n 80082fc <_printf_i+0xc4>
80082f4: 0645 lsls r5, r0, #25
80082f6: d5fb bpl.n 80082f0 <_printf_i+0xb8>
80082f8: f9b3 5000 ldrsh.w r5, [r3]
80082fc: 2d00 cmp r5, #0
80082fe: da03 bge.n 8008308 <_printf_i+0xd0>
8008300: 232d movs r3, #45 @ 0x2d
8008302: 426d negs r5, r5
8008304: f884 3043 strb.w r3, [r4, #67] @ 0x43
8008308: 4858 ldr r0, [pc, #352] @ (800846c <_printf_i+0x234>)
800830a: 230a movs r3, #10
800830c: e011 b.n 8008332 <_printf_i+0xfa>
800830e: 6821 ldr r1, [r4, #0]
8008310: 6833 ldr r3, [r6, #0]
8008312: 0608 lsls r0, r1, #24
8008314: f853 5b04 ldr.w r5, [r3], #4
8008318: d402 bmi.n 8008320 <_printf_i+0xe8>
800831a: 0649 lsls r1, r1, #25
800831c: bf48 it mi
800831e: b2ad uxthmi r5, r5
8008320: 2f6f cmp r7, #111 @ 0x6f
8008322: 4852 ldr r0, [pc, #328] @ (800846c <_printf_i+0x234>)
8008324: 6033 str r3, [r6, #0]
8008326: bf14 ite ne
8008328: 230a movne r3, #10
800832a: 2308 moveq r3, #8
800832c: 2100 movs r1, #0
800832e: f884 1043 strb.w r1, [r4, #67] @ 0x43
8008332: 6866 ldr r6, [r4, #4]
8008334: 60a6 str r6, [r4, #8]
8008336: 2e00 cmp r6, #0
8008338: db05 blt.n 8008346 <_printf_i+0x10e>
800833a: 6821 ldr r1, [r4, #0]
800833c: 432e orrs r6, r5
800833e: f021 0104 bic.w r1, r1, #4
8008342: 6021 str r1, [r4, #0]
8008344: d04b beq.n 80083de <_printf_i+0x1a6>
8008346: 4616 mov r6, r2
8008348: fbb5 f1f3 udiv r1, r5, r3
800834c: fb03 5711 mls r7, r3, r1, r5
8008350: 5dc7 ldrb r7, [r0, r7]
8008352: f806 7d01 strb.w r7, [r6, #-1]!
8008356: 462f mov r7, r5
8008358: 42bb cmp r3, r7
800835a: 460d mov r5, r1
800835c: d9f4 bls.n 8008348 <_printf_i+0x110>
800835e: 2b08 cmp r3, #8
8008360: d10b bne.n 800837a <_printf_i+0x142>
8008362: 6823 ldr r3, [r4, #0]
8008364: 07df lsls r7, r3, #31
8008366: d508 bpl.n 800837a <_printf_i+0x142>
8008368: 6923 ldr r3, [r4, #16]
800836a: 6861 ldr r1, [r4, #4]
800836c: 4299 cmp r1, r3
800836e: bfde ittt le
8008370: 2330 movle r3, #48 @ 0x30
8008372: f806 3c01 strble.w r3, [r6, #-1]
8008376: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff
800837a: 1b92 subs r2, r2, r6
800837c: 6122 str r2, [r4, #16]
800837e: f8cd a000 str.w sl, [sp]
8008382: 464b mov r3, r9
8008384: aa03 add r2, sp, #12
8008386: 4621 mov r1, r4
8008388: 4640 mov r0, r8
800838a: f7ff fee7 bl 800815c <_printf_common>
800838e: 3001 adds r0, #1
8008390: d14a bne.n 8008428 <_printf_i+0x1f0>
8008392: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8008396: b004 add sp, #16
8008398: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800839c: 6823 ldr r3, [r4, #0]
800839e: f043 0320 orr.w r3, r3, #32
80083a2: 6023 str r3, [r4, #0]
80083a4: 4832 ldr r0, [pc, #200] @ (8008470 <_printf_i+0x238>)
80083a6: 2778 movs r7, #120 @ 0x78
80083a8: f884 7045 strb.w r7, [r4, #69] @ 0x45
80083ac: 6823 ldr r3, [r4, #0]
80083ae: 6831 ldr r1, [r6, #0]
80083b0: 061f lsls r7, r3, #24
80083b2: f851 5b04 ldr.w r5, [r1], #4
80083b6: d402 bmi.n 80083be <_printf_i+0x186>
80083b8: 065f lsls r7, r3, #25
80083ba: bf48 it mi
80083bc: b2ad uxthmi r5, r5
80083be: 6031 str r1, [r6, #0]
80083c0: 07d9 lsls r1, r3, #31
80083c2: bf44 itt mi
80083c4: f043 0320 orrmi.w r3, r3, #32
80083c8: 6023 strmi r3, [r4, #0]
80083ca: b11d cbz r5, 80083d4 <_printf_i+0x19c>
80083cc: 2310 movs r3, #16
80083ce: e7ad b.n 800832c <_printf_i+0xf4>
80083d0: 4826 ldr r0, [pc, #152] @ (800846c <_printf_i+0x234>)
80083d2: e7e9 b.n 80083a8 <_printf_i+0x170>
80083d4: 6823 ldr r3, [r4, #0]
80083d6: f023 0320 bic.w r3, r3, #32
80083da: 6023 str r3, [r4, #0]
80083dc: e7f6 b.n 80083cc <_printf_i+0x194>
80083de: 4616 mov r6, r2
80083e0: e7bd b.n 800835e <_printf_i+0x126>
80083e2: 6833 ldr r3, [r6, #0]
80083e4: 6825 ldr r5, [r4, #0]
80083e6: 6961 ldr r1, [r4, #20]
80083e8: 1d18 adds r0, r3, #4
80083ea: 6030 str r0, [r6, #0]
80083ec: 062e lsls r6, r5, #24
80083ee: 681b ldr r3, [r3, #0]
80083f0: d501 bpl.n 80083f6 <_printf_i+0x1be>
80083f2: 6019 str r1, [r3, #0]
80083f4: e002 b.n 80083fc <_printf_i+0x1c4>
80083f6: 0668 lsls r0, r5, #25
80083f8: d5fb bpl.n 80083f2 <_printf_i+0x1ba>
80083fa: 8019 strh r1, [r3, #0]
80083fc: 2300 movs r3, #0
80083fe: 6123 str r3, [r4, #16]
8008400: 4616 mov r6, r2
8008402: e7bc b.n 800837e <_printf_i+0x146>
8008404: 6833 ldr r3, [r6, #0]
8008406: 1d1a adds r2, r3, #4
8008408: 6032 str r2, [r6, #0]
800840a: 681e ldr r6, [r3, #0]
800840c: 6862 ldr r2, [r4, #4]
800840e: 2100 movs r1, #0
8008410: 4630 mov r0, r6
8008412: f7f7 ff05 bl 8000220 <memchr>
8008416: b108 cbz r0, 800841c <_printf_i+0x1e4>
8008418: 1b80 subs r0, r0, r6
800841a: 6060 str r0, [r4, #4]
800841c: 6863 ldr r3, [r4, #4]
800841e: 6123 str r3, [r4, #16]
8008420: 2300 movs r3, #0
8008422: f884 3043 strb.w r3, [r4, #67] @ 0x43
8008426: e7aa b.n 800837e <_printf_i+0x146>
8008428: 6923 ldr r3, [r4, #16]
800842a: 4632 mov r2, r6
800842c: 4649 mov r1, r9
800842e: 4640 mov r0, r8
8008430: 47d0 blx sl
8008432: 3001 adds r0, #1
8008434: d0ad beq.n 8008392 <_printf_i+0x15a>
8008436: 6823 ldr r3, [r4, #0]
8008438: 079b lsls r3, r3, #30
800843a: d413 bmi.n 8008464 <_printf_i+0x22c>
800843c: 68e0 ldr r0, [r4, #12]
800843e: 9b03 ldr r3, [sp, #12]
8008440: 4298 cmp r0, r3
8008442: bfb8 it lt
8008444: 4618 movlt r0, r3
8008446: e7a6 b.n 8008396 <_printf_i+0x15e>
8008448: 2301 movs r3, #1
800844a: 4632 mov r2, r6
800844c: 4649 mov r1, r9
800844e: 4640 mov r0, r8
8008450: 47d0 blx sl
8008452: 3001 adds r0, #1
8008454: d09d beq.n 8008392 <_printf_i+0x15a>
8008456: 3501 adds r5, #1
8008458: 68e3 ldr r3, [r4, #12]
800845a: 9903 ldr r1, [sp, #12]
800845c: 1a5b subs r3, r3, r1
800845e: 42ab cmp r3, r5
8008460: dcf2 bgt.n 8008448 <_printf_i+0x210>
8008462: e7eb b.n 800843c <_printf_i+0x204>
8008464: 2500 movs r5, #0
8008466: f104 0619 add.w r6, r4, #25
800846a: e7f5 b.n 8008458 <_printf_i+0x220>
800846c: 08008a51 .word 0x08008a51
8008470: 08008a62 .word 0x08008a62
08008474 <__sflush_r>:
8008474: f9b1 200c ldrsh.w r2, [r1, #12]
8008478: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
800847c: 0716 lsls r6, r2, #28
800847e: 4605 mov r5, r0
8008480: 460c mov r4, r1
8008482: d454 bmi.n 800852e <__sflush_r+0xba>
8008484: 684b ldr r3, [r1, #4]
8008486: 2b00 cmp r3, #0
8008488: dc02 bgt.n 8008490 <__sflush_r+0x1c>
800848a: 6c0b ldr r3, [r1, #64] @ 0x40
800848c: 2b00 cmp r3, #0
800848e: dd48 ble.n 8008522 <__sflush_r+0xae>
8008490: 6ae6 ldr r6, [r4, #44] @ 0x2c
8008492: 2e00 cmp r6, #0
8008494: d045 beq.n 8008522 <__sflush_r+0xae>
8008496: 2300 movs r3, #0
8008498: f412 5280 ands.w r2, r2, #4096 @ 0x1000
800849c: 682f ldr r7, [r5, #0]
800849e: 6a21 ldr r1, [r4, #32]
80084a0: 602b str r3, [r5, #0]
80084a2: d030 beq.n 8008506 <__sflush_r+0x92>
80084a4: 6d62 ldr r2, [r4, #84] @ 0x54
80084a6: 89a3 ldrh r3, [r4, #12]
80084a8: 0759 lsls r1, r3, #29
80084aa: d505 bpl.n 80084b8 <__sflush_r+0x44>
80084ac: 6863 ldr r3, [r4, #4]
80084ae: 1ad2 subs r2, r2, r3
80084b0: 6b63 ldr r3, [r4, #52] @ 0x34
80084b2: b10b cbz r3, 80084b8 <__sflush_r+0x44>
80084b4: 6c23 ldr r3, [r4, #64] @ 0x40
80084b6: 1ad2 subs r2, r2, r3
80084b8: 2300 movs r3, #0
80084ba: 6ae6 ldr r6, [r4, #44] @ 0x2c
80084bc: 6a21 ldr r1, [r4, #32]
80084be: 4628 mov r0, r5
80084c0: 47b0 blx r6
80084c2: 1c43 adds r3, r0, #1
80084c4: 89a3 ldrh r3, [r4, #12]
80084c6: d106 bne.n 80084d6 <__sflush_r+0x62>
80084c8: 6829 ldr r1, [r5, #0]
80084ca: 291d cmp r1, #29
80084cc: d82b bhi.n 8008526 <__sflush_r+0xb2>
80084ce: 4a2a ldr r2, [pc, #168] @ (8008578 <__sflush_r+0x104>)
80084d0: 40ca lsrs r2, r1
80084d2: 07d6 lsls r6, r2, #31
80084d4: d527 bpl.n 8008526 <__sflush_r+0xb2>
80084d6: 2200 movs r2, #0
80084d8: 6062 str r2, [r4, #4]
80084da: 04d9 lsls r1, r3, #19
80084dc: 6922 ldr r2, [r4, #16]
80084de: 6022 str r2, [r4, #0]
80084e0: d504 bpl.n 80084ec <__sflush_r+0x78>
80084e2: 1c42 adds r2, r0, #1
80084e4: d101 bne.n 80084ea <__sflush_r+0x76>
80084e6: 682b ldr r3, [r5, #0]
80084e8: b903 cbnz r3, 80084ec <__sflush_r+0x78>
80084ea: 6560 str r0, [r4, #84] @ 0x54
80084ec: 6b61 ldr r1, [r4, #52] @ 0x34
80084ee: 602f str r7, [r5, #0]
80084f0: b1b9 cbz r1, 8008522 <__sflush_r+0xae>
80084f2: f104 0344 add.w r3, r4, #68 @ 0x44
80084f6: 4299 cmp r1, r3
80084f8: d002 beq.n 8008500 <__sflush_r+0x8c>
80084fa: 4628 mov r0, r5
80084fc: f7ff fbf4 bl 8007ce8 <_free_r>
8008500: 2300 movs r3, #0
8008502: 6363 str r3, [r4, #52] @ 0x34
8008504: e00d b.n 8008522 <__sflush_r+0xae>
8008506: 2301 movs r3, #1
8008508: 4628 mov r0, r5
800850a: 47b0 blx r6
800850c: 4602 mov r2, r0
800850e: 1c50 adds r0, r2, #1
8008510: d1c9 bne.n 80084a6 <__sflush_r+0x32>
8008512: 682b ldr r3, [r5, #0]
8008514: 2b00 cmp r3, #0
8008516: d0c6 beq.n 80084a6 <__sflush_r+0x32>
8008518: 2b1d cmp r3, #29
800851a: d001 beq.n 8008520 <__sflush_r+0xac>
800851c: 2b16 cmp r3, #22
800851e: d11e bne.n 800855e <__sflush_r+0xea>
8008520: 602f str r7, [r5, #0]
8008522: 2000 movs r0, #0
8008524: e022 b.n 800856c <__sflush_r+0xf8>
8008526: f043 0340 orr.w r3, r3, #64 @ 0x40
800852a: b21b sxth r3, r3
800852c: e01b b.n 8008566 <__sflush_r+0xf2>
800852e: 690f ldr r7, [r1, #16]
8008530: 2f00 cmp r7, #0
8008532: d0f6 beq.n 8008522 <__sflush_r+0xae>
8008534: 0793 lsls r3, r2, #30
8008536: 680e ldr r6, [r1, #0]
8008538: bf08 it eq
800853a: 694b ldreq r3, [r1, #20]
800853c: 600f str r7, [r1, #0]
800853e: bf18 it ne
8008540: 2300 movne r3, #0
8008542: eba6 0807 sub.w r8, r6, r7
8008546: 608b str r3, [r1, #8]
8008548: f1b8 0f00 cmp.w r8, #0
800854c: dde9 ble.n 8008522 <__sflush_r+0xae>
800854e: 6a21 ldr r1, [r4, #32]
8008550: 6aa6 ldr r6, [r4, #40] @ 0x28
8008552: 4643 mov r3, r8
8008554: 463a mov r2, r7
8008556: 4628 mov r0, r5
8008558: 47b0 blx r6
800855a: 2800 cmp r0, #0
800855c: dc08 bgt.n 8008570 <__sflush_r+0xfc>
800855e: f9b4 300c ldrsh.w r3, [r4, #12]
8008562: f043 0340 orr.w r3, r3, #64 @ 0x40
8008566: 81a3 strh r3, [r4, #12]
8008568: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
800856c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8008570: 4407 add r7, r0
8008572: eba8 0800 sub.w r8, r8, r0
8008576: e7e7 b.n 8008548 <__sflush_r+0xd4>
8008578: 20400001 .word 0x20400001
0800857c <_fflush_r>:
800857c: b538 push {r3, r4, r5, lr}
800857e: 690b ldr r3, [r1, #16]
8008580: 4605 mov r5, r0
8008582: 460c mov r4, r1
8008584: b913 cbnz r3, 800858c <_fflush_r+0x10>
8008586: 2500 movs r5, #0
8008588: 4628 mov r0, r5
800858a: bd38 pop {r3, r4, r5, pc}
800858c: b118 cbz r0, 8008596 <_fflush_r+0x1a>
800858e: 6a03 ldr r3, [r0, #32]
8008590: b90b cbnz r3, 8008596 <_fflush_r+0x1a>
8008592: f7ff fa35 bl 8007a00 <__sinit>
8008596: f9b4 300c ldrsh.w r3, [r4, #12]
800859a: 2b00 cmp r3, #0
800859c: d0f3 beq.n 8008586 <_fflush_r+0xa>
800859e: 6e62 ldr r2, [r4, #100] @ 0x64
80085a0: 07d0 lsls r0, r2, #31
80085a2: d404 bmi.n 80085ae <_fflush_r+0x32>
80085a4: 0599 lsls r1, r3, #22
80085a6: d402 bmi.n 80085ae <_fflush_r+0x32>
80085a8: 6da0 ldr r0, [r4, #88] @ 0x58
80085aa: f7ff fb8c bl 8007cc6 <__retarget_lock_acquire_recursive>
80085ae: 4628 mov r0, r5
80085b0: 4621 mov r1, r4
80085b2: f7ff ff5f bl 8008474 <__sflush_r>
80085b6: 6e63 ldr r3, [r4, #100] @ 0x64
80085b8: 07da lsls r2, r3, #31
80085ba: 4605 mov r5, r0
80085bc: d4e4 bmi.n 8008588 <_fflush_r+0xc>
80085be: 89a3 ldrh r3, [r4, #12]
80085c0: 059b lsls r3, r3, #22
80085c2: d4e1 bmi.n 8008588 <_fflush_r+0xc>
80085c4: 6da0 ldr r0, [r4, #88] @ 0x58
80085c6: f7ff fb7f bl 8007cc8 <__retarget_lock_release_recursive>
80085ca: e7dd b.n 8008588 <_fflush_r+0xc>
080085cc <__swbuf_r>:
80085cc: b5f8 push {r3, r4, r5, r6, r7, lr}
80085ce: 460e mov r6, r1
80085d0: 4614 mov r4, r2
80085d2: 4605 mov r5, r0
80085d4: b118 cbz r0, 80085de <__swbuf_r+0x12>
80085d6: 6a03 ldr r3, [r0, #32]
80085d8: b90b cbnz r3, 80085de <__swbuf_r+0x12>
80085da: f7ff fa11 bl 8007a00 <__sinit>
80085de: 69a3 ldr r3, [r4, #24]
80085e0: 60a3 str r3, [r4, #8]
80085e2: 89a3 ldrh r3, [r4, #12]
80085e4: 071a lsls r2, r3, #28
80085e6: d501 bpl.n 80085ec <__swbuf_r+0x20>
80085e8: 6923 ldr r3, [r4, #16]
80085ea: b943 cbnz r3, 80085fe <__swbuf_r+0x32>
80085ec: 4621 mov r1, r4
80085ee: 4628 mov r0, r5
80085f0: f000 f82a bl 8008648 <__swsetup_r>
80085f4: b118 cbz r0, 80085fe <__swbuf_r+0x32>
80085f6: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff
80085fa: 4638 mov r0, r7
80085fc: bdf8 pop {r3, r4, r5, r6, r7, pc}
80085fe: 6823 ldr r3, [r4, #0]
8008600: 6922 ldr r2, [r4, #16]
8008602: 1a98 subs r0, r3, r2
8008604: 6963 ldr r3, [r4, #20]
8008606: b2f6 uxtb r6, r6
8008608: 4283 cmp r3, r0
800860a: 4637 mov r7, r6
800860c: dc05 bgt.n 800861a <__swbuf_r+0x4e>
800860e: 4621 mov r1, r4
8008610: 4628 mov r0, r5
8008612: f7ff ffb3 bl 800857c <_fflush_r>
8008616: 2800 cmp r0, #0
8008618: d1ed bne.n 80085f6 <__swbuf_r+0x2a>
800861a: 68a3 ldr r3, [r4, #8]
800861c: 3b01 subs r3, #1
800861e: 60a3 str r3, [r4, #8]
8008620: 6823 ldr r3, [r4, #0]
8008622: 1c5a adds r2, r3, #1
8008624: 6022 str r2, [r4, #0]
8008626: 701e strb r6, [r3, #0]
8008628: 6962 ldr r2, [r4, #20]
800862a: 1c43 adds r3, r0, #1
800862c: 429a cmp r2, r3
800862e: d004 beq.n 800863a <__swbuf_r+0x6e>
8008630: 89a3 ldrh r3, [r4, #12]
8008632: 07db lsls r3, r3, #31
8008634: d5e1 bpl.n 80085fa <__swbuf_r+0x2e>
8008636: 2e0a cmp r6, #10
8008638: d1df bne.n 80085fa <__swbuf_r+0x2e>
800863a: 4621 mov r1, r4
800863c: 4628 mov r0, r5
800863e: f7ff ff9d bl 800857c <_fflush_r>
8008642: 2800 cmp r0, #0
8008644: d0d9 beq.n 80085fa <__swbuf_r+0x2e>
8008646: e7d6 b.n 80085f6 <__swbuf_r+0x2a>
08008648 <__swsetup_r>:
8008648: b538 push {r3, r4, r5, lr}
800864a: 4b29 ldr r3, [pc, #164] @ (80086f0 <__swsetup_r+0xa8>)
800864c: 4605 mov r5, r0
800864e: 6818 ldr r0, [r3, #0]
8008650: 460c mov r4, r1
8008652: b118 cbz r0, 800865c <__swsetup_r+0x14>
8008654: 6a03 ldr r3, [r0, #32]
8008656: b90b cbnz r3, 800865c <__swsetup_r+0x14>
8008658: f7ff f9d2 bl 8007a00 <__sinit>
800865c: f9b4 300c ldrsh.w r3, [r4, #12]
8008660: 0719 lsls r1, r3, #28
8008662: d422 bmi.n 80086aa <__swsetup_r+0x62>
8008664: 06da lsls r2, r3, #27
8008666: d407 bmi.n 8008678 <__swsetup_r+0x30>
8008668: 2209 movs r2, #9
800866a: 602a str r2, [r5, #0]
800866c: f043 0340 orr.w r3, r3, #64 @ 0x40
8008670: 81a3 strh r3, [r4, #12]
8008672: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8008676: e033 b.n 80086e0 <__swsetup_r+0x98>
8008678: 0758 lsls r0, r3, #29
800867a: d512 bpl.n 80086a2 <__swsetup_r+0x5a>
800867c: 6b61 ldr r1, [r4, #52] @ 0x34
800867e: b141 cbz r1, 8008692 <__swsetup_r+0x4a>
8008680: f104 0344 add.w r3, r4, #68 @ 0x44
8008684: 4299 cmp r1, r3
8008686: d002 beq.n 800868e <__swsetup_r+0x46>
8008688: 4628 mov r0, r5
800868a: f7ff fb2d bl 8007ce8 <_free_r>
800868e: 2300 movs r3, #0
8008690: 6363 str r3, [r4, #52] @ 0x34
8008692: 89a3 ldrh r3, [r4, #12]
8008694: f023 0324 bic.w r3, r3, #36 @ 0x24
8008698: 81a3 strh r3, [r4, #12]
800869a: 2300 movs r3, #0
800869c: 6063 str r3, [r4, #4]
800869e: 6923 ldr r3, [r4, #16]
80086a0: 6023 str r3, [r4, #0]
80086a2: 89a3 ldrh r3, [r4, #12]
80086a4: f043 0308 orr.w r3, r3, #8
80086a8: 81a3 strh r3, [r4, #12]
80086aa: 6923 ldr r3, [r4, #16]
80086ac: b94b cbnz r3, 80086c2 <__swsetup_r+0x7a>
80086ae: 89a3 ldrh r3, [r4, #12]
80086b0: f403 7320 and.w r3, r3, #640 @ 0x280
80086b4: f5b3 7f00 cmp.w r3, #512 @ 0x200
80086b8: d003 beq.n 80086c2 <__swsetup_r+0x7a>
80086ba: 4621 mov r1, r4
80086bc: 4628 mov r0, r5
80086be: f000 f84f bl 8008760 <__smakebuf_r>
80086c2: f9b4 300c ldrsh.w r3, [r4, #12]
80086c6: f013 0201 ands.w r2, r3, #1
80086ca: d00a beq.n 80086e2 <__swsetup_r+0x9a>
80086cc: 2200 movs r2, #0
80086ce: 60a2 str r2, [r4, #8]
80086d0: 6962 ldr r2, [r4, #20]
80086d2: 4252 negs r2, r2
80086d4: 61a2 str r2, [r4, #24]
80086d6: 6922 ldr r2, [r4, #16]
80086d8: b942 cbnz r2, 80086ec <__swsetup_r+0xa4>
80086da: f013 0080 ands.w r0, r3, #128 @ 0x80
80086de: d1c5 bne.n 800866c <__swsetup_r+0x24>
80086e0: bd38 pop {r3, r4, r5, pc}
80086e2: 0799 lsls r1, r3, #30
80086e4: bf58 it pl
80086e6: 6962 ldrpl r2, [r4, #20]
80086e8: 60a2 str r2, [r4, #8]
80086ea: e7f4 b.n 80086d6 <__swsetup_r+0x8e>
80086ec: 2000 movs r0, #0
80086ee: e7f7 b.n 80086e0 <__swsetup_r+0x98>
80086f0: 2000001c .word 0x2000001c
080086f4 <_sbrk_r>:
80086f4: b538 push {r3, r4, r5, lr}
80086f6: 4d06 ldr r5, [pc, #24] @ (8008710 <_sbrk_r+0x1c>)
80086f8: 2300 movs r3, #0
80086fa: 4604 mov r4, r0
80086fc: 4608 mov r0, r1
80086fe: 602b str r3, [r5, #0]
8008700: f7f9 faa6 bl 8001c50 <_sbrk>
8008704: 1c43 adds r3, r0, #1
8008706: d102 bne.n 800870e <_sbrk_r+0x1a>
8008708: 682b ldr r3, [r5, #0]
800870a: b103 cbz r3, 800870e <_sbrk_r+0x1a>
800870c: 6023 str r3, [r4, #0]
800870e: bd38 pop {r3, r4, r5, pc}
8008710: 20008e28 .word 0x20008e28
08008714 <__swhatbuf_r>:
8008714: b570 push {r4, r5, r6, lr}
8008716: 460c mov r4, r1
8008718: f9b1 100e ldrsh.w r1, [r1, #14]
800871c: 2900 cmp r1, #0
800871e: b096 sub sp, #88 @ 0x58
8008720: 4615 mov r5, r2
8008722: 461e mov r6, r3
8008724: da0d bge.n 8008742 <__swhatbuf_r+0x2e>
8008726: 89a3 ldrh r3, [r4, #12]
8008728: f013 0f80 tst.w r3, #128 @ 0x80
800872c: f04f 0100 mov.w r1, #0
8008730: bf14 ite ne
8008732: 2340 movne r3, #64 @ 0x40
8008734: f44f 6380 moveq.w r3, #1024 @ 0x400
8008738: 2000 movs r0, #0
800873a: 6031 str r1, [r6, #0]
800873c: 602b str r3, [r5, #0]
800873e: b016 add sp, #88 @ 0x58
8008740: bd70 pop {r4, r5, r6, pc}
8008742: 466a mov r2, sp
8008744: f000 f848 bl 80087d8 <_fstat_r>
8008748: 2800 cmp r0, #0
800874a: dbec blt.n 8008726 <__swhatbuf_r+0x12>
800874c: 9901 ldr r1, [sp, #4]
800874e: f401 4170 and.w r1, r1, #61440 @ 0xf000
8008752: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000
8008756: 4259 negs r1, r3
8008758: 4159 adcs r1, r3
800875a: f44f 6380 mov.w r3, #1024 @ 0x400
800875e: e7eb b.n 8008738 <__swhatbuf_r+0x24>
08008760 <__smakebuf_r>:
8008760: 898b ldrh r3, [r1, #12]
8008762: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
8008764: 079d lsls r5, r3, #30
8008766: 4606 mov r6, r0
8008768: 460c mov r4, r1
800876a: d507 bpl.n 800877c <__smakebuf_r+0x1c>
800876c: f104 0347 add.w r3, r4, #71 @ 0x47
8008770: 6023 str r3, [r4, #0]
8008772: 6123 str r3, [r4, #16]
8008774: 2301 movs r3, #1
8008776: 6163 str r3, [r4, #20]
8008778: b003 add sp, #12
800877a: bdf0 pop {r4, r5, r6, r7, pc}
800877c: ab01 add r3, sp, #4
800877e: 466a mov r2, sp
8008780: f7ff ffc8 bl 8008714 <__swhatbuf_r>
8008784: 9f00 ldr r7, [sp, #0]
8008786: 4605 mov r5, r0
8008788: 4639 mov r1, r7
800878a: 4630 mov r0, r6
800878c: f7ff fb18 bl 8007dc0 <_malloc_r>
8008790: b948 cbnz r0, 80087a6 <__smakebuf_r+0x46>
8008792: f9b4 300c ldrsh.w r3, [r4, #12]
8008796: 059a lsls r2, r3, #22
8008798: d4ee bmi.n 8008778 <__smakebuf_r+0x18>
800879a: f023 0303 bic.w r3, r3, #3
800879e: f043 0302 orr.w r3, r3, #2
80087a2: 81a3 strh r3, [r4, #12]
80087a4: e7e2 b.n 800876c <__smakebuf_r+0xc>
80087a6: 89a3 ldrh r3, [r4, #12]
80087a8: 6020 str r0, [r4, #0]
80087aa: f043 0380 orr.w r3, r3, #128 @ 0x80
80087ae: 81a3 strh r3, [r4, #12]
80087b0: 9b01 ldr r3, [sp, #4]
80087b2: e9c4 0704 strd r0, r7, [r4, #16]
80087b6: b15b cbz r3, 80087d0 <__smakebuf_r+0x70>
80087b8: f9b4 100e ldrsh.w r1, [r4, #14]
80087bc: 4630 mov r0, r6
80087be: f000 f81d bl 80087fc <_isatty_r>
80087c2: b128 cbz r0, 80087d0 <__smakebuf_r+0x70>
80087c4: 89a3 ldrh r3, [r4, #12]
80087c6: f023 0303 bic.w r3, r3, #3
80087ca: f043 0301 orr.w r3, r3, #1
80087ce: 81a3 strh r3, [r4, #12]
80087d0: 89a3 ldrh r3, [r4, #12]
80087d2: 431d orrs r5, r3
80087d4: 81a5 strh r5, [r4, #12]
80087d6: e7cf b.n 8008778 <__smakebuf_r+0x18>
080087d8 <_fstat_r>:
80087d8: b538 push {r3, r4, r5, lr}
80087da: 4d07 ldr r5, [pc, #28] @ (80087f8 <_fstat_r+0x20>)
80087dc: 2300 movs r3, #0
80087de: 4604 mov r4, r0
80087e0: 4608 mov r0, r1
80087e2: 4611 mov r1, r2
80087e4: 602b str r3, [r5, #0]
80087e6: f7f9 fa0a bl 8001bfe <_fstat>
80087ea: 1c43 adds r3, r0, #1
80087ec: d102 bne.n 80087f4 <_fstat_r+0x1c>
80087ee: 682b ldr r3, [r5, #0]
80087f0: b103 cbz r3, 80087f4 <_fstat_r+0x1c>
80087f2: 6023 str r3, [r4, #0]
80087f4: bd38 pop {r3, r4, r5, pc}
80087f6: bf00 nop
80087f8: 20008e28 .word 0x20008e28
080087fc <_isatty_r>:
80087fc: b538 push {r3, r4, r5, lr}
80087fe: 4d06 ldr r5, [pc, #24] @ (8008818 <_isatty_r+0x1c>)
8008800: 2300 movs r3, #0
8008802: 4604 mov r4, r0
8008804: 4608 mov r0, r1
8008806: 602b str r3, [r5, #0]
8008808: f7f9 fa09 bl 8001c1e <_isatty>
800880c: 1c43 adds r3, r0, #1
800880e: d102 bne.n 8008816 <_isatty_r+0x1a>
8008810: 682b ldr r3, [r5, #0]
8008812: b103 cbz r3, 8008816 <_isatty_r+0x1a>
8008814: 6023 str r3, [r4, #0]
8008816: bd38 pop {r3, r4, r5, pc}
8008818: 20008e28 .word 0x20008e28
0800881c <_init>:
800881c: b5f8 push {r3, r4, r5, r6, r7, lr}
800881e: bf00 nop
8008820: bcf8 pop {r3, r4, r5, r6, r7}
8008822: bc08 pop {r3}
8008824: 469e mov lr, r3
8008826: 4770 bx lr
08008828 <_fini>:
8008828: b5f8 push {r3, r4, r5, r6, r7, lr}
800882a: bf00 nop
800882c: bcf8 pop {r3, r4, r5, r6, r7}
800882e: bc08 pop {r3}
8008830: 469e mov lr, r3
8008832: 4770 bx lr
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