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HAW-LA_s7-prakt-mikrocontro.../Versuch2/Debug/Versuch2.list
jonny 8c10217a89 init - V1 complete, V2 started
2025-11-16 19:48:16 +01:00

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Versuch2.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001e0 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 000052a8 080001e0 080001e0 000011e0 2**4
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 000000c0 08005488 08005488 00006488 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08005548 08005548 00007068 2**0
CONTENTS, READONLY
4 .ARM 00000008 08005548 08005548 00006548 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08005550 08005550 00007068 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08005550 08005550 00006550 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08005554 08005554 00006554 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000068 20000000 08005558 00007000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000002e8 20000068 080055c0 00007068 2**2
ALLOC
10 ._user_heap_stack 00000600 20000350 080055c0 00007350 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 00007068 2**0
CONTENTS, READONLY
12 .debug_info 000165b3 00000000 00000000 00007098 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00002ea7 00000000 00000000 0001d64b 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00001430 00000000 00000000 000204f8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00000fc1 00000000 00000000 00021928 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 000258f0 00000000 00000000 000228e9 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0001729c 00000000 00000000 000481d9 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000e5d9b 00000000 00000000 0005f475 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 00145210 2**0
CONTENTS, READONLY
20 .debug_frame 00005cfc 00000000 00000000 00145254 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 0000007e 00000000 00000000 0014af50 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001e0 <__do_global_dtors_aux>:
80001e0: b510 push {r4, lr}
80001e2: 4c05 ldr r4, [pc, #20] @ (80001f8 <__do_global_dtors_aux+0x18>)
80001e4: 7823 ldrb r3, [r4, #0]
80001e6: b933 cbnz r3, 80001f6 <__do_global_dtors_aux+0x16>
80001e8: 4b04 ldr r3, [pc, #16] @ (80001fc <__do_global_dtors_aux+0x1c>)
80001ea: b113 cbz r3, 80001f2 <__do_global_dtors_aux+0x12>
80001ec: 4804 ldr r0, [pc, #16] @ (8000200 <__do_global_dtors_aux+0x20>)
80001ee: f3af 8000 nop.w
80001f2: 2301 movs r3, #1
80001f4: 7023 strb r3, [r4, #0]
80001f6: bd10 pop {r4, pc}
80001f8: 20000068 .word 0x20000068
80001fc: 00000000 .word 0x00000000
8000200: 08005470 .word 0x08005470
08000204 <frame_dummy>:
8000204: b508 push {r3, lr}
8000206: 4b03 ldr r3, [pc, #12] @ (8000214 <frame_dummy+0x10>)
8000208: b11b cbz r3, 8000212 <frame_dummy+0xe>
800020a: 4903 ldr r1, [pc, #12] @ (8000218 <frame_dummy+0x14>)
800020c: 4803 ldr r0, [pc, #12] @ (800021c <frame_dummy+0x18>)
800020e: f3af 8000 nop.w
8000212: bd08 pop {r3, pc}
8000214: 00000000 .word 0x00000000
8000218: 2000006c .word 0x2000006c
800021c: 08005470 .word 0x08005470
08000220 <memchr>:
8000220: f001 01ff and.w r1, r1, #255 @ 0xff
8000224: 2a10 cmp r2, #16
8000226: db2b blt.n 8000280 <memchr+0x60>
8000228: f010 0f07 tst.w r0, #7
800022c: d008 beq.n 8000240 <memchr+0x20>
800022e: f810 3b01 ldrb.w r3, [r0], #1
8000232: 3a01 subs r2, #1
8000234: 428b cmp r3, r1
8000236: d02d beq.n 8000294 <memchr+0x74>
8000238: f010 0f07 tst.w r0, #7
800023c: b342 cbz r2, 8000290 <memchr+0x70>
800023e: d1f6 bne.n 800022e <memchr+0xe>
8000240: b4f0 push {r4, r5, r6, r7}
8000242: ea41 2101 orr.w r1, r1, r1, lsl #8
8000246: ea41 4101 orr.w r1, r1, r1, lsl #16
800024a: f022 0407 bic.w r4, r2, #7
800024e: f07f 0700 mvns.w r7, #0
8000252: 2300 movs r3, #0
8000254: e8f0 5602 ldrd r5, r6, [r0], #8
8000258: 3c08 subs r4, #8
800025a: ea85 0501 eor.w r5, r5, r1
800025e: ea86 0601 eor.w r6, r6, r1
8000262: fa85 f547 uadd8 r5, r5, r7
8000266: faa3 f587 sel r5, r3, r7
800026a: fa86 f647 uadd8 r6, r6, r7
800026e: faa5 f687 sel r6, r5, r7
8000272: b98e cbnz r6, 8000298 <memchr+0x78>
8000274: d1ee bne.n 8000254 <memchr+0x34>
8000276: bcf0 pop {r4, r5, r6, r7}
8000278: f001 01ff and.w r1, r1, #255 @ 0xff
800027c: f002 0207 and.w r2, r2, #7
8000280: b132 cbz r2, 8000290 <memchr+0x70>
8000282: f810 3b01 ldrb.w r3, [r0], #1
8000286: 3a01 subs r2, #1
8000288: ea83 0301 eor.w r3, r3, r1
800028c: b113 cbz r3, 8000294 <memchr+0x74>
800028e: d1f8 bne.n 8000282 <memchr+0x62>
8000290: 2000 movs r0, #0
8000292: 4770 bx lr
8000294: 3801 subs r0, #1
8000296: 4770 bx lr
8000298: 2d00 cmp r5, #0
800029a: bf06 itte eq
800029c: 4635 moveq r5, r6
800029e: 3803 subeq r0, #3
80002a0: 3807 subne r0, #7
80002a2: f015 0f01 tst.w r5, #1
80002a6: d107 bne.n 80002b8 <memchr+0x98>
80002a8: 3001 adds r0, #1
80002aa: f415 7f80 tst.w r5, #256 @ 0x100
80002ae: bf02 ittt eq
80002b0: 3001 addeq r0, #1
80002b2: f415 3fc0 tsteq.w r5, #98304 @ 0x18000
80002b6: 3001 addeq r0, #1
80002b8: bcf0 pop {r4, r5, r6, r7}
80002ba: 3801 subs r0, #1
80002bc: 4770 bx lr
80002be: bf00 nop
080002c0 <__aeabi_uldivmod>:
80002c0: b953 cbnz r3, 80002d8 <__aeabi_uldivmod+0x18>
80002c2: b94a cbnz r2, 80002d8 <__aeabi_uldivmod+0x18>
80002c4: 2900 cmp r1, #0
80002c6: bf08 it eq
80002c8: 2800 cmpeq r0, #0
80002ca: bf1c itt ne
80002cc: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
80002d0: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
80002d4: f000 b988 b.w 80005e8 <__aeabi_idiv0>
80002d8: f1ad 0c08 sub.w ip, sp, #8
80002dc: e96d ce04 strd ip, lr, [sp, #-16]!
80002e0: f000 f806 bl 80002f0 <__udivmoddi4>
80002e4: f8dd e004 ldr.w lr, [sp, #4]
80002e8: e9dd 2302 ldrd r2, r3, [sp, #8]
80002ec: b004 add sp, #16
80002ee: 4770 bx lr
080002f0 <__udivmoddi4>:
80002f0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80002f4: 9d08 ldr r5, [sp, #32]
80002f6: 468e mov lr, r1
80002f8: 4604 mov r4, r0
80002fa: 4688 mov r8, r1
80002fc: 2b00 cmp r3, #0
80002fe: d14a bne.n 8000396 <__udivmoddi4+0xa6>
8000300: 428a cmp r2, r1
8000302: 4617 mov r7, r2
8000304: d962 bls.n 80003cc <__udivmoddi4+0xdc>
8000306: fab2 f682 clz r6, r2
800030a: b14e cbz r6, 8000320 <__udivmoddi4+0x30>
800030c: f1c6 0320 rsb r3, r6, #32
8000310: fa01 f806 lsl.w r8, r1, r6
8000314: fa20 f303 lsr.w r3, r0, r3
8000318: 40b7 lsls r7, r6
800031a: ea43 0808 orr.w r8, r3, r8
800031e: 40b4 lsls r4, r6
8000320: ea4f 4e17 mov.w lr, r7, lsr #16
8000324: fa1f fc87 uxth.w ip, r7
8000328: fbb8 f1fe udiv r1, r8, lr
800032c: 0c23 lsrs r3, r4, #16
800032e: fb0e 8811 mls r8, lr, r1, r8
8000332: ea43 4308 orr.w r3, r3, r8, lsl #16
8000336: fb01 f20c mul.w r2, r1, ip
800033a: 429a cmp r2, r3
800033c: d909 bls.n 8000352 <__udivmoddi4+0x62>
800033e: 18fb adds r3, r7, r3
8000340: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
8000344: f080 80ea bcs.w 800051c <__udivmoddi4+0x22c>
8000348: 429a cmp r2, r3
800034a: f240 80e7 bls.w 800051c <__udivmoddi4+0x22c>
800034e: 3902 subs r1, #2
8000350: 443b add r3, r7
8000352: 1a9a subs r2, r3, r2
8000354: b2a3 uxth r3, r4
8000356: fbb2 f0fe udiv r0, r2, lr
800035a: fb0e 2210 mls r2, lr, r0, r2
800035e: ea43 4302 orr.w r3, r3, r2, lsl #16
8000362: fb00 fc0c mul.w ip, r0, ip
8000366: 459c cmp ip, r3
8000368: d909 bls.n 800037e <__udivmoddi4+0x8e>
800036a: 18fb adds r3, r7, r3
800036c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
8000370: f080 80d6 bcs.w 8000520 <__udivmoddi4+0x230>
8000374: 459c cmp ip, r3
8000376: f240 80d3 bls.w 8000520 <__udivmoddi4+0x230>
800037a: 443b add r3, r7
800037c: 3802 subs r0, #2
800037e: ea40 4001 orr.w r0, r0, r1, lsl #16
8000382: eba3 030c sub.w r3, r3, ip
8000386: 2100 movs r1, #0
8000388: b11d cbz r5, 8000392 <__udivmoddi4+0xa2>
800038a: 40f3 lsrs r3, r6
800038c: 2200 movs r2, #0
800038e: e9c5 3200 strd r3, r2, [r5]
8000392: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000396: 428b cmp r3, r1
8000398: d905 bls.n 80003a6 <__udivmoddi4+0xb6>
800039a: b10d cbz r5, 80003a0 <__udivmoddi4+0xb0>
800039c: e9c5 0100 strd r0, r1, [r5]
80003a0: 2100 movs r1, #0
80003a2: 4608 mov r0, r1
80003a4: e7f5 b.n 8000392 <__udivmoddi4+0xa2>
80003a6: fab3 f183 clz r1, r3
80003aa: 2900 cmp r1, #0
80003ac: d146 bne.n 800043c <__udivmoddi4+0x14c>
80003ae: 4573 cmp r3, lr
80003b0: d302 bcc.n 80003b8 <__udivmoddi4+0xc8>
80003b2: 4282 cmp r2, r0
80003b4: f200 8105 bhi.w 80005c2 <__udivmoddi4+0x2d2>
80003b8: 1a84 subs r4, r0, r2
80003ba: eb6e 0203 sbc.w r2, lr, r3
80003be: 2001 movs r0, #1
80003c0: 4690 mov r8, r2
80003c2: 2d00 cmp r5, #0
80003c4: d0e5 beq.n 8000392 <__udivmoddi4+0xa2>
80003c6: e9c5 4800 strd r4, r8, [r5]
80003ca: e7e2 b.n 8000392 <__udivmoddi4+0xa2>
80003cc: 2a00 cmp r2, #0
80003ce: f000 8090 beq.w 80004f2 <__udivmoddi4+0x202>
80003d2: fab2 f682 clz r6, r2
80003d6: 2e00 cmp r6, #0
80003d8: f040 80a4 bne.w 8000524 <__udivmoddi4+0x234>
80003dc: 1a8a subs r2, r1, r2
80003de: 0c03 lsrs r3, r0, #16
80003e0: ea4f 4e17 mov.w lr, r7, lsr #16
80003e4: b280 uxth r0, r0
80003e6: b2bc uxth r4, r7
80003e8: 2101 movs r1, #1
80003ea: fbb2 fcfe udiv ip, r2, lr
80003ee: fb0e 221c mls r2, lr, ip, r2
80003f2: ea43 4302 orr.w r3, r3, r2, lsl #16
80003f6: fb04 f20c mul.w r2, r4, ip
80003fa: 429a cmp r2, r3
80003fc: d907 bls.n 800040e <__udivmoddi4+0x11e>
80003fe: 18fb adds r3, r7, r3
8000400: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
8000404: d202 bcs.n 800040c <__udivmoddi4+0x11c>
8000406: 429a cmp r2, r3
8000408: f200 80e0 bhi.w 80005cc <__udivmoddi4+0x2dc>
800040c: 46c4 mov ip, r8
800040e: 1a9b subs r3, r3, r2
8000410: fbb3 f2fe udiv r2, r3, lr
8000414: fb0e 3312 mls r3, lr, r2, r3
8000418: ea40 4303 orr.w r3, r0, r3, lsl #16
800041c: fb02 f404 mul.w r4, r2, r4
8000420: 429c cmp r4, r3
8000422: d907 bls.n 8000434 <__udivmoddi4+0x144>
8000424: 18fb adds r3, r7, r3
8000426: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
800042a: d202 bcs.n 8000432 <__udivmoddi4+0x142>
800042c: 429c cmp r4, r3
800042e: f200 80ca bhi.w 80005c6 <__udivmoddi4+0x2d6>
8000432: 4602 mov r2, r0
8000434: 1b1b subs r3, r3, r4
8000436: ea42 400c orr.w r0, r2, ip, lsl #16
800043a: e7a5 b.n 8000388 <__udivmoddi4+0x98>
800043c: f1c1 0620 rsb r6, r1, #32
8000440: 408b lsls r3, r1
8000442: fa22 f706 lsr.w r7, r2, r6
8000446: 431f orrs r7, r3
8000448: fa0e f401 lsl.w r4, lr, r1
800044c: fa20 f306 lsr.w r3, r0, r6
8000450: fa2e fe06 lsr.w lr, lr, r6
8000454: ea4f 4917 mov.w r9, r7, lsr #16
8000458: 4323 orrs r3, r4
800045a: fa00 f801 lsl.w r8, r0, r1
800045e: fa1f fc87 uxth.w ip, r7
8000462: fbbe f0f9 udiv r0, lr, r9
8000466: 0c1c lsrs r4, r3, #16
8000468: fb09 ee10 mls lr, r9, r0, lr
800046c: ea44 440e orr.w r4, r4, lr, lsl #16
8000470: fb00 fe0c mul.w lr, r0, ip
8000474: 45a6 cmp lr, r4
8000476: fa02 f201 lsl.w r2, r2, r1
800047a: d909 bls.n 8000490 <__udivmoddi4+0x1a0>
800047c: 193c adds r4, r7, r4
800047e: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
8000482: f080 809c bcs.w 80005be <__udivmoddi4+0x2ce>
8000486: 45a6 cmp lr, r4
8000488: f240 8099 bls.w 80005be <__udivmoddi4+0x2ce>
800048c: 3802 subs r0, #2
800048e: 443c add r4, r7
8000490: eba4 040e sub.w r4, r4, lr
8000494: fa1f fe83 uxth.w lr, r3
8000498: fbb4 f3f9 udiv r3, r4, r9
800049c: fb09 4413 mls r4, r9, r3, r4
80004a0: ea4e 4404 orr.w r4, lr, r4, lsl #16
80004a4: fb03 fc0c mul.w ip, r3, ip
80004a8: 45a4 cmp ip, r4
80004aa: d908 bls.n 80004be <__udivmoddi4+0x1ce>
80004ac: 193c adds r4, r7, r4
80004ae: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
80004b2: f080 8082 bcs.w 80005ba <__udivmoddi4+0x2ca>
80004b6: 45a4 cmp ip, r4
80004b8: d97f bls.n 80005ba <__udivmoddi4+0x2ca>
80004ba: 3b02 subs r3, #2
80004bc: 443c add r4, r7
80004be: ea43 4000 orr.w r0, r3, r0, lsl #16
80004c2: eba4 040c sub.w r4, r4, ip
80004c6: fba0 ec02 umull lr, ip, r0, r2
80004ca: 4564 cmp r4, ip
80004cc: 4673 mov r3, lr
80004ce: 46e1 mov r9, ip
80004d0: d362 bcc.n 8000598 <__udivmoddi4+0x2a8>
80004d2: d05f beq.n 8000594 <__udivmoddi4+0x2a4>
80004d4: b15d cbz r5, 80004ee <__udivmoddi4+0x1fe>
80004d6: ebb8 0203 subs.w r2, r8, r3
80004da: eb64 0409 sbc.w r4, r4, r9
80004de: fa04 f606 lsl.w r6, r4, r6
80004e2: fa22 f301 lsr.w r3, r2, r1
80004e6: 431e orrs r6, r3
80004e8: 40cc lsrs r4, r1
80004ea: e9c5 6400 strd r6, r4, [r5]
80004ee: 2100 movs r1, #0
80004f0: e74f b.n 8000392 <__udivmoddi4+0xa2>
80004f2: fbb1 fcf2 udiv ip, r1, r2
80004f6: 0c01 lsrs r1, r0, #16
80004f8: ea41 410e orr.w r1, r1, lr, lsl #16
80004fc: b280 uxth r0, r0
80004fe: ea40 4201 orr.w r2, r0, r1, lsl #16
8000502: 463b mov r3, r7
8000504: 4638 mov r0, r7
8000506: 463c mov r4, r7
8000508: 46b8 mov r8, r7
800050a: 46be mov lr, r7
800050c: 2620 movs r6, #32
800050e: fbb1 f1f7 udiv r1, r1, r7
8000512: eba2 0208 sub.w r2, r2, r8
8000516: ea41 410c orr.w r1, r1, ip, lsl #16
800051a: e766 b.n 80003ea <__udivmoddi4+0xfa>
800051c: 4601 mov r1, r0
800051e: e718 b.n 8000352 <__udivmoddi4+0x62>
8000520: 4610 mov r0, r2
8000522: e72c b.n 800037e <__udivmoddi4+0x8e>
8000524: f1c6 0220 rsb r2, r6, #32
8000528: fa2e f302 lsr.w r3, lr, r2
800052c: 40b7 lsls r7, r6
800052e: 40b1 lsls r1, r6
8000530: fa20 f202 lsr.w r2, r0, r2
8000534: ea4f 4e17 mov.w lr, r7, lsr #16
8000538: 430a orrs r2, r1
800053a: fbb3 f8fe udiv r8, r3, lr
800053e: b2bc uxth r4, r7
8000540: fb0e 3318 mls r3, lr, r8, r3
8000544: 0c11 lsrs r1, r2, #16
8000546: ea41 4103 orr.w r1, r1, r3, lsl #16
800054a: fb08 f904 mul.w r9, r8, r4
800054e: 40b0 lsls r0, r6
8000550: 4589 cmp r9, r1
8000552: ea4f 4310 mov.w r3, r0, lsr #16
8000556: b280 uxth r0, r0
8000558: d93e bls.n 80005d8 <__udivmoddi4+0x2e8>
800055a: 1879 adds r1, r7, r1
800055c: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
8000560: d201 bcs.n 8000566 <__udivmoddi4+0x276>
8000562: 4589 cmp r9, r1
8000564: d81f bhi.n 80005a6 <__udivmoddi4+0x2b6>
8000566: eba1 0109 sub.w r1, r1, r9
800056a: fbb1 f9fe udiv r9, r1, lr
800056e: fb09 f804 mul.w r8, r9, r4
8000572: fb0e 1119 mls r1, lr, r9, r1
8000576: b292 uxth r2, r2
8000578: ea42 4201 orr.w r2, r2, r1, lsl #16
800057c: 4542 cmp r2, r8
800057e: d229 bcs.n 80005d4 <__udivmoddi4+0x2e4>
8000580: 18ba adds r2, r7, r2
8000582: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
8000586: d2c4 bcs.n 8000512 <__udivmoddi4+0x222>
8000588: 4542 cmp r2, r8
800058a: d2c2 bcs.n 8000512 <__udivmoddi4+0x222>
800058c: f1a9 0102 sub.w r1, r9, #2
8000590: 443a add r2, r7
8000592: e7be b.n 8000512 <__udivmoddi4+0x222>
8000594: 45f0 cmp r8, lr
8000596: d29d bcs.n 80004d4 <__udivmoddi4+0x1e4>
8000598: ebbe 0302 subs.w r3, lr, r2
800059c: eb6c 0c07 sbc.w ip, ip, r7
80005a0: 3801 subs r0, #1
80005a2: 46e1 mov r9, ip
80005a4: e796 b.n 80004d4 <__udivmoddi4+0x1e4>
80005a6: eba7 0909 sub.w r9, r7, r9
80005aa: 4449 add r1, r9
80005ac: f1a8 0c02 sub.w ip, r8, #2
80005b0: fbb1 f9fe udiv r9, r1, lr
80005b4: fb09 f804 mul.w r8, r9, r4
80005b8: e7db b.n 8000572 <__udivmoddi4+0x282>
80005ba: 4673 mov r3, lr
80005bc: e77f b.n 80004be <__udivmoddi4+0x1ce>
80005be: 4650 mov r0, sl
80005c0: e766 b.n 8000490 <__udivmoddi4+0x1a0>
80005c2: 4608 mov r0, r1
80005c4: e6fd b.n 80003c2 <__udivmoddi4+0xd2>
80005c6: 443b add r3, r7
80005c8: 3a02 subs r2, #2
80005ca: e733 b.n 8000434 <__udivmoddi4+0x144>
80005cc: f1ac 0c02 sub.w ip, ip, #2
80005d0: 443b add r3, r7
80005d2: e71c b.n 800040e <__udivmoddi4+0x11e>
80005d4: 4649 mov r1, r9
80005d6: e79c b.n 8000512 <__udivmoddi4+0x222>
80005d8: eba1 0109 sub.w r1, r1, r9
80005dc: 46c4 mov ip, r8
80005de: fbb1 f9fe udiv r9, r1, lr
80005e2: fb09 f804 mul.w r8, r9, r4
80005e6: e7c4 b.n 8000572 <__udivmoddi4+0x282>
080005e8 <__aeabi_idiv0>:
80005e8: 4770 bx lr
80005ea: bf00 nop
080005ec <Display_WriteCommand>:
} LCD_CONTROLLER_TypeDef;
#define FMC_BANK2_BASE ((uint32_t)(0x60000000 | 0x04000000))
#define FMC_BANK2 ((LCD_CONTROLLER_TypeDef *) FMC_BANK2_BASE)
void Display_WriteCommand( uint8_t Reg) {
80005ec: b480 push {r7}
80005ee: b083 sub sp, #12
80005f0: af00 add r7, sp, #0
80005f2: 4603 mov r3, r0
80005f4: 71fb strb r3, [r7, #7]
FMC_BANK2->REG = Reg;
80005f6: f04f 43c8 mov.w r3, #1677721600 @ 0x64000000
80005fa: 79fa ldrb r2, [r7, #7]
80005fc: b292 uxth r2, r2
80005fe: 801a strh r2, [r3, #0]
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__STATIC_FORCEINLINE void __DSB(void)
{
__ASM volatile ("dsb 0xF":::"memory");
8000600: f3bf 8f4f dsb sy
}
8000604: bf00 nop
__DSB();
}
8000606: bf00 nop
8000608: 370c adds r7, #12
800060a: 46bd mov sp, r7
800060c: f85d 7b04 ldr.w r7, [sp], #4
8000610: 4770 bx lr
08000612 <Display_WriteData>:
void Display_WriteData( uint16_t Value ) {
8000612: b480 push {r7}
8000614: b083 sub sp, #12
8000616: af00 add r7, sp, #0
8000618: 4603 mov r3, r0
800061a: 80fb strh r3, [r7, #6]
FMC_BANK2->RAM = Value;
800061c: f04f 42c8 mov.w r2, #1677721600 @ 0x64000000
8000620: 88fb ldrh r3, [r7, #6]
8000622: 8053 strh r3, [r2, #2]
__ASM volatile ("dsb 0xF":::"memory");
8000624: f3bf 8f4f dsb sy
}
8000628: bf00 nop
__DSB();
}
800062a: bf00 nop
800062c: 370c adds r7, #12
800062e: 46bd mov sp, r7
8000630: f85d 7b04 ldr.w r7, [sp], #4
8000634: 4770 bx lr
08000636 <Display_ReadData>:
static uint16_t Display_ReadData(void) {
8000636: b480 push {r7}
8000638: af00 add r7, sp, #0
return FMC_BANK2->RAM;
800063a: f04f 43c8 mov.w r3, #1677721600 @ 0x64000000
800063e: 885b ldrh r3, [r3, #2]
8000640: b29b uxth r3, r3
}
8000642: 4618 mov r0, r3
8000644: 46bd mov sp, r7
8000646: f85d 7b04 ldr.w r7, [sp], #4
800064a: 4770 bx lr
0800064c <Display_ReadReg>:
uint8_t Display_ReadReg(uint8_t Command) {
800064c: b580 push {r7, lr}
800064e: b082 sub sp, #8
8000650: af00 add r7, sp, #0
8000652: 4603 mov r3, r0
8000654: 71fb strb r3, [r7, #7]
Display_WriteCommand(Command);
8000656: 79fb ldrb r3, [r7, #7]
8000658: 4618 mov r0, r3
800065a: f7ff ffc7 bl 80005ec <Display_WriteCommand>
Display_ReadData();
800065e: f7ff ffea bl 8000636 <Display_ReadData>
return (Display_ReadData());
8000662: f7ff ffe8 bl 8000636 <Display_ReadData>
8000666: 4603 mov r3, r0
8000668: b2db uxtb r3, r3
}
800066a: 4618 mov r0, r3
800066c: 3708 adds r7, #8
800066e: 46bd mov sp, r7
8000670: bd80 pop {r7, pc}
08000672 <Display_WriteCommandList>:
0x11, 0, // Sleep out
0x35, 1, 0x00, // Tearing Effect
0xff
};
static void Display_WriteCommandList(const uint8_t *addr) {
8000672: b580 push {r7, lr}
8000674: b084 sub sp, #16
8000676: af00 add r7, sp, #0
8000678: 6078 str r0, [r7, #4]
uint8_t NumArgs;
uint16_t Delay;
while(*addr != 0xff) {
800067a: e033 b.n 80006e4 <Display_WriteCommandList+0x72>
//printf("Cmd %x, ", *addr);
Display_WriteCommand(*addr++); // Command
800067c: 687b ldr r3, [r7, #4]
800067e: 1c5a adds r2, r3, #1
8000680: 607a str r2, [r7, #4]
8000682: 781b ldrb r3, [r3, #0]
8000684: 4618 mov r0, r3
8000686: f7ff ffb1 bl 80005ec <Display_WriteCommand>
NumArgs = *addr++; // Number of arguments
800068a: 687b ldr r3, [r7, #4]
800068c: 1c5a adds r2, r3, #1
800068e: 607a str r2, [r7, #4]
8000690: 781b ldrb r3, [r3, #0]
8000692: 73fb strb r3, [r7, #15]
Delay = NumArgs & 0x80; // Bit 7: Delay flag
8000694: 7bfb ldrb r3, [r7, #15]
8000696: b29b uxth r3, r3
8000698: f003 0380 and.w r3, r3, #128 @ 0x80
800069c: 81bb strh r3, [r7, #12]
NumArgs &= ~0x80;
800069e: 7bfb ldrb r3, [r7, #15]
80006a0: f003 037f and.w r3, r3, #127 @ 0x7f
80006a4: 73fb strb r3, [r7, #15]
//printf("Num: %d: ", NumArgs);
while(NumArgs--) {
80006a6: e006 b.n 80006b6 <Display_WriteCommandList+0x44>
//printf("%x ", *addr );
Display_WriteData(*addr++);
80006a8: 687b ldr r3, [r7, #4]
80006aa: 1c5a adds r2, r3, #1
80006ac: 607a str r2, [r7, #4]
80006ae: 781b ldrb r3, [r3, #0]
80006b0: 4618 mov r0, r3
80006b2: f7ff ffae bl 8000612 <Display_WriteData>
while(NumArgs--) {
80006b6: 7bfb ldrb r3, [r7, #15]
80006b8: 1e5a subs r2, r3, #1
80006ba: 73fa strb r2, [r7, #15]
80006bc: 2b00 cmp r3, #0
80006be: d1f3 bne.n 80006a8 <Display_WriteCommandList+0x36>
}
//printf("\n");
// Delay after command
if(Delay) { // If delay flag set
80006c0: 89bb ldrh r3, [r7, #12]
80006c2: 2b00 cmp r3, #0
80006c4: d00e beq.n 80006e4 <Display_WriteCommandList+0x72>
Delay = *addr++; // Delay time
80006c6: 687b ldr r3, [r7, #4]
80006c8: 1c5a adds r2, r3, #1
80006ca: 607a str r2, [r7, #4]
80006cc: 781b ldrb r3, [r3, #0]
80006ce: 81bb strh r3, [r7, #12]
if( Delay == 255) {
80006d0: 89bb ldrh r3, [r7, #12]
80006d2: 2bff cmp r3, #255 @ 0xff
80006d4: d102 bne.n 80006dc <Display_WriteCommandList+0x6a>
Delay = 500;
80006d6: f44f 73fa mov.w r3, #500 @ 0x1f4
80006da: 81bb strh r3, [r7, #12]
}
//printf("Delay: %d\n", Delay );
HAL_Delay(Delay);
80006dc: 89bb ldrh r3, [r7, #12]
80006de: 4618 mov r0, r3
80006e0: f001 f9e2 bl 8001aa8 <HAL_Delay>
while(*addr != 0xff) {
80006e4: 687b ldr r3, [r7, #4]
80006e6: 781b ldrb r3, [r3, #0]
80006e8: 2bff cmp r3, #255 @ 0xff
80006ea: d1c7 bne.n 800067c <Display_WriteCommandList+0xa>
}
}
}
80006ec: bf00 nop
80006ee: bf00 nop
80006f0: 3710 adds r7, #16
80006f2: 46bd mov sp, r7
80006f4: bd80 pop {r7, pc}
...
080006f8 <Display_InitFmc>:
static void Display_InitFmc( void ) {
80006f8: b580 push {r7, lr}
80006fa: b088 sub sp, #32
80006fc: af00 add r7, sp, #0
FMC_NORSRAM_TimingTypeDef sram_timing={0};
80006fe: 1d3b adds r3, r7, #4
8000700: 2200 movs r2, #0
8000702: 601a str r2, [r3, #0]
8000704: 605a str r2, [r3, #4]
8000706: 609a str r2, [r3, #8]
8000708: 60da str r2, [r3, #12]
800070a: 611a str r2, [r3, #16]
800070c: 615a str r2, [r3, #20]
800070e: 619a str r2, [r3, #24]
// PSRAM device configuration
// Timing configuration derived from system clock (up to 216Mhz) for 108Mhz as PSRAM clock frequency
sram_timing.AddressSetupTime = 9;
8000710: 2309 movs r3, #9
8000712: 607b str r3, [r7, #4]
sram_timing.AddressHoldTime = 2;
8000714: 2302 movs r3, #2
8000716: 60bb str r3, [r7, #8]
sram_timing.DataSetupTime = 6;
8000718: 2306 movs r3, #6
800071a: 60fb str r3, [r7, #12]
sram_timing.BusTurnAroundDuration = 1;
800071c: 2301 movs r3, #1
800071e: 613b str r3, [r7, #16]
sram_timing.CLKDivision = 2;
8000720: 2302 movs r3, #2
8000722: 617b str r3, [r7, #20]
sram_timing.DataLatency = 2;
8000724: 2302 movs r3, #2
8000726: 61bb str r3, [r7, #24]
sram_timing.AccessMode = FMC_ACCESS_MODE_A;
8000728: 2300 movs r3, #0
800072a: 61fb str r3, [r7, #28]
// Initialize the FMC controller for LCD (FMC_NORSRAM_BANK2)
HAL_SRAM_Init(&hsram2, &sram_timing, &sram_timing);
800072c: 1d3a adds r2, r7, #4
800072e: 1d3b adds r3, r7, #4
8000730: 4619 mov r1, r3
8000732: 4803 ldr r0, [pc, #12] @ (8000740 <Display_InitFmc+0x48>)
8000734: f002 fe40 bl 80033b8 <HAL_SRAM_Init>
}
8000738: bf00 nop
800073a: 3720 adds r7, #32
800073c: 46bd mov sp, r7
800073e: bd80 pop {r7, pc}
8000740: 20000160 .word 0x20000160
08000744 <Display_SetOrientation>:
static void Display_SetOrientation(uint32_t orientation) {
8000744: b580 push {r7, lr}
8000746: b084 sub sp, #16
8000748: af00 add r7, sp, #0
800074a: 6078 str r0, [r7, #4]
uint8_t NormalDisplayParam;
if( orientation == LCD_ORIENTATION_LANDSCAPE ) {
800074c: 687b ldr r3, [r7, #4]
800074e: 2b01 cmp r3, #1
8000750: d102 bne.n 8000758 <Display_SetOrientation+0x14>
NormalDisplayParam = 0x00;
8000752: 2300 movs r3, #0
8000754: 73fb strb r3, [r7, #15]
8000756: e025 b.n 80007a4 <Display_SetOrientation+0x60>
} else if( orientation == LCD_ORIENTATION_LANDSCAPE_ROT180 ) {
8000758: 687b ldr r3, [r7, #4]
800075a: 2b02 cmp r3, #2
800075c: d120 bne.n 80007a0 <Display_SetOrientation+0x5c>
// Vertical Scrolling Definition
Display_WriteCommand(0x33);
800075e: 2033 movs r0, #51 @ 0x33
8000760: f7ff ff44 bl 80005ec <Display_WriteCommand>
// TFA describes the Top Fixed Area
Display_WriteData(0x00);
8000764: 2000 movs r0, #0
8000766: f7ff ff54 bl 8000612 <Display_WriteData>
Display_WriteData(0x00);
800076a: 2000 movs r0, #0
800076c: f7ff ff51 bl 8000612 <Display_WriteData>
// VSA describes the height of the Vertical Scrolling Area
Display_WriteData(0x01);
8000770: 2001 movs r0, #1
8000772: f7ff ff4e bl 8000612 <Display_WriteData>
Display_WriteData(0xf0);
8000776: 20f0 movs r0, #240 @ 0xf0
8000778: f7ff ff4b bl 8000612 <Display_WriteData>
// BFA describes the Bottom Fixed Area
Display_WriteData(0x00);
800077c: 2000 movs r0, #0
800077e: f7ff ff48 bl 8000612 <Display_WriteData>
Display_WriteData(0x00);
8000782: 2000 movs r0, #0
8000784: f7ff ff45 bl 8000612 <Display_WriteData>
// Vertical Scroll Start Address of RAM:
// GRAM row nbr (320) - Display row nbr (240) = 80 = 0x50
Display_WriteCommand(0x37);
8000788: 2037 movs r0, #55 @ 0x37
800078a: f7ff ff2f bl 80005ec <Display_WriteCommand>
Display_WriteData(0x00);
800078e: 2000 movs r0, #0
8000790: f7ff ff3f bl 8000612 <Display_WriteData>
Display_WriteData(0x50);
8000794: 2050 movs r0, #80 @ 0x50
8000796: f7ff ff3c bl 8000612 <Display_WriteData>
NormalDisplayParam = 0xC0;
800079a: 23c0 movs r3, #192 @ 0xc0
800079c: 73fb strb r3, [r7, #15]
800079e: e001 b.n 80007a4 <Display_SetOrientation+0x60>
} else {
NormalDisplayParam = 0x60;
80007a0: 2360 movs r3, #96 @ 0x60
80007a2: 73fb strb r3, [r7, #15]
}
Display_WriteCommand(0x36);
80007a4: 2036 movs r0, #54 @ 0x36
80007a6: f7ff ff21 bl 80005ec <Display_WriteCommand>
Display_WriteData(NormalDisplayParam);
80007aa: 7bfb ldrb r3, [r7, #15]
80007ac: b29b uxth r3, r3
80007ae: 4618 mov r0, r3
80007b0: f7ff ff2f bl 8000612 <Display_WriteData>
}
80007b4: bf00 nop
80007b6: 3710 adds r7, #16
80007b8: 46bd mov sp, r7
80007ba: bd80 pop {r7, pc}
080007bc <Display_SetWindow_>:
Display_WriteData( y+1 );
Display_WriteCommand( 0x2c );
}
static void Display_SetWindow_( uint16_t x, uint16_t y, uint16_t Width, uint16_t Height ) {
80007bc: b590 push {r4, r7, lr}
80007be: b083 sub sp, #12
80007c0: af00 add r7, sp, #0
80007c2: 4604 mov r4, r0
80007c4: 4608 mov r0, r1
80007c6: 4611 mov r1, r2
80007c8: 461a mov r2, r3
80007ca: 4623 mov r3, r4
80007cc: 80fb strh r3, [r7, #6]
80007ce: 4603 mov r3, r0
80007d0: 80bb strh r3, [r7, #4]
80007d2: 460b mov r3, r1
80007d4: 807b strh r3, [r7, #2]
80007d6: 4613 mov r3, r2
80007d8: 803b strh r3, [r7, #0]
DISPLAY_LIMIT( x, 0, DISPLAY_WIDTH-1 );
80007da: 88fb ldrh r3, [r7, #6]
80007dc: 2bef cmp r3, #239 @ 0xef
80007de: d901 bls.n 80007e4 <Display_SetWindow_+0x28>
80007e0: 23ef movs r3, #239 @ 0xef
80007e2: 80fb strh r3, [r7, #6]
DISPLAY_LIMIT( y, 0, DISPLAY_HEIGHT-1 );
80007e4: 88bb ldrh r3, [r7, #4]
80007e6: 2bef cmp r3, #239 @ 0xef
80007e8: d901 bls.n 80007ee <Display_SetWindow_+0x32>
80007ea: 23ef movs r3, #239 @ 0xef
80007ec: 80bb strh r3, [r7, #4]
Display_WriteCommand( 0x2a );
80007ee: 202a movs r0, #42 @ 0x2a
80007f0: f7ff fefc bl 80005ec <Display_WriteCommand>
Display_WriteData( 0 );
80007f4: 2000 movs r0, #0
80007f6: f7ff ff0c bl 8000612 <Display_WriteData>
Display_WriteData( x );
80007fa: 88fb ldrh r3, [r7, #6]
80007fc: 4618 mov r0, r3
80007fe: f7ff ff08 bl 8000612 <Display_WriteData>
Display_WriteData( 0 );
8000802: 2000 movs r0, #0
8000804: f7ff ff05 bl 8000612 <Display_WriteData>
Display_WriteData( x+Width );
8000808: 88fa ldrh r2, [r7, #6]
800080a: 887b ldrh r3, [r7, #2]
800080c: 4413 add r3, r2
800080e: b29b uxth r3, r3
8000810: 4618 mov r0, r3
8000812: f7ff fefe bl 8000612 <Display_WriteData>
Display_WriteCommand( 0x2b );
8000816: 202b movs r0, #43 @ 0x2b
8000818: f7ff fee8 bl 80005ec <Display_WriteCommand>
Display_WriteData( 0 );
800081c: 2000 movs r0, #0
800081e: f7ff fef8 bl 8000612 <Display_WriteData>
Display_WriteData( y );
8000822: 88bb ldrh r3, [r7, #4]
8000824: 4618 mov r0, r3
8000826: f7ff fef4 bl 8000612 <Display_WriteData>
Display_WriteData( 0 );
800082a: 2000 movs r0, #0
800082c: f7ff fef1 bl 8000612 <Display_WriteData>
Display_WriteData( y+Height );
8000830: 88ba ldrh r2, [r7, #4]
8000832: 883b ldrh r3, [r7, #0]
8000834: 4413 add r3, r2
8000836: b29b uxth r3, r3
8000838: 4618 mov r0, r3
800083a: f7ff feea bl 8000612 <Display_WriteData>
Display_WriteCommand( 0x2c );
800083e: 202c movs r0, #44 @ 0x2c
8000840: f7ff fed4 bl 80005ec <Display_WriteCommand>
}
8000844: bf00 nop
8000846: 370c adds r7, #12
8000848: 46bd mov sp, r7
800084a: bd90 pop {r4, r7, pc}
0800084c <Display_DrawHLine_>:
static void Display_DrawHLine_( uint16_t x, uint16_t y, uint16_t Length, uint16_t Color ) {
800084c: b590 push {r4, r7, lr}
800084e: b085 sub sp, #20
8000850: af00 add r7, sp, #0
8000852: 4604 mov r4, r0
8000854: 4608 mov r0, r1
8000856: 4611 mov r1, r2
8000858: 461a mov r2, r3
800085a: 4623 mov r3, r4
800085c: 80fb strh r3, [r7, #6]
800085e: 4603 mov r3, r0
8000860: 80bb strh r3, [r7, #4]
8000862: 460b mov r3, r1
8000864: 807b strh r3, [r7, #2]
8000866: 4613 mov r3, r2
8000868: 803b strh r3, [r7, #0]
uint16_t counter = 0;
800086a: 2300 movs r3, #0
800086c: 81fb strh r3, [r7, #14]
Display_SetWindow_( x, y, DISPLAY_WIDTH-1, 0 );
800086e: 88b9 ldrh r1, [r7, #4]
8000870: 88f8 ldrh r0, [r7, #6]
8000872: 2300 movs r3, #0
8000874: 22ef movs r2, #239 @ 0xef
8000876: f7ff ffa1 bl 80007bc <Display_SetWindow_>
for(counter = 0; counter < Length; counter++) {
800087a: 2300 movs r3, #0
800087c: 81fb strh r3, [r7, #14]
800087e: e006 b.n 800088e <Display_DrawHLine_+0x42>
Display_WriteData( Color );
8000880: 883b ldrh r3, [r7, #0]
8000882: 4618 mov r0, r3
8000884: f7ff fec5 bl 8000612 <Display_WriteData>
for(counter = 0; counter < Length; counter++) {
8000888: 89fb ldrh r3, [r7, #14]
800088a: 3301 adds r3, #1
800088c: 81fb strh r3, [r7, #14]
800088e: 89fa ldrh r2, [r7, #14]
8000890: 887b ldrh r3, [r7, #2]
8000892: 429a cmp r2, r3
8000894: d3f4 bcc.n 8000880 <Display_DrawHLine_+0x34>
}
}
8000896: bf00 nop
8000898: bf00 nop
800089a: 3714 adds r7, #20
800089c: 46bd mov sp, r7
800089e: bd90 pop {r4, r7, pc}
080008a0 <Display_GetHeight>:
for(counter = 0; counter < Length; counter++) {
Display_WriteData( Color );
}
}
uint16_t Display_GetHeight( void ) {
80008a0: b480 push {r7}
80008a2: af00 add r7, sp, #0
return DISPLAY_HEIGHT;
80008a4: 23f0 movs r3, #240 @ 0xf0
}
80008a6: 4618 mov r0, r3
80008a8: 46bd mov sp, r7
80008aa: f85d 7b04 ldr.w r7, [sp], #4
80008ae: 4770 bx lr
080008b0 <Display_GetWidth>:
uint16_t Display_GetWidth( void ) {
80008b0: b480 push {r7}
80008b2: af00 add r7, sp, #0
return DISPLAY_WIDTH;
80008b4: 23f0 movs r3, #240 @ 0xf0
}
80008b6: 4618 mov r0, r3
80008b8: 46bd mov sp, r7
80008ba: f85d 7b04 ldr.w r7, [sp], #4
80008be: 4770 bx lr
080008c0 <Display_Clear_>:
x += xinc2; // Change the x as appropriate
y += yinc2; // Change the y as appropriate
}
}
static void Display_Clear_( uint16_t Color ) {
80008c0: b580 push {r7, lr}
80008c2: b084 sub sp, #16
80008c4: af00 add r7, sp, #0
80008c6: 4603 mov r3, r0
80008c8: 80fb strh r3, [r7, #6]
uint16_t y = 0;
80008ca: 2300 movs r3, #0
80008cc: 81fb strh r3, [r7, #14]
uint16_t Height = 0;
80008ce: 2300 movs r3, #0
80008d0: 81bb strh r3, [r7, #12]
uint16_t Width = Display_GetWidth();
80008d2: f7ff ffed bl 80008b0 <Display_GetWidth>
80008d6: 4603 mov r3, r0
80008d8: 817b strh r3, [r7, #10]
Height = Display_GetHeight();
80008da: f7ff ffe1 bl 80008a0 <Display_GetHeight>
80008de: 4603 mov r3, r0
80008e0: 81bb strh r3, [r7, #12]
for( y = 0; y < Height ; y ++ ) {
80008e2: 2300 movs r3, #0
80008e4: 81fb strh r3, [r7, #14]
80008e6: e008 b.n 80008fa <Display_Clear_+0x3a>
Display_DrawHLine_( 0, y, Width, Color );
80008e8: 88fb ldrh r3, [r7, #6]
80008ea: 897a ldrh r2, [r7, #10]
80008ec: 89f9 ldrh r1, [r7, #14]
80008ee: 2000 movs r0, #0
80008f0: f7ff ffac bl 800084c <Display_DrawHLine_>
for( y = 0; y < Height ; y ++ ) {
80008f4: 89fb ldrh r3, [r7, #14]
80008f6: 3301 adds r3, #1
80008f8: 81fb strh r3, [r7, #14]
80008fa: 89fa ldrh r2, [r7, #14]
80008fc: 89bb ldrh r3, [r7, #12]
80008fe: 429a cmp r2, r3
8000900: d3f2 bcc.n 80008e8 <Display_Clear_+0x28>
}
}
8000902: bf00 nop
8000904: bf00 nop
8000906: 3710 adds r7, #16
8000908: 46bd mov sp, r7
800090a: bd80 pop {r7, pc}
0800090c <Display_Init>:
Points[i].x += 100;
}
Display_FillPolygon( Points, 4, LCD_COLOR_LIGHTBLUE );
}
void Display_Init( void ) {
800090c: b580 push {r7, lr}
800090e: b082 sub sp, #8
8000910: af00 add r7, sp, #0
// Backlight control signal assertion:
HAL_GPIO_WritePin(GPIOH, GPIO_PIN_11, GPIO_PIN_SET);
8000912: 2201 movs r2, #1
8000914: f44f 6100 mov.w r1, #2048 @ 0x800
8000918: 481c ldr r0, [pc, #112] @ (800098c <Display_Init+0x80>)
800091a: f001 fb7f bl 800201c <HAL_GPIO_WritePin>
// Apply hardware reset according to procedure indicated in FRD154BP2901 documentation:
HAL_GPIO_WritePin(LCD_RST_GPIO_Port, LCD_RST_Pin, GPIO_PIN_RESET);
800091e: 2200 movs r2, #0
8000920: 2180 movs r1, #128 @ 0x80
8000922: 481a ldr r0, [pc, #104] @ (800098c <Display_Init+0x80>)
8000924: f001 fb7a bl 800201c <HAL_GPIO_WritePin>
HAL_Delay(5);
8000928: 2005 movs r0, #5
800092a: f001 f8bd bl 8001aa8 <HAL_Delay>
HAL_GPIO_WritePin(LCD_RST_GPIO_Port, LCD_RST_Pin, GPIO_PIN_SET);
800092e: 2201 movs r2, #1
8000930: 2180 movs r1, #128 @ 0x80
8000932: 4816 ldr r0, [pc, #88] @ (800098c <Display_Init+0x80>)
8000934: f001 fb72 bl 800201c <HAL_GPIO_WritePin>
HAL_Delay(10);
8000938: 200a movs r0, #10
800093a: f001 f8b5 bl 8001aa8 <HAL_Delay>
HAL_GPIO_WritePin(LCD_RST_GPIO_Port, LCD_RST_Pin, GPIO_PIN_RESET);
800093e: 2200 movs r2, #0
8000940: 2180 movs r1, #128 @ 0x80
8000942: 4812 ldr r0, [pc, #72] @ (800098c <Display_Init+0x80>)
8000944: f001 fb6a bl 800201c <HAL_GPIO_WritePin>
HAL_Delay(20);
8000948: 2014 movs r0, #20
800094a: f001 f8ad bl 8001aa8 <HAL_Delay>
HAL_GPIO_WritePin(LCD_RST_GPIO_Port, LCD_RST_Pin, GPIO_PIN_SET);
800094e: 2201 movs r2, #1
8000950: 2180 movs r1, #128 @ 0x80
8000952: 480e ldr r0, [pc, #56] @ (800098c <Display_Init+0x80>)
8000954: f001 fb62 bl 800201c <HAL_GPIO_WritePin>
HAL_Delay(10);
8000958: 200a movs r0, #10
800095a: f001 f8a5 bl 8001aa8 <HAL_Delay>
Display_InitFmc();
800095e: f7ff fecb bl 80006f8 <Display_InitFmc>
uint8_t DisplayId = Display_ReadReg(0x04);
8000962: 2004 movs r0, #4
8000964: f7ff fe72 bl 800064c <Display_ReadReg>
8000968: 4603 mov r3, r0
800096a: 71fb strb r3, [r7, #7]
if( DisplayId == 0x85 ) {
800096c: 79fb ldrb r3, [r7, #7]
800096e: 2b85 cmp r3, #133 @ 0x85
8000970: d108 bne.n 8000984 <Display_Init+0x78>
Display_WriteCommandList( InitCmd );
8000972: 4807 ldr r0, [pc, #28] @ (8000990 <Display_Init+0x84>)
8000974: f7ff fe7d bl 8000672 <Display_WriteCommandList>
Display_SetOrientation( LCD_ORIENTATION_LANDSCAPE_ROT180 );
8000978: 2002 movs r0, #2
800097a: f7ff fee3 bl 8000744 <Display_SetOrientation>
Display_Clear_( LCD_COLOR_BLACK ); // Use variant without select/deselect to ignore OS and Mutex here!
800097e: 2000 movs r0, #0
8000980: f7ff ff9e bl 80008c0 <Display_Clear_>
}
/* ToDo: Create Mutex */
}
8000984: bf00 nop
8000986: 3708 adds r7, #8
8000988: 46bd mov sp, r7
800098a: bd80 pop {r7, pc}
800098c: 40021c00 .word 0x40021c00
8000990: 08005498 .word 0x08005498
08000994 <_write>:
int _write( int file, char *ptr, int len );
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
int _write( int file, char *ptr, int len ){
8000994: b580 push {r7, lr}
8000996: b084 sub sp, #16
8000998: af00 add r7, sp, #0
800099a: 60f8 str r0, [r7, #12]
800099c: 60b9 str r1, [r7, #8]
800099e: 607a str r2, [r7, #4]
HAL_UART_Transmit(&huart6, (uint8_t*)ptr, len, 1000);
80009a0: 687b ldr r3, [r7, #4]
80009a2: b29a uxth r2, r3
80009a4: f44f 737a mov.w r3, #1000 @ 0x3e8
80009a8: 68b9 ldr r1, [r7, #8]
80009aa: 4804 ldr r0, [pc, #16] @ (80009bc <_write+0x28>)
80009ac: f003 f868 bl 8003a80 <HAL_UART_Transmit>
return len;
80009b0: 687b ldr r3, [r7, #4]
}
80009b2: 4618 mov r0, r3
80009b4: 3710 adds r7, #16
80009b6: 46bd mov sp, r7
80009b8: bd80 pop {r7, pc}
80009ba: bf00 nop
80009bc: 200000d8 .word 0x200000d8
080009c0 <time_msPassedSince>:
// get time in ms passed since a timestamp
uint32_t time_msPassedSince(uint32_t timestampOld)
{
80009c0: b580 push {r7, lr}
80009c2: b082 sub sp, #8
80009c4: af00 add r7, sp, #0
80009c6: 6078 str r0, [r7, #4]
return (uint32_t)(HAL_GetTick() - timestampOld);
80009c8: f001 f862 bl 8001a90 <HAL_GetTick>
80009cc: 4602 mov r2, r0
80009ce: 687b ldr r3, [r7, #4]
80009d0: 1ad3 subs r3, r2, r3
}
80009d2: 4618 mov r0, r3
80009d4: 3708 adds r7, #8
80009d6: 46bd mov sp, r7
80009d8: bd80 pop {r7, pc}
...
080009dc <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80009dc: b580 push {r7, lr}
80009de: b086 sub sp, #24
80009e0: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80009e2: f001 f834 bl 8001a4e <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80009e6: f000 f867 bl 8000ab8 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80009ea: f000 f9a7 bl 8000d3c <MX_GPIO_Init>
MX_USART6_UART_Init();
80009ee: f000 f913 bl 8000c18 <MX_USART6_UART_Init>
MX_FMC_Init();
80009f2: f000 f941 bl 8000c78 <MX_FMC_Init>
MX_I2C3_Init();
80009f6: f000 f8cf bl 8000b98 <MX_I2C3_Init>
/* USER CODE BEGIN 2 */
Display_Init();
80009fa: f7ff ff87 bl 800090c <Display_Init>
// local variables
uint32_t timestamp_lastBlinked = HAL_GetTick();
80009fe: f001 f847 bl 8001a90 <HAL_GetTick>
8000a02: 6178 str r0, [r7, #20]
uint32_t timestamp_lastButtonPolled = timestamp_lastBlinked;
8000a04: 697b ldr r3, [r7, #20]
8000a06: 613b str r3, [r7, #16]
uint32_t timestamp_lastHelloPrinted = timestamp_lastBlinked;
8000a08: 697b ldr r3, [r7, #20]
8000a0a: 60fb str r3, [r7, #12]
uint8_t printCount = 0;
8000a0c: 2300 movs r3, #0
8000a0e: 72fb strb r3, [r7, #11]
uint8_t DataRx[4];
//...
uint8_t Eventflag;
uint16_t xTouch, yTouch;
Eventflag = (uint8_t)(DataRx[0] >> 4);
8000a10: 783b ldrb r3, [r7, #0]
8000a12: 091b lsrs r3, r3, #4
8000a14: 72bb strb r3, [r7, #10]
yTouch = (uint16_t)((DataRx[0] & 0b00001111) << 8) | (uint16_t)DataRx[1];
8000a16: 783b ldrb r3, [r7, #0]
8000a18: b21b sxth r3, r3
8000a1a: 021b lsls r3, r3, #8
8000a1c: b21b sxth r3, r3
8000a1e: f403 6370 and.w r3, r3, #3840 @ 0xf00
8000a22: b21a sxth r2, r3
8000a24: 787b ldrb r3, [r7, #1]
8000a26: b21b sxth r3, r3
8000a28: 4313 orrs r3, r2
8000a2a: b21b sxth r3, r3
8000a2c: 813b strh r3, [r7, #8]
xTouch = (uint16_t)((DataRx[2] & 0b00001111) << 8) | (uint16_t)DataRx[3];
8000a2e: 78bb ldrb r3, [r7, #2]
8000a30: b21b sxth r3, r3
8000a32: 021b lsls r3, r3, #8
8000a34: b21b sxth r3, r3
8000a36: f403 6370 and.w r3, r3, #3840 @ 0xf00
8000a3a: b21a sxth r2, r3
8000a3c: 78fb ldrb r3, [r7, #3]
8000a3e: b21b sxth r3, r3
8000a40: 4313 orrs r3, r2
8000a42: b21b sxth r3, r3
8000a44: 80fb strh r3, [r7, #6]
// blink blue led (toggle state every 500ms)
if (time_msPassedSince(timestamp_lastBlinked) >= 500) {
8000a46: 6978 ldr r0, [r7, #20]
8000a48: f7ff ffba bl 80009c0 <time_msPassedSince>
8000a4c: 4603 mov r3, r0
8000a4e: f5b3 7ffa cmp.w r3, #500 @ 0x1f4
8000a52: d306 bcc.n 8000a62 <main+0x86>
//HAL_GPIO_TogglePin(LED_BLUE_GPIO_PORT, LED_BLUE_GPIO_PIN);
HAL_GPIO_TogglePin(LED_BLUE_GPIO_PORT, LED_BLUE_GPIO_PIN);
8000a54: 2120 movs r1, #32
8000a56: 4816 ldr r0, [pc, #88] @ (8000ab0 <main+0xd4>)
8000a58: f001 faf9 bl 800204e <HAL_GPIO_TogglePin>
//printf("toggle blue led\n\r");
timestamp_lastBlinked = HAL_GetTick();
8000a5c: f001 f818 bl 8001a90 <HAL_GetTick>
8000a60: 6178 str r0, [r7, #20]
}
// poll button every 25ms and set red-led accordingly
if (time_msPassedSince(timestamp_lastButtonPolled) >= 25) {
8000a62: 6938 ldr r0, [r7, #16]
8000a64: f7ff ffac bl 80009c0 <time_msPassedSince>
8000a68: 4603 mov r3, r0
8000a6a: 2b18 cmp r3, #24
8000a6c: d90e bls.n 8000a8c <main+0xb0>
GPIO_PinState buttonState = HAL_GPIO_ReadPin(BUTTON_GPIO_PORT, BUTTON_GPIO_PIN);
8000a6e: 2101 movs r1, #1
8000a70: 480f ldr r0, [pc, #60] @ (8000ab0 <main+0xd4>)
8000a72: f001 fabb bl 8001fec <HAL_GPIO_ReadPin>
8000a76: 4603 mov r3, r0
8000a78: 717b strb r3, [r7, #5]
//printf("buttonState = %d\n\r", buttonState);
HAL_GPIO_WritePin(LED_RED_GPIO_PORT, LED_RED_GPIO_PIN, buttonState);
8000a7a: 797b ldrb r3, [r7, #5]
8000a7c: 461a mov r2, r3
8000a7e: 2180 movs r1, #128 @ 0x80
8000a80: 480b ldr r0, [pc, #44] @ (8000ab0 <main+0xd4>)
8000a82: f001 facb bl 800201c <HAL_GPIO_WritePin>
timestamp_lastButtonPolled = HAL_GetTick();
8000a86: f001 f803 bl 8001a90 <HAL_GetTick>
8000a8a: 6138 str r0, [r7, #16]
}
// print "Hallo Welt" via UART every 1000ms
if (time_msPassedSince(timestamp_lastHelloPrinted) >= 1000) {
8000a8c: 68f8 ldr r0, [r7, #12]
8000a8e: f7ff ff97 bl 80009c0 <time_msPassedSince>
8000a92: 4603 mov r3, r0
8000a94: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
8000a98: d3ba bcc.n 8000a10 <main+0x34>
printf("Hallo Welt %d\n\r", printCount++);
8000a9a: 7afb ldrb r3, [r7, #11]
8000a9c: 1c5a adds r2, r3, #1
8000a9e: 72fa strb r2, [r7, #11]
8000aa0: 4619 mov r1, r3
8000aa2: 4804 ldr r0, [pc, #16] @ (8000ab4 <main+0xd8>)
8000aa4: f003 fe78 bl 8004798 <iprintf>
timestamp_lastHelloPrinted = HAL_GetTick();
8000aa8: f000 fff2 bl 8001a90 <HAL_GetTick>
8000aac: 60f8 str r0, [r7, #12]
{
8000aae: e7af b.n 8000a10 <main+0x34>
8000ab0: 40020000 .word 0x40020000
8000ab4: 08005488 .word 0x08005488
08000ab8 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000ab8: b580 push {r7, lr}
8000aba: b094 sub sp, #80 @ 0x50
8000abc: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000abe: f107 0320 add.w r3, r7, #32
8000ac2: 2230 movs r2, #48 @ 0x30
8000ac4: 2100 movs r1, #0
8000ac6: 4618 mov r0, r3
8000ac8: f003 febb bl 8004842 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000acc: f107 030c add.w r3, r7, #12
8000ad0: 2200 movs r2, #0
8000ad2: 601a str r2, [r3, #0]
8000ad4: 605a str r2, [r3, #4]
8000ad6: 609a str r2, [r3, #8]
8000ad8: 60da str r2, [r3, #12]
8000ada: 611a str r2, [r3, #16]
/** Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess();
8000adc: f001 fc06 bl 80022ec <HAL_PWR_EnableBkUpAccess>
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
8000ae0: 4b2b ldr r3, [pc, #172] @ (8000b90 <SystemClock_Config+0xd8>)
8000ae2: 6c1b ldr r3, [r3, #64] @ 0x40
8000ae4: 4a2a ldr r2, [pc, #168] @ (8000b90 <SystemClock_Config+0xd8>)
8000ae6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000aea: 6413 str r3, [r2, #64] @ 0x40
8000aec: 4b28 ldr r3, [pc, #160] @ (8000b90 <SystemClock_Config+0xd8>)
8000aee: 6c1b ldr r3, [r3, #64] @ 0x40
8000af0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000af4: 60bb str r3, [r7, #8]
8000af6: 68bb ldr r3, [r7, #8]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8000af8: 4b26 ldr r3, [pc, #152] @ (8000b94 <SystemClock_Config+0xdc>)
8000afa: 681b ldr r3, [r3, #0]
8000afc: 4a25 ldr r2, [pc, #148] @ (8000b94 <SystemClock_Config+0xdc>)
8000afe: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8000b02: 6013 str r3, [r2, #0]
8000b04: 4b23 ldr r3, [pc, #140] @ (8000b94 <SystemClock_Config+0xdc>)
8000b06: 681b ldr r3, [r3, #0]
8000b08: f403 4340 and.w r3, r3, #49152 @ 0xc000
8000b0c: 607b str r3, [r7, #4]
8000b0e: 687b ldr r3, [r7, #4]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8000b10: 2301 movs r3, #1
8000b12: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
8000b14: f44f 3380 mov.w r3, #65536 @ 0x10000
8000b18: 627b str r3, [r7, #36] @ 0x24
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000b1a: 2302 movs r3, #2
8000b1c: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
8000b1e: f44f 0380 mov.w r3, #4194304 @ 0x400000
8000b22: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.PLL.PLLM = 25;
8000b24: 2319 movs r3, #25
8000b26: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.PLL.PLLN = 432;
8000b28: f44f 73d8 mov.w r3, #432 @ 0x1b0
8000b2c: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8000b2e: 2302 movs r3, #2
8000b30: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLQ = 9;
8000b32: 2309 movs r3, #9
8000b34: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000b36: f107 0320 add.w r3, r7, #32
8000b3a: 4618 mov r0, r3
8000b3c: f001 fc36 bl 80023ac <HAL_RCC_OscConfig>
8000b40: 4603 mov r3, r0
8000b42: 2b00 cmp r3, #0
8000b44: d001 beq.n 8000b4a <SystemClock_Config+0x92>
{
Error_Handler();
8000b46: f000 fc75 bl 8001434 <Error_Handler>
}
/** Activate the Over-Drive mode
*/
if (HAL_PWREx_EnableOverDrive() != HAL_OK)
8000b4a: f001 fbdf bl 800230c <HAL_PWREx_EnableOverDrive>
8000b4e: 4603 mov r3, r0
8000b50: 2b00 cmp r3, #0
8000b52: d001 beq.n 8000b58 <SystemClock_Config+0xa0>
{
Error_Handler();
8000b54: f000 fc6e bl 8001434 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000b58: 230f movs r3, #15
8000b5a: 60fb str r3, [r7, #12]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000b5c: 2302 movs r3, #2
8000b5e: 613b str r3, [r7, #16]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000b60: 2300 movs r3, #0
8000b62: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
8000b64: f44f 53a0 mov.w r3, #5120 @ 0x1400
8000b68: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
8000b6a: f44f 5380 mov.w r3, #4096 @ 0x1000
8000b6e: 61fb str r3, [r7, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
8000b70: f107 030c add.w r3, r7, #12
8000b74: 2107 movs r1, #7
8000b76: 4618 mov r0, r3
8000b78: f001 febc bl 80028f4 <HAL_RCC_ClockConfig>
8000b7c: 4603 mov r3, r0
8000b7e: 2b00 cmp r3, #0
8000b80: d001 beq.n 8000b86 <SystemClock_Config+0xce>
{
Error_Handler();
8000b82: f000 fc57 bl 8001434 <Error_Handler>
}
}
8000b86: bf00 nop
8000b88: 3750 adds r7, #80 @ 0x50
8000b8a: 46bd mov sp, r7
8000b8c: bd80 pop {r7, pc}
8000b8e: bf00 nop
8000b90: 40023800 .word 0x40023800
8000b94: 40007000 .word 0x40007000
08000b98 <MX_I2C3_Init>:
* @brief I2C3 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C3_Init(void)
{
8000b98: b580 push {r7, lr}
8000b9a: af00 add r7, sp, #0
/* USER CODE END I2C3_Init 0 */
/* USER CODE BEGIN I2C3_Init 1 */
/* USER CODE END I2C3_Init 1 */
hi2c3.Instance = I2C3;
8000b9c: 4b1b ldr r3, [pc, #108] @ (8000c0c <MX_I2C3_Init+0x74>)
8000b9e: 4a1c ldr r2, [pc, #112] @ (8000c10 <MX_I2C3_Init+0x78>)
8000ba0: 601a str r2, [r3, #0]
hi2c3.Init.Timing = 0x6000030D;
8000ba2: 4b1a ldr r3, [pc, #104] @ (8000c0c <MX_I2C3_Init+0x74>)
8000ba4: 4a1b ldr r2, [pc, #108] @ (8000c14 <MX_I2C3_Init+0x7c>)
8000ba6: 605a str r2, [r3, #4]
hi2c3.Init.OwnAddress1 = 0;
8000ba8: 4b18 ldr r3, [pc, #96] @ (8000c0c <MX_I2C3_Init+0x74>)
8000baa: 2200 movs r2, #0
8000bac: 609a str r2, [r3, #8]
hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
8000bae: 4b17 ldr r3, [pc, #92] @ (8000c0c <MX_I2C3_Init+0x74>)
8000bb0: 2201 movs r2, #1
8000bb2: 60da str r2, [r3, #12]
hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
8000bb4: 4b15 ldr r3, [pc, #84] @ (8000c0c <MX_I2C3_Init+0x74>)
8000bb6: 2200 movs r2, #0
8000bb8: 611a str r2, [r3, #16]
hi2c3.Init.OwnAddress2 = 0;
8000bba: 4b14 ldr r3, [pc, #80] @ (8000c0c <MX_I2C3_Init+0x74>)
8000bbc: 2200 movs r2, #0
8000bbe: 615a str r2, [r3, #20]
hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
8000bc0: 4b12 ldr r3, [pc, #72] @ (8000c0c <MX_I2C3_Init+0x74>)
8000bc2: 2200 movs r2, #0
8000bc4: 619a str r2, [r3, #24]
hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8000bc6: 4b11 ldr r3, [pc, #68] @ (8000c0c <MX_I2C3_Init+0x74>)
8000bc8: 2200 movs r2, #0
8000bca: 61da str r2, [r3, #28]
hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
8000bcc: 4b0f ldr r3, [pc, #60] @ (8000c0c <MX_I2C3_Init+0x74>)
8000bce: 2200 movs r2, #0
8000bd0: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c3) != HAL_OK)
8000bd2: 480e ldr r0, [pc, #56] @ (8000c0c <MX_I2C3_Init+0x74>)
8000bd4: f001 fa56 bl 8002084 <HAL_I2C_Init>
8000bd8: 4603 mov r3, r0
8000bda: 2b00 cmp r3, #0
8000bdc: d001 beq.n 8000be2 <MX_I2C3_Init+0x4a>
{
Error_Handler();
8000bde: f000 fc29 bl 8001434 <Error_Handler>
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
8000be2: 2100 movs r1, #0
8000be4: 4809 ldr r0, [pc, #36] @ (8000c0c <MX_I2C3_Init+0x74>)
8000be6: f001 fae9 bl 80021bc <HAL_I2CEx_ConfigAnalogFilter>
8000bea: 4603 mov r3, r0
8000bec: 2b00 cmp r3, #0
8000bee: d001 beq.n 8000bf4 <MX_I2C3_Init+0x5c>
{
Error_Handler();
8000bf0: f000 fc20 bl 8001434 <Error_Handler>
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK)
8000bf4: 2100 movs r1, #0
8000bf6: 4805 ldr r0, [pc, #20] @ (8000c0c <MX_I2C3_Init+0x74>)
8000bf8: f001 fb2b bl 8002252 <HAL_I2CEx_ConfigDigitalFilter>
8000bfc: 4603 mov r3, r0
8000bfe: 2b00 cmp r3, #0
8000c00: d001 beq.n 8000c06 <MX_I2C3_Init+0x6e>
{
Error_Handler();
8000c02: f000 fc17 bl 8001434 <Error_Handler>
}
/* USER CODE BEGIN I2C3_Init 2 */
/* USER CODE END I2C3_Init 2 */
}
8000c06: bf00 nop
8000c08: bd80 pop {r7, pc}
8000c0a: bf00 nop
8000c0c: 20000084 .word 0x20000084
8000c10: 40005c00 .word 0x40005c00
8000c14: 6000030d .word 0x6000030d
08000c18 <MX_USART6_UART_Init>:
* @brief USART6 Initialization Function
* @param None
* @retval None
*/
static void MX_USART6_UART_Init(void)
{
8000c18: b580 push {r7, lr}
8000c1a: af00 add r7, sp, #0
/* USER CODE END USART6_Init 0 */
/* USER CODE BEGIN USART6_Init 1 */
/* USER CODE END USART6_Init 1 */
huart6.Instance = USART6;
8000c1c: 4b14 ldr r3, [pc, #80] @ (8000c70 <MX_USART6_UART_Init+0x58>)
8000c1e: 4a15 ldr r2, [pc, #84] @ (8000c74 <MX_USART6_UART_Init+0x5c>)
8000c20: 601a str r2, [r3, #0]
huart6.Init.BaudRate = 115200;
8000c22: 4b13 ldr r3, [pc, #76] @ (8000c70 <MX_USART6_UART_Init+0x58>)
8000c24: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8000c28: 605a str r2, [r3, #4]
huart6.Init.WordLength = UART_WORDLENGTH_8B;
8000c2a: 4b11 ldr r3, [pc, #68] @ (8000c70 <MX_USART6_UART_Init+0x58>)
8000c2c: 2200 movs r2, #0
8000c2e: 609a str r2, [r3, #8]
huart6.Init.StopBits = UART_STOPBITS_1;
8000c30: 4b0f ldr r3, [pc, #60] @ (8000c70 <MX_USART6_UART_Init+0x58>)
8000c32: 2200 movs r2, #0
8000c34: 60da str r2, [r3, #12]
huart6.Init.Parity = UART_PARITY_NONE;
8000c36: 4b0e ldr r3, [pc, #56] @ (8000c70 <MX_USART6_UART_Init+0x58>)
8000c38: 2200 movs r2, #0
8000c3a: 611a str r2, [r3, #16]
huart6.Init.Mode = UART_MODE_TX_RX;
8000c3c: 4b0c ldr r3, [pc, #48] @ (8000c70 <MX_USART6_UART_Init+0x58>)
8000c3e: 220c movs r2, #12
8000c40: 615a str r2, [r3, #20]
huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000c42: 4b0b ldr r3, [pc, #44] @ (8000c70 <MX_USART6_UART_Init+0x58>)
8000c44: 2200 movs r2, #0
8000c46: 619a str r2, [r3, #24]
huart6.Init.OverSampling = UART_OVERSAMPLING_16;
8000c48: 4b09 ldr r3, [pc, #36] @ (8000c70 <MX_USART6_UART_Init+0x58>)
8000c4a: 2200 movs r2, #0
8000c4c: 61da str r2, [r3, #28]
huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
8000c4e: 4b08 ldr r3, [pc, #32] @ (8000c70 <MX_USART6_UART_Init+0x58>)
8000c50: 2200 movs r2, #0
8000c52: 621a str r2, [r3, #32]
huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8000c54: 4b06 ldr r3, [pc, #24] @ (8000c70 <MX_USART6_UART_Init+0x58>)
8000c56: 2200 movs r2, #0
8000c58: 625a str r2, [r3, #36] @ 0x24
if (HAL_UART_Init(&huart6) != HAL_OK)
8000c5a: 4805 ldr r0, [pc, #20] @ (8000c70 <MX_USART6_UART_Init+0x58>)
8000c5c: f002 fec2 bl 80039e4 <HAL_UART_Init>
8000c60: 4603 mov r3, r0
8000c62: 2b00 cmp r3, #0
8000c64: d001 beq.n 8000c6a <MX_USART6_UART_Init+0x52>
{
Error_Handler();
8000c66: f000 fbe5 bl 8001434 <Error_Handler>
}
/* USER CODE BEGIN USART6_Init 2 */
/* USER CODE END USART6_Init 2 */
}
8000c6a: bf00 nop
8000c6c: bd80 pop {r7, pc}
8000c6e: bf00 nop
8000c70: 200000d8 .word 0x200000d8
8000c74: 40011400 .word 0x40011400
08000c78 <MX_FMC_Init>:
/* FMC initialization function */
static void MX_FMC_Init(void)
{
8000c78: b580 push {r7, lr}
8000c7a: b088 sub sp, #32
8000c7c: af00 add r7, sp, #0
/* USER CODE BEGIN FMC_Init 0 */
/* USER CODE END FMC_Init 0 */
FMC_NORSRAM_TimingTypeDef Timing = {0};
8000c7e: 1d3b adds r3, r7, #4
8000c80: 2200 movs r2, #0
8000c82: 601a str r2, [r3, #0]
8000c84: 605a str r2, [r3, #4]
8000c86: 609a str r2, [r3, #8]
8000c88: 60da str r2, [r3, #12]
8000c8a: 611a str r2, [r3, #16]
8000c8c: 615a str r2, [r3, #20]
8000c8e: 619a str r2, [r3, #24]
/* USER CODE END FMC_Init 1 */
/** Perform the SRAM2 memory initialization sequence
*/
hsram2.Instance = FMC_NORSRAM_DEVICE;
8000c90: 4b28 ldr r3, [pc, #160] @ (8000d34 <MX_FMC_Init+0xbc>)
8000c92: f04f 4220 mov.w r2, #2684354560 @ 0xa0000000
8000c96: 601a str r2, [r3, #0]
hsram2.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
8000c98: 4b26 ldr r3, [pc, #152] @ (8000d34 <MX_FMC_Init+0xbc>)
8000c9a: 4a27 ldr r2, [pc, #156] @ (8000d38 <MX_FMC_Init+0xc0>)
8000c9c: 605a str r2, [r3, #4]
/* hsram2.Init */
hsram2.Init.NSBank = FMC_NORSRAM_BANK2;
8000c9e: 4b25 ldr r3, [pc, #148] @ (8000d34 <MX_FMC_Init+0xbc>)
8000ca0: 2202 movs r2, #2
8000ca2: 609a str r2, [r3, #8]
hsram2.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
8000ca4: 4b23 ldr r3, [pc, #140] @ (8000d34 <MX_FMC_Init+0xbc>)
8000ca6: 2200 movs r2, #0
8000ca8: 60da str r2, [r3, #12]
hsram2.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
8000caa: 4b22 ldr r3, [pc, #136] @ (8000d34 <MX_FMC_Init+0xbc>)
8000cac: 2200 movs r2, #0
8000cae: 611a str r2, [r3, #16]
hsram2.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
8000cb0: 4b20 ldr r3, [pc, #128] @ (8000d34 <MX_FMC_Init+0xbc>)
8000cb2: 2210 movs r2, #16
8000cb4: 615a str r2, [r3, #20]
hsram2.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
8000cb6: 4b1f ldr r3, [pc, #124] @ (8000d34 <MX_FMC_Init+0xbc>)
8000cb8: 2200 movs r2, #0
8000cba: 619a str r2, [r3, #24]
hsram2.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
8000cbc: 4b1d ldr r3, [pc, #116] @ (8000d34 <MX_FMC_Init+0xbc>)
8000cbe: 2200 movs r2, #0
8000cc0: 61da str r2, [r3, #28]
hsram2.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
8000cc2: 4b1c ldr r3, [pc, #112] @ (8000d34 <MX_FMC_Init+0xbc>)
8000cc4: 2200 movs r2, #0
8000cc6: 621a str r2, [r3, #32]
hsram2.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
8000cc8: 4b1a ldr r3, [pc, #104] @ (8000d34 <MX_FMC_Init+0xbc>)
8000cca: f44f 5280 mov.w r2, #4096 @ 0x1000
8000cce: 625a str r2, [r3, #36] @ 0x24
hsram2.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
8000cd0: 4b18 ldr r3, [pc, #96] @ (8000d34 <MX_FMC_Init+0xbc>)
8000cd2: 2200 movs r2, #0
8000cd4: 629a str r2, [r3, #40] @ 0x28
hsram2.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
8000cd6: 4b17 ldr r3, [pc, #92] @ (8000d34 <MX_FMC_Init+0xbc>)
8000cd8: 2200 movs r2, #0
8000cda: 62da str r2, [r3, #44] @ 0x2c
hsram2.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
8000cdc: 4b15 ldr r3, [pc, #84] @ (8000d34 <MX_FMC_Init+0xbc>)
8000cde: 2200 movs r2, #0
8000ce0: 631a str r2, [r3, #48] @ 0x30
hsram2.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
8000ce2: 4b14 ldr r3, [pc, #80] @ (8000d34 <MX_FMC_Init+0xbc>)
8000ce4: 2200 movs r2, #0
8000ce6: 635a str r2, [r3, #52] @ 0x34
hsram2.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
8000ce8: 4b12 ldr r3, [pc, #72] @ (8000d34 <MX_FMC_Init+0xbc>)
8000cea: 2200 movs r2, #0
8000cec: 639a str r2, [r3, #56] @ 0x38
hsram2.Init.WriteFifo = FMC_WRITE_FIFO_ENABLE;
8000cee: 4b11 ldr r3, [pc, #68] @ (8000d34 <MX_FMC_Init+0xbc>)
8000cf0: 2200 movs r2, #0
8000cf2: 63da str r2, [r3, #60] @ 0x3c
hsram2.Init.PageSize = FMC_PAGE_SIZE_NONE;
8000cf4: 4b0f ldr r3, [pc, #60] @ (8000d34 <MX_FMC_Init+0xbc>)
8000cf6: 2200 movs r2, #0
8000cf8: 641a str r2, [r3, #64] @ 0x40
/* Timing */
Timing.AddressSetupTime = 15;
8000cfa: 230f movs r3, #15
8000cfc: 607b str r3, [r7, #4]
Timing.AddressHoldTime = 15;
8000cfe: 230f movs r3, #15
8000d00: 60bb str r3, [r7, #8]
Timing.DataSetupTime = 255;
8000d02: 23ff movs r3, #255 @ 0xff
8000d04: 60fb str r3, [r7, #12]
Timing.BusTurnAroundDuration = 15;
8000d06: 230f movs r3, #15
8000d08: 613b str r3, [r7, #16]
Timing.CLKDivision = 16;
8000d0a: 2310 movs r3, #16
8000d0c: 617b str r3, [r7, #20]
Timing.DataLatency = 17;
8000d0e: 2311 movs r3, #17
8000d10: 61bb str r3, [r7, #24]
Timing.AccessMode = FMC_ACCESS_MODE_A;
8000d12: 2300 movs r3, #0
8000d14: 61fb str r3, [r7, #28]
/* ExtTiming */
if (HAL_SRAM_Init(&hsram2, &Timing, NULL) != HAL_OK)
8000d16: 1d3b adds r3, r7, #4
8000d18: 2200 movs r2, #0
8000d1a: 4619 mov r1, r3
8000d1c: 4805 ldr r0, [pc, #20] @ (8000d34 <MX_FMC_Init+0xbc>)
8000d1e: f002 fb4b bl 80033b8 <HAL_SRAM_Init>
8000d22: 4603 mov r3, r0
8000d24: 2b00 cmp r3, #0
8000d26: d001 beq.n 8000d2c <MX_FMC_Init+0xb4>
{
Error_Handler( );
8000d28: f000 fb84 bl 8001434 <Error_Handler>
}
/* USER CODE BEGIN FMC_Init 2 */
/* USER CODE END FMC_Init 2 */
}
8000d2c: bf00 nop
8000d2e: 3720 adds r7, #32
8000d30: 46bd mov sp, r7
8000d32: bd80 pop {r7, pc}
8000d34: 20000160 .word 0x20000160
8000d38: a0000104 .word 0xa0000104
08000d3c <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000d3c: b580 push {r7, lr}
8000d3e: b08e sub sp, #56 @ 0x38
8000d40: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000d42: f107 0324 add.w r3, r7, #36 @ 0x24
8000d46: 2200 movs r2, #0
8000d48: 601a str r2, [r3, #0]
8000d4a: 605a str r2, [r3, #4]
8000d4c: 609a str r2, [r3, #8]
8000d4e: 60da str r2, [r3, #12]
8000d50: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
8000d52: 4bb3 ldr r3, [pc, #716] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000d54: 6b1b ldr r3, [r3, #48] @ 0x30
8000d56: 4ab2 ldr r2, [pc, #712] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000d58: f043 0310 orr.w r3, r3, #16
8000d5c: 6313 str r3, [r2, #48] @ 0x30
8000d5e: 4bb0 ldr r3, [pc, #704] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000d60: 6b1b ldr r3, [r3, #48] @ 0x30
8000d62: f003 0310 and.w r3, r3, #16
8000d66: 623b str r3, [r7, #32]
8000d68: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000d6a: 4bad ldr r3, [pc, #692] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000d6c: 6b1b ldr r3, [r3, #48] @ 0x30
8000d6e: 4aac ldr r2, [pc, #688] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000d70: f043 0302 orr.w r3, r3, #2
8000d74: 6313 str r3, [r2, #48] @ 0x30
8000d76: 4baa ldr r3, [pc, #680] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000d78: 6b1b ldr r3, [r3, #48] @ 0x30
8000d7a: f003 0302 and.w r3, r3, #2
8000d7e: 61fb str r3, [r7, #28]
8000d80: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOG_CLK_ENABLE();
8000d82: 4ba7 ldr r3, [pc, #668] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000d84: 6b1b ldr r3, [r3, #48] @ 0x30
8000d86: 4aa6 ldr r2, [pc, #664] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000d88: f043 0340 orr.w r3, r3, #64 @ 0x40
8000d8c: 6313 str r3, [r2, #48] @ 0x30
8000d8e: 4ba4 ldr r3, [pc, #656] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000d90: 6b1b ldr r3, [r3, #48] @ 0x30
8000d92: f003 0340 and.w r3, r3, #64 @ 0x40
8000d96: 61bb str r3, [r7, #24]
8000d98: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOD_CLK_ENABLE();
8000d9a: 4ba1 ldr r3, [pc, #644] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000d9c: 6b1b ldr r3, [r3, #48] @ 0x30
8000d9e: 4aa0 ldr r2, [pc, #640] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000da0: f043 0308 orr.w r3, r3, #8
8000da4: 6313 str r3, [r2, #48] @ 0x30
8000da6: 4b9e ldr r3, [pc, #632] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000da8: 6b1b ldr r3, [r3, #48] @ 0x30
8000daa: f003 0308 and.w r3, r3, #8
8000dae: 617b str r3, [r7, #20]
8000db0: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOC_CLK_ENABLE();
8000db2: 4b9b ldr r3, [pc, #620] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000db4: 6b1b ldr r3, [r3, #48] @ 0x30
8000db6: 4a9a ldr r2, [pc, #616] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000db8: f043 0304 orr.w r3, r3, #4
8000dbc: 6313 str r3, [r2, #48] @ 0x30
8000dbe: 4b98 ldr r3, [pc, #608] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000dc0: 6b1b ldr r3, [r3, #48] @ 0x30
8000dc2: f003 0304 and.w r3, r3, #4
8000dc6: 613b str r3, [r7, #16]
8000dc8: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000dca: 4b95 ldr r3, [pc, #596] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000dcc: 6b1b ldr r3, [r3, #48] @ 0x30
8000dce: 4a94 ldr r2, [pc, #592] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000dd0: f043 0301 orr.w r3, r3, #1
8000dd4: 6313 str r3, [r2, #48] @ 0x30
8000dd6: 4b92 ldr r3, [pc, #584] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000dd8: 6b1b ldr r3, [r3, #48] @ 0x30
8000dda: f003 0301 and.w r3, r3, #1
8000dde: 60fb str r3, [r7, #12]
8000de0: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOI_CLK_ENABLE();
8000de2: 4b8f ldr r3, [pc, #572] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000de4: 6b1b ldr r3, [r3, #48] @ 0x30
8000de6: 4a8e ldr r2, [pc, #568] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000de8: f443 7380 orr.w r3, r3, #256 @ 0x100
8000dec: 6313 str r3, [r2, #48] @ 0x30
8000dee: 4b8c ldr r3, [pc, #560] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000df0: 6b1b ldr r3, [r3, #48] @ 0x30
8000df2: f403 7380 and.w r3, r3, #256 @ 0x100
8000df6: 60bb str r3, [r7, #8]
8000df8: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOH_CLK_ENABLE();
8000dfa: 4b89 ldr r3, [pc, #548] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000dfc: 6b1b ldr r3, [r3, #48] @ 0x30
8000dfe: 4a88 ldr r2, [pc, #544] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000e00: f043 0380 orr.w r3, r3, #128 @ 0x80
8000e04: 6313 str r3, [r2, #48] @ 0x30
8000e06: 4b86 ldr r3, [pc, #536] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000e08: 6b1b ldr r3, [r3, #48] @ 0x30
8000e0a: f003 0380 and.w r3, r3, #128 @ 0x80
8000e0e: 607b str r3, [r7, #4]
8000e10: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOF_CLK_ENABLE();
8000e12: 4b83 ldr r3, [pc, #524] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000e14: 6b1b ldr r3, [r3, #48] @ 0x30
8000e16: 4a82 ldr r2, [pc, #520] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000e18: f043 0320 orr.w r3, r3, #32
8000e1c: 6313 str r3, [r2, #48] @ 0x30
8000e1e: 4b80 ldr r3, [pc, #512] @ (8001020 <MX_GPIO_Init+0x2e4>)
8000e20: 6b1b ldr r3, [r3, #48] @ 0x30
8000e22: f003 0320 and.w r3, r3, #32
8000e26: 603b str r3, [r7, #0]
8000e28: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, ARD_D7_GPIO_Pin|ARD_D8_GPIO_Pin, GPIO_PIN_RESET);
8000e2a: 2200 movs r2, #0
8000e2c: 2118 movs r1, #24
8000e2e: 487d ldr r0, [pc, #500] @ (8001024 <MX_GPIO_Init+0x2e8>)
8000e30: f001 f8f4 bl 800201c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOG, WIFI_RST_Pin|WIFI_GPIO_0_Pin|PMOD_GPIO_0_Pin|USB_OTGFS_PPWR_EN_Pin, GPIO_PIN_RESET);
8000e34: 2200 movs r2, #0
8000e36: f44f 41e2 mov.w r1, #28928 @ 0x7100
8000e3a: 487b ldr r0, [pc, #492] @ (8001028 <MX_GPIO_Init+0x2ec>)
8000e3c: f001 f8ee bl 800201c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, WIFI_GPIO_2_Pin|WIFI_CH_PD_Pin, GPIO_PIN_RESET);
8000e40: 2200 movs r2, #0
8000e42: 2148 movs r1, #72 @ 0x48
8000e44: 4879 ldr r0, [pc, #484] @ (800102c <MX_GPIO_Init+0x2f0>)
8000e46: f001 f8e9 bl 800201c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, STMOD_UART4_RXD_s_Pin|ARD_D2_GPIO_Pin, GPIO_PIN_RESET);
8000e4a: 2200 movs r2, #0
8000e4c: f44f 6102 mov.w r1, #2080 @ 0x820
8000e50: 4877 ldr r0, [pc, #476] @ (8001030 <MX_GPIO_Init+0x2f4>)
8000e52: f001 f8e3 bl 800201c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOI, PMOD_SPI2_MOSI_Pin|PMOD_SPI2_MISO_Pin|GPIO_PIN_10, GPIO_PIN_RESET);
8000e56: 2200 movs r2, #0
8000e58: f240 410c movw r1, #1036 @ 0x40c
8000e5c: 4875 ldr r0, [pc, #468] @ (8001034 <MX_GPIO_Init+0x2f8>)
8000e5e: f001 f8dd bl 800201c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOH, PMOD_SEL_0_Pin|CTP_RST_Pin, GPIO_PIN_SET);
8000e62: 2201 movs r2, #1
8000e64: f44f 4102 mov.w r1, #33280 @ 0x8200
8000e68: 4873 ldr r0, [pc, #460] @ (8001038 <MX_GPIO_Init+0x2fc>)
8000e6a: f001 f8d7 bl 800201c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, USB_OTG_FS_ID_Pin|GPIO_PIN_5|SYS_LD_USER1_Pin, GPIO_PIN_RESET);
8000e6e: 2200 movs r2, #0
8000e70: f44f 6194 mov.w r1, #1184 @ 0x4a0
8000e74: 4871 ldr r0, [pc, #452] @ (800103c <MX_GPIO_Init+0x300>)
8000e76: f001 f8d1 bl 800201c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOH, PMOD_GPIO_1_Pin|ARD_D4_GPIO_Pin|USB_OTGHS_PPWR_EN_Pin|LCD_RST_Pin, GPIO_PIN_RESET);
8000e7a: 2200 movs r2, #0
8000e7c: f241 018c movw r1, #4236 @ 0x108c
8000e80: 486d ldr r0, [pc, #436] @ (8001038 <MX_GPIO_Init+0x2fc>)
8000e82: f001 f8cb bl 800201c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, USB_OTG_HS_ID_Pin|SYS_LD_USER2_Pin, GPIO_PIN_RESET);
8000e86: 2200 movs r2, #0
8000e88: f241 0102 movw r1, #4098 @ 0x1002
8000e8c: 486c ldr r0, [pc, #432] @ (8001040 <MX_GPIO_Init+0x304>)
8000e8e: f001 f8c5 bl 800201c <HAL_GPIO_WritePin>
/*Configure GPIO pins : ARD_D7_GPIO_Pin ARD_D8_GPIO_Pin */
GPIO_InitStruct.Pin = ARD_D7_GPIO_Pin|ARD_D8_GPIO_Pin;
8000e92: 2318 movs r3, #24
8000e94: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000e96: 2301 movs r3, #1
8000e98: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e9a: 2300 movs r3, #0
8000e9c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000e9e: 2300 movs r3, #0
8000ea0: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8000ea2: f107 0324 add.w r3, r7, #36 @ 0x24
8000ea6: 4619 mov r1, r3
8000ea8: 485e ldr r0, [pc, #376] @ (8001024 <MX_GPIO_Init+0x2e8>)
8000eaa: f000 ff03 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : QSPI_D2_Pin */
GPIO_InitStruct.Pin = QSPI_D2_Pin;
8000eae: 2304 movs r3, #4
8000eb0: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000eb2: 2302 movs r3, #2
8000eb4: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000eb6: 2300 movs r3, #0
8000eb8: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000eba: 2303 movs r3, #3
8000ebc: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
8000ebe: 2309 movs r3, #9
8000ec0: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(QSPI_D2_GPIO_Port, &GPIO_InitStruct);
8000ec2: f107 0324 add.w r3, r7, #36 @ 0x24
8000ec6: 4619 mov r1, r3
8000ec8: 4856 ldr r0, [pc, #344] @ (8001024 <MX_GPIO_Init+0x2e8>)
8000eca: f000 fef3 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : SAI2_I2C1_SCL_Pin SAI2_I2C1_SDA_Pin */
GPIO_InitStruct.Pin = SAI2_I2C1_SCL_Pin|SAI2_I2C1_SDA_Pin;
8000ece: f44f 7340 mov.w r3, #768 @ 0x300
8000ed2: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000ed4: 2312 movs r3, #18
8000ed6: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ed8: 2300 movs r3, #0
8000eda: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000edc: 2303 movs r3, #3
8000ede: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
8000ee0: 2304 movs r3, #4
8000ee2: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000ee4: f107 0324 add.w r3, r7, #36 @ 0x24
8000ee8: 4619 mov r1, r3
8000eea: 4855 ldr r0, [pc, #340] @ (8001040 <MX_GPIO_Init+0x304>)
8000eec: f000 fee2 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D11_TIM3_CH2_SPI1_MOSI_Pin ARD_D12_SPI1_MISO_Pin */
GPIO_InitStruct.Pin = ARD_D11_TIM3_CH2_SPI1_MOSI_Pin|ARD_D12_SPI1_MISO_Pin;
8000ef0: 2330 movs r3, #48 @ 0x30
8000ef2: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000ef4: 2302 movs r3, #2
8000ef6: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ef8: 2300 movs r3, #0
8000efa: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000efc: 2303 movs r3, #3
8000efe: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
8000f00: 2305 movs r3, #5
8000f02: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000f04: f107 0324 add.w r3, r7, #36 @ 0x24
8000f08: 4619 mov r1, r3
8000f0a: 484d ldr r0, [pc, #308] @ (8001040 <MX_GPIO_Init+0x304>)
8000f0c: f000 fed2 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : WIFI_RST_Pin WIFI_GPIO_0_Pin PMOD_GPIO_0_Pin USB_OTGFS_PPWR_EN_Pin */
GPIO_InitStruct.Pin = WIFI_RST_Pin|WIFI_GPIO_0_Pin|PMOD_GPIO_0_Pin|USB_OTGFS_PPWR_EN_Pin;
8000f10: f44f 43e2 mov.w r3, #28928 @ 0x7100
8000f14: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000f16: 2301 movs r3, #1
8000f18: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f1a: 2300 movs r3, #0
8000f1c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000f1e: 2300 movs r3, #0
8000f20: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8000f22: f107 0324 add.w r3, r7, #36 @ 0x24
8000f26: 4619 mov r1, r3
8000f28: 483f ldr r0, [pc, #252] @ (8001028 <MX_GPIO_Init+0x2ec>)
8000f2a: f000 fec3 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : UART_TXD_WIFI_RX_Pin */
GPIO_InitStruct.Pin = UART_TXD_WIFI_RX_Pin;
8000f2e: f44f 5380 mov.w r3, #4096 @ 0x1000
8000f32: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000f34: 2302 movs r3, #2
8000f36: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f38: 2300 movs r3, #0
8000f3a: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000f3c: 2303 movs r3, #3
8000f3e: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
8000f40: 2308 movs r3, #8
8000f42: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(UART_TXD_WIFI_RX_GPIO_Port, &GPIO_InitStruct);
8000f44: f107 0324 add.w r3, r7, #36 @ 0x24
8000f48: 4619 mov r1, r3
8000f4a: 4839 ldr r0, [pc, #228] @ (8001030 <MX_GPIO_Init+0x2f4>)
8000f4c: f000 feb2 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : STMOD_TIM2_CH1_2_ETR_Pin ARD_D10_TIM2_CH2_SPI1_NSS_Pin */
GPIO_InitStruct.Pin = STMOD_TIM2_CH1_2_ETR_Pin|ARD_D10_TIM2_CH2_SPI1_NSS_Pin;
8000f50: f248 0302 movw r3, #32770 @ 0x8002
8000f54: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000f56: 2302 movs r3, #2
8000f58: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f5a: 2300 movs r3, #0
8000f5c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000f5e: 2300 movs r3, #0
8000f60: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
8000f62: 2301 movs r3, #1
8000f64: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000f66: f107 0324 add.w r3, r7, #36 @ 0x24
8000f6a: 4619 mov r1, r3
8000f6c: 4833 ldr r0, [pc, #204] @ (800103c <MX_GPIO_Init+0x300>)
8000f6e: f000 fea1 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D3_TIM9_CH1_Pin ARD_D6_TIM9_CH2_Pin */
GPIO_InitStruct.Pin = ARD_D3_TIM9_CH1_Pin|ARD_D6_TIM9_CH2_Pin;
8000f72: 2360 movs r3, #96 @ 0x60
8000f74: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000f76: 2302 movs r3, #2
8000f78: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f7a: 2300 movs r3, #0
8000f7c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000f7e: 2300 movs r3, #0
8000f80: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF3_TIM9;
8000f82: 2303 movs r3, #3
8000f84: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8000f86: f107 0324 add.w r3, r7, #36 @ 0x24
8000f8a: 4619 mov r1, r3
8000f8c: 4825 ldr r0, [pc, #148] @ (8001024 <MX_GPIO_Init+0x2e8>)
8000f8e: f000 fe91 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : QSPI_NCS_Pin */
GPIO_InitStruct.Pin = QSPI_NCS_Pin;
8000f92: 2340 movs r3, #64 @ 0x40
8000f94: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000f96: 2302 movs r3, #2
8000f98: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f9a: 2300 movs r3, #0
8000f9c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000f9e: 2303 movs r3, #3
8000fa0: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
8000fa2: 230a movs r3, #10
8000fa4: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(QSPI_NCS_GPIO_Port, &GPIO_InitStruct);
8000fa6: f107 0324 add.w r3, r7, #36 @ 0x24
8000faa: 4619 mov r1, r3
8000fac: 4824 ldr r0, [pc, #144] @ (8001040 <MX_GPIO_Init+0x304>)
8000fae: f000 fe81 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : SAI2_INT_Pin */
GPIO_InitStruct.Pin = SAI2_INT_Pin;
8000fb2: f44f 4300 mov.w r3, #32768 @ 0x8000
8000fb6: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000fb8: f44f 1388 mov.w r3, #1114112 @ 0x110000
8000fbc: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000fbe: 2300 movs r3, #0
8000fc0: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(SAI2_INT_GPIO_Port, &GPIO_InitStruct);
8000fc2: f107 0324 add.w r3, r7, #36 @ 0x24
8000fc6: 4619 mov r1, r3
8000fc8: 4817 ldr r0, [pc, #92] @ (8001028 <MX_GPIO_Init+0x2ec>)
8000fca: f000 fe73 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : SAI2_SD_B_Pin */
GPIO_InitStruct.Pin = SAI2_SD_B_Pin;
8000fce: f44f 6380 mov.w r3, #1024 @ 0x400
8000fd2: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000fd4: 2302 movs r3, #2
8000fd6: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000fd8: 2300 movs r3, #0
8000fda: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000fdc: 2300 movs r3, #0
8000fde: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF10_SAI2;
8000fe0: 230a movs r3, #10
8000fe2: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(SAI2_SD_B_GPIO_Port, &GPIO_InitStruct);
8000fe4: f107 0324 add.w r3, r7, #36 @ 0x24
8000fe8: 4619 mov r1, r3
8000fea: 480f ldr r0, [pc, #60] @ (8001028 <MX_GPIO_Init+0x2ec>)
8000fec: f000 fe62 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : WIFI_GPIO_2_Pin WIFI_CH_PD_Pin */
GPIO_InitStruct.Pin = WIFI_GPIO_2_Pin|WIFI_CH_PD_Pin;
8000ff0: 2348 movs r3, #72 @ 0x48
8000ff2: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000ff4: 2301 movs r3, #1
8000ff6: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ff8: 2300 movs r3, #0
8000ffa: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000ffc: 2300 movs r3, #0
8000ffe: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8001000: f107 0324 add.w r3, r7, #36 @ 0x24
8001004: 4619 mov r1, r3
8001006: 4809 ldr r0, [pc, #36] @ (800102c <MX_GPIO_Init+0x2f0>)
8001008: f000 fe54 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : STMOD_UART4_RXD_s_Pin ARD_D2_GPIO_Pin */
GPIO_InitStruct.Pin = STMOD_UART4_RXD_s_Pin|ARD_D2_GPIO_Pin;
800100c: f44f 6302 mov.w r3, #2080 @ 0x820
8001010: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001012: 2301 movs r3, #1
8001014: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001016: 2300 movs r3, #0
8001018: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800101a: 2300 movs r3, #0
800101c: e012 b.n 8001044 <MX_GPIO_Init+0x308>
800101e: bf00 nop
8001020: 40023800 .word 0x40023800
8001024: 40021000 .word 0x40021000
8001028: 40021800 .word 0x40021800
800102c: 40020c00 .word 0x40020c00
8001030: 40020800 .word 0x40020800
8001034: 40022000 .word 0x40022000
8001038: 40021c00 .word 0x40021c00
800103c: 40020000 .word 0x40020000
8001040: 40020400 .word 0x40020400
8001044: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001046: f107 0324 add.w r3, r7, #36 @ 0x24
800104a: 4619 mov r1, r3
800104c: 48bc ldr r0, [pc, #752] @ (8001340 <MX_GPIO_Init+0x604>)
800104e: f000 fe31 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : QSPI_D1_Pin QSPI_D0_Pin */
GPIO_InitStruct.Pin = QSPI_D1_Pin|QSPI_D0_Pin;
8001052: f44f 63c0 mov.w r3, #1536 @ 0x600
8001056: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001058: 2302 movs r3, #2
800105a: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800105c: 2300 movs r3, #0
800105e: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001060: 2303 movs r3, #3
8001062: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
8001064: 2309 movs r3, #9
8001066: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001068: f107 0324 add.w r3, r7, #36 @ 0x24
800106c: 4619 mov r1, r3
800106e: 48b4 ldr r0, [pc, #720] @ (8001340 <MX_GPIO_Init+0x604>)
8001070: f000 fe20 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : PA12 PA11 */
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11;
8001074: f44f 53c0 mov.w r3, #6144 @ 0x1800
8001078: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800107a: 2302 movs r3, #2
800107c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800107e: 2300 movs r3, #0
8001080: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001082: 2303 movs r3, #3
8001084: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
8001086: 230a movs r3, #10
8001088: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800108a: f107 0324 add.w r3, r7, #36 @ 0x24
800108e: 4619 mov r1, r3
8001090: 48ac ldr r0, [pc, #688] @ (8001344 <MX_GPIO_Init+0x608>)
8001092: f000 fe0f bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : SAI2_FS_A_Pin SAI2_SD_A_Pin SAI2_SCK_A_Pin SAI2_MCLK_A_Pin */
GPIO_InitStruct.Pin = SAI2_FS_A_Pin|SAI2_SD_A_Pin|SAI2_SCK_A_Pin|SAI2_MCLK_A_Pin;
8001096: 23f0 movs r3, #240 @ 0xf0
8001098: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800109a: 2302 movs r3, #2
800109c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800109e: 2300 movs r3, #0
80010a0: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80010a2: 2300 movs r3, #0
80010a4: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF10_SAI2;
80010a6: 230a movs r3, #10
80010a8: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
80010aa: f107 0324 add.w r3, r7, #36 @ 0x24
80010ae: 4619 mov r1, r3
80010b0: 48a5 ldr r0, [pc, #660] @ (8001348 <MX_GPIO_Init+0x60c>)
80010b2: f000 fdff bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_SPI2_MOSI_Pin PMOD_SPI2_MISO_Pin PI10 */
GPIO_InitStruct.Pin = PMOD_SPI2_MOSI_Pin|PMOD_SPI2_MISO_Pin|GPIO_PIN_10;
80010b6: f240 430c movw r3, #1036 @ 0x40c
80010ba: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80010bc: 2301 movs r3, #1
80010be: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80010c0: 2300 movs r3, #0
80010c2: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80010c4: 2300 movs r3, #0
80010c6: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
80010c8: f107 0324 add.w r3, r7, #36 @ 0x24
80010cc: 4619 mov r1, r3
80010ce: 489e ldr r0, [pc, #632] @ (8001348 <MX_GPIO_Init+0x60c>)
80010d0: f000 fdf0 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : CTP_INT_Pin */
GPIO_InitStruct.Pin = CTP_INT_Pin;
80010d4: f44f 7300 mov.w r3, #512 @ 0x200
80010d8: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
80010da: f44f 1388 mov.w r3, #1114112 @ 0x110000
80010de: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80010e0: 2300 movs r3, #0
80010e2: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(CTP_INT_GPIO_Port, &GPIO_InitStruct);
80010e4: f107 0324 add.w r3, r7, #36 @ 0x24
80010e8: 4619 mov r1, r3
80010ea: 4897 ldr r0, [pc, #604] @ (8001348 <MX_GPIO_Init+0x60c>)
80010ec: f000 fde2 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : UART_RXD_WIFI_TX_Pin */
GPIO_InitStruct.Pin = UART_RXD_WIFI_TX_Pin;
80010f0: 2304 movs r3, #4
80010f2: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80010f4: 2302 movs r3, #2
80010f6: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80010f8: 2300 movs r3, #0
80010fa: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80010fc: 2303 movs r3, #3
80010fe: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
8001100: 2308 movs r3, #8
8001102: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(UART_RXD_WIFI_TX_GPIO_Port, &GPIO_InitStruct);
8001104: f107 0324 add.w r3, r7, #36 @ 0x24
8001108: 4619 mov r1, r3
800110a: 4890 ldr r0, [pc, #576] @ (800134c <MX_GPIO_Init+0x610>)
800110c: f000 fdd2 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_SEL_0_Pin PMOD_GPIO_1_Pin ARD_D4_GPIO_Pin USB_OTGHS_PPWR_EN_Pin
CTP_RST_Pin LCD_RST_Pin */
GPIO_InitStruct.Pin = PMOD_SEL_0_Pin|PMOD_GPIO_1_Pin|ARD_D4_GPIO_Pin|USB_OTGHS_PPWR_EN_Pin
8001110: f249 238c movw r3, #37516 @ 0x928c
8001114: 627b str r3, [r7, #36] @ 0x24
|CTP_RST_Pin|LCD_RST_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001116: 2301 movs r3, #1
8001118: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800111a: 2300 movs r3, #0
800111c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800111e: 2300 movs r3, #0
8001120: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8001122: f107 0324 add.w r3, r7, #36 @ 0x24
8001126: 4619 mov r1, r3
8001128: 4889 ldr r0, [pc, #548] @ (8001350 <MX_GPIO_Init+0x614>)
800112a: f000 fdc3 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_SPI2_SCK_Pin PMOD_SPI2_NSS_Pin */
GPIO_InitStruct.Pin = PMOD_SPI2_SCK_Pin|PMOD_SPI2_NSS_Pin;
800112e: 2303 movs r3, #3
8001130: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001132: 2302 movs r3, #2
8001134: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001136: 2300 movs r3, #0
8001138: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800113a: 2303 movs r3, #3
800113c: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
800113e: 2305 movs r3, #5
8001140: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8001142: f107 0324 add.w r3, r7, #36 @ 0x24
8001146: 4619 mov r1, r3
8001148: 487f ldr r0, [pc, #508] @ (8001348 <MX_GPIO_Init+0x60c>)
800114a: f000 fdb3 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : USB_OTG_FS_ID_Pin PA5 SYS_LD_USER1_Pin */
GPIO_InitStruct.Pin = USB_OTG_FS_ID_Pin|GPIO_PIN_5|SYS_LD_USER1_Pin;
800114e: f44f 6394 mov.w r3, #1184 @ 0x4a0
8001152: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001154: 2301 movs r3, #1
8001156: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001158: 2300 movs r3, #0
800115a: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800115c: 2300 movs r3, #0
800115e: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001160: f107 0324 add.w r3, r7, #36 @ 0x24
8001164: 4619 mov r1, r3
8001166: 4877 ldr r0, [pc, #476] @ (8001344 <MX_GPIO_Init+0x608>)
8001168: f000 fda4 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : STMOD_UART4_TXD_Pin STMOD_UART4_RXD_Pin */
GPIO_InitStruct.Pin = STMOD_UART4_TXD_Pin|STMOD_UART4_RXD_Pin;
800116c: f44f 43c0 mov.w r3, #24576 @ 0x6000
8001170: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001172: 2302 movs r3, #2
8001174: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001176: 2300 movs r3, #0
8001178: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800117a: 2303 movs r3, #3
800117c: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
800117e: 2308 movs r3, #8
8001180: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8001182: f107 0324 add.w r3, r7, #36 @ 0x24
8001186: 4619 mov r1, r3
8001188: 4871 ldr r0, [pc, #452] @ (8001350 <MX_GPIO_Init+0x614>)
800118a: f000 fd93 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : PA9 */
GPIO_InitStruct.Pin = GPIO_PIN_9;
800118e: f44f 7300 mov.w r3, #512 @ 0x200
8001192: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001194: 2300 movs r3, #0
8001196: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001198: 2300 movs r3, #0
800119a: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800119c: f107 0324 add.w r3, r7, #36 @ 0x24
80011a0: 4619 mov r1, r3
80011a2: 4868 ldr r0, [pc, #416] @ (8001344 <MX_GPIO_Init+0x608>)
80011a4: f000 fd86 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : LCD_TE_INT_Pin */
GPIO_InitStruct.Pin = LCD_TE_INT_Pin;
80011a8: f44f 7380 mov.w r3, #256 @ 0x100
80011ac: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
80011ae: f44f 1388 mov.w r3, #1114112 @ 0x110000
80011b2: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80011b4: 2300 movs r3, #0
80011b6: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(LCD_TE_INT_GPIO_Port, &GPIO_InitStruct);
80011b8: f107 0324 add.w r3, r7, #36 @ 0x24
80011bc: 4619 mov r1, r3
80011be: 4860 ldr r0, [pc, #384] @ (8001340 <MX_GPIO_Init+0x604>)
80011c0: f000 fd78 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D15_STMOD_I2C2_SCL_Pin ARD_D14_STMOD_I2C2_SDA_Pin */
GPIO_InitStruct.Pin = ARD_D15_STMOD_I2C2_SCL_Pin|ARD_D14_STMOD_I2C2_SDA_Pin;
80011c4: 2330 movs r3, #48 @ 0x30
80011c6: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
80011c8: 2312 movs r3, #18
80011ca: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80011cc: 2300 movs r3, #0
80011ce: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80011d0: 2303 movs r3, #3
80011d2: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
80011d4: 2304 movs r3, #4
80011d6: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
80011d8: f107 0324 add.w r3, r7, #36 @ 0x24
80011dc: 4619 mov r1, r3
80011de: 485c ldr r0, [pc, #368] @ (8001350 <MX_GPIO_Init+0x614>)
80011e0: f000 fd68 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_UART7_TXD_Pin PMOD_UART7_RXD_Pin PMOD_UART7_CTS_Pin PMOD_UART7_RTS_Pin */
GPIO_InitStruct.Pin = PMOD_UART7_TXD_Pin|PMOD_UART7_RXD_Pin|PMOD_UART7_CTS_Pin|PMOD_UART7_RTS_Pin;
80011e4: f44f 7370 mov.w r3, #960 @ 0x3c0
80011e8: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80011ea: 2302 movs r3, #2
80011ec: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80011ee: 2300 movs r3, #0
80011f0: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80011f2: 2303 movs r3, #3
80011f4: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART7;
80011f6: 2308 movs r3, #8
80011f8: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
80011fa: f107 0324 add.w r3, r7, #36 @ 0x24
80011fe: 4619 mov r1, r3
8001200: 4854 ldr r0, [pc, #336] @ (8001354 <MX_GPIO_Init+0x618>)
8001202: f000 fd57 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_A3_ADC3_IN8_Pin */
GPIO_InitStruct.Pin = ARD_A3_ADC3_IN8_Pin;
8001206: f44f 6380 mov.w r3, #1024 @ 0x400
800120a: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
800120c: 2303 movs r3, #3
800120e: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001210: 2300 movs r3, #0
8001212: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(ARD_A3_ADC3_IN8_GPIO_Port, &GPIO_InitStruct);
8001214: f107 0324 add.w r3, r7, #36 @ 0x24
8001218: 4619 mov r1, r3
800121a: 484e ldr r0, [pc, #312] @ (8001354 <MX_GPIO_Init+0x618>)
800121c: f000 fd4a bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : LCD_BL_Pin */
GPIO_InitStruct.Pin = LCD_BL_Pin;
8001220: f44f 6300 mov.w r3, #2048 @ 0x800
8001224: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001226: 2302 movs r3, #2
8001228: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800122a: 2300 movs r3, #0
800122c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800122e: 2300 movs r3, #0
8001230: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF2_TIM5;
8001232: 2302 movs r3, #2
8001234: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(LCD_BL_GPIO_Port, &GPIO_InitStruct);
8001236: f107 0324 add.w r3, r7, #36 @ 0x24
800123a: 4619 mov r1, r3
800123c: 4844 ldr r0, [pc, #272] @ (8001350 <MX_GPIO_Init+0x614>)
800123e: f000 fd39 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : USB_OTGHS_OVCR_INT_Pin */
GPIO_InitStruct.Pin = USB_OTGHS_OVCR_INT_Pin;
8001242: f44f 6380 mov.w r3, #1024 @ 0x400
8001246: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001248: 2300 movs r3, #0
800124a: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800124c: 2300 movs r3, #0
800124e: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(USB_OTGHS_OVCR_INT_GPIO_Port, &GPIO_InitStruct);
8001250: f107 0324 add.w r3, r7, #36 @ 0x24
8001254: 4619 mov r1, r3
8001256: 483e ldr r0, [pc, #248] @ (8001350 <MX_GPIO_Init+0x614>)
8001258: f000 fd2c bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_A4_Pin ARD_A5_Pin ARD_A2_Pin */
GPIO_InitStruct.Pin = ARD_A4_Pin|ARD_A5_Pin|ARD_A2_Pin;
800125c: 2313 movs r3, #19
800125e: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001260: 2303 movs r3, #3
8001262: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001264: 2300 movs r3, #0
8001266: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001268: f107 0324 add.w r3, r7, #36 @ 0x24
800126c: 4619 mov r1, r3
800126e: 4834 ldr r0, [pc, #208] @ (8001340 <MX_GPIO_Init+0x604>)
8001270: f000 fd20 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : STMOD_SPI2_MISOs_Pin STMOD_SPI2_MOSIs_Pin */
GPIO_InitStruct.Pin = STMOD_SPI2_MISOs_Pin|STMOD_SPI2_MOSIs_Pin;
8001274: 230c movs r3, #12
8001276: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001278: 2302 movs r3, #2
800127a: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800127c: 2300 movs r3, #0
800127e: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001280: 2303 movs r3, #3
8001282: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8001284: 2305 movs r3, #5
8001286: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001288: f107 0324 add.w r3, r7, #36 @ 0x24
800128c: 4619 mov r1, r3
800128e: 482c ldr r0, [pc, #176] @ (8001340 <MX_GPIO_Init+0x604>)
8001290: f000 fd10 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : QSPI_CLK_Pin */
GPIO_InitStruct.Pin = QSPI_CLK_Pin;
8001294: 2304 movs r3, #4
8001296: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001298: 2302 movs r3, #2
800129a: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800129c: 2300 movs r3, #0
800129e: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80012a0: 2303 movs r3, #3
80012a2: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
80012a4: 2309 movs r3, #9
80012a6: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(QSPI_CLK_GPIO_Port, &GPIO_InitStruct);
80012a8: f107 0324 add.w r3, r7, #36 @ 0x24
80012ac: 4619 mov r1, r3
80012ae: 482a ldr r0, [pc, #168] @ (8001358 <MX_GPIO_Init+0x61c>)
80012b0: f000 fd00 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_D9_TIM12_CH1_Pin */
GPIO_InitStruct.Pin = ARD_D9_TIM12_CH1_Pin;
80012b4: 2340 movs r3, #64 @ 0x40
80012b6: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80012b8: 2302 movs r3, #2
80012ba: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80012bc: 2300 movs r3, #0
80012be: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80012c0: 2300 movs r3, #0
80012c2: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_TIM12;
80012c4: 2309 movs r3, #9
80012c6: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(ARD_D9_TIM12_CH1_GPIO_Port, &GPIO_InitStruct);
80012c8: f107 0324 add.w r3, r7, #36 @ 0x24
80012cc: 4619 mov r1, r3
80012ce: 4820 ldr r0, [pc, #128] @ (8001350 <MX_GPIO_Init+0x614>)
80012d0: f000 fcf0 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : QSPI_D3_Pin */
GPIO_InitStruct.Pin = QSPI_D3_Pin;
80012d4: f44f 5300 mov.w r3, #8192 @ 0x2000
80012d8: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80012da: 2302 movs r3, #2
80012dc: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80012de: 2300 movs r3, #0
80012e0: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80012e2: 2303 movs r3, #3
80012e4: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
80012e6: 2309 movs r3, #9
80012e8: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(QSPI_D3_GPIO_Port, &GPIO_InitStruct);
80012ea: f107 0324 add.w r3, r7, #36 @ 0x24
80012ee: 4619 mov r1, r3
80012f0: 4816 ldr r0, [pc, #88] @ (800134c <MX_GPIO_Init+0x610>)
80012f2: f000 fcdf bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : PA0 */
GPIO_InitStruct.Pin = GPIO_PIN_0;
80012f6: 2301 movs r3, #1
80012f8: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80012fa: 2300 movs r3, #0
80012fc: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80012fe: 2300 movs r3, #0
8001300: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001302: f107 0324 add.w r3, r7, #36 @ 0x24
8001306: 4619 mov r1, r3
8001308: 480e ldr r0, [pc, #56] @ (8001344 <MX_GPIO_Init+0x608>)
800130a: f000 fcd3 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_A1_Pin ARD_A0_Pin */
GPIO_InitStruct.Pin = ARD_A1_Pin|ARD_A0_Pin;
800130e: 2350 movs r3, #80 @ 0x50
8001310: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001312: 2303 movs r3, #3
8001314: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001316: 2300 movs r3, #0
8001318: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800131a: f107 0324 add.w r3, r7, #36 @ 0x24
800131e: 4619 mov r1, r3
8001320: 4808 ldr r0, [pc, #32] @ (8001344 <MX_GPIO_Init+0x608>)
8001322: f000 fcc7 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D1_USART2_TX_Pin ARD_D0_USART2_RX_Pin */
GPIO_InitStruct.Pin = ARD_D1_USART2_TX_Pin|ARD_D0_USART2_RX_Pin;
8001326: 230c movs r3, #12
8001328: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800132a: 2302 movs r3, #2
800132c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800132e: 2300 movs r3, #0
8001330: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001332: 2303 movs r3, #3
8001334: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
8001336: 2307 movs r3, #7
8001338: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800133a: f107 0324 add.w r3, r7, #36 @ 0x24
800133e: e00d b.n 800135c <MX_GPIO_Init+0x620>
8001340: 40020800 .word 0x40020800
8001344: 40020000 .word 0x40020000
8001348: 40022000 .word 0x40022000
800134c: 40020c00 .word 0x40020c00
8001350: 40021c00 .word 0x40021c00
8001354: 40021400 .word 0x40021400
8001358: 40020400 .word 0x40020400
800135c: 4619 mov r1, r3
800135e: 4829 ldr r0, [pc, #164] @ (8001404 <MX_GPIO_Init+0x6c8>)
8001360: f000 fca8 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : USB_OTG_HS_ID_Pin SYS_LD_USER2_Pin */
GPIO_InitStruct.Pin = USB_OTG_HS_ID_Pin|SYS_LD_USER2_Pin;
8001364: f241 0302 movw r3, #4098 @ 0x1002
8001368: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800136a: 2301 movs r3, #1
800136c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800136e: 2300 movs r3, #0
8001370: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001372: 2300 movs r3, #0
8001374: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001376: f107 0324 add.w r3, r7, #36 @ 0x24
800137a: 4619 mov r1, r3
800137c: 4822 ldr r0, [pc, #136] @ (8001408 <MX_GPIO_Init+0x6cc>)
800137e: f000 fc99 bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : USB_OTG_HS_VBUS_Pin USB_OTGFS_OVCR_INT_Pin PMOD_INT_Pin */
GPIO_InitStruct.Pin = USB_OTG_HS_VBUS_Pin|USB_OTGFS_OVCR_INT_Pin|PMOD_INT_Pin;
8001382: f44f 5330 mov.w r3, #11264 @ 0x2c00
8001386: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8001388: f44f 1388 mov.w r3, #1114112 @ 0x110000
800138c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800138e: 2300 movs r3, #0
8001390: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001392: f107 0324 add.w r3, r7, #36 @ 0x24
8001396: 4619 mov r1, r3
8001398: 481b ldr r0, [pc, #108] @ (8001408 <MX_GPIO_Init+0x6cc>)
800139a: f000 fc8b bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_D5_STMOD_TIM3_CH3_Pin */
GPIO_InitStruct.Pin = ARD_D5_STMOD_TIM3_CH3_Pin;
800139e: 2301 movs r3, #1
80013a0: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80013a2: 2302 movs r3, #2
80013a4: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80013a6: 2300 movs r3, #0
80013a8: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80013aa: 2300 movs r3, #0
80013ac: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
80013ae: 2302 movs r3, #2
80013b0: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(ARD_D5_STMOD_TIM3_CH3_GPIO_Port, &GPIO_InitStruct);
80013b2: f107 0324 add.w r3, r7, #36 @ 0x24
80013b6: 4619 mov r1, r3
80013b8: 4813 ldr r0, [pc, #76] @ (8001408 <MX_GPIO_Init+0x6cc>)
80013ba: f000 fc7b bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pin : PMOD_RESET_Pin */
GPIO_InitStruct.Pin = PMOD_RESET_Pin;
80013be: f44f 6300 mov.w r3, #2048 @ 0x800
80013c2: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80013c4: 2300 movs r3, #0
80013c6: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80013c8: 2300 movs r3, #0
80013ca: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(PMOD_RESET_GPIO_Port, &GPIO_InitStruct);
80013cc: f107 0324 add.w r3, r7, #36 @ 0x24
80013d0: 4619 mov r1, r3
80013d2: 480e ldr r0, [pc, #56] @ (800140c <MX_GPIO_Init+0x6d0>)
80013d4: f000 fc6e bl 8001cb4 <HAL_GPIO_Init>
/*Configure GPIO pins : PB14 PB15 */
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
80013d8: f44f 4340 mov.w r3, #49152 @ 0xc000
80013dc: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80013de: 2302 movs r3, #2
80013e0: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80013e2: 2300 movs r3, #0
80013e4: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80013e6: 2303 movs r3, #3
80013e8: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;
80013ea: 230c movs r3, #12
80013ec: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80013ee: f107 0324 add.w r3, r7, #36 @ 0x24
80013f2: 4619 mov r1, r3
80013f4: 4804 ldr r0, [pc, #16] @ (8001408 <MX_GPIO_Init+0x6cc>)
80013f6: f000 fc5d bl 8001cb4 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
80013fa: bf00 nop
80013fc: 3738 adds r7, #56 @ 0x38
80013fe: 46bd mov sp, r7
8001400: bd80 pop {r7, pc}
8001402: bf00 nop
8001404: 40020000 .word 0x40020000
8001408: 40020400 .word 0x40020400
800140c: 40021400 .word 0x40021400
08001410 <HAL_TIM_PeriodElapsedCallback>:
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8001410: b580 push {r7, lr}
8001412: b082 sub sp, #8
8001414: af00 add r7, sp, #0
8001416: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM14)
8001418: 687b ldr r3, [r7, #4]
800141a: 681b ldr r3, [r3, #0]
800141c: 4a04 ldr r2, [pc, #16] @ (8001430 <HAL_TIM_PeriodElapsedCallback+0x20>)
800141e: 4293 cmp r3, r2
8001420: d101 bne.n 8001426 <HAL_TIM_PeriodElapsedCallback+0x16>
{
HAL_IncTick();
8001422: f000 fb21 bl 8001a68 <HAL_IncTick>
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
8001426: bf00 nop
8001428: 3708 adds r7, #8
800142a: 46bd mov sp, r7
800142c: bd80 pop {r7, pc}
800142e: bf00 nop
8001430: 40002000 .word 0x40002000
08001434 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8001434: b480 push {r7}
8001436: af00 add r7, sp, #0
__ASM volatile ("cpsid i" : : : "memory");
8001438: b672 cpsid i
}
800143a: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
800143c: bf00 nop
800143e: e7fd b.n 800143c <Error_Handler+0x8>
08001440 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8001440: b480 push {r7}
8001442: b083 sub sp, #12
8001444: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_PWR_CLK_ENABLE();
8001446: 4b0f ldr r3, [pc, #60] @ (8001484 <HAL_MspInit+0x44>)
8001448: 6c1b ldr r3, [r3, #64] @ 0x40
800144a: 4a0e ldr r2, [pc, #56] @ (8001484 <HAL_MspInit+0x44>)
800144c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001450: 6413 str r3, [r2, #64] @ 0x40
8001452: 4b0c ldr r3, [pc, #48] @ (8001484 <HAL_MspInit+0x44>)
8001454: 6c1b ldr r3, [r3, #64] @ 0x40
8001456: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800145a: 607b str r3, [r7, #4]
800145c: 687b ldr r3, [r7, #4]
__HAL_RCC_SYSCFG_CLK_ENABLE();
800145e: 4b09 ldr r3, [pc, #36] @ (8001484 <HAL_MspInit+0x44>)
8001460: 6c5b ldr r3, [r3, #68] @ 0x44
8001462: 4a08 ldr r2, [pc, #32] @ (8001484 <HAL_MspInit+0x44>)
8001464: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8001468: 6453 str r3, [r2, #68] @ 0x44
800146a: 4b06 ldr r3, [pc, #24] @ (8001484 <HAL_MspInit+0x44>)
800146c: 6c5b ldr r3, [r3, #68] @ 0x44
800146e: f403 4380 and.w r3, r3, #16384 @ 0x4000
8001472: 603b str r3, [r7, #0]
8001474: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8001476: bf00 nop
8001478: 370c adds r7, #12
800147a: 46bd mov sp, r7
800147c: f85d 7b04 ldr.w r7, [sp], #4
8001480: 4770 bx lr
8001482: bf00 nop
8001484: 40023800 .word 0x40023800
08001488 <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
8001488: b580 push {r7, lr}
800148a: b0aa sub sp, #168 @ 0xa8
800148c: af00 add r7, sp, #0
800148e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001490: f107 0394 add.w r3, r7, #148 @ 0x94
8001494: 2200 movs r2, #0
8001496: 601a str r2, [r3, #0]
8001498: 605a str r2, [r3, #4]
800149a: 609a str r2, [r3, #8]
800149c: 60da str r2, [r3, #12]
800149e: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
80014a0: f107 0314 add.w r3, r7, #20
80014a4: 2280 movs r2, #128 @ 0x80
80014a6: 2100 movs r1, #0
80014a8: 4618 mov r0, r3
80014aa: f003 f9ca bl 8004842 <memset>
if(hi2c->Instance==I2C3)
80014ae: 687b ldr r3, [r7, #4]
80014b0: 681b ldr r3, [r3, #0]
80014b2: 4a33 ldr r2, [pc, #204] @ (8001580 <HAL_I2C_MspInit+0xf8>)
80014b4: 4293 cmp r3, r2
80014b6: d15e bne.n 8001576 <HAL_I2C_MspInit+0xee>
/* USER CODE END I2C3_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C3;
80014b8: f44f 3380 mov.w r3, #65536 @ 0x10000
80014bc: 617b str r3, [r7, #20]
PeriphClkInitStruct.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1;
80014be: 2300 movs r3, #0
80014c0: 67bb str r3, [r7, #120] @ 0x78
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
80014c2: f107 0314 add.w r3, r7, #20
80014c6: 4618 mov r0, r3
80014c8: f001 fc2c bl 8002d24 <HAL_RCCEx_PeriphCLKConfig>
80014cc: 4603 mov r3, r0
80014ce: 2b00 cmp r3, #0
80014d0: d001 beq.n 80014d6 <HAL_I2C_MspInit+0x4e>
{
Error_Handler();
80014d2: f7ff ffaf bl 8001434 <Error_Handler>
}
__HAL_RCC_GPIOA_CLK_ENABLE();
80014d6: 4b2b ldr r3, [pc, #172] @ (8001584 <HAL_I2C_MspInit+0xfc>)
80014d8: 6b1b ldr r3, [r3, #48] @ 0x30
80014da: 4a2a ldr r2, [pc, #168] @ (8001584 <HAL_I2C_MspInit+0xfc>)
80014dc: f043 0301 orr.w r3, r3, #1
80014e0: 6313 str r3, [r2, #48] @ 0x30
80014e2: 4b28 ldr r3, [pc, #160] @ (8001584 <HAL_I2C_MspInit+0xfc>)
80014e4: 6b1b ldr r3, [r3, #48] @ 0x30
80014e6: f003 0301 and.w r3, r3, #1
80014ea: 613b str r3, [r7, #16]
80014ec: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOH_CLK_ENABLE();
80014ee: 4b25 ldr r3, [pc, #148] @ (8001584 <HAL_I2C_MspInit+0xfc>)
80014f0: 6b1b ldr r3, [r3, #48] @ 0x30
80014f2: 4a24 ldr r2, [pc, #144] @ (8001584 <HAL_I2C_MspInit+0xfc>)
80014f4: f043 0380 orr.w r3, r3, #128 @ 0x80
80014f8: 6313 str r3, [r2, #48] @ 0x30
80014fa: 4b22 ldr r3, [pc, #136] @ (8001584 <HAL_I2C_MspInit+0xfc>)
80014fc: 6b1b ldr r3, [r3, #48] @ 0x30
80014fe: f003 0380 and.w r3, r3, #128 @ 0x80
8001502: 60fb str r3, [r7, #12]
8001504: 68fb ldr r3, [r7, #12]
/**I2C3 GPIO Configuration
PA8 ------> I2C3_SCL
PH8 ------> I2C3_SDA
*/
GPIO_InitStruct.Pin = CTP_SCL_Pin;
8001506: f44f 7380 mov.w r3, #256 @ 0x100
800150a: f8c7 3094 str.w r3, [r7, #148] @ 0x94
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
800150e: 2312 movs r3, #18
8001510: f8c7 3098 str.w r3, [r7, #152] @ 0x98
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001514: 2300 movs r3, #0
8001516: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800151a: 2303 movs r3, #3
800151c: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
8001520: 2304 movs r3, #4
8001522: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
HAL_GPIO_Init(CTP_SCL_GPIO_Port, &GPIO_InitStruct);
8001526: f107 0394 add.w r3, r7, #148 @ 0x94
800152a: 4619 mov r1, r3
800152c: 4816 ldr r0, [pc, #88] @ (8001588 <HAL_I2C_MspInit+0x100>)
800152e: f000 fbc1 bl 8001cb4 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = CTP_SDA_Pin;
8001532: f44f 7380 mov.w r3, #256 @ 0x100
8001536: f8c7 3094 str.w r3, [r7, #148] @ 0x94
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
800153a: 2312 movs r3, #18
800153c: f8c7 3098 str.w r3, [r7, #152] @ 0x98
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001540: 2300 movs r3, #0
8001542: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001546: 2303 movs r3, #3
8001548: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
800154c: 2304 movs r3, #4
800154e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
HAL_GPIO_Init(CTP_SDA_GPIO_Port, &GPIO_InitStruct);
8001552: f107 0394 add.w r3, r7, #148 @ 0x94
8001556: 4619 mov r1, r3
8001558: 480c ldr r0, [pc, #48] @ (800158c <HAL_I2C_MspInit+0x104>)
800155a: f000 fbab bl 8001cb4 <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_I2C3_CLK_ENABLE();
800155e: 4b09 ldr r3, [pc, #36] @ (8001584 <HAL_I2C_MspInit+0xfc>)
8001560: 6c1b ldr r3, [r3, #64] @ 0x40
8001562: 4a08 ldr r2, [pc, #32] @ (8001584 <HAL_I2C_MspInit+0xfc>)
8001564: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
8001568: 6413 str r3, [r2, #64] @ 0x40
800156a: 4b06 ldr r3, [pc, #24] @ (8001584 <HAL_I2C_MspInit+0xfc>)
800156c: 6c1b ldr r3, [r3, #64] @ 0x40
800156e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8001572: 60bb str r3, [r7, #8]
8001574: 68bb ldr r3, [r7, #8]
/* USER CODE END I2C3_MspInit 1 */
}
}
8001576: bf00 nop
8001578: 37a8 adds r7, #168 @ 0xa8
800157a: 46bd mov sp, r7
800157c: bd80 pop {r7, pc}
800157e: bf00 nop
8001580: 40005c00 .word 0x40005c00
8001584: 40023800 .word 0x40023800
8001588: 40020000 .word 0x40020000
800158c: 40021c00 .word 0x40021c00
08001590 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8001590: b580 push {r7, lr}
8001592: b0aa sub sp, #168 @ 0xa8
8001594: af00 add r7, sp, #0
8001596: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001598: f107 0394 add.w r3, r7, #148 @ 0x94
800159c: 2200 movs r2, #0
800159e: 601a str r2, [r3, #0]
80015a0: 605a str r2, [r3, #4]
80015a2: 609a str r2, [r3, #8]
80015a4: 60da str r2, [r3, #12]
80015a6: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
80015a8: f107 0314 add.w r3, r7, #20
80015ac: 2280 movs r2, #128 @ 0x80
80015ae: 2100 movs r1, #0
80015b0: 4618 mov r0, r3
80015b2: f003 f946 bl 8004842 <memset>
if(huart->Instance==USART6)
80015b6: 687b ldr r3, [r7, #4]
80015b8: 681b ldr r3, [r3, #0]
80015ba: 4a21 ldr r2, [pc, #132] @ (8001640 <HAL_UART_MspInit+0xb0>)
80015bc: 4293 cmp r3, r2
80015be: d13b bne.n 8001638 <HAL_UART_MspInit+0xa8>
/* USER CODE END USART6_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6;
80015c0: f44f 6300 mov.w r3, #2048 @ 0x800
80015c4: 617b str r3, [r7, #20]
PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
80015c6: 2300 movs r3, #0
80015c8: 667b str r3, [r7, #100] @ 0x64
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
80015ca: f107 0314 add.w r3, r7, #20
80015ce: 4618 mov r0, r3
80015d0: f001 fba8 bl 8002d24 <HAL_RCCEx_PeriphCLKConfig>
80015d4: 4603 mov r3, r0
80015d6: 2b00 cmp r3, #0
80015d8: d001 beq.n 80015de <HAL_UART_MspInit+0x4e>
{
Error_Handler();
80015da: f7ff ff2b bl 8001434 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_USART6_CLK_ENABLE();
80015de: 4b19 ldr r3, [pc, #100] @ (8001644 <HAL_UART_MspInit+0xb4>)
80015e0: 6c5b ldr r3, [r3, #68] @ 0x44
80015e2: 4a18 ldr r2, [pc, #96] @ (8001644 <HAL_UART_MspInit+0xb4>)
80015e4: f043 0320 orr.w r3, r3, #32
80015e8: 6453 str r3, [r2, #68] @ 0x44
80015ea: 4b16 ldr r3, [pc, #88] @ (8001644 <HAL_UART_MspInit+0xb4>)
80015ec: 6c5b ldr r3, [r3, #68] @ 0x44
80015ee: f003 0320 and.w r3, r3, #32
80015f2: 613b str r3, [r7, #16]
80015f4: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
80015f6: 4b13 ldr r3, [pc, #76] @ (8001644 <HAL_UART_MspInit+0xb4>)
80015f8: 6b1b ldr r3, [r3, #48] @ 0x30
80015fa: 4a12 ldr r2, [pc, #72] @ (8001644 <HAL_UART_MspInit+0xb4>)
80015fc: f043 0304 orr.w r3, r3, #4
8001600: 6313 str r3, [r2, #48] @ 0x30
8001602: 4b10 ldr r3, [pc, #64] @ (8001644 <HAL_UART_MspInit+0xb4>)
8001604: 6b1b ldr r3, [r3, #48] @ 0x30
8001606: f003 0304 and.w r3, r3, #4
800160a: 60fb str r3, [r7, #12]
800160c: 68fb ldr r3, [r7, #12]
/**USART6 GPIO Configuration
PC7 ------> USART6_RX
PC6 ------> USART6_TX
*/
GPIO_InitStruct.Pin = VCP_RX_Pin|VCP_TX_Pin;
800160e: 23c0 movs r3, #192 @ 0xc0
8001610: f8c7 3094 str.w r3, [r7, #148] @ 0x94
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001614: 2302 movs r3, #2
8001616: f8c7 3098 str.w r3, [r7, #152] @ 0x98
GPIO_InitStruct.Pull = GPIO_NOPULL;
800161a: 2300 movs r3, #0
800161c: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001620: 2303 movs r3, #3
8001622: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
8001626: 2308 movs r3, #8
8001628: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
800162c: f107 0394 add.w r3, r7, #148 @ 0x94
8001630: 4619 mov r1, r3
8001632: 4805 ldr r0, [pc, #20] @ (8001648 <HAL_UART_MspInit+0xb8>)
8001634: f000 fb3e bl 8001cb4 <HAL_GPIO_Init>
/* USER CODE END USART6_MspInit 1 */
}
}
8001638: bf00 nop
800163a: 37a8 adds r7, #168 @ 0xa8
800163c: 46bd mov sp, r7
800163e: bd80 pop {r7, pc}
8001640: 40011400 .word 0x40011400
8001644: 40023800 .word 0x40023800
8001648: 40020800 .word 0x40020800
0800164c <HAL_FMC_MspInit>:
}
static uint32_t FMC_Initialized = 0;
static void HAL_FMC_MspInit(void){
800164c: b580 push {r7, lr}
800164e: b086 sub sp, #24
8001650: af00 add r7, sp, #0
/* USER CODE BEGIN FMC_MspInit 0 */
/* USER CODE END FMC_MspInit 0 */
GPIO_InitTypeDef GPIO_InitStruct ={0};
8001652: 1d3b adds r3, r7, #4
8001654: 2200 movs r2, #0
8001656: 601a str r2, [r3, #0]
8001658: 605a str r2, [r3, #4]
800165a: 609a str r2, [r3, #8]
800165c: 60da str r2, [r3, #12]
800165e: 611a str r2, [r3, #16]
if (FMC_Initialized) {
8001660: 4b33 ldr r3, [pc, #204] @ (8001730 <HAL_FMC_MspInit+0xe4>)
8001662: 681b ldr r3, [r3, #0]
8001664: 2b00 cmp r3, #0
8001666: d15e bne.n 8001726 <HAL_FMC_MspInit+0xda>
return;
}
FMC_Initialized = 1;
8001668: 4b31 ldr r3, [pc, #196] @ (8001730 <HAL_FMC_MspInit+0xe4>)
800166a: 2201 movs r2, #1
800166c: 601a str r2, [r3, #0]
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_ENABLE();
800166e: 4b31 ldr r3, [pc, #196] @ (8001734 <HAL_FMC_MspInit+0xe8>)
8001670: 6b9b ldr r3, [r3, #56] @ 0x38
8001672: 4a30 ldr r2, [pc, #192] @ (8001734 <HAL_FMC_MspInit+0xe8>)
8001674: f043 0301 orr.w r3, r3, #1
8001678: 6393 str r3, [r2, #56] @ 0x38
800167a: 4b2e ldr r3, [pc, #184] @ (8001734 <HAL_FMC_MspInit+0xe8>)
800167c: 6b9b ldr r3, [r3, #56] @ 0x38
800167e: f003 0301 and.w r3, r3, #1
8001682: 603b str r3, [r7, #0]
8001684: 683b ldr r3, [r7, #0]
PE7 ------> FMC_D4
PE10 ------> FMC_D7
PE12 ------> FMC_D9
PE15 ------> FMC_D12
*/
GPIO_InitStruct.Pin = PSRAM_NBL1_Pin|PSRAM_NBL0_Pin|LCD_PSRAM_D10_Pin|LCD_PSRAM_D5_Pin
8001686: f64f 7383 movw r3, #65411 @ 0xff83
800168a: 607b str r3, [r7, #4]
|LCD_PSRAM_D6_Pin|LCD_PSRAM_D8_Pin|LCD_PSRAM_D11_Pin|LCD_PSRAM_D4_Pin
|LCD_PSRAM_D7_Pin|LCD_PSRAM_D9_Pin|LCD_PSRAM_D12_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800168c: 2302 movs r3, #2
800168e: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001690: 2300 movs r3, #0
8001692: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001694: 2303 movs r3, #3
8001696: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8001698: 230c movs r3, #12
800169a: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
800169c: 1d3b adds r3, r7, #4
800169e: 4619 mov r1, r3
80016a0: 4825 ldr r0, [pc, #148] @ (8001738 <HAL_FMC_MspInit+0xec>)
80016a2: f000 fb07 bl 8001cb4 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = PSRAM_NE1_Pin|LCD_PSRAM_D2_Pin|LCD_PSRAM_NWE_Pin|LCD_PSRAM_D3_Pin
80016a6: f64d 73b3 movw r3, #57267 @ 0xdfb3
80016aa: 607b str r3, [r7, #4]
|LCD_PSRAM_NWED4_Pin|LCD_PSRAM_D1_Pin|LCD_PSRAM_D0_Pin|PSRAM_A17_Pin
|PSRAM_A16_Pin|LCD_PSRAM_D15_Pin|LCD_PSRAM_D14_Pin|LCD_PSRAM_D13_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80016ac: 2302 movs r3, #2
80016ae: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80016b0: 2300 movs r3, #0
80016b2: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80016b4: 2303 movs r3, #3
80016b6: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80016b8: 230c movs r3, #12
80016ba: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
80016bc: 1d3b adds r3, r7, #4
80016be: 4619 mov r1, r3
80016c0: 481e ldr r0, [pc, #120] @ (800173c <HAL_FMC_MspInit+0xf0>)
80016c2: f000 faf7 bl 8001cb4 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = NC1_Pin;
80016c6: 2380 movs r3, #128 @ 0x80
80016c8: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80016ca: 2302 movs r3, #2
80016cc: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80016ce: 2300 movs r3, #0
80016d0: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80016d2: 2303 movs r3, #3
80016d4: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80016d6: 230c movs r3, #12
80016d8: 617b str r3, [r7, #20]
HAL_GPIO_Init(NC1_GPIO_Port, &GPIO_InitStruct);
80016da: 1d3b adds r3, r7, #4
80016dc: 4619 mov r1, r3
80016de: 4818 ldr r0, [pc, #96] @ (8001740 <HAL_FMC_MspInit+0xf4>)
80016e0: f000 fae8 bl 8001cb4 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_NE_Pin|PSRAM_A15_Pin|PSRAM_A14_Pin|PSRAM_A13_Pin
80016e4: f240 233f movw r3, #575 @ 0x23f
80016e8: 607b str r3, [r7, #4]
|PSRAM_A12_Pin|PSRAM_A11_Pin|PSRAM_A10_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80016ea: 2302 movs r3, #2
80016ec: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80016ee: 2300 movs r3, #0
80016f0: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80016f2: 2303 movs r3, #3
80016f4: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80016f6: 230c movs r3, #12
80016f8: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
80016fa: 1d3b adds r3, r7, #4
80016fc: 4619 mov r1, r3
80016fe: 4811 ldr r0, [pc, #68] @ (8001744 <HAL_FMC_MspInit+0xf8>)
8001700: f000 fad8 bl 8001cb4 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = PSRAM_A0_Pin|PSRAM_A2_Pin|PSRAM_A1_Pin|PSRAM_A3_Pin
8001704: f24f 033f movw r3, #61503 @ 0xf03f
8001708: 607b str r3, [r7, #4]
|PSRAM_A4_Pin|PSRAM_A5_Pin|PSRAM_A7_Pin|PSRAM_A6_Pin
|PSRAM_A9_Pin|PSRAM_A8_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800170a: 2302 movs r3, #2
800170c: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800170e: 2300 movs r3, #0
8001710: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001712: 2303 movs r3, #3
8001714: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8001716: 230c movs r3, #12
8001718: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
800171a: 1d3b adds r3, r7, #4
800171c: 4619 mov r1, r3
800171e: 480a ldr r0, [pc, #40] @ (8001748 <HAL_FMC_MspInit+0xfc>)
8001720: f000 fac8 bl 8001cb4 <HAL_GPIO_Init>
8001724: e000 b.n 8001728 <HAL_FMC_MspInit+0xdc>
return;
8001726: bf00 nop
/* USER CODE BEGIN FMC_MspInit 1 */
/* USER CODE END FMC_MspInit 1 */
}
8001728: 3718 adds r7, #24
800172a: 46bd mov sp, r7
800172c: bd80 pop {r7, pc}
800172e: bf00 nop
8001730: 200001ac .word 0x200001ac
8001734: 40023800 .word 0x40023800
8001738: 40021000 .word 0x40021000
800173c: 40020c00 .word 0x40020c00
8001740: 40020400 .word 0x40020400
8001744: 40021800 .word 0x40021800
8001748: 40021400 .word 0x40021400
0800174c <HAL_SRAM_MspInit>:
void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){
800174c: b580 push {r7, lr}
800174e: b082 sub sp, #8
8001750: af00 add r7, sp, #0
8001752: 6078 str r0, [r7, #4]
/* USER CODE BEGIN SRAM_MspInit 0 */
/* USER CODE END SRAM_MspInit 0 */
HAL_FMC_MspInit();
8001754: f7ff ff7a bl 800164c <HAL_FMC_MspInit>
/* USER CODE BEGIN SRAM_MspInit 1 */
/* USER CODE END SRAM_MspInit 1 */
}
8001758: bf00 nop
800175a: 3708 adds r7, #8
800175c: 46bd mov sp, r7
800175e: bd80 pop {r7, pc}
08001760 <HAL_InitTick>:
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001760: b580 push {r7, lr}
8001762: b08e sub sp, #56 @ 0x38
8001764: af00 add r7, sp, #0
8001766: 6078 str r0, [r7, #4]
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock, uwAPB1Prescaler = 0U;
8001768: 2300 movs r3, #0
800176a: 62fb str r3, [r7, #44] @ 0x2c
uint32_t uwPrescalerValue = 0U;
800176c: 2300 movs r3, #0
800176e: 62bb str r3, [r7, #40] @ 0x28
uint32_t pFLatency;
HAL_StatusTypeDef status;
/* Enable TIM14 clock */
__HAL_RCC_TIM14_CLK_ENABLE();
8001770: 4b33 ldr r3, [pc, #204] @ (8001840 <HAL_InitTick+0xe0>)
8001772: 6c1b ldr r3, [r3, #64] @ 0x40
8001774: 4a32 ldr r2, [pc, #200] @ (8001840 <HAL_InitTick+0xe0>)
8001776: f443 7380 orr.w r3, r3, #256 @ 0x100
800177a: 6413 str r3, [r2, #64] @ 0x40
800177c: 4b30 ldr r3, [pc, #192] @ (8001840 <HAL_InitTick+0xe0>)
800177e: 6c1b ldr r3, [r3, #64] @ 0x40
8001780: f403 7380 and.w r3, r3, #256 @ 0x100
8001784: 60fb str r3, [r7, #12]
8001786: 68fb ldr r3, [r7, #12]
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
8001788: f107 0210 add.w r2, r7, #16
800178c: f107 0314 add.w r3, r7, #20
8001790: 4611 mov r1, r2
8001792: 4618 mov r0, r3
8001794: f001 fa94 bl 8002cc0 <HAL_RCC_GetClockConfig>
/* Get APB1 prescaler */
uwAPB1Prescaler = clkconfig.APB1CLKDivider;
8001798: 6a3b ldr r3, [r7, #32]
800179a: 62fb str r3, [r7, #44] @ 0x2c
/* Compute TIM14 clock */
if (uwAPB1Prescaler == RCC_HCLK_DIV1)
800179c: 6afb ldr r3, [r7, #44] @ 0x2c
800179e: 2b00 cmp r3, #0
80017a0: d103 bne.n 80017aa <HAL_InitTick+0x4a>
{
uwTimclock = HAL_RCC_GetPCLK1Freq();
80017a2: f001 fa65 bl 8002c70 <HAL_RCC_GetPCLK1Freq>
80017a6: 6378 str r0, [r7, #52] @ 0x34
80017a8: e004 b.n 80017b4 <HAL_InitTick+0x54>
}
else
{
uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
80017aa: f001 fa61 bl 8002c70 <HAL_RCC_GetPCLK1Freq>
80017ae: 4603 mov r3, r0
80017b0: 005b lsls r3, r3, #1
80017b2: 637b str r3, [r7, #52] @ 0x34
}
/* Compute the prescaler value to have TIM14 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
80017b4: 6b7b ldr r3, [r7, #52] @ 0x34
80017b6: 4a23 ldr r2, [pc, #140] @ (8001844 <HAL_InitTick+0xe4>)
80017b8: fba2 2303 umull r2, r3, r2, r3
80017bc: 0c9b lsrs r3, r3, #18
80017be: 3b01 subs r3, #1
80017c0: 62bb str r3, [r7, #40] @ 0x28
/* Initialize TIM14 */
htim14.Instance = TIM14;
80017c2: 4b21 ldr r3, [pc, #132] @ (8001848 <HAL_InitTick+0xe8>)
80017c4: 4a21 ldr r2, [pc, #132] @ (800184c <HAL_InitTick+0xec>)
80017c6: 601a str r2, [r3, #0]
* Period = [(TIM14CLK/1000) - 1]. to have a (1/1000) s time base.
* Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
* ClockDivision = 0
* Counter direction = Up
*/
htim14.Init.Period = (1000000U / 1000U) - 1U;
80017c8: 4b1f ldr r3, [pc, #124] @ (8001848 <HAL_InitTick+0xe8>)
80017ca: f240 32e7 movw r2, #999 @ 0x3e7
80017ce: 60da str r2, [r3, #12]
htim14.Init.Prescaler = uwPrescalerValue;
80017d0: 4a1d ldr r2, [pc, #116] @ (8001848 <HAL_InitTick+0xe8>)
80017d2: 6abb ldr r3, [r7, #40] @ 0x28
80017d4: 6053 str r3, [r2, #4]
htim14.Init.ClockDivision = 0;
80017d6: 4b1c ldr r3, [pc, #112] @ (8001848 <HAL_InitTick+0xe8>)
80017d8: 2200 movs r2, #0
80017da: 611a str r2, [r3, #16]
htim14.Init.CounterMode = TIM_COUNTERMODE_UP;
80017dc: 4b1a ldr r3, [pc, #104] @ (8001848 <HAL_InitTick+0xe8>)
80017de: 2200 movs r2, #0
80017e0: 609a str r2, [r3, #8]
htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80017e2: 4b19 ldr r3, [pc, #100] @ (8001848 <HAL_InitTick+0xe8>)
80017e4: 2200 movs r2, #0
80017e6: 619a str r2, [r3, #24]
status = HAL_TIM_Base_Init(&htim14);
80017e8: 4817 ldr r0, [pc, #92] @ (8001848 <HAL_InitTick+0xe8>)
80017ea: f001 fe2d bl 8003448 <HAL_TIM_Base_Init>
80017ee: 4603 mov r3, r0
80017f0: f887 3033 strb.w r3, [r7, #51] @ 0x33
if (status == HAL_OK)
80017f4: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
80017f8: 2b00 cmp r3, #0
80017fa: d11b bne.n 8001834 <HAL_InitTick+0xd4>
{
/* Start the TIM time Base generation in interrupt mode */
status = HAL_TIM_Base_Start_IT(&htim14);
80017fc: 4812 ldr r0, [pc, #72] @ (8001848 <HAL_InitTick+0xe8>)
80017fe: f001 fe85 bl 800350c <HAL_TIM_Base_Start_IT>
8001802: 4603 mov r3, r0
8001804: f887 3033 strb.w r3, [r7, #51] @ 0x33
if (status == HAL_OK)
8001808: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
800180c: 2b00 cmp r3, #0
800180e: d111 bne.n 8001834 <HAL_InitTick+0xd4>
{
/* Enable the TIM14 global Interrupt */
HAL_NVIC_EnableIRQ(TIM8_TRG_COM_TIM14_IRQn);
8001810: 202d movs r0, #45 @ 0x2d
8001812: f000 fa41 bl 8001c98 <HAL_NVIC_EnableIRQ>
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001816: 687b ldr r3, [r7, #4]
8001818: 2b0f cmp r3, #15
800181a: d808 bhi.n 800182e <HAL_InitTick+0xce>
{
/* Configure the TIM IRQ priority */
HAL_NVIC_SetPriority(TIM8_TRG_COM_TIM14_IRQn, TickPriority, 0U);
800181c: 2200 movs r2, #0
800181e: 6879 ldr r1, [r7, #4]
8001820: 202d movs r0, #45 @ 0x2d
8001822: f000 fa1d bl 8001c60 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8001826: 4a0a ldr r2, [pc, #40] @ (8001850 <HAL_InitTick+0xf0>)
8001828: 687b ldr r3, [r7, #4]
800182a: 6013 str r3, [r2, #0]
800182c: e002 b.n 8001834 <HAL_InitTick+0xd4>
}
else
{
status = HAL_ERROR;
800182e: 2301 movs r3, #1
8001830: f887 3033 strb.w r3, [r7, #51] @ 0x33
}
}
}
/* Return function status */
return status;
8001834: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
}
8001838: 4618 mov r0, r3
800183a: 3738 adds r7, #56 @ 0x38
800183c: 46bd mov sp, r7
800183e: bd80 pop {r7, pc}
8001840: 40023800 .word 0x40023800
8001844: 431bde83 .word 0x431bde83
8001848: 200001b0 .word 0x200001b0
800184c: 40002000 .word 0x40002000
8001850: 20000004 .word 0x20000004
08001854 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001854: b480 push {r7}
8001856: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001858: bf00 nop
800185a: e7fd b.n 8001858 <NMI_Handler+0x4>
0800185c <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800185c: b480 push {r7}
800185e: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001860: bf00 nop
8001862: e7fd b.n 8001860 <HardFault_Handler+0x4>
08001864 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001864: b480 push {r7}
8001866: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001868: bf00 nop
800186a: e7fd b.n 8001868 <MemManage_Handler+0x4>
0800186c <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
800186c: b480 push {r7}
800186e: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8001870: bf00 nop
8001872: e7fd b.n 8001870 <BusFault_Handler+0x4>
08001874 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8001874: b480 push {r7}
8001876: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001878: bf00 nop
800187a: e7fd b.n 8001878 <UsageFault_Handler+0x4>
0800187c <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
800187c: b480 push {r7}
800187e: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8001880: bf00 nop
8001882: 46bd mov sp, r7
8001884: f85d 7b04 ldr.w r7, [sp], #4
8001888: 4770 bx lr
0800188a <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
800188a: b480 push {r7}
800188c: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
800188e: bf00 nop
8001890: 46bd mov sp, r7
8001892: f85d 7b04 ldr.w r7, [sp], #4
8001896: 4770 bx lr
08001898 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001898: b480 push {r7}
800189a: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
800189c: bf00 nop
800189e: 46bd mov sp, r7
80018a0: f85d 7b04 ldr.w r7, [sp], #4
80018a4: 4770 bx lr
080018a6 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80018a6: b480 push {r7}
80018a8: af00 add r7, sp, #0
/* USER CODE END SysTick_IRQn 0 */
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80018aa: bf00 nop
80018ac: 46bd mov sp, r7
80018ae: f85d 7b04 ldr.w r7, [sp], #4
80018b2: 4770 bx lr
080018b4 <TIM8_TRG_COM_TIM14_IRQHandler>:
/**
* @brief This function handles TIM8 trigger and commutation interrupts and TIM14 global interrupt.
*/
void TIM8_TRG_COM_TIM14_IRQHandler(void)
{
80018b4: b580 push {r7, lr}
80018b6: af00 add r7, sp, #0
/* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 0 */
/* USER CODE END TIM8_TRG_COM_TIM14_IRQn 0 */
HAL_TIM_IRQHandler(&htim14);
80018b8: 4802 ldr r0, [pc, #8] @ (80018c4 <TIM8_TRG_COM_TIM14_IRQHandler+0x10>)
80018ba: f001 fe9f bl 80035fc <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 1 */
/* USER CODE END TIM8_TRG_COM_TIM14_IRQn 1 */
}
80018be: bf00 nop
80018c0: bd80 pop {r7, pc}
80018c2: bf00 nop
80018c4: 200001b0 .word 0x200001b0
080018c8 <_read>:
_kill(status, -1);
while (1) {} /* Make sure we hang here */
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
80018c8: b580 push {r7, lr}
80018ca: b086 sub sp, #24
80018cc: af00 add r7, sp, #0
80018ce: 60f8 str r0, [r7, #12]
80018d0: 60b9 str r1, [r7, #8]
80018d2: 607a str r2, [r7, #4]
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
80018d4: 2300 movs r3, #0
80018d6: 617b str r3, [r7, #20]
80018d8: e00a b.n 80018f0 <_read+0x28>
{
*ptr++ = __io_getchar();
80018da: f3af 8000 nop.w
80018de: 4601 mov r1, r0
80018e0: 68bb ldr r3, [r7, #8]
80018e2: 1c5a adds r2, r3, #1
80018e4: 60ba str r2, [r7, #8]
80018e6: b2ca uxtb r2, r1
80018e8: 701a strb r2, [r3, #0]
for (DataIdx = 0; DataIdx < len; DataIdx++)
80018ea: 697b ldr r3, [r7, #20]
80018ec: 3301 adds r3, #1
80018ee: 617b str r3, [r7, #20]
80018f0: 697a ldr r2, [r7, #20]
80018f2: 687b ldr r3, [r7, #4]
80018f4: 429a cmp r2, r3
80018f6: dbf0 blt.n 80018da <_read+0x12>
}
return len;
80018f8: 687b ldr r3, [r7, #4]
}
80018fa: 4618 mov r0, r3
80018fc: 3718 adds r7, #24
80018fe: 46bd mov sp, r7
8001900: bd80 pop {r7, pc}
08001902 <_close>:
}
return len;
}
int _close(int file)
{
8001902: b480 push {r7}
8001904: b083 sub sp, #12
8001906: af00 add r7, sp, #0
8001908: 6078 str r0, [r7, #4]
(void)file;
return -1;
800190a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
}
800190e: 4618 mov r0, r3
8001910: 370c adds r7, #12
8001912: 46bd mov sp, r7
8001914: f85d 7b04 ldr.w r7, [sp], #4
8001918: 4770 bx lr
0800191a <_fstat>:
int _fstat(int file, struct stat *st)
{
800191a: b480 push {r7}
800191c: b083 sub sp, #12
800191e: af00 add r7, sp, #0
8001920: 6078 str r0, [r7, #4]
8001922: 6039 str r1, [r7, #0]
(void)file;
st->st_mode = S_IFCHR;
8001924: 683b ldr r3, [r7, #0]
8001926: f44f 5200 mov.w r2, #8192 @ 0x2000
800192a: 605a str r2, [r3, #4]
return 0;
800192c: 2300 movs r3, #0
}
800192e: 4618 mov r0, r3
8001930: 370c adds r7, #12
8001932: 46bd mov sp, r7
8001934: f85d 7b04 ldr.w r7, [sp], #4
8001938: 4770 bx lr
0800193a <_isatty>:
int _isatty(int file)
{
800193a: b480 push {r7}
800193c: b083 sub sp, #12
800193e: af00 add r7, sp, #0
8001940: 6078 str r0, [r7, #4]
(void)file;
return 1;
8001942: 2301 movs r3, #1
}
8001944: 4618 mov r0, r3
8001946: 370c adds r7, #12
8001948: 46bd mov sp, r7
800194a: f85d 7b04 ldr.w r7, [sp], #4
800194e: 4770 bx lr
08001950 <_lseek>:
int _lseek(int file, int ptr, int dir)
{
8001950: b480 push {r7}
8001952: b085 sub sp, #20
8001954: af00 add r7, sp, #0
8001956: 60f8 str r0, [r7, #12]
8001958: 60b9 str r1, [r7, #8]
800195a: 607a str r2, [r7, #4]
(void)file;
(void)ptr;
(void)dir;
return 0;
800195c: 2300 movs r3, #0
}
800195e: 4618 mov r0, r3
8001960: 3714 adds r7, #20
8001962: 46bd mov sp, r7
8001964: f85d 7b04 ldr.w r7, [sp], #4
8001968: 4770 bx lr
...
0800196c <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
800196c: b580 push {r7, lr}
800196e: b086 sub sp, #24
8001970: af00 add r7, sp, #0
8001972: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
8001974: 4a14 ldr r2, [pc, #80] @ (80019c8 <_sbrk+0x5c>)
8001976: 4b15 ldr r3, [pc, #84] @ (80019cc <_sbrk+0x60>)
8001978: 1ad3 subs r3, r2, r3
800197a: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
800197c: 697b ldr r3, [r7, #20]
800197e: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
8001980: 4b13 ldr r3, [pc, #76] @ (80019d0 <_sbrk+0x64>)
8001982: 681b ldr r3, [r3, #0]
8001984: 2b00 cmp r3, #0
8001986: d102 bne.n 800198e <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
8001988: 4b11 ldr r3, [pc, #68] @ (80019d0 <_sbrk+0x64>)
800198a: 4a12 ldr r2, [pc, #72] @ (80019d4 <_sbrk+0x68>)
800198c: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
800198e: 4b10 ldr r3, [pc, #64] @ (80019d0 <_sbrk+0x64>)
8001990: 681a ldr r2, [r3, #0]
8001992: 687b ldr r3, [r7, #4]
8001994: 4413 add r3, r2
8001996: 693a ldr r2, [r7, #16]
8001998: 429a cmp r2, r3
800199a: d207 bcs.n 80019ac <_sbrk+0x40>
{
errno = ENOMEM;
800199c: f002 ffa0 bl 80048e0 <__errno>
80019a0: 4603 mov r3, r0
80019a2: 220c movs r2, #12
80019a4: 601a str r2, [r3, #0]
return (void *)-1;
80019a6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
80019aa: e009 b.n 80019c0 <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
80019ac: 4b08 ldr r3, [pc, #32] @ (80019d0 <_sbrk+0x64>)
80019ae: 681b ldr r3, [r3, #0]
80019b0: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
80019b2: 4b07 ldr r3, [pc, #28] @ (80019d0 <_sbrk+0x64>)
80019b4: 681a ldr r2, [r3, #0]
80019b6: 687b ldr r3, [r7, #4]
80019b8: 4413 add r3, r2
80019ba: 4a05 ldr r2, [pc, #20] @ (80019d0 <_sbrk+0x64>)
80019bc: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
80019be: 68fb ldr r3, [r7, #12]
}
80019c0: 4618 mov r0, r3
80019c2: 3718 adds r7, #24
80019c4: 46bd mov sp, r7
80019c6: bd80 pop {r7, pc}
80019c8: 20040000 .word 0x20040000
80019cc: 00000400 .word 0x00000400
80019d0: 200001fc .word 0x200001fc
80019d4: 20000350 .word 0x20000350
080019d8 <SystemInit>:
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
80019d8: b480 push {r7}
80019da: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
80019dc: 4b06 ldr r3, [pc, #24] @ (80019f8 <SystemInit+0x20>)
80019de: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80019e2: 4a05 ldr r2, [pc, #20] @ (80019f8 <SystemInit+0x20>)
80019e4: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
80019e8: f8c2 3088 str.w r3, [r2, #136] @ 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
80019ec: bf00 nop
80019ee: 46bd mov sp, r7
80019f0: f85d 7b04 ldr.w r7, [sp], #4
80019f4: 4770 bx lr
80019f6: bf00 nop
80019f8: e000ed00 .word 0xe000ed00
080019fc <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
80019fc: f8df d034 ldr.w sp, [pc, #52] @ 8001a34 <LoopFillZerobss+0xe>
/* Call the clock system initialization function.*/
bl SystemInit
8001a00: f7ff ffea bl 80019d8 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8001a04: 480c ldr r0, [pc, #48] @ (8001a38 <LoopFillZerobss+0x12>)
ldr r1, =_edata
8001a06: 490d ldr r1, [pc, #52] @ (8001a3c <LoopFillZerobss+0x16>)
ldr r2, =_sidata
8001a08: 4a0d ldr r2, [pc, #52] @ (8001a40 <LoopFillZerobss+0x1a>)
movs r3, #0
8001a0a: 2300 movs r3, #0
b LoopCopyDataInit
8001a0c: e002 b.n 8001a14 <LoopCopyDataInit>
08001a0e <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8001a0e: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8001a10: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8001a12: 3304 adds r3, #4
08001a14 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8001a14: 18c4 adds r4, r0, r3
cmp r4, r1
8001a16: 428c cmp r4, r1
bcc CopyDataInit
8001a18: d3f9 bcc.n 8001a0e <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8001a1a: 4a0a ldr r2, [pc, #40] @ (8001a44 <LoopFillZerobss+0x1e>)
ldr r4, =_ebss
8001a1c: 4c0a ldr r4, [pc, #40] @ (8001a48 <LoopFillZerobss+0x22>)
movs r3, #0
8001a1e: 2300 movs r3, #0
b LoopFillZerobss
8001a20: e001 b.n 8001a26 <LoopFillZerobss>
08001a22 <FillZerobss>:
FillZerobss:
str r3, [r2]
8001a22: 6013 str r3, [r2, #0]
adds r2, r2, #4
8001a24: 3204 adds r2, #4
08001a26 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8001a26: 42a2 cmp r2, r4
bcc FillZerobss
8001a28: d3fb bcc.n 8001a22 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8001a2a: f002 ff5f bl 80048ec <__libc_init_array>
/* Call the application's entry point.*/
bl main
8001a2e: f7fe ffd5 bl 80009dc <main>
bx lr
8001a32: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8001a34: 20040000 .word 0x20040000
ldr r0, =_sdata
8001a38: 20000000 .word 0x20000000
ldr r1, =_edata
8001a3c: 20000068 .word 0x20000068
ldr r2, =_sidata
8001a40: 08005558 .word 0x08005558
ldr r2, =_sbss
8001a44: 20000068 .word 0x20000068
ldr r4, =_ebss
8001a48: 20000350 .word 0x20000350
08001a4c <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001a4c: e7fe b.n 8001a4c <ADC_IRQHandler>
08001a4e <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8001a4e: b580 push {r7, lr}
8001a50: af00 add r7, sp, #0
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8001a52: 2003 movs r0, #3
8001a54: f000 f8f9 bl 8001c4a <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8001a58: 200f movs r0, #15
8001a5a: f7ff fe81 bl 8001760 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8001a5e: f7ff fcef bl 8001440 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8001a62: 2300 movs r3, #0
}
8001a64: 4618 mov r0, r3
8001a66: bd80 pop {r7, pc}
08001a68 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001a68: b480 push {r7}
8001a6a: af00 add r7, sp, #0
uwTick += uwTickFreq;
8001a6c: 4b06 ldr r3, [pc, #24] @ (8001a88 <HAL_IncTick+0x20>)
8001a6e: 781b ldrb r3, [r3, #0]
8001a70: 461a mov r2, r3
8001a72: 4b06 ldr r3, [pc, #24] @ (8001a8c <HAL_IncTick+0x24>)
8001a74: 681b ldr r3, [r3, #0]
8001a76: 4413 add r3, r2
8001a78: 4a04 ldr r2, [pc, #16] @ (8001a8c <HAL_IncTick+0x24>)
8001a7a: 6013 str r3, [r2, #0]
}
8001a7c: bf00 nop
8001a7e: 46bd mov sp, r7
8001a80: f85d 7b04 ldr.w r7, [sp], #4
8001a84: 4770 bx lr
8001a86: bf00 nop
8001a88: 20000008 .word 0x20000008
8001a8c: 20000200 .word 0x20000200
08001a90 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8001a90: b480 push {r7}
8001a92: af00 add r7, sp, #0
return uwTick;
8001a94: 4b03 ldr r3, [pc, #12] @ (8001aa4 <HAL_GetTick+0x14>)
8001a96: 681b ldr r3, [r3, #0]
}
8001a98: 4618 mov r0, r3
8001a9a: 46bd mov sp, r7
8001a9c: f85d 7b04 ldr.w r7, [sp], #4
8001aa0: 4770 bx lr
8001aa2: bf00 nop
8001aa4: 20000200 .word 0x20000200
08001aa8 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8001aa8: b580 push {r7, lr}
8001aaa: b084 sub sp, #16
8001aac: af00 add r7, sp, #0
8001aae: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8001ab0: f7ff ffee bl 8001a90 <HAL_GetTick>
8001ab4: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8001ab6: 687b ldr r3, [r7, #4]
8001ab8: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8001aba: 68fb ldr r3, [r7, #12]
8001abc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8001ac0: d005 beq.n 8001ace <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8001ac2: 4b0a ldr r3, [pc, #40] @ (8001aec <HAL_Delay+0x44>)
8001ac4: 781b ldrb r3, [r3, #0]
8001ac6: 461a mov r2, r3
8001ac8: 68fb ldr r3, [r7, #12]
8001aca: 4413 add r3, r2
8001acc: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
8001ace: bf00 nop
8001ad0: f7ff ffde bl 8001a90 <HAL_GetTick>
8001ad4: 4602 mov r2, r0
8001ad6: 68bb ldr r3, [r7, #8]
8001ad8: 1ad3 subs r3, r2, r3
8001ada: 68fa ldr r2, [r7, #12]
8001adc: 429a cmp r2, r3
8001ade: d8f7 bhi.n 8001ad0 <HAL_Delay+0x28>
{
}
}
8001ae0: bf00 nop
8001ae2: bf00 nop
8001ae4: 3710 adds r7, #16
8001ae6: 46bd mov sp, r7
8001ae8: bd80 pop {r7, pc}
8001aea: bf00 nop
8001aec: 20000008 .word 0x20000008
08001af0 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001af0: b480 push {r7}
8001af2: b085 sub sp, #20
8001af4: af00 add r7, sp, #0
8001af6: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8001af8: 687b ldr r3, [r7, #4]
8001afa: f003 0307 and.w r3, r3, #7
8001afe: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8001b00: 4b0b ldr r3, [pc, #44] @ (8001b30 <__NVIC_SetPriorityGrouping+0x40>)
8001b02: 68db ldr r3, [r3, #12]
8001b04: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8001b06: 68ba ldr r2, [r7, #8]
8001b08: f64f 03ff movw r3, #63743 @ 0xf8ff
8001b0c: 4013 ands r3, r2
8001b0e: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8001b10: 68fb ldr r3, [r7, #12]
8001b12: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8001b14: 68bb ldr r3, [r7, #8]
8001b16: 431a orrs r2, r3
reg_value = (reg_value |
8001b18: 4b06 ldr r3, [pc, #24] @ (8001b34 <__NVIC_SetPriorityGrouping+0x44>)
8001b1a: 4313 orrs r3, r2
8001b1c: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8001b1e: 4a04 ldr r2, [pc, #16] @ (8001b30 <__NVIC_SetPriorityGrouping+0x40>)
8001b20: 68bb ldr r3, [r7, #8]
8001b22: 60d3 str r3, [r2, #12]
}
8001b24: bf00 nop
8001b26: 3714 adds r7, #20
8001b28: 46bd mov sp, r7
8001b2a: f85d 7b04 ldr.w r7, [sp], #4
8001b2e: 4770 bx lr
8001b30: e000ed00 .word 0xe000ed00
8001b34: 05fa0000 .word 0x05fa0000
08001b38 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8001b38: b480 push {r7}
8001b3a: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8001b3c: 4b04 ldr r3, [pc, #16] @ (8001b50 <__NVIC_GetPriorityGrouping+0x18>)
8001b3e: 68db ldr r3, [r3, #12]
8001b40: 0a1b lsrs r3, r3, #8
8001b42: f003 0307 and.w r3, r3, #7
}
8001b46: 4618 mov r0, r3
8001b48: 46bd mov sp, r7
8001b4a: f85d 7b04 ldr.w r7, [sp], #4
8001b4e: 4770 bx lr
8001b50: e000ed00 .word 0xe000ed00
08001b54 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8001b54: b480 push {r7}
8001b56: b083 sub sp, #12
8001b58: af00 add r7, sp, #0
8001b5a: 4603 mov r3, r0
8001b5c: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001b5e: f997 3007 ldrsb.w r3, [r7, #7]
8001b62: 2b00 cmp r3, #0
8001b64: db0b blt.n 8001b7e <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8001b66: 79fb ldrb r3, [r7, #7]
8001b68: f003 021f and.w r2, r3, #31
8001b6c: 4907 ldr r1, [pc, #28] @ (8001b8c <__NVIC_EnableIRQ+0x38>)
8001b6e: f997 3007 ldrsb.w r3, [r7, #7]
8001b72: 095b lsrs r3, r3, #5
8001b74: 2001 movs r0, #1
8001b76: fa00 f202 lsl.w r2, r0, r2
8001b7a: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8001b7e: bf00 nop
8001b80: 370c adds r7, #12
8001b82: 46bd mov sp, r7
8001b84: f85d 7b04 ldr.w r7, [sp], #4
8001b88: 4770 bx lr
8001b8a: bf00 nop
8001b8c: e000e100 .word 0xe000e100
08001b90 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001b90: b480 push {r7}
8001b92: b083 sub sp, #12
8001b94: af00 add r7, sp, #0
8001b96: 4603 mov r3, r0
8001b98: 6039 str r1, [r7, #0]
8001b9a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001b9c: f997 3007 ldrsb.w r3, [r7, #7]
8001ba0: 2b00 cmp r3, #0
8001ba2: db0a blt.n 8001bba <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001ba4: 683b ldr r3, [r7, #0]
8001ba6: b2da uxtb r2, r3
8001ba8: 490c ldr r1, [pc, #48] @ (8001bdc <__NVIC_SetPriority+0x4c>)
8001baa: f997 3007 ldrsb.w r3, [r7, #7]
8001bae: 0112 lsls r2, r2, #4
8001bb0: b2d2 uxtb r2, r2
8001bb2: 440b add r3, r1
8001bb4: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8001bb8: e00a b.n 8001bd0 <__NVIC_SetPriority+0x40>
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001bba: 683b ldr r3, [r7, #0]
8001bbc: b2da uxtb r2, r3
8001bbe: 4908 ldr r1, [pc, #32] @ (8001be0 <__NVIC_SetPriority+0x50>)
8001bc0: 79fb ldrb r3, [r7, #7]
8001bc2: f003 030f and.w r3, r3, #15
8001bc6: 3b04 subs r3, #4
8001bc8: 0112 lsls r2, r2, #4
8001bca: b2d2 uxtb r2, r2
8001bcc: 440b add r3, r1
8001bce: 761a strb r2, [r3, #24]
}
8001bd0: bf00 nop
8001bd2: 370c adds r7, #12
8001bd4: 46bd mov sp, r7
8001bd6: f85d 7b04 ldr.w r7, [sp], #4
8001bda: 4770 bx lr
8001bdc: e000e100 .word 0xe000e100
8001be0: e000ed00 .word 0xe000ed00
08001be4 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001be4: b480 push {r7}
8001be6: b089 sub sp, #36 @ 0x24
8001be8: af00 add r7, sp, #0
8001bea: 60f8 str r0, [r7, #12]
8001bec: 60b9 str r1, [r7, #8]
8001bee: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8001bf0: 68fb ldr r3, [r7, #12]
8001bf2: f003 0307 and.w r3, r3, #7
8001bf6: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8001bf8: 69fb ldr r3, [r7, #28]
8001bfa: f1c3 0307 rsb r3, r3, #7
8001bfe: 2b04 cmp r3, #4
8001c00: bf28 it cs
8001c02: 2304 movcs r3, #4
8001c04: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8001c06: 69fb ldr r3, [r7, #28]
8001c08: 3304 adds r3, #4
8001c0a: 2b06 cmp r3, #6
8001c0c: d902 bls.n 8001c14 <NVIC_EncodePriority+0x30>
8001c0e: 69fb ldr r3, [r7, #28]
8001c10: 3b03 subs r3, #3
8001c12: e000 b.n 8001c16 <NVIC_EncodePriority+0x32>
8001c14: 2300 movs r3, #0
8001c16: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001c18: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8001c1c: 69bb ldr r3, [r7, #24]
8001c1e: fa02 f303 lsl.w r3, r2, r3
8001c22: 43da mvns r2, r3
8001c24: 68bb ldr r3, [r7, #8]
8001c26: 401a ands r2, r3
8001c28: 697b ldr r3, [r7, #20]
8001c2a: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8001c2c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
8001c30: 697b ldr r3, [r7, #20]
8001c32: fa01 f303 lsl.w r3, r1, r3
8001c36: 43d9 mvns r1, r3
8001c38: 687b ldr r3, [r7, #4]
8001c3a: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001c3c: 4313 orrs r3, r2
);
}
8001c3e: 4618 mov r0, r3
8001c40: 3724 adds r7, #36 @ 0x24
8001c42: 46bd mov sp, r7
8001c44: f85d 7b04 ldr.w r7, [sp], #4
8001c48: 4770 bx lr
08001c4a <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001c4a: b580 push {r7, lr}
8001c4c: b082 sub sp, #8
8001c4e: af00 add r7, sp, #0
8001c50: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8001c52: 6878 ldr r0, [r7, #4]
8001c54: f7ff ff4c bl 8001af0 <__NVIC_SetPriorityGrouping>
}
8001c58: bf00 nop
8001c5a: 3708 adds r7, #8
8001c5c: 46bd mov sp, r7
8001c5e: bd80 pop {r7, pc}
08001c60 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001c60: b580 push {r7, lr}
8001c62: b086 sub sp, #24
8001c64: af00 add r7, sp, #0
8001c66: 4603 mov r3, r0
8001c68: 60b9 str r1, [r7, #8]
8001c6a: 607a str r2, [r7, #4]
8001c6c: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
8001c6e: 2300 movs r3, #0
8001c70: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8001c72: f7ff ff61 bl 8001b38 <__NVIC_GetPriorityGrouping>
8001c76: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8001c78: 687a ldr r2, [r7, #4]
8001c7a: 68b9 ldr r1, [r7, #8]
8001c7c: 6978 ldr r0, [r7, #20]
8001c7e: f7ff ffb1 bl 8001be4 <NVIC_EncodePriority>
8001c82: 4602 mov r2, r0
8001c84: f997 300f ldrsb.w r3, [r7, #15]
8001c88: 4611 mov r1, r2
8001c8a: 4618 mov r0, r3
8001c8c: f7ff ff80 bl 8001b90 <__NVIC_SetPriority>
}
8001c90: bf00 nop
8001c92: 3718 adds r7, #24
8001c94: 46bd mov sp, r7
8001c96: bd80 pop {r7, pc}
08001c98 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8001c98: b580 push {r7, lr}
8001c9a: b082 sub sp, #8
8001c9c: af00 add r7, sp, #0
8001c9e: 4603 mov r3, r0
8001ca0: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8001ca2: f997 3007 ldrsb.w r3, [r7, #7]
8001ca6: 4618 mov r0, r3
8001ca8: f7ff ff54 bl 8001b54 <__NVIC_EnableIRQ>
}
8001cac: bf00 nop
8001cae: 3708 adds r7, #8
8001cb0: 46bd mov sp, r7
8001cb2: bd80 pop {r7, pc}
08001cb4 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8001cb4: b480 push {r7}
8001cb6: b089 sub sp, #36 @ 0x24
8001cb8: af00 add r7, sp, #0
8001cba: 6078 str r0, [r7, #4]
8001cbc: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
8001cbe: 2300 movs r3, #0
8001cc0: 61fb str r3, [r7, #28]
uint32_t ioposition = 0x00;
8001cc2: 2300 movs r3, #0
8001cc4: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
8001cc6: 2300 movs r3, #0
8001cc8: 613b str r3, [r7, #16]
uint32_t temp = 0x00;
8001cca: 2300 movs r3, #0
8001ccc: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for (position = 0; position < GPIO_NUMBER; position++)
8001cce: 2300 movs r3, #0
8001cd0: 61fb str r3, [r7, #28]
8001cd2: e169 b.n 8001fa8 <HAL_GPIO_Init+0x2f4>
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
8001cd4: 2201 movs r2, #1
8001cd6: 69fb ldr r3, [r7, #28]
8001cd8: fa02 f303 lsl.w r3, r2, r3
8001cdc: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8001cde: 683b ldr r3, [r7, #0]
8001ce0: 681b ldr r3, [r3, #0]
8001ce2: 697a ldr r2, [r7, #20]
8001ce4: 4013 ands r3, r2
8001ce6: 613b str r3, [r7, #16]
if (iocurrent == ioposition)
8001ce8: 693a ldr r2, [r7, #16]
8001cea: 697b ldr r3, [r7, #20]
8001cec: 429a cmp r2, r3
8001cee: f040 8158 bne.w 8001fa2 <HAL_GPIO_Init+0x2ee>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8001cf2: 683b ldr r3, [r7, #0]
8001cf4: 685b ldr r3, [r3, #4]
8001cf6: f003 0303 and.w r3, r3, #3
8001cfa: 2b01 cmp r3, #1
8001cfc: d005 beq.n 8001d0a <HAL_GPIO_Init+0x56>
8001cfe: 683b ldr r3, [r7, #0]
8001d00: 685b ldr r3, [r3, #4]
8001d02: f003 0303 and.w r3, r3, #3
8001d06: 2b02 cmp r3, #2
8001d08: d130 bne.n 8001d6c <HAL_GPIO_Init+0xb8>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001d0a: 687b ldr r3, [r7, #4]
8001d0c: 689b ldr r3, [r3, #8]
8001d0e: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
8001d10: 69fb ldr r3, [r7, #28]
8001d12: 005b lsls r3, r3, #1
8001d14: 2203 movs r2, #3
8001d16: fa02 f303 lsl.w r3, r2, r3
8001d1a: 43db mvns r3, r3
8001d1c: 69ba ldr r2, [r7, #24]
8001d1e: 4013 ands r3, r2
8001d20: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2));
8001d22: 683b ldr r3, [r7, #0]
8001d24: 68da ldr r2, [r3, #12]
8001d26: 69fb ldr r3, [r7, #28]
8001d28: 005b lsls r3, r3, #1
8001d2a: fa02 f303 lsl.w r3, r2, r3
8001d2e: 69ba ldr r2, [r7, #24]
8001d30: 4313 orrs r3, r2
8001d32: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8001d34: 687b ldr r3, [r7, #4]
8001d36: 69ba ldr r2, [r7, #24]
8001d38: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001d3a: 687b ldr r3, [r7, #4]
8001d3c: 685b ldr r3, [r3, #4]
8001d3e: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8001d40: 2201 movs r2, #1
8001d42: 69fb ldr r3, [r7, #28]
8001d44: fa02 f303 lsl.w r3, r2, r3
8001d48: 43db mvns r3, r3
8001d4a: 69ba ldr r2, [r7, #24]
8001d4c: 4013 ands r3, r2
8001d4e: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8001d50: 683b ldr r3, [r7, #0]
8001d52: 685b ldr r3, [r3, #4]
8001d54: 091b lsrs r3, r3, #4
8001d56: f003 0201 and.w r2, r3, #1
8001d5a: 69fb ldr r3, [r7, #28]
8001d5c: fa02 f303 lsl.w r3, r2, r3
8001d60: 69ba ldr r2, [r7, #24]
8001d62: 4313 orrs r3, r2
8001d64: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
8001d66: 687b ldr r3, [r7, #4]
8001d68: 69ba ldr r2, [r7, #24]
8001d6a: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8001d6c: 683b ldr r3, [r7, #0]
8001d6e: 685b ldr r3, [r3, #4]
8001d70: f003 0303 and.w r3, r3, #3
8001d74: 2b03 cmp r3, #3
8001d76: d017 beq.n 8001da8 <HAL_GPIO_Init+0xf4>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8001d78: 687b ldr r3, [r7, #4]
8001d7a: 68db ldr r3, [r3, #12]
8001d7c: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
8001d7e: 69fb ldr r3, [r7, #28]
8001d80: 005b lsls r3, r3, #1
8001d82: 2203 movs r2, #3
8001d84: fa02 f303 lsl.w r3, r2, r3
8001d88: 43db mvns r3, r3
8001d8a: 69ba ldr r2, [r7, #24]
8001d8c: 4013 ands r3, r2
8001d8e: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2));
8001d90: 683b ldr r3, [r7, #0]
8001d92: 689a ldr r2, [r3, #8]
8001d94: 69fb ldr r3, [r7, #28]
8001d96: 005b lsls r3, r3, #1
8001d98: fa02 f303 lsl.w r3, r2, r3
8001d9c: 69ba ldr r2, [r7, #24]
8001d9e: 4313 orrs r3, r2
8001da0: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
8001da2: 687b ldr r3, [r7, #4]
8001da4: 69ba ldr r2, [r7, #24]
8001da6: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001da8: 683b ldr r3, [r7, #0]
8001daa: 685b ldr r3, [r3, #4]
8001dac: f003 0303 and.w r3, r3, #3
8001db0: 2b02 cmp r3, #2
8001db2: d123 bne.n 8001dfc <HAL_GPIO_Init+0x148>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
8001db4: 69fb ldr r3, [r7, #28]
8001db6: 08da lsrs r2, r3, #3
8001db8: 687b ldr r3, [r7, #4]
8001dba: 3208 adds r2, #8
8001dbc: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8001dc0: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
8001dc2: 69fb ldr r3, [r7, #28]
8001dc4: f003 0307 and.w r3, r3, #7
8001dc8: 009b lsls r3, r3, #2
8001dca: 220f movs r2, #15
8001dcc: fa02 f303 lsl.w r3, r2, r3
8001dd0: 43db mvns r3, r3
8001dd2: 69ba ldr r2, [r7, #24]
8001dd4: 4013 ands r3, r2
8001dd6: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
8001dd8: 683b ldr r3, [r7, #0]
8001dda: 691a ldr r2, [r3, #16]
8001ddc: 69fb ldr r3, [r7, #28]
8001dde: f003 0307 and.w r3, r3, #7
8001de2: 009b lsls r3, r3, #2
8001de4: fa02 f303 lsl.w r3, r2, r3
8001de8: 69ba ldr r2, [r7, #24]
8001dea: 4313 orrs r3, r2
8001dec: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3] = temp;
8001dee: 69fb ldr r3, [r7, #28]
8001df0: 08da lsrs r2, r3, #3
8001df2: 687b ldr r3, [r7, #4]
8001df4: 3208 adds r2, #8
8001df6: 69b9 ldr r1, [r7, #24]
8001df8: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8001dfc: 687b ldr r3, [r7, #4]
8001dfe: 681b ldr r3, [r3, #0]
8001e00: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
8001e02: 69fb ldr r3, [r7, #28]
8001e04: 005b lsls r3, r3, #1
8001e06: 2203 movs r2, #3
8001e08: fa02 f303 lsl.w r3, r2, r3
8001e0c: 43db mvns r3, r3
8001e0e: 69ba ldr r2, [r7, #24]
8001e10: 4013 ands r3, r2
8001e12: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
8001e14: 683b ldr r3, [r7, #0]
8001e16: 685b ldr r3, [r3, #4]
8001e18: f003 0203 and.w r2, r3, #3
8001e1c: 69fb ldr r3, [r7, #28]
8001e1e: 005b lsls r3, r3, #1
8001e20: fa02 f303 lsl.w r3, r2, r3
8001e24: 69ba ldr r2, [r7, #24]
8001e26: 4313 orrs r3, r2
8001e28: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8001e2a: 687b ldr r3, [r7, #4]
8001e2c: 69ba ldr r2, [r7, #24]
8001e2e: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8001e30: 683b ldr r3, [r7, #0]
8001e32: 685b ldr r3, [r3, #4]
8001e34: f403 3340 and.w r3, r3, #196608 @ 0x30000
8001e38: 2b00 cmp r3, #0
8001e3a: f000 80b2 beq.w 8001fa2 <HAL_GPIO_Init+0x2ee>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001e3e: 4b60 ldr r3, [pc, #384] @ (8001fc0 <HAL_GPIO_Init+0x30c>)
8001e40: 6c5b ldr r3, [r3, #68] @ 0x44
8001e42: 4a5f ldr r2, [pc, #380] @ (8001fc0 <HAL_GPIO_Init+0x30c>)
8001e44: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8001e48: 6453 str r3, [r2, #68] @ 0x44
8001e4a: 4b5d ldr r3, [pc, #372] @ (8001fc0 <HAL_GPIO_Init+0x30c>)
8001e4c: 6c5b ldr r3, [r3, #68] @ 0x44
8001e4e: f403 4380 and.w r3, r3, #16384 @ 0x4000
8001e52: 60fb str r3, [r7, #12]
8001e54: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2];
8001e56: 4a5b ldr r2, [pc, #364] @ (8001fc4 <HAL_GPIO_Init+0x310>)
8001e58: 69fb ldr r3, [r7, #28]
8001e5a: 089b lsrs r3, r3, #2
8001e5c: 3302 adds r3, #2
8001e5e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001e62: 61bb str r3, [r7, #24]
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
8001e64: 69fb ldr r3, [r7, #28]
8001e66: f003 0303 and.w r3, r3, #3
8001e6a: 009b lsls r3, r3, #2
8001e6c: 220f movs r2, #15
8001e6e: fa02 f303 lsl.w r3, r2, r3
8001e72: 43db mvns r3, r3
8001e74: 69ba ldr r2, [r7, #24]
8001e76: 4013 ands r3, r2
8001e78: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
8001e7a: 687b ldr r3, [r7, #4]
8001e7c: 4a52 ldr r2, [pc, #328] @ (8001fc8 <HAL_GPIO_Init+0x314>)
8001e7e: 4293 cmp r3, r2
8001e80: d02b beq.n 8001eda <HAL_GPIO_Init+0x226>
8001e82: 687b ldr r3, [r7, #4]
8001e84: 4a51 ldr r2, [pc, #324] @ (8001fcc <HAL_GPIO_Init+0x318>)
8001e86: 4293 cmp r3, r2
8001e88: d025 beq.n 8001ed6 <HAL_GPIO_Init+0x222>
8001e8a: 687b ldr r3, [r7, #4]
8001e8c: 4a50 ldr r2, [pc, #320] @ (8001fd0 <HAL_GPIO_Init+0x31c>)
8001e8e: 4293 cmp r3, r2
8001e90: d01f beq.n 8001ed2 <HAL_GPIO_Init+0x21e>
8001e92: 687b ldr r3, [r7, #4]
8001e94: 4a4f ldr r2, [pc, #316] @ (8001fd4 <HAL_GPIO_Init+0x320>)
8001e96: 4293 cmp r3, r2
8001e98: d019 beq.n 8001ece <HAL_GPIO_Init+0x21a>
8001e9a: 687b ldr r3, [r7, #4]
8001e9c: 4a4e ldr r2, [pc, #312] @ (8001fd8 <HAL_GPIO_Init+0x324>)
8001e9e: 4293 cmp r3, r2
8001ea0: d013 beq.n 8001eca <HAL_GPIO_Init+0x216>
8001ea2: 687b ldr r3, [r7, #4]
8001ea4: 4a4d ldr r2, [pc, #308] @ (8001fdc <HAL_GPIO_Init+0x328>)
8001ea6: 4293 cmp r3, r2
8001ea8: d00d beq.n 8001ec6 <HAL_GPIO_Init+0x212>
8001eaa: 687b ldr r3, [r7, #4]
8001eac: 4a4c ldr r2, [pc, #304] @ (8001fe0 <HAL_GPIO_Init+0x32c>)
8001eae: 4293 cmp r3, r2
8001eb0: d007 beq.n 8001ec2 <HAL_GPIO_Init+0x20e>
8001eb2: 687b ldr r3, [r7, #4]
8001eb4: 4a4b ldr r2, [pc, #300] @ (8001fe4 <HAL_GPIO_Init+0x330>)
8001eb6: 4293 cmp r3, r2
8001eb8: d101 bne.n 8001ebe <HAL_GPIO_Init+0x20a>
8001eba: 2307 movs r3, #7
8001ebc: e00e b.n 8001edc <HAL_GPIO_Init+0x228>
8001ebe: 2308 movs r3, #8
8001ec0: e00c b.n 8001edc <HAL_GPIO_Init+0x228>
8001ec2: 2306 movs r3, #6
8001ec4: e00a b.n 8001edc <HAL_GPIO_Init+0x228>
8001ec6: 2305 movs r3, #5
8001ec8: e008 b.n 8001edc <HAL_GPIO_Init+0x228>
8001eca: 2304 movs r3, #4
8001ecc: e006 b.n 8001edc <HAL_GPIO_Init+0x228>
8001ece: 2303 movs r3, #3
8001ed0: e004 b.n 8001edc <HAL_GPIO_Init+0x228>
8001ed2: 2302 movs r3, #2
8001ed4: e002 b.n 8001edc <HAL_GPIO_Init+0x228>
8001ed6: 2301 movs r3, #1
8001ed8: e000 b.n 8001edc <HAL_GPIO_Init+0x228>
8001eda: 2300 movs r3, #0
8001edc: 69fa ldr r2, [r7, #28]
8001ede: f002 0203 and.w r2, r2, #3
8001ee2: 0092 lsls r2, r2, #2
8001ee4: 4093 lsls r3, r2
8001ee6: 69ba ldr r2, [r7, #24]
8001ee8: 4313 orrs r3, r2
8001eea: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2] = temp;
8001eec: 4935 ldr r1, [pc, #212] @ (8001fc4 <HAL_GPIO_Init+0x310>)
8001eee: 69fb ldr r3, [r7, #28]
8001ef0: 089b lsrs r3, r3, #2
8001ef2: 3302 adds r3, #2
8001ef4: 69ba ldr r2, [r7, #24]
8001ef6: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8001efa: 4b3b ldr r3, [pc, #236] @ (8001fe8 <HAL_GPIO_Init+0x334>)
8001efc: 689b ldr r3, [r3, #8]
8001efe: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001f00: 693b ldr r3, [r7, #16]
8001f02: 43db mvns r3, r3
8001f04: 69ba ldr r2, [r7, #24]
8001f06: 4013 ands r3, r2
8001f08: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8001f0a: 683b ldr r3, [r7, #0]
8001f0c: 685b ldr r3, [r3, #4]
8001f0e: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8001f12: 2b00 cmp r3, #0
8001f14: d003 beq.n 8001f1e <HAL_GPIO_Init+0x26a>
{
temp |= iocurrent;
8001f16: 69ba ldr r2, [r7, #24]
8001f18: 693b ldr r3, [r7, #16]
8001f1a: 4313 orrs r3, r2
8001f1c: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
8001f1e: 4a32 ldr r2, [pc, #200] @ (8001fe8 <HAL_GPIO_Init+0x334>)
8001f20: 69bb ldr r3, [r7, #24]
8001f22: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8001f24: 4b30 ldr r3, [pc, #192] @ (8001fe8 <HAL_GPIO_Init+0x334>)
8001f26: 68db ldr r3, [r3, #12]
8001f28: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001f2a: 693b ldr r3, [r7, #16]
8001f2c: 43db mvns r3, r3
8001f2e: 69ba ldr r2, [r7, #24]
8001f30: 4013 ands r3, r2
8001f32: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8001f34: 683b ldr r3, [r7, #0]
8001f36: 685b ldr r3, [r3, #4]
8001f38: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8001f3c: 2b00 cmp r3, #0
8001f3e: d003 beq.n 8001f48 <HAL_GPIO_Init+0x294>
{
temp |= iocurrent;
8001f40: 69ba ldr r2, [r7, #24]
8001f42: 693b ldr r3, [r7, #16]
8001f44: 4313 orrs r3, r2
8001f46: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8001f48: 4a27 ldr r2, [pc, #156] @ (8001fe8 <HAL_GPIO_Init+0x334>)
8001f4a: 69bb ldr r3, [r7, #24]
8001f4c: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8001f4e: 4b26 ldr r3, [pc, #152] @ (8001fe8 <HAL_GPIO_Init+0x334>)
8001f50: 685b ldr r3, [r3, #4]
8001f52: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001f54: 693b ldr r3, [r7, #16]
8001f56: 43db mvns r3, r3
8001f58: 69ba ldr r2, [r7, #24]
8001f5a: 4013 ands r3, r2
8001f5c: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8001f5e: 683b ldr r3, [r7, #0]
8001f60: 685b ldr r3, [r3, #4]
8001f62: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001f66: 2b00 cmp r3, #0
8001f68: d003 beq.n 8001f72 <HAL_GPIO_Init+0x2be>
{
temp |= iocurrent;
8001f6a: 69ba ldr r2, [r7, #24]
8001f6c: 693b ldr r3, [r7, #16]
8001f6e: 4313 orrs r3, r2
8001f70: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
8001f72: 4a1d ldr r2, [pc, #116] @ (8001fe8 <HAL_GPIO_Init+0x334>)
8001f74: 69bb ldr r3, [r7, #24]
8001f76: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8001f78: 4b1b ldr r3, [pc, #108] @ (8001fe8 <HAL_GPIO_Init+0x334>)
8001f7a: 681b ldr r3, [r3, #0]
8001f7c: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001f7e: 693b ldr r3, [r7, #16]
8001f80: 43db mvns r3, r3
8001f82: 69ba ldr r2, [r7, #24]
8001f84: 4013 ands r3, r2
8001f86: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8001f88: 683b ldr r3, [r7, #0]
8001f8a: 685b ldr r3, [r3, #4]
8001f8c: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001f90: 2b00 cmp r3, #0
8001f92: d003 beq.n 8001f9c <HAL_GPIO_Init+0x2e8>
{
temp |= iocurrent;
8001f94: 69ba ldr r2, [r7, #24]
8001f96: 693b ldr r3, [r7, #16]
8001f98: 4313 orrs r3, r2
8001f9a: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
8001f9c: 4a12 ldr r2, [pc, #72] @ (8001fe8 <HAL_GPIO_Init+0x334>)
8001f9e: 69bb ldr r3, [r7, #24]
8001fa0: 6013 str r3, [r2, #0]
for (position = 0; position < GPIO_NUMBER; position++)
8001fa2: 69fb ldr r3, [r7, #28]
8001fa4: 3301 adds r3, #1
8001fa6: 61fb str r3, [r7, #28]
8001fa8: 69fb ldr r3, [r7, #28]
8001faa: 2b0f cmp r3, #15
8001fac: f67f ae92 bls.w 8001cd4 <HAL_GPIO_Init+0x20>
}
}
}
}
8001fb0: bf00 nop
8001fb2: bf00 nop
8001fb4: 3724 adds r7, #36 @ 0x24
8001fb6: 46bd mov sp, r7
8001fb8: f85d 7b04 ldr.w r7, [sp], #4
8001fbc: 4770 bx lr
8001fbe: bf00 nop
8001fc0: 40023800 .word 0x40023800
8001fc4: 40013800 .word 0x40013800
8001fc8: 40020000 .word 0x40020000
8001fcc: 40020400 .word 0x40020400
8001fd0: 40020800 .word 0x40020800
8001fd4: 40020c00 .word 0x40020c00
8001fd8: 40021000 .word 0x40021000
8001fdc: 40021400 .word 0x40021400
8001fe0: 40021800 .word 0x40021800
8001fe4: 40021c00 .word 0x40021c00
8001fe8: 40013c00 .word 0x40013c00
08001fec <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
8001fec: b480 push {r7}
8001fee: b085 sub sp, #20
8001ff0: af00 add r7, sp, #0
8001ff2: 6078 str r0, [r7, #4]
8001ff4: 460b mov r3, r1
8001ff6: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
8001ff8: 687b ldr r3, [r7, #4]
8001ffa: 691a ldr r2, [r3, #16]
8001ffc: 887b ldrh r3, [r7, #2]
8001ffe: 4013 ands r3, r2
8002000: 2b00 cmp r3, #0
8002002: d002 beq.n 800200a <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8002004: 2301 movs r3, #1
8002006: 73fb strb r3, [r7, #15]
8002008: e001 b.n 800200e <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
800200a: 2300 movs r3, #0
800200c: 73fb strb r3, [r7, #15]
}
return bitstatus;
800200e: 7bfb ldrb r3, [r7, #15]
}
8002010: 4618 mov r0, r3
8002012: 3714 adds r7, #20
8002014: 46bd mov sp, r7
8002016: f85d 7b04 ldr.w r7, [sp], #4
800201a: 4770 bx lr
0800201c <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
800201c: b480 push {r7}
800201e: b083 sub sp, #12
8002020: af00 add r7, sp, #0
8002022: 6078 str r0, [r7, #4]
8002024: 460b mov r3, r1
8002026: 807b strh r3, [r7, #2]
8002028: 4613 mov r3, r2
800202a: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
800202c: 787b ldrb r3, [r7, #1]
800202e: 2b00 cmp r3, #0
8002030: d003 beq.n 800203a <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8002032: 887a ldrh r2, [r7, #2]
8002034: 687b ldr r3, [r7, #4]
8002036: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
}
}
8002038: e003 b.n 8002042 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
800203a: 887b ldrh r3, [r7, #2]
800203c: 041a lsls r2, r3, #16
800203e: 687b ldr r3, [r7, #4]
8002040: 619a str r2, [r3, #24]
}
8002042: bf00 nop
8002044: 370c adds r7, #12
8002046: 46bd mov sp, r7
8002048: f85d 7b04 ldr.w r7, [sp], #4
800204c: 4770 bx lr
0800204e <HAL_GPIO_TogglePin>:
* @param GPIO_Pin Specifies the pins to be toggled.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
800204e: b480 push {r7}
8002050: b085 sub sp, #20
8002052: af00 add r7, sp, #0
8002054: 6078 str r0, [r7, #4]
8002056: 460b mov r3, r1
8002058: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
800205a: 687b ldr r3, [r7, #4]
800205c: 695b ldr r3, [r3, #20]
800205e: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
8002060: 887a ldrh r2, [r7, #2]
8002062: 68fb ldr r3, [r7, #12]
8002064: 4013 ands r3, r2
8002066: 041a lsls r2, r3, #16
8002068: 68fb ldr r3, [r7, #12]
800206a: 43d9 mvns r1, r3
800206c: 887b ldrh r3, [r7, #2]
800206e: 400b ands r3, r1
8002070: 431a orrs r2, r3
8002072: 687b ldr r3, [r7, #4]
8002074: 619a str r2, [r3, #24]
}
8002076: bf00 nop
8002078: 3714 adds r7, #20
800207a: 46bd mov sp, r7
800207c: f85d 7b04 ldr.w r7, [sp], #4
8002080: 4770 bx lr
...
08002084 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8002084: b580 push {r7, lr}
8002086: b082 sub sp, #8
8002088: af00 add r7, sp, #0
800208a: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
800208c: 687b ldr r3, [r7, #4]
800208e: 2b00 cmp r3, #0
8002090: d101 bne.n 8002096 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
8002092: 2301 movs r3, #1
8002094: e08b b.n 80021ae <HAL_I2C_Init+0x12a>
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8002096: 687b ldr r3, [r7, #4]
8002098: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800209c: b2db uxtb r3, r3
800209e: 2b00 cmp r3, #0
80020a0: d106 bne.n 80020b0 <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
80020a2: 687b ldr r3, [r7, #4]
80020a4: 2200 movs r2, #0
80020a6: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
80020aa: 6878 ldr r0, [r7, #4]
80020ac: f7ff f9ec bl 8001488 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
80020b0: 687b ldr r3, [r7, #4]
80020b2: 2224 movs r2, #36 @ 0x24
80020b4: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
80020b8: 687b ldr r3, [r7, #4]
80020ba: 681b ldr r3, [r3, #0]
80020bc: 681a ldr r2, [r3, #0]
80020be: 687b ldr r3, [r7, #4]
80020c0: 681b ldr r3, [r3, #0]
80020c2: f022 0201 bic.w r2, r2, #1
80020c6: 601a str r2, [r3, #0]
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
80020c8: 687b ldr r3, [r7, #4]
80020ca: 685a ldr r2, [r3, #4]
80020cc: 687b ldr r3, [r7, #4]
80020ce: 681b ldr r3, [r3, #0]
80020d0: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000
80020d4: 611a str r2, [r3, #16]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
80020d6: 687b ldr r3, [r7, #4]
80020d8: 681b ldr r3, [r3, #0]
80020da: 689a ldr r2, [r3, #8]
80020dc: 687b ldr r3, [r7, #4]
80020de: 681b ldr r3, [r3, #0]
80020e0: f422 4200 bic.w r2, r2, #32768 @ 0x8000
80020e4: 609a str r2, [r3, #8]
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
80020e6: 687b ldr r3, [r7, #4]
80020e8: 68db ldr r3, [r3, #12]
80020ea: 2b01 cmp r3, #1
80020ec: d107 bne.n 80020fe <HAL_I2C_Init+0x7a>
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
80020ee: 687b ldr r3, [r7, #4]
80020f0: 689a ldr r2, [r3, #8]
80020f2: 687b ldr r3, [r7, #4]
80020f4: 681b ldr r3, [r3, #0]
80020f6: f442 4200 orr.w r2, r2, #32768 @ 0x8000
80020fa: 609a str r2, [r3, #8]
80020fc: e006 b.n 800210c <HAL_I2C_Init+0x88>
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
80020fe: 687b ldr r3, [r7, #4]
8002100: 689a ldr r2, [r3, #8]
8002102: 687b ldr r3, [r7, #4]
8002104: 681b ldr r3, [r3, #0]
8002106: f442 4204 orr.w r2, r2, #33792 @ 0x8400
800210a: 609a str r2, [r3, #8]
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
800210c: 687b ldr r3, [r7, #4]
800210e: 68db ldr r3, [r3, #12]
8002110: 2b02 cmp r3, #2
8002112: d108 bne.n 8002126 <HAL_I2C_Init+0xa2>
{
SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
8002114: 687b ldr r3, [r7, #4]
8002116: 681b ldr r3, [r3, #0]
8002118: 685a ldr r2, [r3, #4]
800211a: 687b ldr r3, [r7, #4]
800211c: 681b ldr r3, [r3, #0]
800211e: f442 6200 orr.w r2, r2, #2048 @ 0x800
8002122: 605a str r2, [r3, #4]
8002124: e007 b.n 8002136 <HAL_I2C_Init+0xb2>
}
else
{
/* Clear the I2C ADD10 bit */
CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
8002126: 687b ldr r3, [r7, #4]
8002128: 681b ldr r3, [r3, #0]
800212a: 685a ldr r2, [r3, #4]
800212c: 687b ldr r3, [r7, #4]
800212e: 681b ldr r3, [r3, #0]
8002130: f422 6200 bic.w r2, r2, #2048 @ 0x800
8002134: 605a str r2, [r3, #4]
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
8002136: 687b ldr r3, [r7, #4]
8002138: 681b ldr r3, [r3, #0]
800213a: 6859 ldr r1, [r3, #4]
800213c: 687b ldr r3, [r7, #4]
800213e: 681a ldr r2, [r3, #0]
8002140: 4b1d ldr r3, [pc, #116] @ (80021b8 <HAL_I2C_Init+0x134>)
8002142: 430b orrs r3, r1
8002144: 6053 str r3, [r2, #4]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
8002146: 687b ldr r3, [r7, #4]
8002148: 681b ldr r3, [r3, #0]
800214a: 68da ldr r2, [r3, #12]
800214c: 687b ldr r3, [r7, #4]
800214e: 681b ldr r3, [r3, #0]
8002150: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8002154: 60da str r2, [r3, #12]
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
8002156: 687b ldr r3, [r7, #4]
8002158: 691a ldr r2, [r3, #16]
800215a: 687b ldr r3, [r7, #4]
800215c: 695b ldr r3, [r3, #20]
800215e: ea42 0103 orr.w r1, r2, r3
(hi2c->Init.OwnAddress2Masks << 8));
8002162: 687b ldr r3, [r7, #4]
8002164: 699b ldr r3, [r3, #24]
8002166: 021a lsls r2, r3, #8
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
8002168: 687b ldr r3, [r7, #4]
800216a: 681b ldr r3, [r3, #0]
800216c: 430a orrs r2, r1
800216e: 60da str r2, [r3, #12]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
8002170: 687b ldr r3, [r7, #4]
8002172: 69d9 ldr r1, [r3, #28]
8002174: 687b ldr r3, [r7, #4]
8002176: 6a1a ldr r2, [r3, #32]
8002178: 687b ldr r3, [r7, #4]
800217a: 681b ldr r3, [r3, #0]
800217c: 430a orrs r2, r1
800217e: 601a str r2, [r3, #0]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8002180: 687b ldr r3, [r7, #4]
8002182: 681b ldr r3, [r3, #0]
8002184: 681a ldr r2, [r3, #0]
8002186: 687b ldr r3, [r7, #4]
8002188: 681b ldr r3, [r3, #0]
800218a: f042 0201 orr.w r2, r2, #1
800218e: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8002190: 687b ldr r3, [r7, #4]
8002192: 2200 movs r2, #0
8002194: 645a str r2, [r3, #68] @ 0x44
hi2c->State = HAL_I2C_STATE_READY;
8002196: 687b ldr r3, [r7, #4]
8002198: 2220 movs r2, #32
800219a: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_NONE;
800219e: 687b ldr r3, [r7, #4]
80021a0: 2200 movs r2, #0
80021a2: 631a str r2, [r3, #48] @ 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
80021a4: 687b ldr r3, [r7, #4]
80021a6: 2200 movs r2, #0
80021a8: f883 2042 strb.w r2, [r3, #66] @ 0x42
return HAL_OK;
80021ac: 2300 movs r3, #0
}
80021ae: 4618 mov r0, r3
80021b0: 3708 adds r7, #8
80021b2: 46bd mov sp, r7
80021b4: bd80 pop {r7, pc}
80021b6: bf00 nop
80021b8: 02008000 .word 0x02008000
080021bc <HAL_I2CEx_ConfigAnalogFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
80021bc: b480 push {r7}
80021be: b083 sub sp, #12
80021c0: af00 add r7, sp, #0
80021c2: 6078 str r0, [r7, #4]
80021c4: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
80021c6: 687b ldr r3, [r7, #4]
80021c8: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
80021cc: b2db uxtb r3, r3
80021ce: 2b20 cmp r3, #32
80021d0: d138 bne.n 8002244 <HAL_I2CEx_ConfigAnalogFilter+0x88>
{
/* Process Locked */
__HAL_LOCK(hi2c);
80021d2: 687b ldr r3, [r7, #4]
80021d4: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
80021d8: 2b01 cmp r3, #1
80021da: d101 bne.n 80021e0 <HAL_I2CEx_ConfigAnalogFilter+0x24>
80021dc: 2302 movs r3, #2
80021de: e032 b.n 8002246 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
80021e0: 687b ldr r3, [r7, #4]
80021e2: 2201 movs r2, #1
80021e4: f883 2040 strb.w r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
80021e8: 687b ldr r3, [r7, #4]
80021ea: 2224 movs r2, #36 @ 0x24
80021ec: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
80021f0: 687b ldr r3, [r7, #4]
80021f2: 681b ldr r3, [r3, #0]
80021f4: 681a ldr r2, [r3, #0]
80021f6: 687b ldr r3, [r7, #4]
80021f8: 681b ldr r3, [r3, #0]
80021fa: f022 0201 bic.w r2, r2, #1
80021fe: 601a str r2, [r3, #0]
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
8002200: 687b ldr r3, [r7, #4]
8002202: 681b ldr r3, [r3, #0]
8002204: 681a ldr r2, [r3, #0]
8002206: 687b ldr r3, [r7, #4]
8002208: 681b ldr r3, [r3, #0]
800220a: f422 5280 bic.w r2, r2, #4096 @ 0x1000
800220e: 601a str r2, [r3, #0]
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
8002210: 687b ldr r3, [r7, #4]
8002212: 681b ldr r3, [r3, #0]
8002214: 6819 ldr r1, [r3, #0]
8002216: 687b ldr r3, [r7, #4]
8002218: 681b ldr r3, [r3, #0]
800221a: 683a ldr r2, [r7, #0]
800221c: 430a orrs r2, r1
800221e: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
8002220: 687b ldr r3, [r7, #4]
8002222: 681b ldr r3, [r3, #0]
8002224: 681a ldr r2, [r3, #0]
8002226: 687b ldr r3, [r7, #4]
8002228: 681b ldr r3, [r3, #0]
800222a: f042 0201 orr.w r2, r2, #1
800222e: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8002230: 687b ldr r3, [r7, #4]
8002232: 2220 movs r2, #32
8002234: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8002238: 687b ldr r3, [r7, #4]
800223a: 2200 movs r2, #0
800223c: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
8002240: 2300 movs r3, #0
8002242: e000 b.n 8002246 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
}
else
{
return HAL_BUSY;
8002244: 2302 movs r3, #2
}
}
8002246: 4618 mov r0, r3
8002248: 370c adds r7, #12
800224a: 46bd mov sp, r7
800224c: f85d 7b04 ldr.w r7, [sp], #4
8002250: 4770 bx lr
08002252 <HAL_I2CEx_ConfigDigitalFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
8002252: b480 push {r7}
8002254: b085 sub sp, #20
8002256: af00 add r7, sp, #0
8002258: 6078 str r0, [r7, #4]
800225a: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
800225c: 687b ldr r3, [r7, #4]
800225e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8002262: b2db uxtb r3, r3
8002264: 2b20 cmp r3, #32
8002266: d139 bne.n 80022dc <HAL_I2CEx_ConfigDigitalFilter+0x8a>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8002268: 687b ldr r3, [r7, #4]
800226a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
800226e: 2b01 cmp r3, #1
8002270: d101 bne.n 8002276 <HAL_I2CEx_ConfigDigitalFilter+0x24>
8002272: 2302 movs r3, #2
8002274: e033 b.n 80022de <HAL_I2CEx_ConfigDigitalFilter+0x8c>
8002276: 687b ldr r3, [r7, #4]
8002278: 2201 movs r2, #1
800227a: f883 2040 strb.w r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
800227e: 687b ldr r3, [r7, #4]
8002280: 2224 movs r2, #36 @ 0x24
8002282: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8002286: 687b ldr r3, [r7, #4]
8002288: 681b ldr r3, [r3, #0]
800228a: 681a ldr r2, [r3, #0]
800228c: 687b ldr r3, [r7, #4]
800228e: 681b ldr r3, [r3, #0]
8002290: f022 0201 bic.w r2, r2, #1
8002294: 601a str r2, [r3, #0]
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
8002296: 687b ldr r3, [r7, #4]
8002298: 681b ldr r3, [r3, #0]
800229a: 681b ldr r3, [r3, #0]
800229c: 60fb str r3, [r7, #12]
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
800229e: 68fb ldr r3, [r7, #12]
80022a0: f423 6370 bic.w r3, r3, #3840 @ 0xf00
80022a4: 60fb str r3, [r7, #12]
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
80022a6: 683b ldr r3, [r7, #0]
80022a8: 021b lsls r3, r3, #8
80022aa: 68fa ldr r2, [r7, #12]
80022ac: 4313 orrs r3, r2
80022ae: 60fb str r3, [r7, #12]
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
80022b0: 687b ldr r3, [r7, #4]
80022b2: 681b ldr r3, [r3, #0]
80022b4: 68fa ldr r2, [r7, #12]
80022b6: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
80022b8: 687b ldr r3, [r7, #4]
80022ba: 681b ldr r3, [r3, #0]
80022bc: 681a ldr r2, [r3, #0]
80022be: 687b ldr r3, [r7, #4]
80022c0: 681b ldr r3, [r3, #0]
80022c2: f042 0201 orr.w r2, r2, #1
80022c6: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
80022c8: 687b ldr r3, [r7, #4]
80022ca: 2220 movs r2, #32
80022cc: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80022d0: 687b ldr r3, [r7, #4]
80022d2: 2200 movs r2, #0
80022d4: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
80022d8: 2300 movs r3, #0
80022da: e000 b.n 80022de <HAL_I2CEx_ConfigDigitalFilter+0x8c>
}
else
{
return HAL_BUSY;
80022dc: 2302 movs r3, #2
}
}
80022de: 4618 mov r0, r3
80022e0: 3714 adds r7, #20
80022e2: 46bd mov sp, r7
80022e4: f85d 7b04 ldr.w r7, [sp], #4
80022e8: 4770 bx lr
...
080022ec <HAL_PWR_EnableBkUpAccess>:
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
80022ec: b480 push {r7}
80022ee: af00 add r7, sp, #0
/* Enable access to RTC and backup registers */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
80022f0: 4b05 ldr r3, [pc, #20] @ (8002308 <HAL_PWR_EnableBkUpAccess+0x1c>)
80022f2: 681b ldr r3, [r3, #0]
80022f4: 4a04 ldr r2, [pc, #16] @ (8002308 <HAL_PWR_EnableBkUpAccess+0x1c>)
80022f6: f443 7380 orr.w r3, r3, #256 @ 0x100
80022fa: 6013 str r3, [r2, #0]
}
80022fc: bf00 nop
80022fe: 46bd mov sp, r7
8002300: f85d 7b04 ldr.w r7, [sp], #4
8002304: 4770 bx lr
8002306: bf00 nop
8002308: 40007000 .word 0x40007000
0800230c <HAL_PWREx_EnableOverDrive>:
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
{
800230c: b580 push {r7, lr}
800230e: b082 sub sp, #8
8002310: af00 add r7, sp, #0
uint32_t tickstart = 0;
8002312: 2300 movs r3, #0
8002314: 607b str r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8002316: 4b23 ldr r3, [pc, #140] @ (80023a4 <HAL_PWREx_EnableOverDrive+0x98>)
8002318: 6c1b ldr r3, [r3, #64] @ 0x40
800231a: 4a22 ldr r2, [pc, #136] @ (80023a4 <HAL_PWREx_EnableOverDrive+0x98>)
800231c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002320: 6413 str r3, [r2, #64] @ 0x40
8002322: 4b20 ldr r3, [pc, #128] @ (80023a4 <HAL_PWREx_EnableOverDrive+0x98>)
8002324: 6c1b ldr r3, [r3, #64] @ 0x40
8002326: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800232a: 603b str r3, [r7, #0]
800232c: 683b ldr r3, [r7, #0]
/* Enable the Over-drive to extend the clock frequency to 216 MHz */
__HAL_PWR_OVERDRIVE_ENABLE();
800232e: 4b1e ldr r3, [pc, #120] @ (80023a8 <HAL_PWREx_EnableOverDrive+0x9c>)
8002330: 681b ldr r3, [r3, #0]
8002332: 4a1d ldr r2, [pc, #116] @ (80023a8 <HAL_PWREx_EnableOverDrive+0x9c>)
8002334: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002338: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
800233a: f7ff fba9 bl 8001a90 <HAL_GetTick>
800233e: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
8002340: e009 b.n 8002356 <HAL_PWREx_EnableOverDrive+0x4a>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8002342: f7ff fba5 bl 8001a90 <HAL_GetTick>
8002346: 4602 mov r2, r0
8002348: 687b ldr r3, [r7, #4]
800234a: 1ad3 subs r3, r2, r3
800234c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
8002350: d901 bls.n 8002356 <HAL_PWREx_EnableOverDrive+0x4a>
{
return HAL_TIMEOUT;
8002352: 2303 movs r3, #3
8002354: e022 b.n 800239c <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
8002356: 4b14 ldr r3, [pc, #80] @ (80023a8 <HAL_PWREx_EnableOverDrive+0x9c>)
8002358: 685b ldr r3, [r3, #4]
800235a: f403 3380 and.w r3, r3, #65536 @ 0x10000
800235e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8002362: d1ee bne.n 8002342 <HAL_PWREx_EnableOverDrive+0x36>
}
}
/* Enable the Over-drive switch */
__HAL_PWR_OVERDRIVESWITCHING_ENABLE();
8002364: 4b10 ldr r3, [pc, #64] @ (80023a8 <HAL_PWREx_EnableOverDrive+0x9c>)
8002366: 681b ldr r3, [r3, #0]
8002368: 4a0f ldr r2, [pc, #60] @ (80023a8 <HAL_PWREx_EnableOverDrive+0x9c>)
800236a: f443 3300 orr.w r3, r3, #131072 @ 0x20000
800236e: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8002370: f7ff fb8e bl 8001a90 <HAL_GetTick>
8002374: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
8002376: e009 b.n 800238c <HAL_PWREx_EnableOverDrive+0x80>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8002378: f7ff fb8a bl 8001a90 <HAL_GetTick>
800237c: 4602 mov r2, r0
800237e: 687b ldr r3, [r7, #4]
8002380: 1ad3 subs r3, r2, r3
8002382: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
8002386: d901 bls.n 800238c <HAL_PWREx_EnableOverDrive+0x80>
{
return HAL_TIMEOUT;
8002388: 2303 movs r3, #3
800238a: e007 b.n 800239c <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
800238c: 4b06 ldr r3, [pc, #24] @ (80023a8 <HAL_PWREx_EnableOverDrive+0x9c>)
800238e: 685b ldr r3, [r3, #4]
8002390: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002394: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
8002398: d1ee bne.n 8002378 <HAL_PWREx_EnableOverDrive+0x6c>
}
}
return HAL_OK;
800239a: 2300 movs r3, #0
}
800239c: 4618 mov r0, r3
800239e: 3708 adds r7, #8
80023a0: 46bd mov sp, r7
80023a2: bd80 pop {r7, pc}
80023a4: 40023800 .word 0x40023800
80023a8: 40007000 .word 0x40007000
080023ac <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80023ac: b580 push {r7, lr}
80023ae: b086 sub sp, #24
80023b0: af00 add r7, sp, #0
80023b2: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
FlagStatus pwrclkchanged = RESET;
80023b4: 2300 movs r3, #0
80023b6: 75fb strb r3, [r7, #23]
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
80023b8: 687b ldr r3, [r7, #4]
80023ba: 2b00 cmp r3, #0
80023bc: d101 bne.n 80023c2 <HAL_RCC_OscConfig+0x16>
{
return HAL_ERROR;
80023be: 2301 movs r3, #1
80023c0: e291 b.n 80028e6 <HAL_RCC_OscConfig+0x53a>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80023c2: 687b ldr r3, [r7, #4]
80023c4: 681b ldr r3, [r3, #0]
80023c6: f003 0301 and.w r3, r3, #1
80023ca: 2b00 cmp r3, #0
80023cc: f000 8087 beq.w 80024de <HAL_RCC_OscConfig+0x132>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
80023d0: 4b96 ldr r3, [pc, #600] @ (800262c <HAL_RCC_OscConfig+0x280>)
80023d2: 689b ldr r3, [r3, #8]
80023d4: f003 030c and.w r3, r3, #12
80023d8: 2b04 cmp r3, #4
80023da: d00c beq.n 80023f6 <HAL_RCC_OscConfig+0x4a>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
80023dc: 4b93 ldr r3, [pc, #588] @ (800262c <HAL_RCC_OscConfig+0x280>)
80023de: 689b ldr r3, [r3, #8]
80023e0: f003 030c and.w r3, r3, #12
80023e4: 2b08 cmp r3, #8
80023e6: d112 bne.n 800240e <HAL_RCC_OscConfig+0x62>
80023e8: 4b90 ldr r3, [pc, #576] @ (800262c <HAL_RCC_OscConfig+0x280>)
80023ea: 685b ldr r3, [r3, #4]
80023ec: f403 0380 and.w r3, r3, #4194304 @ 0x400000
80023f0: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
80023f4: d10b bne.n 800240e <HAL_RCC_OscConfig+0x62>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80023f6: 4b8d ldr r3, [pc, #564] @ (800262c <HAL_RCC_OscConfig+0x280>)
80023f8: 681b ldr r3, [r3, #0]
80023fa: f403 3300 and.w r3, r3, #131072 @ 0x20000
80023fe: 2b00 cmp r3, #0
8002400: d06c beq.n 80024dc <HAL_RCC_OscConfig+0x130>
8002402: 687b ldr r3, [r7, #4]
8002404: 685b ldr r3, [r3, #4]
8002406: 2b00 cmp r3, #0
8002408: d168 bne.n 80024dc <HAL_RCC_OscConfig+0x130>
{
return HAL_ERROR;
800240a: 2301 movs r3, #1
800240c: e26b b.n 80028e6 <HAL_RCC_OscConfig+0x53a>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
800240e: 687b ldr r3, [r7, #4]
8002410: 685b ldr r3, [r3, #4]
8002412: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8002416: d106 bne.n 8002426 <HAL_RCC_OscConfig+0x7a>
8002418: 4b84 ldr r3, [pc, #528] @ (800262c <HAL_RCC_OscConfig+0x280>)
800241a: 681b ldr r3, [r3, #0]
800241c: 4a83 ldr r2, [pc, #524] @ (800262c <HAL_RCC_OscConfig+0x280>)
800241e: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002422: 6013 str r3, [r2, #0]
8002424: e02e b.n 8002484 <HAL_RCC_OscConfig+0xd8>
8002426: 687b ldr r3, [r7, #4]
8002428: 685b ldr r3, [r3, #4]
800242a: 2b00 cmp r3, #0
800242c: d10c bne.n 8002448 <HAL_RCC_OscConfig+0x9c>
800242e: 4b7f ldr r3, [pc, #508] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002430: 681b ldr r3, [r3, #0]
8002432: 4a7e ldr r2, [pc, #504] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002434: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8002438: 6013 str r3, [r2, #0]
800243a: 4b7c ldr r3, [pc, #496] @ (800262c <HAL_RCC_OscConfig+0x280>)
800243c: 681b ldr r3, [r3, #0]
800243e: 4a7b ldr r2, [pc, #492] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002440: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8002444: 6013 str r3, [r2, #0]
8002446: e01d b.n 8002484 <HAL_RCC_OscConfig+0xd8>
8002448: 687b ldr r3, [r7, #4]
800244a: 685b ldr r3, [r3, #4]
800244c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8002450: d10c bne.n 800246c <HAL_RCC_OscConfig+0xc0>
8002452: 4b76 ldr r3, [pc, #472] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002454: 681b ldr r3, [r3, #0]
8002456: 4a75 ldr r2, [pc, #468] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002458: f443 2380 orr.w r3, r3, #262144 @ 0x40000
800245c: 6013 str r3, [r2, #0]
800245e: 4b73 ldr r3, [pc, #460] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002460: 681b ldr r3, [r3, #0]
8002462: 4a72 ldr r2, [pc, #456] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002464: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002468: 6013 str r3, [r2, #0]
800246a: e00b b.n 8002484 <HAL_RCC_OscConfig+0xd8>
800246c: 4b6f ldr r3, [pc, #444] @ (800262c <HAL_RCC_OscConfig+0x280>)
800246e: 681b ldr r3, [r3, #0]
8002470: 4a6e ldr r2, [pc, #440] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002472: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8002476: 6013 str r3, [r2, #0]
8002478: 4b6c ldr r3, [pc, #432] @ (800262c <HAL_RCC_OscConfig+0x280>)
800247a: 681b ldr r3, [r3, #0]
800247c: 4a6b ldr r2, [pc, #428] @ (800262c <HAL_RCC_OscConfig+0x280>)
800247e: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8002482: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8002484: 687b ldr r3, [r7, #4]
8002486: 685b ldr r3, [r3, #4]
8002488: 2b00 cmp r3, #0
800248a: d013 beq.n 80024b4 <HAL_RCC_OscConfig+0x108>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800248c: f7ff fb00 bl 8001a90 <HAL_GetTick>
8002490: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002492: e008 b.n 80024a6 <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8002494: f7ff fafc bl 8001a90 <HAL_GetTick>
8002498: 4602 mov r2, r0
800249a: 693b ldr r3, [r7, #16]
800249c: 1ad3 subs r3, r2, r3
800249e: 2b64 cmp r3, #100 @ 0x64
80024a0: d901 bls.n 80024a6 <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
80024a2: 2303 movs r3, #3
80024a4: e21f b.n 80028e6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80024a6: 4b61 ldr r3, [pc, #388] @ (800262c <HAL_RCC_OscConfig+0x280>)
80024a8: 681b ldr r3, [r3, #0]
80024aa: f403 3300 and.w r3, r3, #131072 @ 0x20000
80024ae: 2b00 cmp r3, #0
80024b0: d0f0 beq.n 8002494 <HAL_RCC_OscConfig+0xe8>
80024b2: e014 b.n 80024de <HAL_RCC_OscConfig+0x132>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80024b4: f7ff faec bl 8001a90 <HAL_GetTick>
80024b8: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80024ba: e008 b.n 80024ce <HAL_RCC_OscConfig+0x122>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80024bc: f7ff fae8 bl 8001a90 <HAL_GetTick>
80024c0: 4602 mov r2, r0
80024c2: 693b ldr r3, [r7, #16]
80024c4: 1ad3 subs r3, r2, r3
80024c6: 2b64 cmp r3, #100 @ 0x64
80024c8: d901 bls.n 80024ce <HAL_RCC_OscConfig+0x122>
{
return HAL_TIMEOUT;
80024ca: 2303 movs r3, #3
80024cc: e20b b.n 80028e6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80024ce: 4b57 ldr r3, [pc, #348] @ (800262c <HAL_RCC_OscConfig+0x280>)
80024d0: 681b ldr r3, [r3, #0]
80024d2: f403 3300 and.w r3, r3, #131072 @ 0x20000
80024d6: 2b00 cmp r3, #0
80024d8: d1f0 bne.n 80024bc <HAL_RCC_OscConfig+0x110>
80024da: e000 b.n 80024de <HAL_RCC_OscConfig+0x132>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80024dc: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80024de: 687b ldr r3, [r7, #4]
80024e0: 681b ldr r3, [r3, #0]
80024e2: f003 0302 and.w r3, r3, #2
80024e6: 2b00 cmp r3, #0
80024e8: d069 beq.n 80025be <HAL_RCC_OscConfig+0x212>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
80024ea: 4b50 ldr r3, [pc, #320] @ (800262c <HAL_RCC_OscConfig+0x280>)
80024ec: 689b ldr r3, [r3, #8]
80024ee: f003 030c and.w r3, r3, #12
80024f2: 2b00 cmp r3, #0
80024f4: d00b beq.n 800250e <HAL_RCC_OscConfig+0x162>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
80024f6: 4b4d ldr r3, [pc, #308] @ (800262c <HAL_RCC_OscConfig+0x280>)
80024f8: 689b ldr r3, [r3, #8]
80024fa: f003 030c and.w r3, r3, #12
80024fe: 2b08 cmp r3, #8
8002500: d11c bne.n 800253c <HAL_RCC_OscConfig+0x190>
8002502: 4b4a ldr r3, [pc, #296] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002504: 685b ldr r3, [r3, #4]
8002506: f403 0380 and.w r3, r3, #4194304 @ 0x400000
800250a: 2b00 cmp r3, #0
800250c: d116 bne.n 800253c <HAL_RCC_OscConfig+0x190>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
800250e: 4b47 ldr r3, [pc, #284] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002510: 681b ldr r3, [r3, #0]
8002512: f003 0302 and.w r3, r3, #2
8002516: 2b00 cmp r3, #0
8002518: d005 beq.n 8002526 <HAL_RCC_OscConfig+0x17a>
800251a: 687b ldr r3, [r7, #4]
800251c: 68db ldr r3, [r3, #12]
800251e: 2b01 cmp r3, #1
8002520: d001 beq.n 8002526 <HAL_RCC_OscConfig+0x17a>
{
return HAL_ERROR;
8002522: 2301 movs r3, #1
8002524: e1df b.n 80028e6 <HAL_RCC_OscConfig+0x53a>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002526: 4b41 ldr r3, [pc, #260] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002528: 681b ldr r3, [r3, #0]
800252a: f023 02f8 bic.w r2, r3, #248 @ 0xf8
800252e: 687b ldr r3, [r7, #4]
8002530: 691b ldr r3, [r3, #16]
8002532: 00db lsls r3, r3, #3
8002534: 493d ldr r1, [pc, #244] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002536: 4313 orrs r3, r2
8002538: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
800253a: e040 b.n 80025be <HAL_RCC_OscConfig+0x212>
}
}
else
{
/* Check the HSI State */
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
800253c: 687b ldr r3, [r7, #4]
800253e: 68db ldr r3, [r3, #12]
8002540: 2b00 cmp r3, #0
8002542: d023 beq.n 800258c <HAL_RCC_OscConfig+0x1e0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8002544: 4b39 ldr r3, [pc, #228] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002546: 681b ldr r3, [r3, #0]
8002548: 4a38 ldr r2, [pc, #224] @ (800262c <HAL_RCC_OscConfig+0x280>)
800254a: f043 0301 orr.w r3, r3, #1
800254e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002550: f7ff fa9e bl 8001a90 <HAL_GetTick>
8002554: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002556: e008 b.n 800256a <HAL_RCC_OscConfig+0x1be>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8002558: f7ff fa9a bl 8001a90 <HAL_GetTick>
800255c: 4602 mov r2, r0
800255e: 693b ldr r3, [r7, #16]
8002560: 1ad3 subs r3, r2, r3
8002562: 2b02 cmp r3, #2
8002564: d901 bls.n 800256a <HAL_RCC_OscConfig+0x1be>
{
return HAL_TIMEOUT;
8002566: 2303 movs r3, #3
8002568: e1bd b.n 80028e6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800256a: 4b30 ldr r3, [pc, #192] @ (800262c <HAL_RCC_OscConfig+0x280>)
800256c: 681b ldr r3, [r3, #0]
800256e: f003 0302 and.w r3, r3, #2
8002572: 2b00 cmp r3, #0
8002574: d0f0 beq.n 8002558 <HAL_RCC_OscConfig+0x1ac>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002576: 4b2d ldr r3, [pc, #180] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002578: 681b ldr r3, [r3, #0]
800257a: f023 02f8 bic.w r2, r3, #248 @ 0xf8
800257e: 687b ldr r3, [r7, #4]
8002580: 691b ldr r3, [r3, #16]
8002582: 00db lsls r3, r3, #3
8002584: 4929 ldr r1, [pc, #164] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002586: 4313 orrs r3, r2
8002588: 600b str r3, [r1, #0]
800258a: e018 b.n 80025be <HAL_RCC_OscConfig+0x212>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
800258c: 4b27 ldr r3, [pc, #156] @ (800262c <HAL_RCC_OscConfig+0x280>)
800258e: 681b ldr r3, [r3, #0]
8002590: 4a26 ldr r2, [pc, #152] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002592: f023 0301 bic.w r3, r3, #1
8002596: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002598: f7ff fa7a bl 8001a90 <HAL_GetTick>
800259c: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800259e: e008 b.n 80025b2 <HAL_RCC_OscConfig+0x206>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80025a0: f7ff fa76 bl 8001a90 <HAL_GetTick>
80025a4: 4602 mov r2, r0
80025a6: 693b ldr r3, [r7, #16]
80025a8: 1ad3 subs r3, r2, r3
80025aa: 2b02 cmp r3, #2
80025ac: d901 bls.n 80025b2 <HAL_RCC_OscConfig+0x206>
{
return HAL_TIMEOUT;
80025ae: 2303 movs r3, #3
80025b0: e199 b.n 80028e6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80025b2: 4b1e ldr r3, [pc, #120] @ (800262c <HAL_RCC_OscConfig+0x280>)
80025b4: 681b ldr r3, [r3, #0]
80025b6: f003 0302 and.w r3, r3, #2
80025ba: 2b00 cmp r3, #0
80025bc: d1f0 bne.n 80025a0 <HAL_RCC_OscConfig+0x1f4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80025be: 687b ldr r3, [r7, #4]
80025c0: 681b ldr r3, [r3, #0]
80025c2: f003 0308 and.w r3, r3, #8
80025c6: 2b00 cmp r3, #0
80025c8: d038 beq.n 800263c <HAL_RCC_OscConfig+0x290>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
80025ca: 687b ldr r3, [r7, #4]
80025cc: 695b ldr r3, [r3, #20]
80025ce: 2b00 cmp r3, #0
80025d0: d019 beq.n 8002606 <HAL_RCC_OscConfig+0x25a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80025d2: 4b16 ldr r3, [pc, #88] @ (800262c <HAL_RCC_OscConfig+0x280>)
80025d4: 6f5b ldr r3, [r3, #116] @ 0x74
80025d6: 4a15 ldr r2, [pc, #84] @ (800262c <HAL_RCC_OscConfig+0x280>)
80025d8: f043 0301 orr.w r3, r3, #1
80025dc: 6753 str r3, [r2, #116] @ 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
80025de: f7ff fa57 bl 8001a90 <HAL_GetTick>
80025e2: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80025e4: e008 b.n 80025f8 <HAL_RCC_OscConfig+0x24c>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80025e6: f7ff fa53 bl 8001a90 <HAL_GetTick>
80025ea: 4602 mov r2, r0
80025ec: 693b ldr r3, [r7, #16]
80025ee: 1ad3 subs r3, r2, r3
80025f0: 2b02 cmp r3, #2
80025f2: d901 bls.n 80025f8 <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
80025f4: 2303 movs r3, #3
80025f6: e176 b.n 80028e6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80025f8: 4b0c ldr r3, [pc, #48] @ (800262c <HAL_RCC_OscConfig+0x280>)
80025fa: 6f5b ldr r3, [r3, #116] @ 0x74
80025fc: f003 0302 and.w r3, r3, #2
8002600: 2b00 cmp r3, #0
8002602: d0f0 beq.n 80025e6 <HAL_RCC_OscConfig+0x23a>
8002604: e01a b.n 800263c <HAL_RCC_OscConfig+0x290>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8002606: 4b09 ldr r3, [pc, #36] @ (800262c <HAL_RCC_OscConfig+0x280>)
8002608: 6f5b ldr r3, [r3, #116] @ 0x74
800260a: 4a08 ldr r2, [pc, #32] @ (800262c <HAL_RCC_OscConfig+0x280>)
800260c: f023 0301 bic.w r3, r3, #1
8002610: 6753 str r3, [r2, #116] @ 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002612: f7ff fa3d bl 8001a90 <HAL_GetTick>
8002616: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8002618: e00a b.n 8002630 <HAL_RCC_OscConfig+0x284>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800261a: f7ff fa39 bl 8001a90 <HAL_GetTick>
800261e: 4602 mov r2, r0
8002620: 693b ldr r3, [r7, #16]
8002622: 1ad3 subs r3, r2, r3
8002624: 2b02 cmp r3, #2
8002626: d903 bls.n 8002630 <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
8002628: 2303 movs r3, #3
800262a: e15c b.n 80028e6 <HAL_RCC_OscConfig+0x53a>
800262c: 40023800 .word 0x40023800
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8002630: 4b91 ldr r3, [pc, #580] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
8002632: 6f5b ldr r3, [r3, #116] @ 0x74
8002634: f003 0302 and.w r3, r3, #2
8002638: 2b00 cmp r3, #0
800263a: d1ee bne.n 800261a <HAL_RCC_OscConfig+0x26e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
800263c: 687b ldr r3, [r7, #4]
800263e: 681b ldr r3, [r3, #0]
8002640: f003 0304 and.w r3, r3, #4
8002644: 2b00 cmp r3, #0
8002646: f000 80a4 beq.w 8002792 <HAL_RCC_OscConfig+0x3e6>
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
800264a: 4b8b ldr r3, [pc, #556] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
800264c: 6c1b ldr r3, [r3, #64] @ 0x40
800264e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002652: 2b00 cmp r3, #0
8002654: d10d bne.n 8002672 <HAL_RCC_OscConfig+0x2c6>
{
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
8002656: 4b88 ldr r3, [pc, #544] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
8002658: 6c1b ldr r3, [r3, #64] @ 0x40
800265a: 4a87 ldr r2, [pc, #540] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
800265c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002660: 6413 str r3, [r2, #64] @ 0x40
8002662: 4b85 ldr r3, [pc, #532] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
8002664: 6c1b ldr r3, [r3, #64] @ 0x40
8002666: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800266a: 60bb str r3, [r7, #8]
800266c: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
800266e: 2301 movs r3, #1
8002670: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8002672: 4b82 ldr r3, [pc, #520] @ (800287c <HAL_RCC_OscConfig+0x4d0>)
8002674: 681b ldr r3, [r3, #0]
8002676: f403 7380 and.w r3, r3, #256 @ 0x100
800267a: 2b00 cmp r3, #0
800267c: d118 bne.n 80026b0 <HAL_RCC_OscConfig+0x304>
{
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
800267e: 4b7f ldr r3, [pc, #508] @ (800287c <HAL_RCC_OscConfig+0x4d0>)
8002680: 681b ldr r3, [r3, #0]
8002682: 4a7e ldr r2, [pc, #504] @ (800287c <HAL_RCC_OscConfig+0x4d0>)
8002684: f443 7380 orr.w r3, r3, #256 @ 0x100
8002688: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800268a: f7ff fa01 bl 8001a90 <HAL_GetTick>
800268e: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8002690: e008 b.n 80026a4 <HAL_RCC_OscConfig+0x2f8>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8002692: f7ff f9fd bl 8001a90 <HAL_GetTick>
8002696: 4602 mov r2, r0
8002698: 693b ldr r3, [r7, #16]
800269a: 1ad3 subs r3, r2, r3
800269c: 2b64 cmp r3, #100 @ 0x64
800269e: d901 bls.n 80026a4 <HAL_RCC_OscConfig+0x2f8>
{
return HAL_TIMEOUT;
80026a0: 2303 movs r3, #3
80026a2: e120 b.n 80028e6 <HAL_RCC_OscConfig+0x53a>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80026a4: 4b75 ldr r3, [pc, #468] @ (800287c <HAL_RCC_OscConfig+0x4d0>)
80026a6: 681b ldr r3, [r3, #0]
80026a8: f403 7380 and.w r3, r3, #256 @ 0x100
80026ac: 2b00 cmp r3, #0
80026ae: d0f0 beq.n 8002692 <HAL_RCC_OscConfig+0x2e6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80026b0: 687b ldr r3, [r7, #4]
80026b2: 689b ldr r3, [r3, #8]
80026b4: 2b01 cmp r3, #1
80026b6: d106 bne.n 80026c6 <HAL_RCC_OscConfig+0x31a>
80026b8: 4b6f ldr r3, [pc, #444] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
80026ba: 6f1b ldr r3, [r3, #112] @ 0x70
80026bc: 4a6e ldr r2, [pc, #440] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
80026be: f043 0301 orr.w r3, r3, #1
80026c2: 6713 str r3, [r2, #112] @ 0x70
80026c4: e02d b.n 8002722 <HAL_RCC_OscConfig+0x376>
80026c6: 687b ldr r3, [r7, #4]
80026c8: 689b ldr r3, [r3, #8]
80026ca: 2b00 cmp r3, #0
80026cc: d10c bne.n 80026e8 <HAL_RCC_OscConfig+0x33c>
80026ce: 4b6a ldr r3, [pc, #424] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
80026d0: 6f1b ldr r3, [r3, #112] @ 0x70
80026d2: 4a69 ldr r2, [pc, #420] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
80026d4: f023 0301 bic.w r3, r3, #1
80026d8: 6713 str r3, [r2, #112] @ 0x70
80026da: 4b67 ldr r3, [pc, #412] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
80026dc: 6f1b ldr r3, [r3, #112] @ 0x70
80026de: 4a66 ldr r2, [pc, #408] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
80026e0: f023 0304 bic.w r3, r3, #4
80026e4: 6713 str r3, [r2, #112] @ 0x70
80026e6: e01c b.n 8002722 <HAL_RCC_OscConfig+0x376>
80026e8: 687b ldr r3, [r7, #4]
80026ea: 689b ldr r3, [r3, #8]
80026ec: 2b05 cmp r3, #5
80026ee: d10c bne.n 800270a <HAL_RCC_OscConfig+0x35e>
80026f0: 4b61 ldr r3, [pc, #388] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
80026f2: 6f1b ldr r3, [r3, #112] @ 0x70
80026f4: 4a60 ldr r2, [pc, #384] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
80026f6: f043 0304 orr.w r3, r3, #4
80026fa: 6713 str r3, [r2, #112] @ 0x70
80026fc: 4b5e ldr r3, [pc, #376] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
80026fe: 6f1b ldr r3, [r3, #112] @ 0x70
8002700: 4a5d ldr r2, [pc, #372] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
8002702: f043 0301 orr.w r3, r3, #1
8002706: 6713 str r3, [r2, #112] @ 0x70
8002708: e00b b.n 8002722 <HAL_RCC_OscConfig+0x376>
800270a: 4b5b ldr r3, [pc, #364] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
800270c: 6f1b ldr r3, [r3, #112] @ 0x70
800270e: 4a5a ldr r2, [pc, #360] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
8002710: f023 0301 bic.w r3, r3, #1
8002714: 6713 str r3, [r2, #112] @ 0x70
8002716: 4b58 ldr r3, [pc, #352] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
8002718: 6f1b ldr r3, [r3, #112] @ 0x70
800271a: 4a57 ldr r2, [pc, #348] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
800271c: f023 0304 bic.w r3, r3, #4
8002720: 6713 str r3, [r2, #112] @ 0x70
/* Check the LSE State */
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8002722: 687b ldr r3, [r7, #4]
8002724: 689b ldr r3, [r3, #8]
8002726: 2b00 cmp r3, #0
8002728: d015 beq.n 8002756 <HAL_RCC_OscConfig+0x3aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800272a: f7ff f9b1 bl 8001a90 <HAL_GetTick>
800272e: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002730: e00a b.n 8002748 <HAL_RCC_OscConfig+0x39c>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8002732: f7ff f9ad bl 8001a90 <HAL_GetTick>
8002736: 4602 mov r2, r0
8002738: 693b ldr r3, [r7, #16]
800273a: 1ad3 subs r3, r2, r3
800273c: f241 3288 movw r2, #5000 @ 0x1388
8002740: 4293 cmp r3, r2
8002742: d901 bls.n 8002748 <HAL_RCC_OscConfig+0x39c>
{
return HAL_TIMEOUT;
8002744: 2303 movs r3, #3
8002746: e0ce b.n 80028e6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002748: 4b4b ldr r3, [pc, #300] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
800274a: 6f1b ldr r3, [r3, #112] @ 0x70
800274c: f003 0302 and.w r3, r3, #2
8002750: 2b00 cmp r3, #0
8002752: d0ee beq.n 8002732 <HAL_RCC_OscConfig+0x386>
8002754: e014 b.n 8002780 <HAL_RCC_OscConfig+0x3d4>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002756: f7ff f99b bl 8001a90 <HAL_GetTick>
800275a: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
800275c: e00a b.n 8002774 <HAL_RCC_OscConfig+0x3c8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800275e: f7ff f997 bl 8001a90 <HAL_GetTick>
8002762: 4602 mov r2, r0
8002764: 693b ldr r3, [r7, #16]
8002766: 1ad3 subs r3, r2, r3
8002768: f241 3288 movw r2, #5000 @ 0x1388
800276c: 4293 cmp r3, r2
800276e: d901 bls.n 8002774 <HAL_RCC_OscConfig+0x3c8>
{
return HAL_TIMEOUT;
8002770: 2303 movs r3, #3
8002772: e0b8 b.n 80028e6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8002774: 4b40 ldr r3, [pc, #256] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
8002776: 6f1b ldr r3, [r3, #112] @ 0x70
8002778: f003 0302 and.w r3, r3, #2
800277c: 2b00 cmp r3, #0
800277e: d1ee bne.n 800275e <HAL_RCC_OscConfig+0x3b2>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
8002780: 7dfb ldrb r3, [r7, #23]
8002782: 2b01 cmp r3, #1
8002784: d105 bne.n 8002792 <HAL_RCC_OscConfig+0x3e6>
{
__HAL_RCC_PWR_CLK_DISABLE();
8002786: 4b3c ldr r3, [pc, #240] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
8002788: 6c1b ldr r3, [r3, #64] @ 0x40
800278a: 4a3b ldr r2, [pc, #236] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
800278c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8002790: 6413 str r3, [r2, #64] @ 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8002792: 687b ldr r3, [r7, #4]
8002794: 699b ldr r3, [r3, #24]
8002796: 2b00 cmp r3, #0
8002798: f000 80a4 beq.w 80028e4 <HAL_RCC_OscConfig+0x538>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
800279c: 4b36 ldr r3, [pc, #216] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
800279e: 689b ldr r3, [r3, #8]
80027a0: f003 030c and.w r3, r3, #12
80027a4: 2b08 cmp r3, #8
80027a6: d06b beq.n 8002880 <HAL_RCC_OscConfig+0x4d4>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80027a8: 687b ldr r3, [r7, #4]
80027aa: 699b ldr r3, [r3, #24]
80027ac: 2b02 cmp r3, #2
80027ae: d149 bne.n 8002844 <HAL_RCC_OscConfig+0x498>
#if defined (RCC_PLLCFGR_PLLR)
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80027b0: 4b31 ldr r3, [pc, #196] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
80027b2: 681b ldr r3, [r3, #0]
80027b4: 4a30 ldr r2, [pc, #192] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
80027b6: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
80027ba: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80027bc: f7ff f968 bl 8001a90 <HAL_GetTick>
80027c0: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80027c2: e008 b.n 80027d6 <HAL_RCC_OscConfig+0x42a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80027c4: f7ff f964 bl 8001a90 <HAL_GetTick>
80027c8: 4602 mov r2, r0
80027ca: 693b ldr r3, [r7, #16]
80027cc: 1ad3 subs r3, r2, r3
80027ce: 2b02 cmp r3, #2
80027d0: d901 bls.n 80027d6 <HAL_RCC_OscConfig+0x42a>
{
return HAL_TIMEOUT;
80027d2: 2303 movs r3, #3
80027d4: e087 b.n 80028e6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80027d6: 4b28 ldr r3, [pc, #160] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
80027d8: 681b ldr r3, [r3, #0]
80027da: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80027de: 2b00 cmp r3, #0
80027e0: d1f0 bne.n 80027c4 <HAL_RCC_OscConfig+0x418>
RCC_OscInitStruct->PLL.PLLN,
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#else
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
80027e2: 687b ldr r3, [r7, #4]
80027e4: 69da ldr r2, [r3, #28]
80027e6: 687b ldr r3, [r7, #4]
80027e8: 6a1b ldr r3, [r3, #32]
80027ea: 431a orrs r2, r3
80027ec: 687b ldr r3, [r7, #4]
80027ee: 6a5b ldr r3, [r3, #36] @ 0x24
80027f0: 019b lsls r3, r3, #6
80027f2: 431a orrs r2, r3
80027f4: 687b ldr r3, [r7, #4]
80027f6: 6a9b ldr r3, [r3, #40] @ 0x28
80027f8: 085b lsrs r3, r3, #1
80027fa: 3b01 subs r3, #1
80027fc: 041b lsls r3, r3, #16
80027fe: 431a orrs r2, r3
8002800: 687b ldr r3, [r7, #4]
8002802: 6adb ldr r3, [r3, #44] @ 0x2c
8002804: 061b lsls r3, r3, #24
8002806: 4313 orrs r3, r2
8002808: 4a1b ldr r2, [pc, #108] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
800280a: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
800280e: 6053 str r3, [r2, #4]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8002810: 4b19 ldr r3, [pc, #100] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
8002812: 681b ldr r3, [r3, #0]
8002814: 4a18 ldr r2, [pc, #96] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
8002816: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
800281a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800281c: f7ff f938 bl 8001a90 <HAL_GetTick>
8002820: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002822: e008 b.n 8002836 <HAL_RCC_OscConfig+0x48a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002824: f7ff f934 bl 8001a90 <HAL_GetTick>
8002828: 4602 mov r2, r0
800282a: 693b ldr r3, [r7, #16]
800282c: 1ad3 subs r3, r2, r3
800282e: 2b02 cmp r3, #2
8002830: d901 bls.n 8002836 <HAL_RCC_OscConfig+0x48a>
{
return HAL_TIMEOUT;
8002832: 2303 movs r3, #3
8002834: e057 b.n 80028e6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002836: 4b10 ldr r3, [pc, #64] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
8002838: 681b ldr r3, [r3, #0]
800283a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800283e: 2b00 cmp r3, #0
8002840: d0f0 beq.n 8002824 <HAL_RCC_OscConfig+0x478>
8002842: e04f b.n 80028e4 <HAL_RCC_OscConfig+0x538>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002844: 4b0c ldr r3, [pc, #48] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
8002846: 681b ldr r3, [r3, #0]
8002848: 4a0b ldr r2, [pc, #44] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
800284a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
800284e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002850: f7ff f91e bl 8001a90 <HAL_GetTick>
8002854: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002856: e008 b.n 800286a <HAL_RCC_OscConfig+0x4be>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002858: f7ff f91a bl 8001a90 <HAL_GetTick>
800285c: 4602 mov r2, r0
800285e: 693b ldr r3, [r7, #16]
8002860: 1ad3 subs r3, r2, r3
8002862: 2b02 cmp r3, #2
8002864: d901 bls.n 800286a <HAL_RCC_OscConfig+0x4be>
{
return HAL_TIMEOUT;
8002866: 2303 movs r3, #3
8002868: e03d b.n 80028e6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800286a: 4b03 ldr r3, [pc, #12] @ (8002878 <HAL_RCC_OscConfig+0x4cc>)
800286c: 681b ldr r3, [r3, #0]
800286e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002872: 2b00 cmp r3, #0
8002874: d1f0 bne.n 8002858 <HAL_RCC_OscConfig+0x4ac>
8002876: e035 b.n 80028e4 <HAL_RCC_OscConfig+0x538>
8002878: 40023800 .word 0x40023800
800287c: 40007000 .word 0x40007000
}
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
8002880: 4b1b ldr r3, [pc, #108] @ (80028f0 <HAL_RCC_OscConfig+0x544>)
8002882: 685b ldr r3, [r3, #4]
8002884: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8002886: 687b ldr r3, [r7, #4]
8002888: 699b ldr r3, [r3, #24]
800288a: 2b01 cmp r3, #1
800288c: d028 beq.n 80028e0 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800288e: 68fb ldr r3, [r7, #12]
8002890: f403 0280 and.w r2, r3, #4194304 @ 0x400000
8002894: 687b ldr r3, [r7, #4]
8002896: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8002898: 429a cmp r2, r3
800289a: d121 bne.n 80028e0 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
800289c: 68fb ldr r3, [r7, #12]
800289e: f003 023f and.w r2, r3, #63 @ 0x3f
80028a2: 687b ldr r3, [r7, #4]
80028a4: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80028a6: 429a cmp r2, r3
80028a8: d11a bne.n 80028e0 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
80028aa: 68fa ldr r2, [r7, #12]
80028ac: f647 73c0 movw r3, #32704 @ 0x7fc0
80028b0: 4013 ands r3, r2
80028b2: 687a ldr r2, [r7, #4]
80028b4: 6a52 ldr r2, [r2, #36] @ 0x24
80028b6: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
80028b8: 4293 cmp r3, r2
80028ba: d111 bne.n 80028e0 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
80028bc: 68fb ldr r3, [r7, #12]
80028be: f403 3240 and.w r2, r3, #196608 @ 0x30000
80028c2: 687b ldr r3, [r7, #4]
80028c4: 6a9b ldr r3, [r3, #40] @ 0x28
80028c6: 085b lsrs r3, r3, #1
80028c8: 3b01 subs r3, #1
80028ca: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
80028cc: 429a cmp r2, r3
80028ce: d107 bne.n 80028e0 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
80028d0: 68fb ldr r3, [r7, #12]
80028d2: f003 6270 and.w r2, r3, #251658240 @ 0xf000000
80028d6: 687b ldr r3, [r7, #4]
80028d8: 6adb ldr r3, [r3, #44] @ 0x2c
80028da: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
80028dc: 429a cmp r2, r3
80028de: d001 beq.n 80028e4 <HAL_RCC_OscConfig+0x538>
#endif
{
return HAL_ERROR;
80028e0: 2301 movs r3, #1
80028e2: e000 b.n 80028e6 <HAL_RCC_OscConfig+0x53a>
}
}
}
return HAL_OK;
80028e4: 2300 movs r3, #0
}
80028e6: 4618 mov r0, r3
80028e8: 3718 adds r7, #24
80028ea: 46bd mov sp, r7
80028ec: bd80 pop {r7, pc}
80028ee: bf00 nop
80028f0: 40023800 .word 0x40023800
080028f4 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80028f4: b580 push {r7, lr}
80028f6: b084 sub sp, #16
80028f8: af00 add r7, sp, #0
80028fa: 6078 str r0, [r7, #4]
80028fc: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
80028fe: 2300 movs r3, #0
8002900: 60fb str r3, [r7, #12]
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8002902: 687b ldr r3, [r7, #4]
8002904: 2b00 cmp r3, #0
8002906: d101 bne.n 800290c <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8002908: 2301 movs r3, #1
800290a: e0d0 b.n 8002aae <HAL_RCC_ClockConfig+0x1ba>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
800290c: 4b6a ldr r3, [pc, #424] @ (8002ab8 <HAL_RCC_ClockConfig+0x1c4>)
800290e: 681b ldr r3, [r3, #0]
8002910: f003 030f and.w r3, r3, #15
8002914: 683a ldr r2, [r7, #0]
8002916: 429a cmp r2, r3
8002918: d910 bls.n 800293c <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800291a: 4b67 ldr r3, [pc, #412] @ (8002ab8 <HAL_RCC_ClockConfig+0x1c4>)
800291c: 681b ldr r3, [r3, #0]
800291e: f023 020f bic.w r2, r3, #15
8002922: 4965 ldr r1, [pc, #404] @ (8002ab8 <HAL_RCC_ClockConfig+0x1c4>)
8002924: 683b ldr r3, [r7, #0]
8002926: 4313 orrs r3, r2
8002928: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
800292a: 4b63 ldr r3, [pc, #396] @ (8002ab8 <HAL_RCC_ClockConfig+0x1c4>)
800292c: 681b ldr r3, [r3, #0]
800292e: f003 030f and.w r3, r3, #15
8002932: 683a ldr r2, [r7, #0]
8002934: 429a cmp r2, r3
8002936: d001 beq.n 800293c <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
8002938: 2301 movs r3, #1
800293a: e0b8 b.n 8002aae <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800293c: 687b ldr r3, [r7, #4]
800293e: 681b ldr r3, [r3, #0]
8002940: f003 0302 and.w r3, r3, #2
8002944: 2b00 cmp r3, #0
8002946: d020 beq.n 800298a <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002948: 687b ldr r3, [r7, #4]
800294a: 681b ldr r3, [r3, #0]
800294c: f003 0304 and.w r3, r3, #4
8002950: 2b00 cmp r3, #0
8002952: d005 beq.n 8002960 <HAL_RCC_ClockConfig+0x6c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8002954: 4b59 ldr r3, [pc, #356] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
8002956: 689b ldr r3, [r3, #8]
8002958: 4a58 ldr r2, [pc, #352] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
800295a: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00
800295e: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002960: 687b ldr r3, [r7, #4]
8002962: 681b ldr r3, [r3, #0]
8002964: f003 0308 and.w r3, r3, #8
8002968: 2b00 cmp r3, #0
800296a: d005 beq.n 8002978 <HAL_RCC_ClockConfig+0x84>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
800296c: 4b53 ldr r3, [pc, #332] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
800296e: 689b ldr r3, [r3, #8]
8002970: 4a52 ldr r2, [pc, #328] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
8002972: f443 4360 orr.w r3, r3, #57344 @ 0xe000
8002976: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002978: 4b50 ldr r3, [pc, #320] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
800297a: 689b ldr r3, [r3, #8]
800297c: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8002980: 687b ldr r3, [r7, #4]
8002982: 689b ldr r3, [r3, #8]
8002984: 494d ldr r1, [pc, #308] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
8002986: 4313 orrs r3, r2
8002988: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800298a: 687b ldr r3, [r7, #4]
800298c: 681b ldr r3, [r3, #0]
800298e: f003 0301 and.w r3, r3, #1
8002992: 2b00 cmp r3, #0
8002994: d040 beq.n 8002a18 <HAL_RCC_ClockConfig+0x124>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8002996: 687b ldr r3, [r7, #4]
8002998: 685b ldr r3, [r3, #4]
800299a: 2b01 cmp r3, #1
800299c: d107 bne.n 80029ae <HAL_RCC_ClockConfig+0xba>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800299e: 4b47 ldr r3, [pc, #284] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
80029a0: 681b ldr r3, [r3, #0]
80029a2: f403 3300 and.w r3, r3, #131072 @ 0x20000
80029a6: 2b00 cmp r3, #0
80029a8: d115 bne.n 80029d6 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
80029aa: 2301 movs r3, #1
80029ac: e07f b.n 8002aae <HAL_RCC_ClockConfig+0x1ba>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
80029ae: 687b ldr r3, [r7, #4]
80029b0: 685b ldr r3, [r3, #4]
80029b2: 2b02 cmp r3, #2
80029b4: d107 bne.n 80029c6 <HAL_RCC_ClockConfig+0xd2>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80029b6: 4b41 ldr r3, [pc, #260] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
80029b8: 681b ldr r3, [r3, #0]
80029ba: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80029be: 2b00 cmp r3, #0
80029c0: d109 bne.n 80029d6 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
80029c2: 2301 movs r3, #1
80029c4: e073 b.n 8002aae <HAL_RCC_ClockConfig+0x1ba>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80029c6: 4b3d ldr r3, [pc, #244] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
80029c8: 681b ldr r3, [r3, #0]
80029ca: f003 0302 and.w r3, r3, #2
80029ce: 2b00 cmp r3, #0
80029d0: d101 bne.n 80029d6 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
80029d2: 2301 movs r3, #1
80029d4: e06b b.n 8002aae <HAL_RCC_ClockConfig+0x1ba>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
80029d6: 4b39 ldr r3, [pc, #228] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
80029d8: 689b ldr r3, [r3, #8]
80029da: f023 0203 bic.w r2, r3, #3
80029de: 687b ldr r3, [r7, #4]
80029e0: 685b ldr r3, [r3, #4]
80029e2: 4936 ldr r1, [pc, #216] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
80029e4: 4313 orrs r3, r2
80029e6: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80029e8: f7ff f852 bl 8001a90 <HAL_GetTick>
80029ec: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80029ee: e00a b.n 8002a06 <HAL_RCC_ClockConfig+0x112>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80029f0: f7ff f84e bl 8001a90 <HAL_GetTick>
80029f4: 4602 mov r2, r0
80029f6: 68fb ldr r3, [r7, #12]
80029f8: 1ad3 subs r3, r2, r3
80029fa: f241 3288 movw r2, #5000 @ 0x1388
80029fe: 4293 cmp r3, r2
8002a00: d901 bls.n 8002a06 <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
8002a02: 2303 movs r3, #3
8002a04: e053 b.n 8002aae <HAL_RCC_ClockConfig+0x1ba>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002a06: 4b2d ldr r3, [pc, #180] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
8002a08: 689b ldr r3, [r3, #8]
8002a0a: f003 020c and.w r2, r3, #12
8002a0e: 687b ldr r3, [r7, #4]
8002a10: 685b ldr r3, [r3, #4]
8002a12: 009b lsls r3, r3, #2
8002a14: 429a cmp r2, r3
8002a16: d1eb bne.n 80029f0 <HAL_RCC_ClockConfig+0xfc>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8002a18: 4b27 ldr r3, [pc, #156] @ (8002ab8 <HAL_RCC_ClockConfig+0x1c4>)
8002a1a: 681b ldr r3, [r3, #0]
8002a1c: f003 030f and.w r3, r3, #15
8002a20: 683a ldr r2, [r7, #0]
8002a22: 429a cmp r2, r3
8002a24: d210 bcs.n 8002a48 <HAL_RCC_ClockConfig+0x154>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002a26: 4b24 ldr r3, [pc, #144] @ (8002ab8 <HAL_RCC_ClockConfig+0x1c4>)
8002a28: 681b ldr r3, [r3, #0]
8002a2a: f023 020f bic.w r2, r3, #15
8002a2e: 4922 ldr r1, [pc, #136] @ (8002ab8 <HAL_RCC_ClockConfig+0x1c4>)
8002a30: 683b ldr r3, [r7, #0]
8002a32: 4313 orrs r3, r2
8002a34: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8002a36: 4b20 ldr r3, [pc, #128] @ (8002ab8 <HAL_RCC_ClockConfig+0x1c4>)
8002a38: 681b ldr r3, [r3, #0]
8002a3a: f003 030f and.w r3, r3, #15
8002a3e: 683a ldr r2, [r7, #0]
8002a40: 429a cmp r2, r3
8002a42: d001 beq.n 8002a48 <HAL_RCC_ClockConfig+0x154>
{
return HAL_ERROR;
8002a44: 2301 movs r3, #1
8002a46: e032 b.n 8002aae <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002a48: 687b ldr r3, [r7, #4]
8002a4a: 681b ldr r3, [r3, #0]
8002a4c: f003 0304 and.w r3, r3, #4
8002a50: 2b00 cmp r3, #0
8002a52: d008 beq.n 8002a66 <HAL_RCC_ClockConfig+0x172>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8002a54: 4b19 ldr r3, [pc, #100] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
8002a56: 689b ldr r3, [r3, #8]
8002a58: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00
8002a5c: 687b ldr r3, [r7, #4]
8002a5e: 68db ldr r3, [r3, #12]
8002a60: 4916 ldr r1, [pc, #88] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
8002a62: 4313 orrs r3, r2
8002a64: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002a66: 687b ldr r3, [r7, #4]
8002a68: 681b ldr r3, [r3, #0]
8002a6a: f003 0308 and.w r3, r3, #8
8002a6e: 2b00 cmp r3, #0
8002a70: d009 beq.n 8002a86 <HAL_RCC_ClockConfig+0x192>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
8002a72: 4b12 ldr r3, [pc, #72] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
8002a74: 689b ldr r3, [r3, #8]
8002a76: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8002a7a: 687b ldr r3, [r7, #4]
8002a7c: 691b ldr r3, [r3, #16]
8002a7e: 00db lsls r3, r3, #3
8002a80: 490e ldr r1, [pc, #56] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
8002a82: 4313 orrs r3, r2
8002a84: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8002a86: f000 f821 bl 8002acc <HAL_RCC_GetSysClockFreq>
8002a8a: 4602 mov r2, r0
8002a8c: 4b0b ldr r3, [pc, #44] @ (8002abc <HAL_RCC_ClockConfig+0x1c8>)
8002a8e: 689b ldr r3, [r3, #8]
8002a90: 091b lsrs r3, r3, #4
8002a92: f003 030f and.w r3, r3, #15
8002a96: 490a ldr r1, [pc, #40] @ (8002ac0 <HAL_RCC_ClockConfig+0x1cc>)
8002a98: 5ccb ldrb r3, [r1, r3]
8002a9a: fa22 f303 lsr.w r3, r2, r3
8002a9e: 4a09 ldr r2, [pc, #36] @ (8002ac4 <HAL_RCC_ClockConfig+0x1d0>)
8002aa0: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
8002aa2: 4b09 ldr r3, [pc, #36] @ (8002ac8 <HAL_RCC_ClockConfig+0x1d4>)
8002aa4: 681b ldr r3, [r3, #0]
8002aa6: 4618 mov r0, r3
8002aa8: f7fe fe5a bl 8001760 <HAL_InitTick>
return HAL_OK;
8002aac: 2300 movs r3, #0
}
8002aae: 4618 mov r0, r3
8002ab0: 3710 adds r7, #16
8002ab2: 46bd mov sp, r7
8002ab4: bd80 pop {r7, pc}
8002ab6: bf00 nop
8002ab8: 40023c00 .word 0x40023c00
8002abc: 40023800 .word 0x40023800
8002ac0: 080054fc .word 0x080054fc
8002ac4: 20000000 .word 0x20000000
8002ac8: 20000004 .word 0x20000004
08002acc <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8002acc: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8002ad0: b090 sub sp, #64 @ 0x40
8002ad2: af00 add r7, sp, #0
uint32_t pllm = 0, pllvco = 0, pllp = 0;
8002ad4: 2300 movs r3, #0
8002ad6: 637b str r3, [r7, #52] @ 0x34
8002ad8: 2300 movs r3, #0
8002ada: 63fb str r3, [r7, #60] @ 0x3c
8002adc: 2300 movs r3, #0
8002ade: 633b str r3, [r7, #48] @ 0x30
uint32_t sysclockfreq = 0;
8002ae0: 2300 movs r3, #0
8002ae2: 63bb str r3, [r7, #56] @ 0x38
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8002ae4: 4b59 ldr r3, [pc, #356] @ (8002c4c <HAL_RCC_GetSysClockFreq+0x180>)
8002ae6: 689b ldr r3, [r3, #8]
8002ae8: f003 030c and.w r3, r3, #12
8002aec: 2b08 cmp r3, #8
8002aee: d00d beq.n 8002b0c <HAL_RCC_GetSysClockFreq+0x40>
8002af0: 2b08 cmp r3, #8
8002af2: f200 80a1 bhi.w 8002c38 <HAL_RCC_GetSysClockFreq+0x16c>
8002af6: 2b00 cmp r3, #0
8002af8: d002 beq.n 8002b00 <HAL_RCC_GetSysClockFreq+0x34>
8002afa: 2b04 cmp r3, #4
8002afc: d003 beq.n 8002b06 <HAL_RCC_GetSysClockFreq+0x3a>
8002afe: e09b b.n 8002c38 <HAL_RCC_GetSysClockFreq+0x16c>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8002b00: 4b53 ldr r3, [pc, #332] @ (8002c50 <HAL_RCC_GetSysClockFreq+0x184>)
8002b02: 63bb str r3, [r7, #56] @ 0x38
break;
8002b04: e09b b.n 8002c3e <HAL_RCC_GetSysClockFreq+0x172>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8002b06: 4b53 ldr r3, [pc, #332] @ (8002c54 <HAL_RCC_GetSysClockFreq+0x188>)
8002b08: 63bb str r3, [r7, #56] @ 0x38
break;
8002b0a: e098 b.n 8002c3e <HAL_RCC_GetSysClockFreq+0x172>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8002b0c: 4b4f ldr r3, [pc, #316] @ (8002c4c <HAL_RCC_GetSysClockFreq+0x180>)
8002b0e: 685b ldr r3, [r3, #4]
8002b10: f003 033f and.w r3, r3, #63 @ 0x3f
8002b14: 637b str r3, [r7, #52] @ 0x34
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
8002b16: 4b4d ldr r3, [pc, #308] @ (8002c4c <HAL_RCC_GetSysClockFreq+0x180>)
8002b18: 685b ldr r3, [r3, #4]
8002b1a: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8002b1e: 2b00 cmp r3, #0
8002b20: d028 beq.n 8002b74 <HAL_RCC_GetSysClockFreq+0xa8>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8002b22: 4b4a ldr r3, [pc, #296] @ (8002c4c <HAL_RCC_GetSysClockFreq+0x180>)
8002b24: 685b ldr r3, [r3, #4]
8002b26: 099b lsrs r3, r3, #6
8002b28: 2200 movs r2, #0
8002b2a: 623b str r3, [r7, #32]
8002b2c: 627a str r2, [r7, #36] @ 0x24
8002b2e: 6a3b ldr r3, [r7, #32]
8002b30: f3c3 0008 ubfx r0, r3, #0, #9
8002b34: 2100 movs r1, #0
8002b36: 4b47 ldr r3, [pc, #284] @ (8002c54 <HAL_RCC_GetSysClockFreq+0x188>)
8002b38: fb03 f201 mul.w r2, r3, r1
8002b3c: 2300 movs r3, #0
8002b3e: fb00 f303 mul.w r3, r0, r3
8002b42: 4413 add r3, r2
8002b44: 4a43 ldr r2, [pc, #268] @ (8002c54 <HAL_RCC_GetSysClockFreq+0x188>)
8002b46: fba0 1202 umull r1, r2, r0, r2
8002b4a: 62fa str r2, [r7, #44] @ 0x2c
8002b4c: 460a mov r2, r1
8002b4e: 62ba str r2, [r7, #40] @ 0x28
8002b50: 6afa ldr r2, [r7, #44] @ 0x2c
8002b52: 4413 add r3, r2
8002b54: 62fb str r3, [r7, #44] @ 0x2c
8002b56: 6b7b ldr r3, [r7, #52] @ 0x34
8002b58: 2200 movs r2, #0
8002b5a: 61bb str r3, [r7, #24]
8002b5c: 61fa str r2, [r7, #28]
8002b5e: e9d7 2306 ldrd r2, r3, [r7, #24]
8002b62: e9d7 010a ldrd r0, r1, [r7, #40] @ 0x28
8002b66: f7fd fbab bl 80002c0 <__aeabi_uldivmod>
8002b6a: 4602 mov r2, r0
8002b6c: 460b mov r3, r1
8002b6e: 4613 mov r3, r2
8002b70: 63fb str r3, [r7, #60] @ 0x3c
8002b72: e053 b.n 8002c1c <HAL_RCC_GetSysClockFreq+0x150>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8002b74: 4b35 ldr r3, [pc, #212] @ (8002c4c <HAL_RCC_GetSysClockFreq+0x180>)
8002b76: 685b ldr r3, [r3, #4]
8002b78: 099b lsrs r3, r3, #6
8002b7a: 2200 movs r2, #0
8002b7c: 613b str r3, [r7, #16]
8002b7e: 617a str r2, [r7, #20]
8002b80: 693b ldr r3, [r7, #16]
8002b82: f3c3 0a08 ubfx sl, r3, #0, #9
8002b86: f04f 0b00 mov.w fp, #0
8002b8a: 4652 mov r2, sl
8002b8c: 465b mov r3, fp
8002b8e: f04f 0000 mov.w r0, #0
8002b92: f04f 0100 mov.w r1, #0
8002b96: 0159 lsls r1, r3, #5
8002b98: ea41 61d2 orr.w r1, r1, r2, lsr #27
8002b9c: 0150 lsls r0, r2, #5
8002b9e: 4602 mov r2, r0
8002ba0: 460b mov r3, r1
8002ba2: ebb2 080a subs.w r8, r2, sl
8002ba6: eb63 090b sbc.w r9, r3, fp
8002baa: f04f 0200 mov.w r2, #0
8002bae: f04f 0300 mov.w r3, #0
8002bb2: ea4f 1389 mov.w r3, r9, lsl #6
8002bb6: ea43 6398 orr.w r3, r3, r8, lsr #26
8002bba: ea4f 1288 mov.w r2, r8, lsl #6
8002bbe: ebb2 0408 subs.w r4, r2, r8
8002bc2: eb63 0509 sbc.w r5, r3, r9
8002bc6: f04f 0200 mov.w r2, #0
8002bca: f04f 0300 mov.w r3, #0
8002bce: 00eb lsls r3, r5, #3
8002bd0: ea43 7354 orr.w r3, r3, r4, lsr #29
8002bd4: 00e2 lsls r2, r4, #3
8002bd6: 4614 mov r4, r2
8002bd8: 461d mov r5, r3
8002bda: eb14 030a adds.w r3, r4, sl
8002bde: 603b str r3, [r7, #0]
8002be0: eb45 030b adc.w r3, r5, fp
8002be4: 607b str r3, [r7, #4]
8002be6: f04f 0200 mov.w r2, #0
8002bea: f04f 0300 mov.w r3, #0
8002bee: e9d7 4500 ldrd r4, r5, [r7]
8002bf2: 4629 mov r1, r5
8002bf4: 028b lsls r3, r1, #10
8002bf6: 4621 mov r1, r4
8002bf8: ea43 5391 orr.w r3, r3, r1, lsr #22
8002bfc: 4621 mov r1, r4
8002bfe: 028a lsls r2, r1, #10
8002c00: 4610 mov r0, r2
8002c02: 4619 mov r1, r3
8002c04: 6b7b ldr r3, [r7, #52] @ 0x34
8002c06: 2200 movs r2, #0
8002c08: 60bb str r3, [r7, #8]
8002c0a: 60fa str r2, [r7, #12]
8002c0c: e9d7 2302 ldrd r2, r3, [r7, #8]
8002c10: f7fd fb56 bl 80002c0 <__aeabi_uldivmod>
8002c14: 4602 mov r2, r0
8002c16: 460b mov r3, r1
8002c18: 4613 mov r3, r2
8002c1a: 63fb str r3, [r7, #60] @ 0x3c
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
8002c1c: 4b0b ldr r3, [pc, #44] @ (8002c4c <HAL_RCC_GetSysClockFreq+0x180>)
8002c1e: 685b ldr r3, [r3, #4]
8002c20: 0c1b lsrs r3, r3, #16
8002c22: f003 0303 and.w r3, r3, #3
8002c26: 3301 adds r3, #1
8002c28: 005b lsls r3, r3, #1
8002c2a: 633b str r3, [r7, #48] @ 0x30
sysclockfreq = pllvco / pllp;
8002c2c: 6bfa ldr r2, [r7, #60] @ 0x3c
8002c2e: 6b3b ldr r3, [r7, #48] @ 0x30
8002c30: fbb2 f3f3 udiv r3, r2, r3
8002c34: 63bb str r3, [r7, #56] @ 0x38
break;
8002c36: e002 b.n 8002c3e <HAL_RCC_GetSysClockFreq+0x172>
}
default:
{
sysclockfreq = HSI_VALUE;
8002c38: 4b05 ldr r3, [pc, #20] @ (8002c50 <HAL_RCC_GetSysClockFreq+0x184>)
8002c3a: 63bb str r3, [r7, #56] @ 0x38
break;
8002c3c: bf00 nop
}
}
return sysclockfreq;
8002c3e: 6bbb ldr r3, [r7, #56] @ 0x38
}
8002c40: 4618 mov r0, r3
8002c42: 3740 adds r7, #64 @ 0x40
8002c44: 46bd mov sp, r7
8002c46: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8002c4a: bf00 nop
8002c4c: 40023800 .word 0x40023800
8002c50: 00f42400 .word 0x00f42400
8002c54: 017d7840 .word 0x017d7840
08002c58 <HAL_RCC_GetHCLKFreq>:
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8002c58: b480 push {r7}
8002c5a: af00 add r7, sp, #0
return SystemCoreClock;
8002c5c: 4b03 ldr r3, [pc, #12] @ (8002c6c <HAL_RCC_GetHCLKFreq+0x14>)
8002c5e: 681b ldr r3, [r3, #0]
}
8002c60: 4618 mov r0, r3
8002c62: 46bd mov sp, r7
8002c64: f85d 7b04 ldr.w r7, [sp], #4
8002c68: 4770 bx lr
8002c6a: bf00 nop
8002c6c: 20000000 .word 0x20000000
08002c70 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8002c70: b580 push {r7, lr}
8002c72: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8002c74: f7ff fff0 bl 8002c58 <HAL_RCC_GetHCLKFreq>
8002c78: 4602 mov r2, r0
8002c7a: 4b05 ldr r3, [pc, #20] @ (8002c90 <HAL_RCC_GetPCLK1Freq+0x20>)
8002c7c: 689b ldr r3, [r3, #8]
8002c7e: 0a9b lsrs r3, r3, #10
8002c80: f003 0307 and.w r3, r3, #7
8002c84: 4903 ldr r1, [pc, #12] @ (8002c94 <HAL_RCC_GetPCLK1Freq+0x24>)
8002c86: 5ccb ldrb r3, [r1, r3]
8002c88: fa22 f303 lsr.w r3, r2, r3
}
8002c8c: 4618 mov r0, r3
8002c8e: bd80 pop {r7, pc}
8002c90: 40023800 .word 0x40023800
8002c94: 0800550c .word 0x0800550c
08002c98 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8002c98: b580 push {r7, lr}
8002c9a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
8002c9c: f7ff ffdc bl 8002c58 <HAL_RCC_GetHCLKFreq>
8002ca0: 4602 mov r2, r0
8002ca2: 4b05 ldr r3, [pc, #20] @ (8002cb8 <HAL_RCC_GetPCLK2Freq+0x20>)
8002ca4: 689b ldr r3, [r3, #8]
8002ca6: 0b5b lsrs r3, r3, #13
8002ca8: f003 0307 and.w r3, r3, #7
8002cac: 4903 ldr r1, [pc, #12] @ (8002cbc <HAL_RCC_GetPCLK2Freq+0x24>)
8002cae: 5ccb ldrb r3, [r1, r3]
8002cb0: fa22 f303 lsr.w r3, r2, r3
}
8002cb4: 4618 mov r0, r3
8002cb6: bd80 pop {r7, pc}
8002cb8: 40023800 .word 0x40023800
8002cbc: 0800550c .word 0x0800550c
08002cc0 <HAL_RCC_GetClockConfig>:
* will be configured.
* @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
8002cc0: b480 push {r7}
8002cc2: b083 sub sp, #12
8002cc4: af00 add r7, sp, #0
8002cc6: 6078 str r0, [r7, #4]
8002cc8: 6039 str r1, [r7, #0]
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
8002cca: 687b ldr r3, [r7, #4]
8002ccc: 220f movs r2, #15
8002cce: 601a str r2, [r3, #0]
/* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
8002cd0: 4b12 ldr r3, [pc, #72] @ (8002d1c <HAL_RCC_GetClockConfig+0x5c>)
8002cd2: 689b ldr r3, [r3, #8]
8002cd4: f003 0203 and.w r2, r3, #3
8002cd8: 687b ldr r3, [r7, #4]
8002cda: 605a str r2, [r3, #4]
/* Get the HCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
8002cdc: 4b0f ldr r3, [pc, #60] @ (8002d1c <HAL_RCC_GetClockConfig+0x5c>)
8002cde: 689b ldr r3, [r3, #8]
8002ce0: f003 02f0 and.w r2, r3, #240 @ 0xf0
8002ce4: 687b ldr r3, [r7, #4]
8002ce6: 609a str r2, [r3, #8]
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
8002ce8: 4b0c ldr r3, [pc, #48] @ (8002d1c <HAL_RCC_GetClockConfig+0x5c>)
8002cea: 689b ldr r3, [r3, #8]
8002cec: f403 52e0 and.w r2, r3, #7168 @ 0x1c00
8002cf0: 687b ldr r3, [r7, #4]
8002cf2: 60da str r2, [r3, #12]
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
8002cf4: 4b09 ldr r3, [pc, #36] @ (8002d1c <HAL_RCC_GetClockConfig+0x5c>)
8002cf6: 689b ldr r3, [r3, #8]
8002cf8: 08db lsrs r3, r3, #3
8002cfa: f403 52e0 and.w r2, r3, #7168 @ 0x1c00
8002cfe: 687b ldr r3, [r7, #4]
8002d00: 611a str r2, [r3, #16]
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
8002d02: 4b07 ldr r3, [pc, #28] @ (8002d20 <HAL_RCC_GetClockConfig+0x60>)
8002d04: 681b ldr r3, [r3, #0]
8002d06: f003 020f and.w r2, r3, #15
8002d0a: 683b ldr r3, [r7, #0]
8002d0c: 601a str r2, [r3, #0]
}
8002d0e: bf00 nop
8002d10: 370c adds r7, #12
8002d12: 46bd mov sp, r7
8002d14: f85d 7b04 ldr.w r7, [sp], #4
8002d18: 4770 bx lr
8002d1a: bf00 nop
8002d1c: 40023800 .word 0x40023800
8002d20: 40023c00 .word 0x40023c00
08002d24 <HAL_RCCEx_PeriphCLKConfig>:
* the backup registers) are set to their reset values.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8002d24: b580 push {r7, lr}
8002d26: b088 sub sp, #32
8002d28: af00 add r7, sp, #0
8002d2a: 6078 str r0, [r7, #4]
uint32_t tickstart = 0;
8002d2c: 2300 movs r3, #0
8002d2e: 617b str r3, [r7, #20]
uint32_t tmpreg0 = 0;
8002d30: 2300 movs r3, #0
8002d32: 613b str r3, [r7, #16]
uint32_t plli2sused = 0;
8002d34: 2300 movs r3, #0
8002d36: 61fb str r3, [r7, #28]
uint32_t pllsaiused = 0;
8002d38: 2300 movs r3, #0
8002d3a: 61bb str r3, [r7, #24]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*----------------------------------- I2S configuration ----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
8002d3c: 687b ldr r3, [r7, #4]
8002d3e: 681b ldr r3, [r3, #0]
8002d40: f003 0301 and.w r3, r3, #1
8002d44: 2b00 cmp r3, #0
8002d46: d012 beq.n 8002d6e <HAL_RCCEx_PeriphCLKConfig+0x4a>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure I2S Clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
8002d48: 4b65 ldr r3, [pc, #404] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002d4a: 689b ldr r3, [r3, #8]
8002d4c: 4a64 ldr r2, [pc, #400] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002d4e: f423 0300 bic.w r3, r3, #8388608 @ 0x800000
8002d52: 6093 str r3, [r2, #8]
8002d54: 4b62 ldr r3, [pc, #392] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002d56: 689a ldr r2, [r3, #8]
8002d58: 687b ldr r3, [r7, #4]
8002d5a: 6adb ldr r3, [r3, #44] @ 0x2c
8002d5c: 4960 ldr r1, [pc, #384] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002d5e: 4313 orrs r3, r2
8002d60: 608b str r3, [r1, #8]
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
8002d62: 687b ldr r3, [r7, #4]
8002d64: 6adb ldr r3, [r3, #44] @ 0x2c
8002d66: 2b00 cmp r3, #0
8002d68: d101 bne.n 8002d6e <HAL_RCCEx_PeriphCLKConfig+0x4a>
{
plli2sused = 1;
8002d6a: 2301 movs r3, #1
8002d6c: 61fb str r3, [r7, #28]
}
}
/*------------------------------------ SAI1 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
8002d6e: 687b ldr r3, [r7, #4]
8002d70: 681b ldr r3, [r3, #0]
8002d72: f403 2300 and.w r3, r3, #524288 @ 0x80000
8002d76: 2b00 cmp r3, #0
8002d78: d017 beq.n 8002daa <HAL_RCCEx_PeriphCLKConfig+0x86>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure SAI1 Clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
8002d7a: 4b59 ldr r3, [pc, #356] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002d7c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8002d80: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
8002d84: 687b ldr r3, [r7, #4]
8002d86: 6b5b ldr r3, [r3, #52] @ 0x34
8002d88: 4955 ldr r1, [pc, #340] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002d8a: 4313 orrs r3, r2
8002d8c: f8c1 308c str.w r3, [r1, #140] @ 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
8002d90: 687b ldr r3, [r7, #4]
8002d92: 6b5b ldr r3, [r3, #52] @ 0x34
8002d94: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8002d98: d101 bne.n 8002d9e <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
plli2sused = 1;
8002d9a: 2301 movs r3, #1
8002d9c: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
8002d9e: 687b ldr r3, [r7, #4]
8002da0: 6b5b ldr r3, [r3, #52] @ 0x34
8002da2: 2b00 cmp r3, #0
8002da4: d101 bne.n 8002daa <HAL_RCCEx_PeriphCLKConfig+0x86>
{
pllsaiused = 1;
8002da6: 2301 movs r3, #1
8002da8: 61bb str r3, [r7, #24]
}
}
/*------------------------------------ SAI2 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
8002daa: 687b ldr r3, [r7, #4]
8002dac: 681b ldr r3, [r3, #0]
8002dae: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8002db2: 2b00 cmp r3, #0
8002db4: d017 beq.n 8002de6 <HAL_RCCEx_PeriphCLKConfig+0xc2>
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
/* Configure SAI2 Clock source */
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
8002db6: 4b4a ldr r3, [pc, #296] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002db8: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8002dbc: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
8002dc0: 687b ldr r3, [r7, #4]
8002dc2: 6b9b ldr r3, [r3, #56] @ 0x38
8002dc4: 4946 ldr r1, [pc, #280] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002dc6: 4313 orrs r3, r2
8002dc8: f8c1 308c str.w r3, [r1, #140] @ 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
8002dcc: 687b ldr r3, [r7, #4]
8002dce: 6b9b ldr r3, [r3, #56] @ 0x38
8002dd0: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8002dd4: d101 bne.n 8002dda <HAL_RCCEx_PeriphCLKConfig+0xb6>
{
plli2sused = 1;
8002dd6: 2301 movs r3, #1
8002dd8: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
8002dda: 687b ldr r3, [r7, #4]
8002ddc: 6b9b ldr r3, [r3, #56] @ 0x38
8002dde: 2b00 cmp r3, #0
8002de0: d101 bne.n 8002de6 <HAL_RCCEx_PeriphCLKConfig+0xc2>
{
pllsaiused = 1;
8002de2: 2301 movs r3, #1
8002de4: 61bb str r3, [r7, #24]
}
}
/*------------------------------------ RTC configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
8002de6: 687b ldr r3, [r7, #4]
8002de8: 681b ldr r3, [r3, #0]
8002dea: f003 0320 and.w r3, r3, #32
8002dee: 2b00 cmp r3, #0
8002df0: f000 808b beq.w 8002f0a <HAL_RCCEx_PeriphCLKConfig+0x1e6>
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
8002df4: 4b3a ldr r3, [pc, #232] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002df6: 6c1b ldr r3, [r3, #64] @ 0x40
8002df8: 4a39 ldr r2, [pc, #228] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002dfa: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002dfe: 6413 str r3, [r2, #64] @ 0x40
8002e00: 4b37 ldr r3, [pc, #220] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002e02: 6c1b ldr r3, [r3, #64] @ 0x40
8002e04: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002e08: 60fb str r3, [r7, #12]
8002e0a: 68fb ldr r3, [r7, #12]
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
8002e0c: 4b35 ldr r3, [pc, #212] @ (8002ee4 <HAL_RCCEx_PeriphCLKConfig+0x1c0>)
8002e0e: 681b ldr r3, [r3, #0]
8002e10: 4a34 ldr r2, [pc, #208] @ (8002ee4 <HAL_RCCEx_PeriphCLKConfig+0x1c0>)
8002e12: f443 7380 orr.w r3, r3, #256 @ 0x100
8002e16: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002e18: f7fe fe3a bl 8001a90 <HAL_GetTick>
8002e1c: 6178 str r0, [r7, #20]
/* Wait for Backup domain Write protection disable */
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
8002e1e: e008 b.n 8002e32 <HAL_RCCEx_PeriphCLKConfig+0x10e>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8002e20: f7fe fe36 bl 8001a90 <HAL_GetTick>
8002e24: 4602 mov r2, r0
8002e26: 697b ldr r3, [r7, #20]
8002e28: 1ad3 subs r3, r2, r3
8002e2a: 2b64 cmp r3, #100 @ 0x64
8002e2c: d901 bls.n 8002e32 <HAL_RCCEx_PeriphCLKConfig+0x10e>
{
return HAL_TIMEOUT;
8002e2e: 2303 movs r3, #3
8002e30: e2bc b.n 80033ac <HAL_RCCEx_PeriphCLKConfig+0x688>
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
8002e32: 4b2c ldr r3, [pc, #176] @ (8002ee4 <HAL_RCCEx_PeriphCLKConfig+0x1c0>)
8002e34: 681b ldr r3, [r3, #0]
8002e36: f403 7380 and.w r3, r3, #256 @ 0x100
8002e3a: 2b00 cmp r3, #0
8002e3c: d0f0 beq.n 8002e20 <HAL_RCCEx_PeriphCLKConfig+0xfc>
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified */
tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
8002e3e: 4b28 ldr r3, [pc, #160] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002e40: 6f1b ldr r3, [r3, #112] @ 0x70
8002e42: f403 7340 and.w r3, r3, #768 @ 0x300
8002e46: 613b str r3, [r7, #16]
if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
8002e48: 693b ldr r3, [r7, #16]
8002e4a: 2b00 cmp r3, #0
8002e4c: d035 beq.n 8002eba <HAL_RCCEx_PeriphCLKConfig+0x196>
8002e4e: 687b ldr r3, [r7, #4]
8002e50: 6a9b ldr r3, [r3, #40] @ 0x28
8002e52: f403 7340 and.w r3, r3, #768 @ 0x300
8002e56: 693a ldr r2, [r7, #16]
8002e58: 429a cmp r2, r3
8002e5a: d02e beq.n 8002eba <HAL_RCCEx_PeriphCLKConfig+0x196>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8002e5c: 4b20 ldr r3, [pc, #128] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002e5e: 6f1b ldr r3, [r3, #112] @ 0x70
8002e60: f423 7340 bic.w r3, r3, #768 @ 0x300
8002e64: 613b str r3, [r7, #16]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8002e66: 4b1e ldr r3, [pc, #120] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002e68: 6f1b ldr r3, [r3, #112] @ 0x70
8002e6a: 4a1d ldr r2, [pc, #116] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002e6c: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002e70: 6713 str r3, [r2, #112] @ 0x70
__HAL_RCC_BACKUPRESET_RELEASE();
8002e72: 4b1b ldr r3, [pc, #108] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002e74: 6f1b ldr r3, [r3, #112] @ 0x70
8002e76: 4a1a ldr r2, [pc, #104] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002e78: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8002e7c: 6713 str r3, [r2, #112] @ 0x70
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg0;
8002e7e: 4a18 ldr r2, [pc, #96] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002e80: 693b ldr r3, [r7, #16]
8002e82: 6713 str r3, [r2, #112] @ 0x70
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
8002e84: 4b16 ldr r3, [pc, #88] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002e86: 6f1b ldr r3, [r3, #112] @ 0x70
8002e88: f003 0301 and.w r3, r3, #1
8002e8c: 2b01 cmp r3, #1
8002e8e: d114 bne.n 8002eba <HAL_RCCEx_PeriphCLKConfig+0x196>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002e90: f7fe fdfe bl 8001a90 <HAL_GetTick>
8002e94: 6178 str r0, [r7, #20]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002e96: e00a b.n 8002eae <HAL_RCCEx_PeriphCLKConfig+0x18a>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8002e98: f7fe fdfa bl 8001a90 <HAL_GetTick>
8002e9c: 4602 mov r2, r0
8002e9e: 697b ldr r3, [r7, #20]
8002ea0: 1ad3 subs r3, r2, r3
8002ea2: f241 3288 movw r2, #5000 @ 0x1388
8002ea6: 4293 cmp r3, r2
8002ea8: d901 bls.n 8002eae <HAL_RCCEx_PeriphCLKConfig+0x18a>
{
return HAL_TIMEOUT;
8002eaa: 2303 movs r3, #3
8002eac: e27e b.n 80033ac <HAL_RCCEx_PeriphCLKConfig+0x688>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002eae: 4b0c ldr r3, [pc, #48] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002eb0: 6f1b ldr r3, [r3, #112] @ 0x70
8002eb2: f003 0302 and.w r3, r3, #2
8002eb6: 2b00 cmp r3, #0
8002eb8: d0ee beq.n 8002e98 <HAL_RCCEx_PeriphCLKConfig+0x174>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8002eba: 687b ldr r3, [r7, #4]
8002ebc: 6a9b ldr r3, [r3, #40] @ 0x28
8002ebe: f403 7340 and.w r3, r3, #768 @ 0x300
8002ec2: f5b3 7f40 cmp.w r3, #768 @ 0x300
8002ec6: d111 bne.n 8002eec <HAL_RCCEx_PeriphCLKConfig+0x1c8>
8002ec8: 4b05 ldr r3, [pc, #20] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002eca: 689b ldr r3, [r3, #8]
8002ecc: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000
8002ed0: 687b ldr r3, [r7, #4]
8002ed2: 6a99 ldr r1, [r3, #40] @ 0x28
8002ed4: 4b04 ldr r3, [pc, #16] @ (8002ee8 <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
8002ed6: 400b ands r3, r1
8002ed8: 4901 ldr r1, [pc, #4] @ (8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002eda: 4313 orrs r3, r2
8002edc: 608b str r3, [r1, #8]
8002ede: e00b b.n 8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x1d4>
8002ee0: 40023800 .word 0x40023800
8002ee4: 40007000 .word 0x40007000
8002ee8: 0ffffcff .word 0x0ffffcff
8002eec: 4ba4 ldr r3, [pc, #656] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002eee: 689b ldr r3, [r3, #8]
8002ef0: 4aa3 ldr r2, [pc, #652] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002ef2: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000
8002ef6: 6093 str r3, [r2, #8]
8002ef8: 4ba1 ldr r3, [pc, #644] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002efa: 6f1a ldr r2, [r3, #112] @ 0x70
8002efc: 687b ldr r3, [r7, #4]
8002efe: 6a9b ldr r3, [r3, #40] @ 0x28
8002f00: f3c3 030b ubfx r3, r3, #0, #12
8002f04: 499e ldr r1, [pc, #632] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002f06: 4313 orrs r3, r2
8002f08: 670b str r3, [r1, #112] @ 0x70
}
/*------------------------------------ TIM configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
8002f0a: 687b ldr r3, [r7, #4]
8002f0c: 681b ldr r3, [r3, #0]
8002f0e: f003 0310 and.w r3, r3, #16
8002f12: 2b00 cmp r3, #0
8002f14: d010 beq.n 8002f38 <HAL_RCCEx_PeriphCLKConfig+0x214>
{
/* Check the parameters */
assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
/* Configure Timer Prescaler */
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
8002f16: 4b9a ldr r3, [pc, #616] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002f18: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8002f1c: 4a98 ldr r2, [pc, #608] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002f1e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8002f22: f8c2 308c str.w r3, [r2, #140] @ 0x8c
8002f26: 4b96 ldr r3, [pc, #600] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002f28: f8d3 208c ldr.w r2, [r3, #140] @ 0x8c
8002f2c: 687b ldr r3, [r7, #4]
8002f2e: 6b1b ldr r3, [r3, #48] @ 0x30
8002f30: 4993 ldr r1, [pc, #588] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002f32: 4313 orrs r3, r2
8002f34: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*-------------------------------------- I2C1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
8002f38: 687b ldr r3, [r7, #4]
8002f3a: 681b ldr r3, [r3, #0]
8002f3c: f403 4380 and.w r3, r3, #16384 @ 0x4000
8002f40: 2b00 cmp r3, #0
8002f42: d00a beq.n 8002f5a <HAL_RCCEx_PeriphCLKConfig+0x236>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
8002f44: 4b8e ldr r3, [pc, #568] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002f46: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002f4a: f423 3240 bic.w r2, r3, #196608 @ 0x30000
8002f4e: 687b ldr r3, [r7, #4]
8002f50: 6ddb ldr r3, [r3, #92] @ 0x5c
8002f52: 498b ldr r1, [pc, #556] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002f54: 4313 orrs r3, r2
8002f56: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- I2C2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
8002f5a: 687b ldr r3, [r7, #4]
8002f5c: 681b ldr r3, [r3, #0]
8002f5e: f403 4300 and.w r3, r3, #32768 @ 0x8000
8002f62: 2b00 cmp r3, #0
8002f64: d00a beq.n 8002f7c <HAL_RCCEx_PeriphCLKConfig+0x258>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
8002f66: 4b86 ldr r3, [pc, #536] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002f68: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002f6c: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
8002f70: 687b ldr r3, [r7, #4]
8002f72: 6e1b ldr r3, [r3, #96] @ 0x60
8002f74: 4982 ldr r1, [pc, #520] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002f76: 4313 orrs r3, r2
8002f78: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- I2C3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
8002f7c: 687b ldr r3, [r7, #4]
8002f7e: 681b ldr r3, [r3, #0]
8002f80: f403 3380 and.w r3, r3, #65536 @ 0x10000
8002f84: 2b00 cmp r3, #0
8002f86: d00a beq.n 8002f9e <HAL_RCCEx_PeriphCLKConfig+0x27a>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
8002f88: 4b7d ldr r3, [pc, #500] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002f8a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002f8e: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
8002f92: 687b ldr r3, [r7, #4]
8002f94: 6e5b ldr r3, [r3, #100] @ 0x64
8002f96: 497a ldr r1, [pc, #488] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002f98: 4313 orrs r3, r2
8002f9a: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
8002f9e: 687b ldr r3, [r7, #4]
8002fa0: 681b ldr r3, [r3, #0]
8002fa2: f003 0340 and.w r3, r3, #64 @ 0x40
8002fa6: 2b00 cmp r3, #0
8002fa8: d00a beq.n 8002fc0 <HAL_RCCEx_PeriphCLKConfig+0x29c>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8002faa: 4b75 ldr r3, [pc, #468] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002fac: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002fb0: f023 0203 bic.w r2, r3, #3
8002fb4: 687b ldr r3, [r7, #4]
8002fb6: 6bdb ldr r3, [r3, #60] @ 0x3c
8002fb8: 4971 ldr r1, [pc, #452] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002fba: 4313 orrs r3, r2
8002fbc: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
8002fc0: 687b ldr r3, [r7, #4]
8002fc2: 681b ldr r3, [r3, #0]
8002fc4: f003 0380 and.w r3, r3, #128 @ 0x80
8002fc8: 2b00 cmp r3, #0
8002fca: d00a beq.n 8002fe2 <HAL_RCCEx_PeriphCLKConfig+0x2be>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
8002fcc: 4b6c ldr r3, [pc, #432] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002fce: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002fd2: f023 020c bic.w r2, r3, #12
8002fd6: 687b ldr r3, [r7, #4]
8002fd8: 6c1b ldr r3, [r3, #64] @ 0x40
8002fda: 4969 ldr r1, [pc, #420] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002fdc: 4313 orrs r3, r2
8002fde: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
8002fe2: 687b ldr r3, [r7, #4]
8002fe4: 681b ldr r3, [r3, #0]
8002fe6: f403 7380 and.w r3, r3, #256 @ 0x100
8002fea: 2b00 cmp r3, #0
8002fec: d00a beq.n 8003004 <HAL_RCCEx_PeriphCLKConfig+0x2e0>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
8002fee: 4b64 ldr r3, [pc, #400] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002ff0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002ff4: f023 0230 bic.w r2, r3, #48 @ 0x30
8002ff8: 687b ldr r3, [r7, #4]
8002ffa: 6c5b ldr r3, [r3, #68] @ 0x44
8002ffc: 4960 ldr r1, [pc, #384] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002ffe: 4313 orrs r3, r2
8003000: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
8003004: 687b ldr r3, [r7, #4]
8003006: 681b ldr r3, [r3, #0]
8003008: f403 7300 and.w r3, r3, #512 @ 0x200
800300c: 2b00 cmp r3, #0
800300e: d00a beq.n 8003026 <HAL_RCCEx_PeriphCLKConfig+0x302>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
8003010: 4b5b ldr r3, [pc, #364] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003012: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003016: f023 02c0 bic.w r2, r3, #192 @ 0xc0
800301a: 687b ldr r3, [r7, #4]
800301c: 6c9b ldr r3, [r3, #72] @ 0x48
800301e: 4958 ldr r1, [pc, #352] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003020: 4313 orrs r3, r2
8003022: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART5 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
8003026: 687b ldr r3, [r7, #4]
8003028: 681b ldr r3, [r3, #0]
800302a: f403 6380 and.w r3, r3, #1024 @ 0x400
800302e: 2b00 cmp r3, #0
8003030: d00a beq.n 8003048 <HAL_RCCEx_PeriphCLKConfig+0x324>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
8003032: 4b53 ldr r3, [pc, #332] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003034: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003038: f423 7240 bic.w r2, r3, #768 @ 0x300
800303c: 687b ldr r3, [r7, #4]
800303e: 6cdb ldr r3, [r3, #76] @ 0x4c
8003040: 494f ldr r1, [pc, #316] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003042: 4313 orrs r3, r2
8003044: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART6 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
8003048: 687b ldr r3, [r7, #4]
800304a: 681b ldr r3, [r3, #0]
800304c: f403 6300 and.w r3, r3, #2048 @ 0x800
8003050: 2b00 cmp r3, #0
8003052: d00a beq.n 800306a <HAL_RCCEx_PeriphCLKConfig+0x346>
{
/* Check the parameters */
assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
/* Configure the USART6 clock source */
__HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
8003054: 4b4a ldr r3, [pc, #296] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003056: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800305a: f423 6240 bic.w r2, r3, #3072 @ 0xc00
800305e: 687b ldr r3, [r7, #4]
8003060: 6d1b ldr r3, [r3, #80] @ 0x50
8003062: 4947 ldr r1, [pc, #284] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003064: 4313 orrs r3, r2
8003066: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART7 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
800306a: 687b ldr r3, [r7, #4]
800306c: 681b ldr r3, [r3, #0]
800306e: f403 5380 and.w r3, r3, #4096 @ 0x1000
8003072: 2b00 cmp r3, #0
8003074: d00a beq.n 800308c <HAL_RCCEx_PeriphCLKConfig+0x368>
{
/* Check the parameters */
assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
/* Configure the UART7 clock source */
__HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
8003076: 4b42 ldr r3, [pc, #264] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003078: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800307c: f423 5240 bic.w r2, r3, #12288 @ 0x3000
8003080: 687b ldr r3, [r7, #4]
8003082: 6d5b ldr r3, [r3, #84] @ 0x54
8003084: 493e ldr r1, [pc, #248] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003086: 4313 orrs r3, r2
8003088: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART8 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
800308c: 687b ldr r3, [r7, #4]
800308e: 681b ldr r3, [r3, #0]
8003090: f403 5300 and.w r3, r3, #8192 @ 0x2000
8003094: 2b00 cmp r3, #0
8003096: d00a beq.n 80030ae <HAL_RCCEx_PeriphCLKConfig+0x38a>
{
/* Check the parameters */
assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
/* Configure the UART8 clock source */
__HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
8003098: 4b39 ldr r3, [pc, #228] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800309a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800309e: f423 4240 bic.w r2, r3, #49152 @ 0xc000
80030a2: 687b ldr r3, [r7, #4]
80030a4: 6d9b ldr r3, [r3, #88] @ 0x58
80030a6: 4936 ldr r1, [pc, #216] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80030a8: 4313 orrs r3, r2
80030aa: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- CK48 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
80030ae: 687b ldr r3, [r7, #4]
80030b0: 681b ldr r3, [r3, #0]
80030b2: f403 1300 and.w r3, r3, #2097152 @ 0x200000
80030b6: 2b00 cmp r3, #0
80030b8: d011 beq.n 80030de <HAL_RCCEx_PeriphCLKConfig+0x3ba>
{
/* Check the parameters */
assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
/* Configure the CLK48 source */
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
80030ba: 4b31 ldr r3, [pc, #196] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80030bc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80030c0: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000
80030c4: 687b ldr r3, [r7, #4]
80030c6: 6f5b ldr r3, [r3, #116] @ 0x74
80030c8: 492d ldr r1, [pc, #180] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80030ca: 4313 orrs r3, r2
80030cc: f8c1 3090 str.w r3, [r1, #144] @ 0x90
/* Enable the PLLSAI when it's used as clock source for CK48 */
if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
80030d0: 687b ldr r3, [r7, #4]
80030d2: 6f5b ldr r3, [r3, #116] @ 0x74
80030d4: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
80030d8: d101 bne.n 80030de <HAL_RCCEx_PeriphCLKConfig+0x3ba>
{
pllsaiused = 1;
80030da: 2301 movs r3, #1
80030dc: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
80030de: 687b ldr r3, [r7, #4]
80030e0: 681b ldr r3, [r3, #0]
80030e2: f403 2380 and.w r3, r3, #262144 @ 0x40000
80030e6: 2b00 cmp r3, #0
80030e8: d00a beq.n 8003100 <HAL_RCCEx_PeriphCLKConfig+0x3dc>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LTPIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
80030ea: 4b25 ldr r3, [pc, #148] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80030ec: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80030f0: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
80030f4: 687b ldr r3, [r7, #4]
80030f6: 6edb ldr r3, [r3, #108] @ 0x6c
80030f8: 4921 ldr r1, [pc, #132] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80030fa: 4313 orrs r3, r2
80030fc: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*------------------------------------- SDMMC1 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
8003100: 687b ldr r3, [r7, #4]
8003102: 681b ldr r3, [r3, #0]
8003104: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8003108: 2b00 cmp r3, #0
800310a: d00a beq.n 8003122 <HAL_RCCEx_PeriphCLKConfig+0x3fe>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
/* Configure the SDMMC1 clock source */
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
800310c: 4b1c ldr r3, [pc, #112] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800310e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003112: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000
8003116: 687b ldr r3, [r7, #4]
8003118: 6f9b ldr r3, [r3, #120] @ 0x78
800311a: 4919 ldr r1, [pc, #100] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800311c: 4313 orrs r3, r2
800311e: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*------------------------------------- SDMMC2 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
8003122: 687b ldr r3, [r7, #4]
8003124: 681b ldr r3, [r3, #0]
8003126: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
800312a: 2b00 cmp r3, #0
800312c: d00a beq.n 8003144 <HAL_RCCEx_PeriphCLKConfig+0x420>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
/* Configure the SDMMC2 clock source */
__HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
800312e: 4b14 ldr r3, [pc, #80] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8003130: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003134: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000
8003138: 687b ldr r3, [r7, #4]
800313a: 6fdb ldr r3, [r3, #124] @ 0x7c
800313c: 4910 ldr r1, [pc, #64] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800313e: 4313 orrs r3, r2
8003140: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */
if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
8003144: 69fb ldr r3, [r7, #28]
8003146: 2b01 cmp r3, #1
8003148: d006 beq.n 8003158 <HAL_RCCEx_PeriphCLKConfig+0x434>
800314a: 687b ldr r3, [r7, #4]
800314c: 681b ldr r3, [r3, #0]
800314e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8003152: 2b00 cmp r3, #0
8003154: f000 809d beq.w 8003292 <HAL_RCCEx_PeriphCLKConfig+0x56e>
{
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
8003158: 4b09 ldr r3, [pc, #36] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800315a: 681b ldr r3, [r3, #0]
800315c: 4a08 ldr r2, [pc, #32] @ (8003180 <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800315e: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
8003162: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003164: f7fe fc94 bl 8001a90 <HAL_GetTick>
8003168: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
800316a: e00b b.n 8003184 <HAL_RCCEx_PeriphCLKConfig+0x460>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
800316c: f7fe fc90 bl 8001a90 <HAL_GetTick>
8003170: 4602 mov r2, r0
8003172: 697b ldr r3, [r7, #20]
8003174: 1ad3 subs r3, r2, r3
8003176: 2b64 cmp r3, #100 @ 0x64
8003178: d904 bls.n 8003184 <HAL_RCCEx_PeriphCLKConfig+0x460>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
800317a: 2303 movs r3, #3
800317c: e116 b.n 80033ac <HAL_RCCEx_PeriphCLKConfig+0x688>
800317e: bf00 nop
8003180: 40023800 .word 0x40023800
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8003184: 4b8b ldr r3, [pc, #556] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003186: 681b ldr r3, [r3, #0]
8003188: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
800318c: 2b00 cmp r3, #0
800318e: d1ed bne.n 800316c <HAL_RCCEx_PeriphCLKConfig+0x448>
/* check for common PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
/*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
8003190: 687b ldr r3, [r7, #4]
8003192: 681b ldr r3, [r3, #0]
8003194: f003 0301 and.w r3, r3, #1
8003198: 2b00 cmp r3, #0
800319a: d017 beq.n 80031cc <HAL_RCCEx_PeriphCLKConfig+0x4a8>
800319c: 687b ldr r3, [r7, #4]
800319e: 6adb ldr r3, [r3, #44] @ 0x2c
80031a0: 2b00 cmp r3, #0
80031a2: d113 bne.n 80031cc <HAL_RCCEx_PeriphCLKConfig+0x4a8>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
80031a4: 4b83 ldr r3, [pc, #524] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80031a6: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
80031aa: 0e1b lsrs r3, r3, #24
80031ac: f003 030f and.w r3, r3, #15
80031b0: 613b str r3, [r7, #16]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2SR);
80031b2: 687b ldr r3, [r7, #4]
80031b4: 685b ldr r3, [r3, #4]
80031b6: 019a lsls r2, r3, #6
80031b8: 693b ldr r3, [r7, #16]
80031ba: 061b lsls r3, r3, #24
80031bc: 431a orrs r2, r3
80031be: 687b ldr r3, [r7, #4]
80031c0: 689b ldr r3, [r3, #8]
80031c2: 071b lsls r3, r3, #28
80031c4: 497b ldr r1, [pc, #492] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80031c6: 4313 orrs r3, r2
80031c8: f8c1 3084 str.w r3, [r1, #132] @ 0x84
}
/*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
80031cc: 687b ldr r3, [r7, #4]
80031ce: 681b ldr r3, [r3, #0]
80031d0: f403 2300 and.w r3, r3, #524288 @ 0x80000
80031d4: 2b00 cmp r3, #0
80031d6: d004 beq.n 80031e2 <HAL_RCCEx_PeriphCLKConfig+0x4be>
80031d8: 687b ldr r3, [r7, #4]
80031da: 6b5b ldr r3, [r3, #52] @ 0x34
80031dc: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
80031e0: d00a beq.n 80031f8 <HAL_RCCEx_PeriphCLKConfig+0x4d4>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
80031e2: 687b ldr r3, [r7, #4]
80031e4: 681b ldr r3, [r3, #0]
80031e6: f403 1380 and.w r3, r3, #1048576 @ 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
80031ea: 2b00 cmp r3, #0
80031ec: d024 beq.n 8003238 <HAL_RCCEx_PeriphCLKConfig+0x514>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
80031ee: 687b ldr r3, [r7, #4]
80031f0: 6b9b ldr r3, [r3, #56] @ 0x38
80031f2: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
80031f6: d11f bne.n 8003238 <HAL_RCCEx_PeriphCLKConfig+0x514>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Check for PLLI2S/DIVQ parameters */
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
80031f8: 4b6e ldr r3, [pc, #440] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80031fa: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
80031fe: 0f1b lsrs r3, r3, #28
8003200: f003 0307 and.w r3, r3, #7
8003204: 613b str r3, [r7, #16]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0);
8003206: 687b ldr r3, [r7, #4]
8003208: 685b ldr r3, [r3, #4]
800320a: 019a lsls r2, r3, #6
800320c: 687b ldr r3, [r7, #4]
800320e: 68db ldr r3, [r3, #12]
8003210: 061b lsls r3, r3, #24
8003212: 431a orrs r2, r3
8003214: 693b ldr r3, [r7, #16]
8003216: 071b lsls r3, r3, #28
8003218: 4966 ldr r1, [pc, #408] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800321a: 4313 orrs r3, r2
800321c: f8c1 3084 str.w r3, [r1, #132] @ 0x84
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
8003220: 4b64 ldr r3, [pc, #400] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003222: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8003226: f023 021f bic.w r2, r3, #31
800322a: 687b ldr r3, [r7, #4]
800322c: 69db ldr r3, [r3, #28]
800322e: 3b01 subs r3, #1
8003230: 4960 ldr r1, [pc, #384] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003232: 4313 orrs r3, r2
8003234: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
8003238: 687b ldr r3, [r7, #4]
800323a: 681b ldr r3, [r3, #0]
800323c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8003240: 2b00 cmp r3, #0
8003242: d00d beq.n 8003260 <HAL_RCCEx_PeriphCLKConfig+0x53c>
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
8003244: 687b ldr r3, [r7, #4]
8003246: 685b ldr r3, [r3, #4]
8003248: 019a lsls r2, r3, #6
800324a: 687b ldr r3, [r7, #4]
800324c: 68db ldr r3, [r3, #12]
800324e: 061b lsls r3, r3, #24
8003250: 431a orrs r2, r3
8003252: 687b ldr r3, [r7, #4]
8003254: 689b ldr r3, [r3, #8]
8003256: 071b lsls r3, r3, #28
8003258: 4956 ldr r1, [pc, #344] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800325a: 4313 orrs r3, r2
800325c: f8c1 3084 str.w r3, [r1, #132] @ 0x84
}
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
8003260: 4b54 ldr r3, [pc, #336] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003262: 681b ldr r3, [r3, #0]
8003264: 4a53 ldr r2, [pc, #332] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003266: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
800326a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800326c: f7fe fc10 bl 8001a90 <HAL_GetTick>
8003270: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
8003272: e008 b.n 8003286 <HAL_RCCEx_PeriphCLKConfig+0x562>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
8003274: f7fe fc0c bl 8001a90 <HAL_GetTick>
8003278: 4602 mov r2, r0
800327a: 697b ldr r3, [r7, #20]
800327c: 1ad3 subs r3, r2, r3
800327e: 2b64 cmp r3, #100 @ 0x64
8003280: d901 bls.n 8003286 <HAL_RCCEx_PeriphCLKConfig+0x562>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8003282: 2303 movs r3, #3
8003284: e092 b.n 80033ac <HAL_RCCEx_PeriphCLKConfig+0x688>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
8003286: 4b4b ldr r3, [pc, #300] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003288: 681b ldr r3, [r3, #0]
800328a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
800328e: 2b00 cmp r3, #0
8003290: d0f0 beq.n 8003274 <HAL_RCCEx_PeriphCLKConfig+0x550>
}
}
/*-------------------------------------- PLLSAI Configuration ---------------------------------*/
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
if(pllsaiused == 1)
8003292: 69bb ldr r3, [r7, #24]
8003294: 2b01 cmp r3, #1
8003296: f040 8088 bne.w 80033aa <HAL_RCCEx_PeriphCLKConfig+0x686>
{
/* Disable PLLSAI Clock */
__HAL_RCC_PLLSAI_DISABLE();
800329a: 4b46 ldr r3, [pc, #280] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800329c: 681b ldr r3, [r3, #0]
800329e: 4a45 ldr r2, [pc, #276] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80032a0: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80032a4: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80032a6: f7fe fbf3 bl 8001a90 <HAL_GetTick>
80032aa: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
80032ac: e008 b.n 80032c0 <HAL_RCCEx_PeriphCLKConfig+0x59c>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
80032ae: f7fe fbef bl 8001a90 <HAL_GetTick>
80032b2: 4602 mov r2, r0
80032b4: 697b ldr r3, [r7, #20]
80032b6: 1ad3 subs r3, r2, r3
80032b8: 2b64 cmp r3, #100 @ 0x64
80032ba: d901 bls.n 80032c0 <HAL_RCCEx_PeriphCLKConfig+0x59c>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
80032bc: 2303 movs r3, #3
80032be: e075 b.n 80033ac <HAL_RCCEx_PeriphCLKConfig+0x688>
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
80032c0: 4b3c ldr r3, [pc, #240] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80032c2: 681b ldr r3, [r3, #0]
80032c4: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
80032c8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
80032cc: d0ef beq.n 80032ae <HAL_RCCEx_PeriphCLKConfig+0x58a>
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
/*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
80032ce: 687b ldr r3, [r7, #4]
80032d0: 681b ldr r3, [r3, #0]
80032d2: f403 2300 and.w r3, r3, #524288 @ 0x80000
80032d6: 2b00 cmp r3, #0
80032d8: d003 beq.n 80032e2 <HAL_RCCEx_PeriphCLKConfig+0x5be>
80032da: 687b ldr r3, [r7, #4]
80032dc: 6b5b ldr r3, [r3, #52] @ 0x34
80032de: 2b00 cmp r3, #0
80032e0: d009 beq.n 80032f6 <HAL_RCCEx_PeriphCLKConfig+0x5d2>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
80032e2: 687b ldr r3, [r7, #4]
80032e4: 681b ldr r3, [r3, #0]
80032e6: f403 1380 and.w r3, r3, #1048576 @ 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
80032ea: 2b00 cmp r3, #0
80032ec: d024 beq.n 8003338 <HAL_RCCEx_PeriphCLKConfig+0x614>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
80032ee: 687b ldr r3, [r7, #4]
80032f0: 6b9b ldr r3, [r3, #56] @ 0x38
80032f2: 2b00 cmp r3, #0
80032f4: d120 bne.n 8003338 <HAL_RCCEx_PeriphCLKConfig+0x614>
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
/* check for PLLSAI/DIVQ Parameter */
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
80032f6: 4b2f ldr r3, [pc, #188] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80032f8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80032fc: 0c1b lsrs r3, r3, #16
80032fe: f003 0303 and.w r3, r3, #3
8003302: 613b str r3, [r7, #16]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ);
8003304: 687b ldr r3, [r7, #4]
8003306: 691b ldr r3, [r3, #16]
8003308: 019a lsls r2, r3, #6
800330a: 693b ldr r3, [r7, #16]
800330c: 041b lsls r3, r3, #16
800330e: 431a orrs r2, r3
8003310: 687b ldr r3, [r7, #4]
8003312: 695b ldr r3, [r3, #20]
8003314: 061b lsls r3, r3, #24
8003316: 4927 ldr r1, [pc, #156] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003318: 4313 orrs r3, r2
800331a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
800331e: 4b25 ldr r3, [pc, #148] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003320: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8003324: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
8003328: 687b ldr r3, [r7, #4]
800332a: 6a1b ldr r3, [r3, #32]
800332c: 3b01 subs r3, #1
800332e: 021b lsls r3, r3, #8
8003330: 4920 ldr r1, [pc, #128] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003332: 4313 orrs r3, r2
8003334: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
/* In Case of PLLI2S is selected as source clock for CK48 */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
8003338: 687b ldr r3, [r7, #4]
800333a: 681b ldr r3, [r3, #0]
800333c: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8003340: 2b00 cmp r3, #0
8003342: d018 beq.n 8003376 <HAL_RCCEx_PeriphCLKConfig+0x652>
8003344: 687b ldr r3, [r7, #4]
8003346: 6f5b ldr r3, [r3, #116] @ 0x74
8003348: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
800334c: d113 bne.n 8003376 <HAL_RCCEx_PeriphCLKConfig+0x652>
{
/* check for Parameters */
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
800334e: 4b19 ldr r3, [pc, #100] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003350: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003354: 0e1b lsrs r3, r3, #24
8003356: f003 030f and.w r3, r3, #15
800335a: 613b str r3, [r7, #16]
/* Configure the PLLSAI division factors */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0);
800335c: 687b ldr r3, [r7, #4]
800335e: 691b ldr r3, [r3, #16]
8003360: 019a lsls r2, r3, #6
8003362: 687b ldr r3, [r7, #4]
8003364: 699b ldr r3, [r3, #24]
8003366: 041b lsls r3, r3, #16
8003368: 431a orrs r2, r3
800336a: 693b ldr r3, [r7, #16]
800336c: 061b lsls r3, r3, #24
800336e: 4911 ldr r1, [pc, #68] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003370: 4313 orrs r3, r2
8003372: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
8003376: 4b0f ldr r3, [pc, #60] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8003378: 681b ldr r3, [r3, #0]
800337a: 4a0e ldr r2, [pc, #56] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800337c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8003380: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003382: f7fe fb85 bl 8001a90 <HAL_GetTick>
8003386: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is ready */
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
8003388: e008 b.n 800339c <HAL_RCCEx_PeriphCLKConfig+0x678>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
800338a: f7fe fb81 bl 8001a90 <HAL_GetTick>
800338e: 4602 mov r2, r0
8003390: 697b ldr r3, [r7, #20]
8003392: 1ad3 subs r3, r2, r3
8003394: 2b64 cmp r3, #100 @ 0x64
8003396: d901 bls.n 800339c <HAL_RCCEx_PeriphCLKConfig+0x678>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8003398: 2303 movs r3, #3
800339a: e007 b.n 80033ac <HAL_RCCEx_PeriphCLKConfig+0x688>
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
800339c: 4b05 ldr r3, [pc, #20] @ (80033b4 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800339e: 681b ldr r3, [r3, #0]
80033a0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
80033a4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
80033a8: d1ef bne.n 800338a <HAL_RCCEx_PeriphCLKConfig+0x666>
}
}
}
return HAL_OK;
80033aa: 2300 movs r3, #0
}
80033ac: 4618 mov r0, r3
80033ae: 3720 adds r7, #32
80033b0: 46bd mov sp, r7
80033b2: bd80 pop {r7, pc}
80033b4: 40023800 .word 0x40023800
080033b8 <HAL_SRAM_Init>:
* @param ExtTiming Pointer to SRAM extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
FMC_NORSRAM_TimingTypeDef *ExtTiming)
{
80033b8: b580 push {r7, lr}
80033ba: b084 sub sp, #16
80033bc: af00 add r7, sp, #0
80033be: 60f8 str r0, [r7, #12]
80033c0: 60b9 str r1, [r7, #8]
80033c2: 607a str r2, [r7, #4]
/* Check the SRAM handle parameter */
if (hsram == NULL)
80033c4: 68fb ldr r3, [r7, #12]
80033c6: 2b00 cmp r3, #0
80033c8: d101 bne.n 80033ce <HAL_SRAM_Init+0x16>
{
return HAL_ERROR;
80033ca: 2301 movs r3, #1
80033cc: e038 b.n 8003440 <HAL_SRAM_Init+0x88>
}
if (hsram->State == HAL_SRAM_STATE_RESET)
80033ce: 68fb ldr r3, [r7, #12]
80033d0: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
80033d4: b2db uxtb r3, r3
80033d6: 2b00 cmp r3, #0
80033d8: d106 bne.n 80033e8 <HAL_SRAM_Init+0x30>
{
/* Allocate lock resource and initialize it */
hsram->Lock = HAL_UNLOCKED;
80033da: 68fb ldr r3, [r7, #12]
80033dc: 2200 movs r2, #0
80033de: f883 2044 strb.w r2, [r3, #68] @ 0x44
/* Init the low level hardware */
hsram->MspInitCallback(hsram);
#else
/* Initialize the low level hardware (MSP) */
HAL_SRAM_MspInit(hsram);
80033e2: 68f8 ldr r0, [r7, #12]
80033e4: f7fe f9b2 bl 800174c <HAL_SRAM_MspInit>
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
/* Initialize SRAM control Interface */
(void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
80033e8: 68fb ldr r3, [r7, #12]
80033ea: 681a ldr r2, [r3, #0]
80033ec: 68fb ldr r3, [r7, #12]
80033ee: 3308 adds r3, #8
80033f0: 4619 mov r1, r3
80033f2: 4610 mov r0, r2
80033f4: f000 fffc bl 80043f0 <FMC_NORSRAM_Init>
/* Initialize SRAM timing Interface */
(void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
80033f8: 68fb ldr r3, [r7, #12]
80033fa: 6818 ldr r0, [r3, #0]
80033fc: 68fb ldr r3, [r7, #12]
80033fe: 689b ldr r3, [r3, #8]
8003400: 461a mov r2, r3
8003402: 68b9 ldr r1, [r7, #8]
8003404: f001 f884 bl 8004510 <FMC_NORSRAM_Timing_Init>
/* Initialize SRAM extended mode timing Interface */
(void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
8003408: 68fb ldr r3, [r7, #12]
800340a: 6858 ldr r0, [r3, #4]
800340c: 68fb ldr r3, [r7, #12]
800340e: 689a ldr r2, [r3, #8]
8003410: 68fb ldr r3, [r7, #12]
8003412: 6adb ldr r3, [r3, #44] @ 0x2c
8003414: 6879 ldr r1, [r7, #4]
8003416: f001 f8c5 bl 80045a4 <FMC_NORSRAM_Extended_Timing_Init>
hsram->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
800341a: 68fb ldr r3, [r7, #12]
800341c: 681b ldr r3, [r3, #0]
800341e: 68fa ldr r2, [r7, #12]
8003420: 6892 ldr r2, [r2, #8]
8003422: f853 1022 ldr.w r1, [r3, r2, lsl #2]
8003426: 68fb ldr r3, [r7, #12]
8003428: 681b ldr r3, [r3, #0]
800342a: 68fa ldr r2, [r7, #12]
800342c: 6892 ldr r2, [r2, #8]
800342e: f041 0101 orr.w r1, r1, #1
8003432: f843 1022 str.w r1, [r3, r2, lsl #2]
/* Initialize the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
8003436: 68fb ldr r3, [r7, #12]
8003438: 2201 movs r2, #1
800343a: f883 2045 strb.w r2, [r3, #69] @ 0x45
return HAL_OK;
800343e: 2300 movs r3, #0
}
8003440: 4618 mov r0, r3
8003442: 3710 adds r7, #16
8003444: 46bd mov sp, r7
8003446: bd80 pop {r7, pc}
08003448 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8003448: b580 push {r7, lr}
800344a: b082 sub sp, #8
800344c: af00 add r7, sp, #0
800344e: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8003450: 687b ldr r3, [r7, #4]
8003452: 2b00 cmp r3, #0
8003454: d101 bne.n 800345a <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8003456: 2301 movs r3, #1
8003458: e049 b.n 80034ee <HAL_TIM_Base_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
800345a: 687b ldr r3, [r7, #4]
800345c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8003460: b2db uxtb r3, r3
8003462: 2b00 cmp r3, #0
8003464: d106 bne.n 8003474 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8003466: 687b ldr r3, [r7, #4]
8003468: 2200 movs r2, #0
800346a: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
800346e: 6878 ldr r0, [r7, #4]
8003470: f000 f841 bl 80034f6 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8003474: 687b ldr r3, [r7, #4]
8003476: 2202 movs r2, #2
8003478: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
800347c: 687b ldr r3, [r7, #4]
800347e: 681a ldr r2, [r3, #0]
8003480: 687b ldr r3, [r7, #4]
8003482: 3304 adds r3, #4
8003484: 4619 mov r1, r3
8003486: 4610 mov r0, r2
8003488: f000 f9e8 bl 800385c <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
800348c: 687b ldr r3, [r7, #4]
800348e: 2201 movs r2, #1
8003490: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8003494: 687b ldr r3, [r7, #4]
8003496: 2201 movs r2, #1
8003498: f883 203e strb.w r2, [r3, #62] @ 0x3e
800349c: 687b ldr r3, [r7, #4]
800349e: 2201 movs r2, #1
80034a0: f883 203f strb.w r2, [r3, #63] @ 0x3f
80034a4: 687b ldr r3, [r7, #4]
80034a6: 2201 movs r2, #1
80034a8: f883 2040 strb.w r2, [r3, #64] @ 0x40
80034ac: 687b ldr r3, [r7, #4]
80034ae: 2201 movs r2, #1
80034b0: f883 2041 strb.w r2, [r3, #65] @ 0x41
80034b4: 687b ldr r3, [r7, #4]
80034b6: 2201 movs r2, #1
80034b8: f883 2042 strb.w r2, [r3, #66] @ 0x42
80034bc: 687b ldr r3, [r7, #4]
80034be: 2201 movs r2, #1
80034c0: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80034c4: 687b ldr r3, [r7, #4]
80034c6: 2201 movs r2, #1
80034c8: f883 2044 strb.w r2, [r3, #68] @ 0x44
80034cc: 687b ldr r3, [r7, #4]
80034ce: 2201 movs r2, #1
80034d0: f883 2045 strb.w r2, [r3, #69] @ 0x45
80034d4: 687b ldr r3, [r7, #4]
80034d6: 2201 movs r2, #1
80034d8: f883 2046 strb.w r2, [r3, #70] @ 0x46
80034dc: 687b ldr r3, [r7, #4]
80034de: 2201 movs r2, #1
80034e0: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80034e4: 687b ldr r3, [r7, #4]
80034e6: 2201 movs r2, #1
80034e8: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
80034ec: 2300 movs r3, #0
}
80034ee: 4618 mov r0, r3
80034f0: 3708 adds r7, #8
80034f2: 46bd mov sp, r7
80034f4: bd80 pop {r7, pc}
080034f6 <HAL_TIM_Base_MspInit>:
* @brief Initializes the TIM Base MSP.
* @param htim TIM Base handle
* @retval None
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
80034f6: b480 push {r7}
80034f8: b083 sub sp, #12
80034fa: af00 add r7, sp, #0
80034fc: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Base_MspInit could be implemented in the user file
*/
}
80034fe: bf00 nop
8003500: 370c adds r7, #12
8003502: 46bd mov sp, r7
8003504: f85d 7b04 ldr.w r7, [sp], #4
8003508: 4770 bx lr
...
0800350c <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
800350c: b480 push {r7}
800350e: b085 sub sp, #20
8003510: af00 add r7, sp, #0
8003512: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
8003514: 687b ldr r3, [r7, #4]
8003516: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
800351a: b2db uxtb r3, r3
800351c: 2b01 cmp r3, #1
800351e: d001 beq.n 8003524 <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
8003520: 2301 movs r3, #1
8003522: e054 b.n 80035ce <HAL_TIM_Base_Start_IT+0xc2>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8003524: 687b ldr r3, [r7, #4]
8003526: 2202 movs r2, #2
8003528: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
800352c: 687b ldr r3, [r7, #4]
800352e: 681b ldr r3, [r3, #0]
8003530: 68da ldr r2, [r3, #12]
8003532: 687b ldr r3, [r7, #4]
8003534: 681b ldr r3, [r3, #0]
8003536: f042 0201 orr.w r2, r2, #1
800353a: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800353c: 687b ldr r3, [r7, #4]
800353e: 681b ldr r3, [r3, #0]
8003540: 4a26 ldr r2, [pc, #152] @ (80035dc <HAL_TIM_Base_Start_IT+0xd0>)
8003542: 4293 cmp r3, r2
8003544: d022 beq.n 800358c <HAL_TIM_Base_Start_IT+0x80>
8003546: 687b ldr r3, [r7, #4]
8003548: 681b ldr r3, [r3, #0]
800354a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800354e: d01d beq.n 800358c <HAL_TIM_Base_Start_IT+0x80>
8003550: 687b ldr r3, [r7, #4]
8003552: 681b ldr r3, [r3, #0]
8003554: 4a22 ldr r2, [pc, #136] @ (80035e0 <HAL_TIM_Base_Start_IT+0xd4>)
8003556: 4293 cmp r3, r2
8003558: d018 beq.n 800358c <HAL_TIM_Base_Start_IT+0x80>
800355a: 687b ldr r3, [r7, #4]
800355c: 681b ldr r3, [r3, #0]
800355e: 4a21 ldr r2, [pc, #132] @ (80035e4 <HAL_TIM_Base_Start_IT+0xd8>)
8003560: 4293 cmp r3, r2
8003562: d013 beq.n 800358c <HAL_TIM_Base_Start_IT+0x80>
8003564: 687b ldr r3, [r7, #4]
8003566: 681b ldr r3, [r3, #0]
8003568: 4a1f ldr r2, [pc, #124] @ (80035e8 <HAL_TIM_Base_Start_IT+0xdc>)
800356a: 4293 cmp r3, r2
800356c: d00e beq.n 800358c <HAL_TIM_Base_Start_IT+0x80>
800356e: 687b ldr r3, [r7, #4]
8003570: 681b ldr r3, [r3, #0]
8003572: 4a1e ldr r2, [pc, #120] @ (80035ec <HAL_TIM_Base_Start_IT+0xe0>)
8003574: 4293 cmp r3, r2
8003576: d009 beq.n 800358c <HAL_TIM_Base_Start_IT+0x80>
8003578: 687b ldr r3, [r7, #4]
800357a: 681b ldr r3, [r3, #0]
800357c: 4a1c ldr r2, [pc, #112] @ (80035f0 <HAL_TIM_Base_Start_IT+0xe4>)
800357e: 4293 cmp r3, r2
8003580: d004 beq.n 800358c <HAL_TIM_Base_Start_IT+0x80>
8003582: 687b ldr r3, [r7, #4]
8003584: 681b ldr r3, [r3, #0]
8003586: 4a1b ldr r2, [pc, #108] @ (80035f4 <HAL_TIM_Base_Start_IT+0xe8>)
8003588: 4293 cmp r3, r2
800358a: d115 bne.n 80035b8 <HAL_TIM_Base_Start_IT+0xac>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
800358c: 687b ldr r3, [r7, #4]
800358e: 681b ldr r3, [r3, #0]
8003590: 689a ldr r2, [r3, #8]
8003592: 4b19 ldr r3, [pc, #100] @ (80035f8 <HAL_TIM_Base_Start_IT+0xec>)
8003594: 4013 ands r3, r2
8003596: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8003598: 68fb ldr r3, [r7, #12]
800359a: 2b06 cmp r3, #6
800359c: d015 beq.n 80035ca <HAL_TIM_Base_Start_IT+0xbe>
800359e: 68fb ldr r3, [r7, #12]
80035a0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80035a4: d011 beq.n 80035ca <HAL_TIM_Base_Start_IT+0xbe>
{
__HAL_TIM_ENABLE(htim);
80035a6: 687b ldr r3, [r7, #4]
80035a8: 681b ldr r3, [r3, #0]
80035aa: 681a ldr r2, [r3, #0]
80035ac: 687b ldr r3, [r7, #4]
80035ae: 681b ldr r3, [r3, #0]
80035b0: f042 0201 orr.w r2, r2, #1
80035b4: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80035b6: e008 b.n 80035ca <HAL_TIM_Base_Start_IT+0xbe>
}
}
else
{
__HAL_TIM_ENABLE(htim);
80035b8: 687b ldr r3, [r7, #4]
80035ba: 681b ldr r3, [r3, #0]
80035bc: 681a ldr r2, [r3, #0]
80035be: 687b ldr r3, [r7, #4]
80035c0: 681b ldr r3, [r3, #0]
80035c2: f042 0201 orr.w r2, r2, #1
80035c6: 601a str r2, [r3, #0]
80035c8: e000 b.n 80035cc <HAL_TIM_Base_Start_IT+0xc0>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80035ca: bf00 nop
}
/* Return function status */
return HAL_OK;
80035cc: 2300 movs r3, #0
}
80035ce: 4618 mov r0, r3
80035d0: 3714 adds r7, #20
80035d2: 46bd mov sp, r7
80035d4: f85d 7b04 ldr.w r7, [sp], #4
80035d8: 4770 bx lr
80035da: bf00 nop
80035dc: 40010000 .word 0x40010000
80035e0: 40000400 .word 0x40000400
80035e4: 40000800 .word 0x40000800
80035e8: 40000c00 .word 0x40000c00
80035ec: 40010400 .word 0x40010400
80035f0: 40014000 .word 0x40014000
80035f4: 40001800 .word 0x40001800
80035f8: 00010007 .word 0x00010007
080035fc <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
80035fc: b580 push {r7, lr}
80035fe: b084 sub sp, #16
8003600: af00 add r7, sp, #0
8003602: 6078 str r0, [r7, #4]
uint32_t itsource = htim->Instance->DIER;
8003604: 687b ldr r3, [r7, #4]
8003606: 681b ldr r3, [r3, #0]
8003608: 68db ldr r3, [r3, #12]
800360a: 60fb str r3, [r7, #12]
uint32_t itflag = htim->Instance->SR;
800360c: 687b ldr r3, [r7, #4]
800360e: 681b ldr r3, [r3, #0]
8003610: 691b ldr r3, [r3, #16]
8003612: 60bb str r3, [r7, #8]
/* Capture compare 1 event */
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
8003614: 68bb ldr r3, [r7, #8]
8003616: f003 0302 and.w r3, r3, #2
800361a: 2b00 cmp r3, #0
800361c: d020 beq.n 8003660 <HAL_TIM_IRQHandler+0x64>
{
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
800361e: 68fb ldr r3, [r7, #12]
8003620: f003 0302 and.w r3, r3, #2
8003624: 2b00 cmp r3, #0
8003626: d01b beq.n 8003660 <HAL_TIM_IRQHandler+0x64>
{
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
8003628: 687b ldr r3, [r7, #4]
800362a: 681b ldr r3, [r3, #0]
800362c: f06f 0202 mvn.w r2, #2
8003630: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8003632: 687b ldr r3, [r7, #4]
8003634: 2201 movs r2, #1
8003636: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8003638: 687b ldr r3, [r7, #4]
800363a: 681b ldr r3, [r3, #0]
800363c: 699b ldr r3, [r3, #24]
800363e: f003 0303 and.w r3, r3, #3
8003642: 2b00 cmp r3, #0
8003644: d003 beq.n 800364e <HAL_TIM_IRQHandler+0x52>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8003646: 6878 ldr r0, [r7, #4]
8003648: f000 f8e9 bl 800381e <HAL_TIM_IC_CaptureCallback>
800364c: e005 b.n 800365a <HAL_TIM_IRQHandler+0x5e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800364e: 6878 ldr r0, [r7, #4]
8003650: f000 f8db bl 800380a <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003654: 6878 ldr r0, [r7, #4]
8003656: f000 f8ec bl 8003832 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800365a: 687b ldr r3, [r7, #4]
800365c: 2200 movs r2, #0
800365e: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
8003660: 68bb ldr r3, [r7, #8]
8003662: f003 0304 and.w r3, r3, #4
8003666: 2b00 cmp r3, #0
8003668: d020 beq.n 80036ac <HAL_TIM_IRQHandler+0xb0>
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
800366a: 68fb ldr r3, [r7, #12]
800366c: f003 0304 and.w r3, r3, #4
8003670: 2b00 cmp r3, #0
8003672: d01b beq.n 80036ac <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
8003674: 687b ldr r3, [r7, #4]
8003676: 681b ldr r3, [r3, #0]
8003678: f06f 0204 mvn.w r2, #4
800367c: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
800367e: 687b ldr r3, [r7, #4]
8003680: 2202 movs r2, #2
8003682: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8003684: 687b ldr r3, [r7, #4]
8003686: 681b ldr r3, [r3, #0]
8003688: 699b ldr r3, [r3, #24]
800368a: f403 7340 and.w r3, r3, #768 @ 0x300
800368e: 2b00 cmp r3, #0
8003690: d003 beq.n 800369a <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8003692: 6878 ldr r0, [r7, #4]
8003694: f000 f8c3 bl 800381e <HAL_TIM_IC_CaptureCallback>
8003698: e005 b.n 80036a6 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800369a: 6878 ldr r0, [r7, #4]
800369c: f000 f8b5 bl 800380a <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80036a0: 6878 ldr r0, [r7, #4]
80036a2: f000 f8c6 bl 8003832 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80036a6: 687b ldr r3, [r7, #4]
80036a8: 2200 movs r2, #0
80036aa: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
80036ac: 68bb ldr r3, [r7, #8]
80036ae: f003 0308 and.w r3, r3, #8
80036b2: 2b00 cmp r3, #0
80036b4: d020 beq.n 80036f8 <HAL_TIM_IRQHandler+0xfc>
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
80036b6: 68fb ldr r3, [r7, #12]
80036b8: f003 0308 and.w r3, r3, #8
80036bc: 2b00 cmp r3, #0
80036be: d01b beq.n 80036f8 <HAL_TIM_IRQHandler+0xfc>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
80036c0: 687b ldr r3, [r7, #4]
80036c2: 681b ldr r3, [r3, #0]
80036c4: f06f 0208 mvn.w r2, #8
80036c8: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
80036ca: 687b ldr r3, [r7, #4]
80036cc: 2204 movs r2, #4
80036ce: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
80036d0: 687b ldr r3, [r7, #4]
80036d2: 681b ldr r3, [r3, #0]
80036d4: 69db ldr r3, [r3, #28]
80036d6: f003 0303 and.w r3, r3, #3
80036da: 2b00 cmp r3, #0
80036dc: d003 beq.n 80036e6 <HAL_TIM_IRQHandler+0xea>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80036de: 6878 ldr r0, [r7, #4]
80036e0: f000 f89d bl 800381e <HAL_TIM_IC_CaptureCallback>
80036e4: e005 b.n 80036f2 <HAL_TIM_IRQHandler+0xf6>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
80036e6: 6878 ldr r0, [r7, #4]
80036e8: f000 f88f bl 800380a <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80036ec: 6878 ldr r0, [r7, #4]
80036ee: f000 f8a0 bl 8003832 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80036f2: 687b ldr r3, [r7, #4]
80036f4: 2200 movs r2, #0
80036f6: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
80036f8: 68bb ldr r3, [r7, #8]
80036fa: f003 0310 and.w r3, r3, #16
80036fe: 2b00 cmp r3, #0
8003700: d020 beq.n 8003744 <HAL_TIM_IRQHandler+0x148>
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
8003702: 68fb ldr r3, [r7, #12]
8003704: f003 0310 and.w r3, r3, #16
8003708: 2b00 cmp r3, #0
800370a: d01b beq.n 8003744 <HAL_TIM_IRQHandler+0x148>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
800370c: 687b ldr r3, [r7, #4]
800370e: 681b ldr r3, [r3, #0]
8003710: f06f 0210 mvn.w r2, #16
8003714: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8003716: 687b ldr r3, [r7, #4]
8003718: 2208 movs r2, #8
800371a: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
800371c: 687b ldr r3, [r7, #4]
800371e: 681b ldr r3, [r3, #0]
8003720: 69db ldr r3, [r3, #28]
8003722: f403 7340 and.w r3, r3, #768 @ 0x300
8003726: 2b00 cmp r3, #0
8003728: d003 beq.n 8003732 <HAL_TIM_IRQHandler+0x136>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800372a: 6878 ldr r0, [r7, #4]
800372c: f000 f877 bl 800381e <HAL_TIM_IC_CaptureCallback>
8003730: e005 b.n 800373e <HAL_TIM_IRQHandler+0x142>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8003732: 6878 ldr r0, [r7, #4]
8003734: f000 f869 bl 800380a <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003738: 6878 ldr r0, [r7, #4]
800373a: f000 f87a bl 8003832 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800373e: 687b ldr r3, [r7, #4]
8003740: 2200 movs r2, #0
8003742: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
8003744: 68bb ldr r3, [r7, #8]
8003746: f003 0301 and.w r3, r3, #1
800374a: 2b00 cmp r3, #0
800374c: d00c beq.n 8003768 <HAL_TIM_IRQHandler+0x16c>
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
800374e: 68fb ldr r3, [r7, #12]
8003750: f003 0301 and.w r3, r3, #1
8003754: 2b00 cmp r3, #0
8003756: d007 beq.n 8003768 <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
8003758: 687b ldr r3, [r7, #4]
800375a: 681b ldr r3, [r3, #0]
800375c: f06f 0201 mvn.w r2, #1
8003760: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8003762: 6878 ldr r0, [r7, #4]
8003764: f7fd fe54 bl 8001410 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
8003768: 68bb ldr r3, [r7, #8]
800376a: f003 0380 and.w r3, r3, #128 @ 0x80
800376e: 2b00 cmp r3, #0
8003770: d104 bne.n 800377c <HAL_TIM_IRQHandler+0x180>
((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
8003772: 68bb ldr r3, [r7, #8]
8003774: f403 5300 and.w r3, r3, #8192 @ 0x2000
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
8003778: 2b00 cmp r3, #0
800377a: d00c beq.n 8003796 <HAL_TIM_IRQHandler+0x19a>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
800377c: 68fb ldr r3, [r7, #12]
800377e: f003 0380 and.w r3, r3, #128 @ 0x80
8003782: 2b00 cmp r3, #0
8003784: d007 beq.n 8003796 <HAL_TIM_IRQHandler+0x19a>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
8003786: 687b ldr r3, [r7, #4]
8003788: 681b ldr r3, [r3, #0]
800378a: f46f 5202 mvn.w r2, #8320 @ 0x2080
800378e: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8003790: 6878 ldr r0, [r7, #4]
8003792: f000 f913 bl 80039bc <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
8003796: 68bb ldr r3, [r7, #8]
8003798: f403 7380 and.w r3, r3, #256 @ 0x100
800379c: 2b00 cmp r3, #0
800379e: d00c beq.n 80037ba <HAL_TIM_IRQHandler+0x1be>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
80037a0: 68fb ldr r3, [r7, #12]
80037a2: f003 0380 and.w r3, r3, #128 @ 0x80
80037a6: 2b00 cmp r3, #0
80037a8: d007 beq.n 80037ba <HAL_TIM_IRQHandler+0x1be>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
80037aa: 687b ldr r3, [r7, #4]
80037ac: 681b ldr r3, [r3, #0]
80037ae: f46f 7280 mvn.w r2, #256 @ 0x100
80037b2: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
80037b4: 6878 ldr r0, [r7, #4]
80037b6: f000 f90b bl 80039d0 <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
80037ba: 68bb ldr r3, [r7, #8]
80037bc: f003 0340 and.w r3, r3, #64 @ 0x40
80037c0: 2b00 cmp r3, #0
80037c2: d00c beq.n 80037de <HAL_TIM_IRQHandler+0x1e2>
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
80037c4: 68fb ldr r3, [r7, #12]
80037c6: f003 0340 and.w r3, r3, #64 @ 0x40
80037ca: 2b00 cmp r3, #0
80037cc: d007 beq.n 80037de <HAL_TIM_IRQHandler+0x1e2>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
80037ce: 687b ldr r3, [r7, #4]
80037d0: 681b ldr r3, [r3, #0]
80037d2: f06f 0240 mvn.w r2, #64 @ 0x40
80037d6: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
80037d8: 6878 ldr r0, [r7, #4]
80037da: f000 f834 bl 8003846 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
80037de: 68bb ldr r3, [r7, #8]
80037e0: f003 0320 and.w r3, r3, #32
80037e4: 2b00 cmp r3, #0
80037e6: d00c beq.n 8003802 <HAL_TIM_IRQHandler+0x206>
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
80037e8: 68fb ldr r3, [r7, #12]
80037ea: f003 0320 and.w r3, r3, #32
80037ee: 2b00 cmp r3, #0
80037f0: d007 beq.n 8003802 <HAL_TIM_IRQHandler+0x206>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
80037f2: 687b ldr r3, [r7, #4]
80037f4: 681b ldr r3, [r3, #0]
80037f6: f06f 0220 mvn.w r2, #32
80037fa: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
80037fc: 6878 ldr r0, [r7, #4]
80037fe: f000 f8d3 bl 80039a8 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8003802: bf00 nop
8003804: 3710 adds r7, #16
8003806: 46bd mov sp, r7
8003808: bd80 pop {r7, pc}
0800380a <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
800380a: b480 push {r7}
800380c: b083 sub sp, #12
800380e: af00 add r7, sp, #0
8003810: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8003812: bf00 nop
8003814: 370c adds r7, #12
8003816: 46bd mov sp, r7
8003818: f85d 7b04 ldr.w r7, [sp], #4
800381c: 4770 bx lr
0800381e <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
800381e: b480 push {r7}
8003820: b083 sub sp, #12
8003822: af00 add r7, sp, #0
8003824: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8003826: bf00 nop
8003828: 370c adds r7, #12
800382a: 46bd mov sp, r7
800382c: f85d 7b04 ldr.w r7, [sp], #4
8003830: 4770 bx lr
08003832 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8003832: b480 push {r7}
8003834: b083 sub sp, #12
8003836: af00 add r7, sp, #0
8003838: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
800383a: bf00 nop
800383c: 370c adds r7, #12
800383e: 46bd mov sp, r7
8003840: f85d 7b04 ldr.w r7, [sp], #4
8003844: 4770 bx lr
08003846 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8003846: b480 push {r7}
8003848: b083 sub sp, #12
800384a: af00 add r7, sp, #0
800384c: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
800384e: bf00 nop
8003850: 370c adds r7, #12
8003852: 46bd mov sp, r7
8003854: f85d 7b04 ldr.w r7, [sp], #4
8003858: 4770 bx lr
...
0800385c <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
800385c: b480 push {r7}
800385e: b085 sub sp, #20
8003860: af00 add r7, sp, #0
8003862: 6078 str r0, [r7, #4]
8003864: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8003866: 687b ldr r3, [r7, #4]
8003868: 681b ldr r3, [r3, #0]
800386a: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
800386c: 687b ldr r3, [r7, #4]
800386e: 4a43 ldr r2, [pc, #268] @ (800397c <TIM_Base_SetConfig+0x120>)
8003870: 4293 cmp r3, r2
8003872: d013 beq.n 800389c <TIM_Base_SetConfig+0x40>
8003874: 687b ldr r3, [r7, #4]
8003876: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800387a: d00f beq.n 800389c <TIM_Base_SetConfig+0x40>
800387c: 687b ldr r3, [r7, #4]
800387e: 4a40 ldr r2, [pc, #256] @ (8003980 <TIM_Base_SetConfig+0x124>)
8003880: 4293 cmp r3, r2
8003882: d00b beq.n 800389c <TIM_Base_SetConfig+0x40>
8003884: 687b ldr r3, [r7, #4]
8003886: 4a3f ldr r2, [pc, #252] @ (8003984 <TIM_Base_SetConfig+0x128>)
8003888: 4293 cmp r3, r2
800388a: d007 beq.n 800389c <TIM_Base_SetConfig+0x40>
800388c: 687b ldr r3, [r7, #4]
800388e: 4a3e ldr r2, [pc, #248] @ (8003988 <TIM_Base_SetConfig+0x12c>)
8003890: 4293 cmp r3, r2
8003892: d003 beq.n 800389c <TIM_Base_SetConfig+0x40>
8003894: 687b ldr r3, [r7, #4]
8003896: 4a3d ldr r2, [pc, #244] @ (800398c <TIM_Base_SetConfig+0x130>)
8003898: 4293 cmp r3, r2
800389a: d108 bne.n 80038ae <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
800389c: 68fb ldr r3, [r7, #12]
800389e: f023 0370 bic.w r3, r3, #112 @ 0x70
80038a2: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
80038a4: 683b ldr r3, [r7, #0]
80038a6: 685b ldr r3, [r3, #4]
80038a8: 68fa ldr r2, [r7, #12]
80038aa: 4313 orrs r3, r2
80038ac: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
80038ae: 687b ldr r3, [r7, #4]
80038b0: 4a32 ldr r2, [pc, #200] @ (800397c <TIM_Base_SetConfig+0x120>)
80038b2: 4293 cmp r3, r2
80038b4: d02b beq.n 800390e <TIM_Base_SetConfig+0xb2>
80038b6: 687b ldr r3, [r7, #4]
80038b8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80038bc: d027 beq.n 800390e <TIM_Base_SetConfig+0xb2>
80038be: 687b ldr r3, [r7, #4]
80038c0: 4a2f ldr r2, [pc, #188] @ (8003980 <TIM_Base_SetConfig+0x124>)
80038c2: 4293 cmp r3, r2
80038c4: d023 beq.n 800390e <TIM_Base_SetConfig+0xb2>
80038c6: 687b ldr r3, [r7, #4]
80038c8: 4a2e ldr r2, [pc, #184] @ (8003984 <TIM_Base_SetConfig+0x128>)
80038ca: 4293 cmp r3, r2
80038cc: d01f beq.n 800390e <TIM_Base_SetConfig+0xb2>
80038ce: 687b ldr r3, [r7, #4]
80038d0: 4a2d ldr r2, [pc, #180] @ (8003988 <TIM_Base_SetConfig+0x12c>)
80038d2: 4293 cmp r3, r2
80038d4: d01b beq.n 800390e <TIM_Base_SetConfig+0xb2>
80038d6: 687b ldr r3, [r7, #4]
80038d8: 4a2c ldr r2, [pc, #176] @ (800398c <TIM_Base_SetConfig+0x130>)
80038da: 4293 cmp r3, r2
80038dc: d017 beq.n 800390e <TIM_Base_SetConfig+0xb2>
80038de: 687b ldr r3, [r7, #4]
80038e0: 4a2b ldr r2, [pc, #172] @ (8003990 <TIM_Base_SetConfig+0x134>)
80038e2: 4293 cmp r3, r2
80038e4: d013 beq.n 800390e <TIM_Base_SetConfig+0xb2>
80038e6: 687b ldr r3, [r7, #4]
80038e8: 4a2a ldr r2, [pc, #168] @ (8003994 <TIM_Base_SetConfig+0x138>)
80038ea: 4293 cmp r3, r2
80038ec: d00f beq.n 800390e <TIM_Base_SetConfig+0xb2>
80038ee: 687b ldr r3, [r7, #4]
80038f0: 4a29 ldr r2, [pc, #164] @ (8003998 <TIM_Base_SetConfig+0x13c>)
80038f2: 4293 cmp r3, r2
80038f4: d00b beq.n 800390e <TIM_Base_SetConfig+0xb2>
80038f6: 687b ldr r3, [r7, #4]
80038f8: 4a28 ldr r2, [pc, #160] @ (800399c <TIM_Base_SetConfig+0x140>)
80038fa: 4293 cmp r3, r2
80038fc: d007 beq.n 800390e <TIM_Base_SetConfig+0xb2>
80038fe: 687b ldr r3, [r7, #4]
8003900: 4a27 ldr r2, [pc, #156] @ (80039a0 <TIM_Base_SetConfig+0x144>)
8003902: 4293 cmp r3, r2
8003904: d003 beq.n 800390e <TIM_Base_SetConfig+0xb2>
8003906: 687b ldr r3, [r7, #4]
8003908: 4a26 ldr r2, [pc, #152] @ (80039a4 <TIM_Base_SetConfig+0x148>)
800390a: 4293 cmp r3, r2
800390c: d108 bne.n 8003920 <TIM_Base_SetConfig+0xc4>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
800390e: 68fb ldr r3, [r7, #12]
8003910: f423 7340 bic.w r3, r3, #768 @ 0x300
8003914: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8003916: 683b ldr r3, [r7, #0]
8003918: 68db ldr r3, [r3, #12]
800391a: 68fa ldr r2, [r7, #12]
800391c: 4313 orrs r3, r2
800391e: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8003920: 68fb ldr r3, [r7, #12]
8003922: f023 0280 bic.w r2, r3, #128 @ 0x80
8003926: 683b ldr r3, [r7, #0]
8003928: 695b ldr r3, [r3, #20]
800392a: 4313 orrs r3, r2
800392c: 60fb str r3, [r7, #12]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
800392e: 683b ldr r3, [r7, #0]
8003930: 689a ldr r2, [r3, #8]
8003932: 687b ldr r3, [r7, #4]
8003934: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8003936: 683b ldr r3, [r7, #0]
8003938: 681a ldr r2, [r3, #0]
800393a: 687b ldr r3, [r7, #4]
800393c: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
800393e: 687b ldr r3, [r7, #4]
8003940: 4a0e ldr r2, [pc, #56] @ (800397c <TIM_Base_SetConfig+0x120>)
8003942: 4293 cmp r3, r2
8003944: d003 beq.n 800394e <TIM_Base_SetConfig+0xf2>
8003946: 687b ldr r3, [r7, #4]
8003948: 4a10 ldr r2, [pc, #64] @ (800398c <TIM_Base_SetConfig+0x130>)
800394a: 4293 cmp r3, r2
800394c: d103 bne.n 8003956 <TIM_Base_SetConfig+0xfa>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
800394e: 683b ldr r3, [r7, #0]
8003950: 691a ldr r2, [r3, #16]
8003952: 687b ldr r3, [r7, #4]
8003954: 631a str r2, [r3, #48] @ 0x30
}
/* Disable Update Event (UEV) with Update Generation (UG)
by changing Update Request Source (URS) to avoid Update flag (UIF) */
SET_BIT(TIMx->CR1, TIM_CR1_URS);
8003956: 687b ldr r3, [r7, #4]
8003958: 681b ldr r3, [r3, #0]
800395a: f043 0204 orr.w r2, r3, #4
800395e: 687b ldr r3, [r7, #4]
8003960: 601a str r2, [r3, #0]
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8003962: 687b ldr r3, [r7, #4]
8003964: 2201 movs r2, #1
8003966: 615a str r2, [r3, #20]
TIMx->CR1 = tmpcr1;
8003968: 687b ldr r3, [r7, #4]
800396a: 68fa ldr r2, [r7, #12]
800396c: 601a str r2, [r3, #0]
}
800396e: bf00 nop
8003970: 3714 adds r7, #20
8003972: 46bd mov sp, r7
8003974: f85d 7b04 ldr.w r7, [sp], #4
8003978: 4770 bx lr
800397a: bf00 nop
800397c: 40010000 .word 0x40010000
8003980: 40000400 .word 0x40000400
8003984: 40000800 .word 0x40000800
8003988: 40000c00 .word 0x40000c00
800398c: 40010400 .word 0x40010400
8003990: 40014000 .word 0x40014000
8003994: 40014400 .word 0x40014400
8003998: 40014800 .word 0x40014800
800399c: 40001800 .word 0x40001800
80039a0: 40001c00 .word 0x40001c00
80039a4: 40002000 .word 0x40002000
080039a8 <HAL_TIMEx_CommutCallback>:
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
80039a8: b480 push {r7}
80039aa: b083 sub sp, #12
80039ac: af00 add r7, sp, #0
80039ae: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
80039b0: bf00 nop
80039b2: 370c adds r7, #12
80039b4: 46bd mov sp, r7
80039b6: f85d 7b04 ldr.w r7, [sp], #4
80039ba: 4770 bx lr
080039bc <HAL_TIMEx_BreakCallback>:
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
80039bc: b480 push {r7}
80039be: b083 sub sp, #12
80039c0: af00 add r7, sp, #0
80039c2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
80039c4: bf00 nop
80039c6: 370c adds r7, #12
80039c8: 46bd mov sp, r7
80039ca: f85d 7b04 ldr.w r7, [sp], #4
80039ce: 4770 bx lr
080039d0 <HAL_TIMEx_Break2Callback>:
* @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
80039d0: b480 push {r7}
80039d2: b083 sub sp, #12
80039d4: af00 add r7, sp, #0
80039d6: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
80039d8: bf00 nop
80039da: 370c adds r7, #12
80039dc: 46bd mov sp, r7
80039de: f85d 7b04 ldr.w r7, [sp], #4
80039e2: 4770 bx lr
080039e4 <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
80039e4: b580 push {r7, lr}
80039e6: b082 sub sp, #8
80039e8: af00 add r7, sp, #0
80039ea: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
80039ec: 687b ldr r3, [r7, #4]
80039ee: 2b00 cmp r3, #0
80039f0: d101 bne.n 80039f6 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
80039f2: 2301 movs r3, #1
80039f4: e040 b.n 8003a78 <HAL_UART_Init+0x94>
{
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
}
if (huart->gState == HAL_UART_STATE_RESET)
80039f6: 687b ldr r3, [r7, #4]
80039f8: 6fdb ldr r3, [r3, #124] @ 0x7c
80039fa: 2b00 cmp r3, #0
80039fc: d106 bne.n 8003a0c <HAL_UART_Init+0x28>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
80039fe: 687b ldr r3, [r7, #4]
8003a00: 2200 movs r2, #0
8003a02: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8003a06: 6878 ldr r0, [r7, #4]
8003a08: f7fd fdc2 bl 8001590 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8003a0c: 687b ldr r3, [r7, #4]
8003a0e: 2224 movs r2, #36 @ 0x24
8003a10: 67da str r2, [r3, #124] @ 0x7c
__HAL_UART_DISABLE(huart);
8003a12: 687b ldr r3, [r7, #4]
8003a14: 681b ldr r3, [r3, #0]
8003a16: 681a ldr r2, [r3, #0]
8003a18: 687b ldr r3, [r7, #4]
8003a1a: 681b ldr r3, [r3, #0]
8003a1c: f022 0201 bic.w r2, r2, #1
8003a20: 601a str r2, [r3, #0]
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
8003a22: 687b ldr r3, [r7, #4]
8003a24: 6a5b ldr r3, [r3, #36] @ 0x24
8003a26: 2b00 cmp r3, #0
8003a28: d002 beq.n 8003a30 <HAL_UART_Init+0x4c>
{
UART_AdvFeatureConfig(huart);
8003a2a: 6878 ldr r0, [r7, #4]
8003a2c: f000 fb16 bl 800405c <UART_AdvFeatureConfig>
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
8003a30: 6878 ldr r0, [r7, #4]
8003a32: f000 f8af bl 8003b94 <UART_SetConfig>
8003a36: 4603 mov r3, r0
8003a38: 2b01 cmp r3, #1
8003a3a: d101 bne.n 8003a40 <HAL_UART_Init+0x5c>
{
return HAL_ERROR;
8003a3c: 2301 movs r3, #1
8003a3e: e01b b.n 8003a78 <HAL_UART_Init+0x94>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8003a40: 687b ldr r3, [r7, #4]
8003a42: 681b ldr r3, [r3, #0]
8003a44: 685a ldr r2, [r3, #4]
8003a46: 687b ldr r3, [r7, #4]
8003a48: 681b ldr r3, [r3, #0]
8003a4a: f422 4290 bic.w r2, r2, #18432 @ 0x4800
8003a4e: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8003a50: 687b ldr r3, [r7, #4]
8003a52: 681b ldr r3, [r3, #0]
8003a54: 689a ldr r2, [r3, #8]
8003a56: 687b ldr r3, [r7, #4]
8003a58: 681b ldr r3, [r3, #0]
8003a5a: f022 022a bic.w r2, r2, #42 @ 0x2a
8003a5e: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
8003a60: 687b ldr r3, [r7, #4]
8003a62: 681b ldr r3, [r3, #0]
8003a64: 681a ldr r2, [r3, #0]
8003a66: 687b ldr r3, [r7, #4]
8003a68: 681b ldr r3, [r3, #0]
8003a6a: f042 0201 orr.w r2, r2, #1
8003a6e: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
8003a70: 6878 ldr r0, [r7, #4]
8003a72: f000 fb95 bl 80041a0 <UART_CheckIdleState>
8003a76: 4603 mov r3, r0
}
8003a78: 4618 mov r0, r3
8003a7a: 3708 adds r7, #8
8003a7c: 46bd mov sp, r7
8003a7e: bd80 pop {r7, pc}
08003a80 <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8003a80: b580 push {r7, lr}
8003a82: b08a sub sp, #40 @ 0x28
8003a84: af02 add r7, sp, #8
8003a86: 60f8 str r0, [r7, #12]
8003a88: 60b9 str r1, [r7, #8]
8003a8a: 603b str r3, [r7, #0]
8003a8c: 4613 mov r3, r2
8003a8e: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
8003a90: 68fb ldr r3, [r7, #12]
8003a92: 6fdb ldr r3, [r3, #124] @ 0x7c
8003a94: 2b20 cmp r3, #32
8003a96: d177 bne.n 8003b88 <HAL_UART_Transmit+0x108>
{
if ((pData == NULL) || (Size == 0U))
8003a98: 68bb ldr r3, [r7, #8]
8003a9a: 2b00 cmp r3, #0
8003a9c: d002 beq.n 8003aa4 <HAL_UART_Transmit+0x24>
8003a9e: 88fb ldrh r3, [r7, #6]
8003aa0: 2b00 cmp r3, #0
8003aa2: d101 bne.n 8003aa8 <HAL_UART_Transmit+0x28>
{
return HAL_ERROR;
8003aa4: 2301 movs r3, #1
8003aa6: e070 b.n 8003b8a <HAL_UART_Transmit+0x10a>
}
huart->ErrorCode = HAL_UART_ERROR_NONE;
8003aa8: 68fb ldr r3, [r7, #12]
8003aaa: 2200 movs r2, #0
8003aac: f8c3 2084 str.w r2, [r3, #132] @ 0x84
huart->gState = HAL_UART_STATE_BUSY_TX;
8003ab0: 68fb ldr r3, [r7, #12]
8003ab2: 2221 movs r2, #33 @ 0x21
8003ab4: 67da str r2, [r3, #124] @ 0x7c
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8003ab6: f7fd ffeb bl 8001a90 <HAL_GetTick>
8003aba: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
8003abc: 68fb ldr r3, [r7, #12]
8003abe: 88fa ldrh r2, [r7, #6]
8003ac0: f8a3 2050 strh.w r2, [r3, #80] @ 0x50
huart->TxXferCount = Size;
8003ac4: 68fb ldr r3, [r7, #12]
8003ac6: 88fa ldrh r2, [r7, #6]
8003ac8: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8003acc: 68fb ldr r3, [r7, #12]
8003ace: 689b ldr r3, [r3, #8]
8003ad0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8003ad4: d108 bne.n 8003ae8 <HAL_UART_Transmit+0x68>
8003ad6: 68fb ldr r3, [r7, #12]
8003ad8: 691b ldr r3, [r3, #16]
8003ada: 2b00 cmp r3, #0
8003adc: d104 bne.n 8003ae8 <HAL_UART_Transmit+0x68>
{
pdata8bits = NULL;
8003ade: 2300 movs r3, #0
8003ae0: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
8003ae2: 68bb ldr r3, [r7, #8]
8003ae4: 61bb str r3, [r7, #24]
8003ae6: e003 b.n 8003af0 <HAL_UART_Transmit+0x70>
}
else
{
pdata8bits = pData;
8003ae8: 68bb ldr r3, [r7, #8]
8003aea: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8003aec: 2300 movs r3, #0
8003aee: 61bb str r3, [r7, #24]
}
while (huart->TxXferCount > 0U)
8003af0: e02f b.n 8003b52 <HAL_UART_Transmit+0xd2>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
8003af2: 683b ldr r3, [r7, #0]
8003af4: 9300 str r3, [sp, #0]
8003af6: 697b ldr r3, [r7, #20]
8003af8: 2200 movs r2, #0
8003afa: 2180 movs r1, #128 @ 0x80
8003afc: 68f8 ldr r0, [r7, #12]
8003afe: f000 fba6 bl 800424e <UART_WaitOnFlagUntilTimeout>
8003b02: 4603 mov r3, r0
8003b04: 2b00 cmp r3, #0
8003b06: d004 beq.n 8003b12 <HAL_UART_Transmit+0x92>
{
huart->gState = HAL_UART_STATE_READY;
8003b08: 68fb ldr r3, [r7, #12]
8003b0a: 2220 movs r2, #32
8003b0c: 67da str r2, [r3, #124] @ 0x7c
return HAL_TIMEOUT;
8003b0e: 2303 movs r3, #3
8003b10: e03b b.n 8003b8a <HAL_UART_Transmit+0x10a>
}
if (pdata8bits == NULL)
8003b12: 69fb ldr r3, [r7, #28]
8003b14: 2b00 cmp r3, #0
8003b16: d10b bne.n 8003b30 <HAL_UART_Transmit+0xb0>
{
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
8003b18: 69bb ldr r3, [r7, #24]
8003b1a: 881b ldrh r3, [r3, #0]
8003b1c: 461a mov r2, r3
8003b1e: 68fb ldr r3, [r7, #12]
8003b20: 681b ldr r3, [r3, #0]
8003b22: f3c2 0208 ubfx r2, r2, #0, #9
8003b26: 629a str r2, [r3, #40] @ 0x28
pdata16bits++;
8003b28: 69bb ldr r3, [r7, #24]
8003b2a: 3302 adds r3, #2
8003b2c: 61bb str r3, [r7, #24]
8003b2e: e007 b.n 8003b40 <HAL_UART_Transmit+0xc0>
}
else
{
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
8003b30: 69fb ldr r3, [r7, #28]
8003b32: 781a ldrb r2, [r3, #0]
8003b34: 68fb ldr r3, [r7, #12]
8003b36: 681b ldr r3, [r3, #0]
8003b38: 629a str r2, [r3, #40] @ 0x28
pdata8bits++;
8003b3a: 69fb ldr r3, [r7, #28]
8003b3c: 3301 adds r3, #1
8003b3e: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
8003b40: 68fb ldr r3, [r7, #12]
8003b42: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
8003b46: b29b uxth r3, r3
8003b48: 3b01 subs r3, #1
8003b4a: b29a uxth r2, r3
8003b4c: 68fb ldr r3, [r7, #12]
8003b4e: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
while (huart->TxXferCount > 0U)
8003b52: 68fb ldr r3, [r7, #12]
8003b54: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
8003b58: b29b uxth r3, r3
8003b5a: 2b00 cmp r3, #0
8003b5c: d1c9 bne.n 8003af2 <HAL_UART_Transmit+0x72>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
8003b5e: 683b ldr r3, [r7, #0]
8003b60: 9300 str r3, [sp, #0]
8003b62: 697b ldr r3, [r7, #20]
8003b64: 2200 movs r2, #0
8003b66: 2140 movs r1, #64 @ 0x40
8003b68: 68f8 ldr r0, [r7, #12]
8003b6a: f000 fb70 bl 800424e <UART_WaitOnFlagUntilTimeout>
8003b6e: 4603 mov r3, r0
8003b70: 2b00 cmp r3, #0
8003b72: d004 beq.n 8003b7e <HAL_UART_Transmit+0xfe>
{
huart->gState = HAL_UART_STATE_READY;
8003b74: 68fb ldr r3, [r7, #12]
8003b76: 2220 movs r2, #32
8003b78: 67da str r2, [r3, #124] @ 0x7c
return HAL_TIMEOUT;
8003b7a: 2303 movs r3, #3
8003b7c: e005 b.n 8003b8a <HAL_UART_Transmit+0x10a>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8003b7e: 68fb ldr r3, [r7, #12]
8003b80: 2220 movs r2, #32
8003b82: 67da str r2, [r3, #124] @ 0x7c
return HAL_OK;
8003b84: 2300 movs r3, #0
8003b86: e000 b.n 8003b8a <HAL_UART_Transmit+0x10a>
}
else
{
return HAL_BUSY;
8003b88: 2302 movs r3, #2
}
}
8003b8a: 4618 mov r0, r3
8003b8c: 3720 adds r7, #32
8003b8e: 46bd mov sp, r7
8003b90: bd80 pop {r7, pc}
...
08003b94 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8003b94: b580 push {r7, lr}
8003b96: b088 sub sp, #32
8003b98: af00 add r7, sp, #0
8003b9a: 6078 str r0, [r7, #4]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
8003b9c: 2300 movs r3, #0
8003b9e: 77bb strb r3, [r7, #30]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8003ba0: 687b ldr r3, [r7, #4]
8003ba2: 689a ldr r2, [r3, #8]
8003ba4: 687b ldr r3, [r7, #4]
8003ba6: 691b ldr r3, [r3, #16]
8003ba8: 431a orrs r2, r3
8003baa: 687b ldr r3, [r7, #4]
8003bac: 695b ldr r3, [r3, #20]
8003bae: 431a orrs r2, r3
8003bb0: 687b ldr r3, [r7, #4]
8003bb2: 69db ldr r3, [r3, #28]
8003bb4: 4313 orrs r3, r2
8003bb6: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8003bb8: 687b ldr r3, [r7, #4]
8003bba: 681b ldr r3, [r3, #0]
8003bbc: 681a ldr r2, [r3, #0]
8003bbe: 4ba6 ldr r3, [pc, #664] @ (8003e58 <UART_SetConfig+0x2c4>)
8003bc0: 4013 ands r3, r2
8003bc2: 687a ldr r2, [r7, #4]
8003bc4: 6812 ldr r2, [r2, #0]
8003bc6: 6979 ldr r1, [r7, #20]
8003bc8: 430b orrs r3, r1
8003bca: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8003bcc: 687b ldr r3, [r7, #4]
8003bce: 681b ldr r3, [r3, #0]
8003bd0: 685b ldr r3, [r3, #4]
8003bd2: f423 5140 bic.w r1, r3, #12288 @ 0x3000
8003bd6: 687b ldr r3, [r7, #4]
8003bd8: 68da ldr r2, [r3, #12]
8003bda: 687b ldr r3, [r7, #4]
8003bdc: 681b ldr r3, [r3, #0]
8003bde: 430a orrs r2, r1
8003be0: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
8003be2: 687b ldr r3, [r7, #4]
8003be4: 699b ldr r3, [r3, #24]
8003be6: 617b str r3, [r7, #20]
tmpreg |= huart->Init.OneBitSampling;
8003be8: 687b ldr r3, [r7, #4]
8003bea: 6a1b ldr r3, [r3, #32]
8003bec: 697a ldr r2, [r7, #20]
8003bee: 4313 orrs r3, r2
8003bf0: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8003bf2: 687b ldr r3, [r7, #4]
8003bf4: 681b ldr r3, [r3, #0]
8003bf6: 689b ldr r3, [r3, #8]
8003bf8: f423 6130 bic.w r1, r3, #2816 @ 0xb00
8003bfc: 687b ldr r3, [r7, #4]
8003bfe: 681b ldr r3, [r3, #0]
8003c00: 697a ldr r2, [r7, #20]
8003c02: 430a orrs r2, r1
8003c04: 609a str r2, [r3, #8]
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
8003c06: 687b ldr r3, [r7, #4]
8003c08: 681b ldr r3, [r3, #0]
8003c0a: 4a94 ldr r2, [pc, #592] @ (8003e5c <UART_SetConfig+0x2c8>)
8003c0c: 4293 cmp r3, r2
8003c0e: d120 bne.n 8003c52 <UART_SetConfig+0xbe>
8003c10: 4b93 ldr r3, [pc, #588] @ (8003e60 <UART_SetConfig+0x2cc>)
8003c12: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003c16: f003 0303 and.w r3, r3, #3
8003c1a: 2b03 cmp r3, #3
8003c1c: d816 bhi.n 8003c4c <UART_SetConfig+0xb8>
8003c1e: a201 add r2, pc, #4 @ (adr r2, 8003c24 <UART_SetConfig+0x90>)
8003c20: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003c24: 08003c35 .word 0x08003c35
8003c28: 08003c41 .word 0x08003c41
8003c2c: 08003c3b .word 0x08003c3b
8003c30: 08003c47 .word 0x08003c47
8003c34: 2301 movs r3, #1
8003c36: 77fb strb r3, [r7, #31]
8003c38: e150 b.n 8003edc <UART_SetConfig+0x348>
8003c3a: 2302 movs r3, #2
8003c3c: 77fb strb r3, [r7, #31]
8003c3e: e14d b.n 8003edc <UART_SetConfig+0x348>
8003c40: 2304 movs r3, #4
8003c42: 77fb strb r3, [r7, #31]
8003c44: e14a b.n 8003edc <UART_SetConfig+0x348>
8003c46: 2308 movs r3, #8
8003c48: 77fb strb r3, [r7, #31]
8003c4a: e147 b.n 8003edc <UART_SetConfig+0x348>
8003c4c: 2310 movs r3, #16
8003c4e: 77fb strb r3, [r7, #31]
8003c50: e144 b.n 8003edc <UART_SetConfig+0x348>
8003c52: 687b ldr r3, [r7, #4]
8003c54: 681b ldr r3, [r3, #0]
8003c56: 4a83 ldr r2, [pc, #524] @ (8003e64 <UART_SetConfig+0x2d0>)
8003c58: 4293 cmp r3, r2
8003c5a: d132 bne.n 8003cc2 <UART_SetConfig+0x12e>
8003c5c: 4b80 ldr r3, [pc, #512] @ (8003e60 <UART_SetConfig+0x2cc>)
8003c5e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003c62: f003 030c and.w r3, r3, #12
8003c66: 2b0c cmp r3, #12
8003c68: d828 bhi.n 8003cbc <UART_SetConfig+0x128>
8003c6a: a201 add r2, pc, #4 @ (adr r2, 8003c70 <UART_SetConfig+0xdc>)
8003c6c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003c70: 08003ca5 .word 0x08003ca5
8003c74: 08003cbd .word 0x08003cbd
8003c78: 08003cbd .word 0x08003cbd
8003c7c: 08003cbd .word 0x08003cbd
8003c80: 08003cb1 .word 0x08003cb1
8003c84: 08003cbd .word 0x08003cbd
8003c88: 08003cbd .word 0x08003cbd
8003c8c: 08003cbd .word 0x08003cbd
8003c90: 08003cab .word 0x08003cab
8003c94: 08003cbd .word 0x08003cbd
8003c98: 08003cbd .word 0x08003cbd
8003c9c: 08003cbd .word 0x08003cbd
8003ca0: 08003cb7 .word 0x08003cb7
8003ca4: 2300 movs r3, #0
8003ca6: 77fb strb r3, [r7, #31]
8003ca8: e118 b.n 8003edc <UART_SetConfig+0x348>
8003caa: 2302 movs r3, #2
8003cac: 77fb strb r3, [r7, #31]
8003cae: e115 b.n 8003edc <UART_SetConfig+0x348>
8003cb0: 2304 movs r3, #4
8003cb2: 77fb strb r3, [r7, #31]
8003cb4: e112 b.n 8003edc <UART_SetConfig+0x348>
8003cb6: 2308 movs r3, #8
8003cb8: 77fb strb r3, [r7, #31]
8003cba: e10f b.n 8003edc <UART_SetConfig+0x348>
8003cbc: 2310 movs r3, #16
8003cbe: 77fb strb r3, [r7, #31]
8003cc0: e10c b.n 8003edc <UART_SetConfig+0x348>
8003cc2: 687b ldr r3, [r7, #4]
8003cc4: 681b ldr r3, [r3, #0]
8003cc6: 4a68 ldr r2, [pc, #416] @ (8003e68 <UART_SetConfig+0x2d4>)
8003cc8: 4293 cmp r3, r2
8003cca: d120 bne.n 8003d0e <UART_SetConfig+0x17a>
8003ccc: 4b64 ldr r3, [pc, #400] @ (8003e60 <UART_SetConfig+0x2cc>)
8003cce: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003cd2: f003 0330 and.w r3, r3, #48 @ 0x30
8003cd6: 2b30 cmp r3, #48 @ 0x30
8003cd8: d013 beq.n 8003d02 <UART_SetConfig+0x16e>
8003cda: 2b30 cmp r3, #48 @ 0x30
8003cdc: d814 bhi.n 8003d08 <UART_SetConfig+0x174>
8003cde: 2b20 cmp r3, #32
8003ce0: d009 beq.n 8003cf6 <UART_SetConfig+0x162>
8003ce2: 2b20 cmp r3, #32
8003ce4: d810 bhi.n 8003d08 <UART_SetConfig+0x174>
8003ce6: 2b00 cmp r3, #0
8003ce8: d002 beq.n 8003cf0 <UART_SetConfig+0x15c>
8003cea: 2b10 cmp r3, #16
8003cec: d006 beq.n 8003cfc <UART_SetConfig+0x168>
8003cee: e00b b.n 8003d08 <UART_SetConfig+0x174>
8003cf0: 2300 movs r3, #0
8003cf2: 77fb strb r3, [r7, #31]
8003cf4: e0f2 b.n 8003edc <UART_SetConfig+0x348>
8003cf6: 2302 movs r3, #2
8003cf8: 77fb strb r3, [r7, #31]
8003cfa: e0ef b.n 8003edc <UART_SetConfig+0x348>
8003cfc: 2304 movs r3, #4
8003cfe: 77fb strb r3, [r7, #31]
8003d00: e0ec b.n 8003edc <UART_SetConfig+0x348>
8003d02: 2308 movs r3, #8
8003d04: 77fb strb r3, [r7, #31]
8003d06: e0e9 b.n 8003edc <UART_SetConfig+0x348>
8003d08: 2310 movs r3, #16
8003d0a: 77fb strb r3, [r7, #31]
8003d0c: e0e6 b.n 8003edc <UART_SetConfig+0x348>
8003d0e: 687b ldr r3, [r7, #4]
8003d10: 681b ldr r3, [r3, #0]
8003d12: 4a56 ldr r2, [pc, #344] @ (8003e6c <UART_SetConfig+0x2d8>)
8003d14: 4293 cmp r3, r2
8003d16: d120 bne.n 8003d5a <UART_SetConfig+0x1c6>
8003d18: 4b51 ldr r3, [pc, #324] @ (8003e60 <UART_SetConfig+0x2cc>)
8003d1a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003d1e: f003 03c0 and.w r3, r3, #192 @ 0xc0
8003d22: 2bc0 cmp r3, #192 @ 0xc0
8003d24: d013 beq.n 8003d4e <UART_SetConfig+0x1ba>
8003d26: 2bc0 cmp r3, #192 @ 0xc0
8003d28: d814 bhi.n 8003d54 <UART_SetConfig+0x1c0>
8003d2a: 2b80 cmp r3, #128 @ 0x80
8003d2c: d009 beq.n 8003d42 <UART_SetConfig+0x1ae>
8003d2e: 2b80 cmp r3, #128 @ 0x80
8003d30: d810 bhi.n 8003d54 <UART_SetConfig+0x1c0>
8003d32: 2b00 cmp r3, #0
8003d34: d002 beq.n 8003d3c <UART_SetConfig+0x1a8>
8003d36: 2b40 cmp r3, #64 @ 0x40
8003d38: d006 beq.n 8003d48 <UART_SetConfig+0x1b4>
8003d3a: e00b b.n 8003d54 <UART_SetConfig+0x1c0>
8003d3c: 2300 movs r3, #0
8003d3e: 77fb strb r3, [r7, #31]
8003d40: e0cc b.n 8003edc <UART_SetConfig+0x348>
8003d42: 2302 movs r3, #2
8003d44: 77fb strb r3, [r7, #31]
8003d46: e0c9 b.n 8003edc <UART_SetConfig+0x348>
8003d48: 2304 movs r3, #4
8003d4a: 77fb strb r3, [r7, #31]
8003d4c: e0c6 b.n 8003edc <UART_SetConfig+0x348>
8003d4e: 2308 movs r3, #8
8003d50: 77fb strb r3, [r7, #31]
8003d52: e0c3 b.n 8003edc <UART_SetConfig+0x348>
8003d54: 2310 movs r3, #16
8003d56: 77fb strb r3, [r7, #31]
8003d58: e0c0 b.n 8003edc <UART_SetConfig+0x348>
8003d5a: 687b ldr r3, [r7, #4]
8003d5c: 681b ldr r3, [r3, #0]
8003d5e: 4a44 ldr r2, [pc, #272] @ (8003e70 <UART_SetConfig+0x2dc>)
8003d60: 4293 cmp r3, r2
8003d62: d125 bne.n 8003db0 <UART_SetConfig+0x21c>
8003d64: 4b3e ldr r3, [pc, #248] @ (8003e60 <UART_SetConfig+0x2cc>)
8003d66: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003d6a: f403 7340 and.w r3, r3, #768 @ 0x300
8003d6e: f5b3 7f40 cmp.w r3, #768 @ 0x300
8003d72: d017 beq.n 8003da4 <UART_SetConfig+0x210>
8003d74: f5b3 7f40 cmp.w r3, #768 @ 0x300
8003d78: d817 bhi.n 8003daa <UART_SetConfig+0x216>
8003d7a: f5b3 7f00 cmp.w r3, #512 @ 0x200
8003d7e: d00b beq.n 8003d98 <UART_SetConfig+0x204>
8003d80: f5b3 7f00 cmp.w r3, #512 @ 0x200
8003d84: d811 bhi.n 8003daa <UART_SetConfig+0x216>
8003d86: 2b00 cmp r3, #0
8003d88: d003 beq.n 8003d92 <UART_SetConfig+0x1fe>
8003d8a: f5b3 7f80 cmp.w r3, #256 @ 0x100
8003d8e: d006 beq.n 8003d9e <UART_SetConfig+0x20a>
8003d90: e00b b.n 8003daa <UART_SetConfig+0x216>
8003d92: 2300 movs r3, #0
8003d94: 77fb strb r3, [r7, #31]
8003d96: e0a1 b.n 8003edc <UART_SetConfig+0x348>
8003d98: 2302 movs r3, #2
8003d9a: 77fb strb r3, [r7, #31]
8003d9c: e09e b.n 8003edc <UART_SetConfig+0x348>
8003d9e: 2304 movs r3, #4
8003da0: 77fb strb r3, [r7, #31]
8003da2: e09b b.n 8003edc <UART_SetConfig+0x348>
8003da4: 2308 movs r3, #8
8003da6: 77fb strb r3, [r7, #31]
8003da8: e098 b.n 8003edc <UART_SetConfig+0x348>
8003daa: 2310 movs r3, #16
8003dac: 77fb strb r3, [r7, #31]
8003dae: e095 b.n 8003edc <UART_SetConfig+0x348>
8003db0: 687b ldr r3, [r7, #4]
8003db2: 681b ldr r3, [r3, #0]
8003db4: 4a2f ldr r2, [pc, #188] @ (8003e74 <UART_SetConfig+0x2e0>)
8003db6: 4293 cmp r3, r2
8003db8: d125 bne.n 8003e06 <UART_SetConfig+0x272>
8003dba: 4b29 ldr r3, [pc, #164] @ (8003e60 <UART_SetConfig+0x2cc>)
8003dbc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003dc0: f403 6340 and.w r3, r3, #3072 @ 0xc00
8003dc4: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
8003dc8: d017 beq.n 8003dfa <UART_SetConfig+0x266>
8003dca: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
8003dce: d817 bhi.n 8003e00 <UART_SetConfig+0x26c>
8003dd0: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8003dd4: d00b beq.n 8003dee <UART_SetConfig+0x25a>
8003dd6: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8003dda: d811 bhi.n 8003e00 <UART_SetConfig+0x26c>
8003ddc: 2b00 cmp r3, #0
8003dde: d003 beq.n 8003de8 <UART_SetConfig+0x254>
8003de0: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003de4: d006 beq.n 8003df4 <UART_SetConfig+0x260>
8003de6: e00b b.n 8003e00 <UART_SetConfig+0x26c>
8003de8: 2301 movs r3, #1
8003dea: 77fb strb r3, [r7, #31]
8003dec: e076 b.n 8003edc <UART_SetConfig+0x348>
8003dee: 2302 movs r3, #2
8003df0: 77fb strb r3, [r7, #31]
8003df2: e073 b.n 8003edc <UART_SetConfig+0x348>
8003df4: 2304 movs r3, #4
8003df6: 77fb strb r3, [r7, #31]
8003df8: e070 b.n 8003edc <UART_SetConfig+0x348>
8003dfa: 2308 movs r3, #8
8003dfc: 77fb strb r3, [r7, #31]
8003dfe: e06d b.n 8003edc <UART_SetConfig+0x348>
8003e00: 2310 movs r3, #16
8003e02: 77fb strb r3, [r7, #31]
8003e04: e06a b.n 8003edc <UART_SetConfig+0x348>
8003e06: 687b ldr r3, [r7, #4]
8003e08: 681b ldr r3, [r3, #0]
8003e0a: 4a1b ldr r2, [pc, #108] @ (8003e78 <UART_SetConfig+0x2e4>)
8003e0c: 4293 cmp r3, r2
8003e0e: d138 bne.n 8003e82 <UART_SetConfig+0x2ee>
8003e10: 4b13 ldr r3, [pc, #76] @ (8003e60 <UART_SetConfig+0x2cc>)
8003e12: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003e16: f403 5340 and.w r3, r3, #12288 @ 0x3000
8003e1a: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
8003e1e: d017 beq.n 8003e50 <UART_SetConfig+0x2bc>
8003e20: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
8003e24: d82a bhi.n 8003e7c <UART_SetConfig+0x2e8>
8003e26: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8003e2a: d00b beq.n 8003e44 <UART_SetConfig+0x2b0>
8003e2c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8003e30: d824 bhi.n 8003e7c <UART_SetConfig+0x2e8>
8003e32: 2b00 cmp r3, #0
8003e34: d003 beq.n 8003e3e <UART_SetConfig+0x2aa>
8003e36: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8003e3a: d006 beq.n 8003e4a <UART_SetConfig+0x2b6>
8003e3c: e01e b.n 8003e7c <UART_SetConfig+0x2e8>
8003e3e: 2300 movs r3, #0
8003e40: 77fb strb r3, [r7, #31]
8003e42: e04b b.n 8003edc <UART_SetConfig+0x348>
8003e44: 2302 movs r3, #2
8003e46: 77fb strb r3, [r7, #31]
8003e48: e048 b.n 8003edc <UART_SetConfig+0x348>
8003e4a: 2304 movs r3, #4
8003e4c: 77fb strb r3, [r7, #31]
8003e4e: e045 b.n 8003edc <UART_SetConfig+0x348>
8003e50: 2308 movs r3, #8
8003e52: 77fb strb r3, [r7, #31]
8003e54: e042 b.n 8003edc <UART_SetConfig+0x348>
8003e56: bf00 nop
8003e58: efff69f3 .word 0xefff69f3
8003e5c: 40011000 .word 0x40011000
8003e60: 40023800 .word 0x40023800
8003e64: 40004400 .word 0x40004400
8003e68: 40004800 .word 0x40004800
8003e6c: 40004c00 .word 0x40004c00
8003e70: 40005000 .word 0x40005000
8003e74: 40011400 .word 0x40011400
8003e78: 40007800 .word 0x40007800
8003e7c: 2310 movs r3, #16
8003e7e: 77fb strb r3, [r7, #31]
8003e80: e02c b.n 8003edc <UART_SetConfig+0x348>
8003e82: 687b ldr r3, [r7, #4]
8003e84: 681b ldr r3, [r3, #0]
8003e86: 4a72 ldr r2, [pc, #456] @ (8004050 <UART_SetConfig+0x4bc>)
8003e88: 4293 cmp r3, r2
8003e8a: d125 bne.n 8003ed8 <UART_SetConfig+0x344>
8003e8c: 4b71 ldr r3, [pc, #452] @ (8004054 <UART_SetConfig+0x4c0>)
8003e8e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003e92: f403 4340 and.w r3, r3, #49152 @ 0xc000
8003e96: f5b3 4f40 cmp.w r3, #49152 @ 0xc000
8003e9a: d017 beq.n 8003ecc <UART_SetConfig+0x338>
8003e9c: f5b3 4f40 cmp.w r3, #49152 @ 0xc000
8003ea0: d817 bhi.n 8003ed2 <UART_SetConfig+0x33e>
8003ea2: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8003ea6: d00b beq.n 8003ec0 <UART_SetConfig+0x32c>
8003ea8: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8003eac: d811 bhi.n 8003ed2 <UART_SetConfig+0x33e>
8003eae: 2b00 cmp r3, #0
8003eb0: d003 beq.n 8003eba <UART_SetConfig+0x326>
8003eb2: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
8003eb6: d006 beq.n 8003ec6 <UART_SetConfig+0x332>
8003eb8: e00b b.n 8003ed2 <UART_SetConfig+0x33e>
8003eba: 2300 movs r3, #0
8003ebc: 77fb strb r3, [r7, #31]
8003ebe: e00d b.n 8003edc <UART_SetConfig+0x348>
8003ec0: 2302 movs r3, #2
8003ec2: 77fb strb r3, [r7, #31]
8003ec4: e00a b.n 8003edc <UART_SetConfig+0x348>
8003ec6: 2304 movs r3, #4
8003ec8: 77fb strb r3, [r7, #31]
8003eca: e007 b.n 8003edc <UART_SetConfig+0x348>
8003ecc: 2308 movs r3, #8
8003ece: 77fb strb r3, [r7, #31]
8003ed0: e004 b.n 8003edc <UART_SetConfig+0x348>
8003ed2: 2310 movs r3, #16
8003ed4: 77fb strb r3, [r7, #31]
8003ed6: e001 b.n 8003edc <UART_SetConfig+0x348>
8003ed8: 2310 movs r3, #16
8003eda: 77fb strb r3, [r7, #31]
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8003edc: 687b ldr r3, [r7, #4]
8003ede: 69db ldr r3, [r3, #28]
8003ee0: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8003ee4: d15b bne.n 8003f9e <UART_SetConfig+0x40a>
{
switch (clocksource)
8003ee6: 7ffb ldrb r3, [r7, #31]
8003ee8: 2b08 cmp r3, #8
8003eea: d828 bhi.n 8003f3e <UART_SetConfig+0x3aa>
8003eec: a201 add r2, pc, #4 @ (adr r2, 8003ef4 <UART_SetConfig+0x360>)
8003eee: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003ef2: bf00 nop
8003ef4: 08003f19 .word 0x08003f19
8003ef8: 08003f21 .word 0x08003f21
8003efc: 08003f29 .word 0x08003f29
8003f00: 08003f3f .word 0x08003f3f
8003f04: 08003f2f .word 0x08003f2f
8003f08: 08003f3f .word 0x08003f3f
8003f0c: 08003f3f .word 0x08003f3f
8003f10: 08003f3f .word 0x08003f3f
8003f14: 08003f37 .word 0x08003f37
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8003f18: f7fe feaa bl 8002c70 <HAL_RCC_GetPCLK1Freq>
8003f1c: 61b8 str r0, [r7, #24]
break;
8003f1e: e013 b.n 8003f48 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8003f20: f7fe feba bl 8002c98 <HAL_RCC_GetPCLK2Freq>
8003f24: 61b8 str r0, [r7, #24]
break;
8003f26: e00f b.n 8003f48 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8003f28: 4b4b ldr r3, [pc, #300] @ (8004058 <UART_SetConfig+0x4c4>)
8003f2a: 61bb str r3, [r7, #24]
break;
8003f2c: e00c b.n 8003f48 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8003f2e: f7fe fdcd bl 8002acc <HAL_RCC_GetSysClockFreq>
8003f32: 61b8 str r0, [r7, #24]
break;
8003f34: e008 b.n 8003f48 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8003f36: f44f 4300 mov.w r3, #32768 @ 0x8000
8003f3a: 61bb str r3, [r7, #24]
break;
8003f3c: e004 b.n 8003f48 <UART_SetConfig+0x3b4>
default:
pclk = 0U;
8003f3e: 2300 movs r3, #0
8003f40: 61bb str r3, [r7, #24]
ret = HAL_ERROR;
8003f42: 2301 movs r3, #1
8003f44: 77bb strb r3, [r7, #30]
break;
8003f46: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
8003f48: 69bb ldr r3, [r7, #24]
8003f4a: 2b00 cmp r3, #0
8003f4c: d074 beq.n 8004038 <UART_SetConfig+0x4a4>
{
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
8003f4e: 69bb ldr r3, [r7, #24]
8003f50: 005a lsls r2, r3, #1
8003f52: 687b ldr r3, [r7, #4]
8003f54: 685b ldr r3, [r3, #4]
8003f56: 085b lsrs r3, r3, #1
8003f58: 441a add r2, r3
8003f5a: 687b ldr r3, [r7, #4]
8003f5c: 685b ldr r3, [r3, #4]
8003f5e: fbb2 f3f3 udiv r3, r2, r3
8003f62: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8003f64: 693b ldr r3, [r7, #16]
8003f66: 2b0f cmp r3, #15
8003f68: d916 bls.n 8003f98 <UART_SetConfig+0x404>
8003f6a: 693b ldr r3, [r7, #16]
8003f6c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8003f70: d212 bcs.n 8003f98 <UART_SetConfig+0x404>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
8003f72: 693b ldr r3, [r7, #16]
8003f74: b29b uxth r3, r3
8003f76: f023 030f bic.w r3, r3, #15
8003f7a: 81fb strh r3, [r7, #14]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8003f7c: 693b ldr r3, [r7, #16]
8003f7e: 085b lsrs r3, r3, #1
8003f80: b29b uxth r3, r3
8003f82: f003 0307 and.w r3, r3, #7
8003f86: b29a uxth r2, r3
8003f88: 89fb ldrh r3, [r7, #14]
8003f8a: 4313 orrs r3, r2
8003f8c: 81fb strh r3, [r7, #14]
huart->Instance->BRR = brrtemp;
8003f8e: 687b ldr r3, [r7, #4]
8003f90: 681b ldr r3, [r3, #0]
8003f92: 89fa ldrh r2, [r7, #14]
8003f94: 60da str r2, [r3, #12]
8003f96: e04f b.n 8004038 <UART_SetConfig+0x4a4>
}
else
{
ret = HAL_ERROR;
8003f98: 2301 movs r3, #1
8003f9a: 77bb strb r3, [r7, #30]
8003f9c: e04c b.n 8004038 <UART_SetConfig+0x4a4>
}
}
}
else
{
switch (clocksource)
8003f9e: 7ffb ldrb r3, [r7, #31]
8003fa0: 2b08 cmp r3, #8
8003fa2: d828 bhi.n 8003ff6 <UART_SetConfig+0x462>
8003fa4: a201 add r2, pc, #4 @ (adr r2, 8003fac <UART_SetConfig+0x418>)
8003fa6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003faa: bf00 nop
8003fac: 08003fd1 .word 0x08003fd1
8003fb0: 08003fd9 .word 0x08003fd9
8003fb4: 08003fe1 .word 0x08003fe1
8003fb8: 08003ff7 .word 0x08003ff7
8003fbc: 08003fe7 .word 0x08003fe7
8003fc0: 08003ff7 .word 0x08003ff7
8003fc4: 08003ff7 .word 0x08003ff7
8003fc8: 08003ff7 .word 0x08003ff7
8003fcc: 08003fef .word 0x08003fef
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8003fd0: f7fe fe4e bl 8002c70 <HAL_RCC_GetPCLK1Freq>
8003fd4: 61b8 str r0, [r7, #24]
break;
8003fd6: e013 b.n 8004000 <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8003fd8: f7fe fe5e bl 8002c98 <HAL_RCC_GetPCLK2Freq>
8003fdc: 61b8 str r0, [r7, #24]
break;
8003fde: e00f b.n 8004000 <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8003fe0: 4b1d ldr r3, [pc, #116] @ (8004058 <UART_SetConfig+0x4c4>)
8003fe2: 61bb str r3, [r7, #24]
break;
8003fe4: e00c b.n 8004000 <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8003fe6: f7fe fd71 bl 8002acc <HAL_RCC_GetSysClockFreq>
8003fea: 61b8 str r0, [r7, #24]
break;
8003fec: e008 b.n 8004000 <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8003fee: f44f 4300 mov.w r3, #32768 @ 0x8000
8003ff2: 61bb str r3, [r7, #24]
break;
8003ff4: e004 b.n 8004000 <UART_SetConfig+0x46c>
default:
pclk = 0U;
8003ff6: 2300 movs r3, #0
8003ff8: 61bb str r3, [r7, #24]
ret = HAL_ERROR;
8003ffa: 2301 movs r3, #1
8003ffc: 77bb strb r3, [r7, #30]
break;
8003ffe: bf00 nop
}
if (pclk != 0U)
8004000: 69bb ldr r3, [r7, #24]
8004002: 2b00 cmp r3, #0
8004004: d018 beq.n 8004038 <UART_SetConfig+0x4a4>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
8004006: 687b ldr r3, [r7, #4]
8004008: 685b ldr r3, [r3, #4]
800400a: 085a lsrs r2, r3, #1
800400c: 69bb ldr r3, [r7, #24]
800400e: 441a add r2, r3
8004010: 687b ldr r3, [r7, #4]
8004012: 685b ldr r3, [r3, #4]
8004014: fbb2 f3f3 udiv r3, r2, r3
8004018: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
800401a: 693b ldr r3, [r7, #16]
800401c: 2b0f cmp r3, #15
800401e: d909 bls.n 8004034 <UART_SetConfig+0x4a0>
8004020: 693b ldr r3, [r7, #16]
8004022: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8004026: d205 bcs.n 8004034 <UART_SetConfig+0x4a0>
{
huart->Instance->BRR = (uint16_t)usartdiv;
8004028: 693b ldr r3, [r7, #16]
800402a: b29a uxth r2, r3
800402c: 687b ldr r3, [r7, #4]
800402e: 681b ldr r3, [r3, #0]
8004030: 60da str r2, [r3, #12]
8004032: e001 b.n 8004038 <UART_SetConfig+0x4a4>
}
else
{
ret = HAL_ERROR;
8004034: 2301 movs r3, #1
8004036: 77bb strb r3, [r7, #30]
}
}
/* Clear ISR function pointers */
huart->RxISR = NULL;
8004038: 687b ldr r3, [r7, #4]
800403a: 2200 movs r2, #0
800403c: 669a str r2, [r3, #104] @ 0x68
huart->TxISR = NULL;
800403e: 687b ldr r3, [r7, #4]
8004040: 2200 movs r2, #0
8004042: 66da str r2, [r3, #108] @ 0x6c
return ret;
8004044: 7fbb ldrb r3, [r7, #30]
}
8004046: 4618 mov r0, r3
8004048: 3720 adds r7, #32
800404a: 46bd mov sp, r7
800404c: bd80 pop {r7, pc}
800404e: bf00 nop
8004050: 40007c00 .word 0x40007c00
8004054: 40023800 .word 0x40023800
8004058: 00f42400 .word 0x00f42400
0800405c <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
800405c: b480 push {r7}
800405e: b083 sub sp, #12
8004060: af00 add r7, sp, #0
8004062: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
8004064: 687b ldr r3, [r7, #4]
8004066: 6a5b ldr r3, [r3, #36] @ 0x24
8004068: f003 0308 and.w r3, r3, #8
800406c: 2b00 cmp r3, #0
800406e: d00a beq.n 8004086 <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
8004070: 687b ldr r3, [r7, #4]
8004072: 681b ldr r3, [r3, #0]
8004074: 685b ldr r3, [r3, #4]
8004076: f423 4100 bic.w r1, r3, #32768 @ 0x8000
800407a: 687b ldr r3, [r7, #4]
800407c: 6b5a ldr r2, [r3, #52] @ 0x34
800407e: 687b ldr r3, [r7, #4]
8004080: 681b ldr r3, [r3, #0]
8004082: 430a orrs r2, r1
8004084: 605a str r2, [r3, #4]
}
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
8004086: 687b ldr r3, [r7, #4]
8004088: 6a5b ldr r3, [r3, #36] @ 0x24
800408a: f003 0301 and.w r3, r3, #1
800408e: 2b00 cmp r3, #0
8004090: d00a beq.n 80040a8 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
8004092: 687b ldr r3, [r7, #4]
8004094: 681b ldr r3, [r3, #0]
8004096: 685b ldr r3, [r3, #4]
8004098: f423 3100 bic.w r1, r3, #131072 @ 0x20000
800409c: 687b ldr r3, [r7, #4]
800409e: 6a9a ldr r2, [r3, #40] @ 0x28
80040a0: 687b ldr r3, [r7, #4]
80040a2: 681b ldr r3, [r3, #0]
80040a4: 430a orrs r2, r1
80040a6: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
80040a8: 687b ldr r3, [r7, #4]
80040aa: 6a5b ldr r3, [r3, #36] @ 0x24
80040ac: f003 0302 and.w r3, r3, #2
80040b0: 2b00 cmp r3, #0
80040b2: d00a beq.n 80040ca <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
80040b4: 687b ldr r3, [r7, #4]
80040b6: 681b ldr r3, [r3, #0]
80040b8: 685b ldr r3, [r3, #4]
80040ba: f423 3180 bic.w r1, r3, #65536 @ 0x10000
80040be: 687b ldr r3, [r7, #4]
80040c0: 6ada ldr r2, [r3, #44] @ 0x2c
80040c2: 687b ldr r3, [r7, #4]
80040c4: 681b ldr r3, [r3, #0]
80040c6: 430a orrs r2, r1
80040c8: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
80040ca: 687b ldr r3, [r7, #4]
80040cc: 6a5b ldr r3, [r3, #36] @ 0x24
80040ce: f003 0304 and.w r3, r3, #4
80040d2: 2b00 cmp r3, #0
80040d4: d00a beq.n 80040ec <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
80040d6: 687b ldr r3, [r7, #4]
80040d8: 681b ldr r3, [r3, #0]
80040da: 685b ldr r3, [r3, #4]
80040dc: f423 2180 bic.w r1, r3, #262144 @ 0x40000
80040e0: 687b ldr r3, [r7, #4]
80040e2: 6b1a ldr r2, [r3, #48] @ 0x30
80040e4: 687b ldr r3, [r7, #4]
80040e6: 681b ldr r3, [r3, #0]
80040e8: 430a orrs r2, r1
80040ea: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
80040ec: 687b ldr r3, [r7, #4]
80040ee: 6a5b ldr r3, [r3, #36] @ 0x24
80040f0: f003 0310 and.w r3, r3, #16
80040f4: 2b00 cmp r3, #0
80040f6: d00a beq.n 800410e <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
80040f8: 687b ldr r3, [r7, #4]
80040fa: 681b ldr r3, [r3, #0]
80040fc: 689b ldr r3, [r3, #8]
80040fe: f423 5180 bic.w r1, r3, #4096 @ 0x1000
8004102: 687b ldr r3, [r7, #4]
8004104: 6b9a ldr r2, [r3, #56] @ 0x38
8004106: 687b ldr r3, [r7, #4]
8004108: 681b ldr r3, [r3, #0]
800410a: 430a orrs r2, r1
800410c: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
800410e: 687b ldr r3, [r7, #4]
8004110: 6a5b ldr r3, [r3, #36] @ 0x24
8004112: f003 0320 and.w r3, r3, #32
8004116: 2b00 cmp r3, #0
8004118: d00a beq.n 8004130 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
800411a: 687b ldr r3, [r7, #4]
800411c: 681b ldr r3, [r3, #0]
800411e: 689b ldr r3, [r3, #8]
8004120: f423 5100 bic.w r1, r3, #8192 @ 0x2000
8004124: 687b ldr r3, [r7, #4]
8004126: 6bda ldr r2, [r3, #60] @ 0x3c
8004128: 687b ldr r3, [r7, #4]
800412a: 681b ldr r3, [r3, #0]
800412c: 430a orrs r2, r1
800412e: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
8004130: 687b ldr r3, [r7, #4]
8004132: 6a5b ldr r3, [r3, #36] @ 0x24
8004134: f003 0340 and.w r3, r3, #64 @ 0x40
8004138: 2b00 cmp r3, #0
800413a: d01a beq.n 8004172 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
800413c: 687b ldr r3, [r7, #4]
800413e: 681b ldr r3, [r3, #0]
8004140: 685b ldr r3, [r3, #4]
8004142: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
8004146: 687b ldr r3, [r7, #4]
8004148: 6c1a ldr r2, [r3, #64] @ 0x40
800414a: 687b ldr r3, [r7, #4]
800414c: 681b ldr r3, [r3, #0]
800414e: 430a orrs r2, r1
8004150: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
8004152: 687b ldr r3, [r7, #4]
8004154: 6c1b ldr r3, [r3, #64] @ 0x40
8004156: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
800415a: d10a bne.n 8004172 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
800415c: 687b ldr r3, [r7, #4]
800415e: 681b ldr r3, [r3, #0]
8004160: 685b ldr r3, [r3, #4]
8004162: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
8004166: 687b ldr r3, [r7, #4]
8004168: 6c5a ldr r2, [r3, #68] @ 0x44
800416a: 687b ldr r3, [r7, #4]
800416c: 681b ldr r3, [r3, #0]
800416e: 430a orrs r2, r1
8004170: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
8004172: 687b ldr r3, [r7, #4]
8004174: 6a5b ldr r3, [r3, #36] @ 0x24
8004176: f003 0380 and.w r3, r3, #128 @ 0x80
800417a: 2b00 cmp r3, #0
800417c: d00a beq.n 8004194 <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
800417e: 687b ldr r3, [r7, #4]
8004180: 681b ldr r3, [r3, #0]
8004182: 685b ldr r3, [r3, #4]
8004184: f423 2100 bic.w r1, r3, #524288 @ 0x80000
8004188: 687b ldr r3, [r7, #4]
800418a: 6c9a ldr r2, [r3, #72] @ 0x48
800418c: 687b ldr r3, [r7, #4]
800418e: 681b ldr r3, [r3, #0]
8004190: 430a orrs r2, r1
8004192: 605a str r2, [r3, #4]
}
}
8004194: bf00 nop
8004196: 370c adds r7, #12
8004198: 46bd mov sp, r7
800419a: f85d 7b04 ldr.w r7, [sp], #4
800419e: 4770 bx lr
080041a0 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
80041a0: b580 push {r7, lr}
80041a2: b08c sub sp, #48 @ 0x30
80041a4: af02 add r7, sp, #8
80041a6: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80041a8: 687b ldr r3, [r7, #4]
80041aa: 2200 movs r2, #0
80041ac: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
80041b0: f7fd fc6e bl 8001a90 <HAL_GetTick>
80041b4: 6278 str r0, [r7, #36] @ 0x24
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
80041b6: 687b ldr r3, [r7, #4]
80041b8: 681b ldr r3, [r3, #0]
80041ba: 681b ldr r3, [r3, #0]
80041bc: f003 0308 and.w r3, r3, #8
80041c0: 2b08 cmp r3, #8
80041c2: d12e bne.n 8004222 <UART_CheckIdleState+0x82>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
80041c4: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
80041c8: 9300 str r3, [sp, #0]
80041ca: 6a7b ldr r3, [r7, #36] @ 0x24
80041cc: 2200 movs r2, #0
80041ce: f44f 1100 mov.w r1, #2097152 @ 0x200000
80041d2: 6878 ldr r0, [r7, #4]
80041d4: f000 f83b bl 800424e <UART_WaitOnFlagUntilTimeout>
80041d8: 4603 mov r3, r0
80041da: 2b00 cmp r3, #0
80041dc: d021 beq.n 8004222 <UART_CheckIdleState+0x82>
{
/* Disable TXE interrupt for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
80041de: 687b ldr r3, [r7, #4]
80041e0: 681b ldr r3, [r3, #0]
80041e2: 613b str r3, [r7, #16]
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80041e4: 693b ldr r3, [r7, #16]
80041e6: e853 3f00 ldrex r3, [r3]
80041ea: 60fb str r3, [r7, #12]
return(result);
80041ec: 68fb ldr r3, [r7, #12]
80041ee: f023 0380 bic.w r3, r3, #128 @ 0x80
80041f2: 623b str r3, [r7, #32]
80041f4: 687b ldr r3, [r7, #4]
80041f6: 681b ldr r3, [r3, #0]
80041f8: 461a mov r2, r3
80041fa: 6a3b ldr r3, [r7, #32]
80041fc: 61fb str r3, [r7, #28]
80041fe: 61ba str r2, [r7, #24]
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004200: 69b9 ldr r1, [r7, #24]
8004202: 69fa ldr r2, [r7, #28]
8004204: e841 2300 strex r3, r2, [r1]
8004208: 617b str r3, [r7, #20]
return(result);
800420a: 697b ldr r3, [r7, #20]
800420c: 2b00 cmp r3, #0
800420e: d1e6 bne.n 80041de <UART_CheckIdleState+0x3e>
huart->gState = HAL_UART_STATE_READY;
8004210: 687b ldr r3, [r7, #4]
8004212: 2220 movs r2, #32
8004214: 67da str r2, [r3, #124] @ 0x7c
__HAL_UNLOCK(huart);
8004216: 687b ldr r3, [r7, #4]
8004218: 2200 movs r2, #0
800421a: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Timeout occurred */
return HAL_TIMEOUT;
800421e: 2303 movs r3, #3
8004220: e011 b.n 8004246 <UART_CheckIdleState+0xa6>
}
}
#endif /* USART_ISR_REACK */
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
8004222: 687b ldr r3, [r7, #4]
8004224: 2220 movs r2, #32
8004226: 67da str r2, [r3, #124] @ 0x7c
huart->RxState = HAL_UART_STATE_READY;
8004228: 687b ldr r3, [r7, #4]
800422a: 2220 movs r2, #32
800422c: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004230: 687b ldr r3, [r7, #4]
8004232: 2200 movs r2, #0
8004234: 661a str r2, [r3, #96] @ 0x60
huart->RxEventType = HAL_UART_RXEVENT_TC;
8004236: 687b ldr r3, [r7, #4]
8004238: 2200 movs r2, #0
800423a: 665a str r2, [r3, #100] @ 0x64
__HAL_UNLOCK(huart);
800423c: 687b ldr r3, [r7, #4]
800423e: 2200 movs r2, #0
8004240: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_OK;
8004244: 2300 movs r3, #0
}
8004246: 4618 mov r0, r3
8004248: 3728 adds r7, #40 @ 0x28
800424a: 46bd mov sp, r7
800424c: bd80 pop {r7, pc}
0800424e <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
800424e: b580 push {r7, lr}
8004250: b084 sub sp, #16
8004252: af00 add r7, sp, #0
8004254: 60f8 str r0, [r7, #12]
8004256: 60b9 str r1, [r7, #8]
8004258: 603b str r3, [r7, #0]
800425a: 4613 mov r3, r2
800425c: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
800425e: e04f b.n 8004300 <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8004260: 69bb ldr r3, [r7, #24]
8004262: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8004266: d04b beq.n 8004300 <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004268: f7fd fc12 bl 8001a90 <HAL_GetTick>
800426c: 4602 mov r2, r0
800426e: 683b ldr r3, [r7, #0]
8004270: 1ad3 subs r3, r2, r3
8004272: 69ba ldr r2, [r7, #24]
8004274: 429a cmp r2, r3
8004276: d302 bcc.n 800427e <UART_WaitOnFlagUntilTimeout+0x30>
8004278: 69bb ldr r3, [r7, #24]
800427a: 2b00 cmp r3, #0
800427c: d101 bne.n 8004282 <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
800427e: 2303 movs r3, #3
8004280: e04e b.n 8004320 <UART_WaitOnFlagUntilTimeout+0xd2>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
8004282: 68fb ldr r3, [r7, #12]
8004284: 681b ldr r3, [r3, #0]
8004286: 681b ldr r3, [r3, #0]
8004288: f003 0304 and.w r3, r3, #4
800428c: 2b00 cmp r3, #0
800428e: d037 beq.n 8004300 <UART_WaitOnFlagUntilTimeout+0xb2>
8004290: 68bb ldr r3, [r7, #8]
8004292: 2b80 cmp r3, #128 @ 0x80
8004294: d034 beq.n 8004300 <UART_WaitOnFlagUntilTimeout+0xb2>
8004296: 68bb ldr r3, [r7, #8]
8004298: 2b40 cmp r3, #64 @ 0x40
800429a: d031 beq.n 8004300 <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
800429c: 68fb ldr r3, [r7, #12]
800429e: 681b ldr r3, [r3, #0]
80042a0: 69db ldr r3, [r3, #28]
80042a2: f003 0308 and.w r3, r3, #8
80042a6: 2b08 cmp r3, #8
80042a8: d110 bne.n 80042cc <UART_WaitOnFlagUntilTimeout+0x7e>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
80042aa: 68fb ldr r3, [r7, #12]
80042ac: 681b ldr r3, [r3, #0]
80042ae: 2208 movs r2, #8
80042b0: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
80042b2: 68f8 ldr r0, [r7, #12]
80042b4: f000 f838 bl 8004328 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
80042b8: 68fb ldr r3, [r7, #12]
80042ba: 2208 movs r2, #8
80042bc: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
80042c0: 68fb ldr r3, [r7, #12]
80042c2: 2200 movs r2, #0
80042c4: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_ERROR;
80042c8: 2301 movs r3, #1
80042ca: e029 b.n 8004320 <UART_WaitOnFlagUntilTimeout+0xd2>
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
80042cc: 68fb ldr r3, [r7, #12]
80042ce: 681b ldr r3, [r3, #0]
80042d0: 69db ldr r3, [r3, #28]
80042d2: f403 6300 and.w r3, r3, #2048 @ 0x800
80042d6: f5b3 6f00 cmp.w r3, #2048 @ 0x800
80042da: d111 bne.n 8004300 <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
80042dc: 68fb ldr r3, [r7, #12]
80042de: 681b ldr r3, [r3, #0]
80042e0: f44f 6200 mov.w r2, #2048 @ 0x800
80042e4: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
80042e6: 68f8 ldr r0, [r7, #12]
80042e8: f000 f81e bl 8004328 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
80042ec: 68fb ldr r3, [r7, #12]
80042ee: 2220 movs r2, #32
80042f0: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
80042f4: 68fb ldr r3, [r7, #12]
80042f6: 2200 movs r2, #0
80042f8: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_TIMEOUT;
80042fc: 2303 movs r3, #3
80042fe: e00f b.n 8004320 <UART_WaitOnFlagUntilTimeout+0xd2>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8004300: 68fb ldr r3, [r7, #12]
8004302: 681b ldr r3, [r3, #0]
8004304: 69da ldr r2, [r3, #28]
8004306: 68bb ldr r3, [r7, #8]
8004308: 4013 ands r3, r2
800430a: 68ba ldr r2, [r7, #8]
800430c: 429a cmp r2, r3
800430e: bf0c ite eq
8004310: 2301 moveq r3, #1
8004312: 2300 movne r3, #0
8004314: b2db uxtb r3, r3
8004316: 461a mov r2, r3
8004318: 79fb ldrb r3, [r7, #7]
800431a: 429a cmp r2, r3
800431c: d0a0 beq.n 8004260 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
800431e: 2300 movs r3, #0
}
8004320: 4618 mov r0, r3
8004322: 3710 adds r7, #16
8004324: 46bd mov sp, r7
8004326: bd80 pop {r7, pc}
08004328 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8004328: b480 push {r7}
800432a: b095 sub sp, #84 @ 0x54
800432c: af00 add r7, sp, #0
800432e: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8004330: 687b ldr r3, [r7, #4]
8004332: 681b ldr r3, [r3, #0]
8004334: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004336: 6b7b ldr r3, [r7, #52] @ 0x34
8004338: e853 3f00 ldrex r3, [r3]
800433c: 633b str r3, [r7, #48] @ 0x30
return(result);
800433e: 6b3b ldr r3, [r7, #48] @ 0x30
8004340: f423 7390 bic.w r3, r3, #288 @ 0x120
8004344: 64fb str r3, [r7, #76] @ 0x4c
8004346: 687b ldr r3, [r7, #4]
8004348: 681b ldr r3, [r3, #0]
800434a: 461a mov r2, r3
800434c: 6cfb ldr r3, [r7, #76] @ 0x4c
800434e: 643b str r3, [r7, #64] @ 0x40
8004350: 63fa str r2, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004352: 6bf9 ldr r1, [r7, #60] @ 0x3c
8004354: 6c3a ldr r2, [r7, #64] @ 0x40
8004356: e841 2300 strex r3, r2, [r1]
800435a: 63bb str r3, [r7, #56] @ 0x38
return(result);
800435c: 6bbb ldr r3, [r7, #56] @ 0x38
800435e: 2b00 cmp r3, #0
8004360: d1e6 bne.n 8004330 <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004362: 687b ldr r3, [r7, #4]
8004364: 681b ldr r3, [r3, #0]
8004366: 3308 adds r3, #8
8004368: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800436a: 6a3b ldr r3, [r7, #32]
800436c: e853 3f00 ldrex r3, [r3]
8004370: 61fb str r3, [r7, #28]
return(result);
8004372: 69fb ldr r3, [r7, #28]
8004374: f023 0301 bic.w r3, r3, #1
8004378: 64bb str r3, [r7, #72] @ 0x48
800437a: 687b ldr r3, [r7, #4]
800437c: 681b ldr r3, [r3, #0]
800437e: 3308 adds r3, #8
8004380: 6cba ldr r2, [r7, #72] @ 0x48
8004382: 62fa str r2, [r7, #44] @ 0x2c
8004384: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004386: 6ab9 ldr r1, [r7, #40] @ 0x28
8004388: 6afa ldr r2, [r7, #44] @ 0x2c
800438a: e841 2300 strex r3, r2, [r1]
800438e: 627b str r3, [r7, #36] @ 0x24
return(result);
8004390: 6a7b ldr r3, [r7, #36] @ 0x24
8004392: 2b00 cmp r3, #0
8004394: d1e5 bne.n 8004362 <UART_EndRxTransfer+0x3a>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8004396: 687b ldr r3, [r7, #4]
8004398: 6e1b ldr r3, [r3, #96] @ 0x60
800439a: 2b01 cmp r3, #1
800439c: d118 bne.n 80043d0 <UART_EndRxTransfer+0xa8>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800439e: 687b ldr r3, [r7, #4]
80043a0: 681b ldr r3, [r3, #0]
80043a2: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80043a4: 68fb ldr r3, [r7, #12]
80043a6: e853 3f00 ldrex r3, [r3]
80043aa: 60bb str r3, [r7, #8]
return(result);
80043ac: 68bb ldr r3, [r7, #8]
80043ae: f023 0310 bic.w r3, r3, #16
80043b2: 647b str r3, [r7, #68] @ 0x44
80043b4: 687b ldr r3, [r7, #4]
80043b6: 681b ldr r3, [r3, #0]
80043b8: 461a mov r2, r3
80043ba: 6c7b ldr r3, [r7, #68] @ 0x44
80043bc: 61bb str r3, [r7, #24]
80043be: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80043c0: 6979 ldr r1, [r7, #20]
80043c2: 69ba ldr r2, [r7, #24]
80043c4: e841 2300 strex r3, r2, [r1]
80043c8: 613b str r3, [r7, #16]
return(result);
80043ca: 693b ldr r3, [r7, #16]
80043cc: 2b00 cmp r3, #0
80043ce: d1e6 bne.n 800439e <UART_EndRxTransfer+0x76>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80043d0: 687b ldr r3, [r7, #4]
80043d2: 2220 movs r2, #32
80043d4: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80043d8: 687b ldr r3, [r7, #4]
80043da: 2200 movs r2, #0
80043dc: 661a str r2, [r3, #96] @ 0x60
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
80043de: 687b ldr r3, [r7, #4]
80043e0: 2200 movs r2, #0
80043e2: 669a str r2, [r3, #104] @ 0x68
}
80043e4: bf00 nop
80043e6: 3754 adds r7, #84 @ 0x54
80043e8: 46bd mov sp, r7
80043ea: f85d 7b04 ldr.w r7, [sp], #4
80043ee: 4770 bx lr
080043f0 <FMC_NORSRAM_Init>:
* @param Init Pointer to NORSRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
const FMC_NORSRAM_InitTypeDef *Init)
{
80043f0: b480 push {r7}
80043f2: b087 sub sp, #28
80043f4: af00 add r7, sp, #0
80043f6: 6078 str r0, [r7, #4]
80043f8: 6039 str r1, [r7, #0]
assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
assert_param(IS_FMC_PAGESIZE(Init->PageSize));
/* Disable NORSRAM Device */
__FMC_NORSRAM_DISABLE(Device, Init->NSBank);
80043fa: 683b ldr r3, [r7, #0]
80043fc: 681a ldr r2, [r3, #0]
80043fe: 687b ldr r3, [r7, #4]
8004400: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8004404: 683a ldr r2, [r7, #0]
8004406: 6812 ldr r2, [r2, #0]
8004408: f023 0101 bic.w r1, r3, #1
800440c: 687b ldr r3, [r7, #4]
800440e: f843 1022 str.w r1, [r3, r2, lsl #2]
/* Set NORSRAM device control parameters */
if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
8004412: 683b ldr r3, [r7, #0]
8004414: 689b ldr r3, [r3, #8]
8004416: 2b08 cmp r3, #8
8004418: d102 bne.n 8004420 <FMC_NORSRAM_Init+0x30>
{
flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
800441a: 2340 movs r3, #64 @ 0x40
800441c: 617b str r3, [r7, #20]
800441e: e001 b.n 8004424 <FMC_NORSRAM_Init+0x34>
}
else
{
flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
8004420: 2300 movs r3, #0
8004422: 617b str r3, [r7, #20]
}
btcr_reg = (flashaccess | \
Init->DataAddressMux | \
8004424: 683b ldr r3, [r7, #0]
8004426: 685a ldr r2, [r3, #4]
btcr_reg = (flashaccess | \
8004428: 697b ldr r3, [r7, #20]
800442a: 431a orrs r2, r3
Init->MemoryType | \
800442c: 683b ldr r3, [r7, #0]
800442e: 689b ldr r3, [r3, #8]
Init->DataAddressMux | \
8004430: 431a orrs r2, r3
Init->MemoryDataWidth | \
8004432: 683b ldr r3, [r7, #0]
8004434: 68db ldr r3, [r3, #12]
Init->MemoryType | \
8004436: 431a orrs r2, r3
Init->BurstAccessMode | \
8004438: 683b ldr r3, [r7, #0]
800443a: 691b ldr r3, [r3, #16]
Init->MemoryDataWidth | \
800443c: 431a orrs r2, r3
Init->WaitSignalPolarity | \
800443e: 683b ldr r3, [r7, #0]
8004440: 695b ldr r3, [r3, #20]
Init->BurstAccessMode | \
8004442: 431a orrs r2, r3
Init->WaitSignalActive | \
8004444: 683b ldr r3, [r7, #0]
8004446: 699b ldr r3, [r3, #24]
Init->WaitSignalPolarity | \
8004448: 431a orrs r2, r3
Init->WriteOperation | \
800444a: 683b ldr r3, [r7, #0]
800444c: 69db ldr r3, [r3, #28]
Init->WaitSignalActive | \
800444e: 431a orrs r2, r3
Init->WaitSignal | \
8004450: 683b ldr r3, [r7, #0]
8004452: 6a1b ldr r3, [r3, #32]
Init->WriteOperation | \
8004454: 431a orrs r2, r3
Init->ExtendedMode | \
8004456: 683b ldr r3, [r7, #0]
8004458: 6a5b ldr r3, [r3, #36] @ 0x24
Init->WaitSignal | \
800445a: 431a orrs r2, r3
Init->AsynchronousWait | \
800445c: 683b ldr r3, [r7, #0]
800445e: 6a9b ldr r3, [r3, #40] @ 0x28
Init->ExtendedMode | \
8004460: 431a orrs r2, r3
Init->WriteBurst);
8004462: 683b ldr r3, [r7, #0]
8004464: 6adb ldr r3, [r3, #44] @ 0x2c
btcr_reg = (flashaccess | \
8004466: 4313 orrs r3, r2
8004468: 613b str r3, [r7, #16]
btcr_reg |= Init->ContinuousClock;
800446a: 683b ldr r3, [r7, #0]
800446c: 6b1b ldr r3, [r3, #48] @ 0x30
800446e: 693a ldr r2, [r7, #16]
8004470: 4313 orrs r3, r2
8004472: 613b str r3, [r7, #16]
btcr_reg |= Init->WriteFifo;
8004474: 683b ldr r3, [r7, #0]
8004476: 6b5b ldr r3, [r3, #52] @ 0x34
8004478: 693a ldr r2, [r7, #16]
800447a: 4313 orrs r3, r2
800447c: 613b str r3, [r7, #16]
btcr_reg |= Init->PageSize;
800447e: 683b ldr r3, [r7, #0]
8004480: 6b9b ldr r3, [r3, #56] @ 0x38
8004482: 693a ldr r2, [r7, #16]
8004484: 4313 orrs r3, r2
8004486: 613b str r3, [r7, #16]
mask = (FMC_BCR1_MBKEN |
8004488: 4b20 ldr r3, [pc, #128] @ (800450c <FMC_NORSRAM_Init+0x11c>)
800448a: 60fb str r3, [r7, #12]
FMC_BCR1_WAITEN |
FMC_BCR1_EXTMOD |
FMC_BCR1_ASYNCWAIT |
FMC_BCR1_CBURSTRW);
mask |= FMC_BCR1_CCLKEN;
800448c: 68fb ldr r3, [r7, #12]
800448e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8004492: 60fb str r3, [r7, #12]
mask |= FMC_BCR1_WFDIS;
8004494: 68fb ldr r3, [r7, #12]
8004496: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
800449a: 60fb str r3, [r7, #12]
mask |= FMC_BCR1_CPSIZE;
800449c: 68fb ldr r3, [r7, #12]
800449e: f443 23e0 orr.w r3, r3, #458752 @ 0x70000
80044a2: 60fb str r3, [r7, #12]
MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
80044a4: 683b ldr r3, [r7, #0]
80044a6: 681a ldr r2, [r3, #0]
80044a8: 687b ldr r3, [r7, #4]
80044aa: f853 2022 ldr.w r2, [r3, r2, lsl #2]
80044ae: 68fb ldr r3, [r7, #12]
80044b0: 43db mvns r3, r3
80044b2: ea02 0103 and.w r1, r2, r3
80044b6: 683b ldr r3, [r7, #0]
80044b8: 681a ldr r2, [r3, #0]
80044ba: 693b ldr r3, [r7, #16]
80044bc: 4319 orrs r1, r3
80044be: 687b ldr r3, [r7, #4]
80044c0: f843 1022 str.w r1, [r3, r2, lsl #2]
/* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
80044c4: 683b ldr r3, [r7, #0]
80044c6: 6b1b ldr r3, [r3, #48] @ 0x30
80044c8: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
80044cc: d10c bne.n 80044e8 <FMC_NORSRAM_Init+0xf8>
80044ce: 683b ldr r3, [r7, #0]
80044d0: 681b ldr r3, [r3, #0]
80044d2: 2b00 cmp r3, #0
80044d4: d008 beq.n 80044e8 <FMC_NORSRAM_Init+0xf8>
{
MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
80044d6: 687b ldr r3, [r7, #4]
80044d8: 681b ldr r3, [r3, #0]
80044da: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
80044de: 683b ldr r3, [r7, #0]
80044e0: 6b1b ldr r3, [r3, #48] @ 0x30
80044e2: 431a orrs r2, r3
80044e4: 687b ldr r3, [r7, #4]
80044e6: 601a str r2, [r3, #0]
}
if (Init->NSBank != FMC_NORSRAM_BANK1)
80044e8: 683b ldr r3, [r7, #0]
80044ea: 681b ldr r3, [r3, #0]
80044ec: 2b00 cmp r3, #0
80044ee: d006 beq.n 80044fe <FMC_NORSRAM_Init+0x10e>
{
/* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
80044f0: 687b ldr r3, [r7, #4]
80044f2: 681a ldr r2, [r3, #0]
80044f4: 683b ldr r3, [r7, #0]
80044f6: 6b5b ldr r3, [r3, #52] @ 0x34
80044f8: 431a orrs r2, r3
80044fa: 687b ldr r3, [r7, #4]
80044fc: 601a str r2, [r3, #0]
}
return HAL_OK;
80044fe: 2300 movs r3, #0
}
8004500: 4618 mov r0, r3
8004502: 371c adds r7, #28
8004504: 46bd mov sp, r7
8004506: f85d 7b04 ldr.w r7, [sp], #4
800450a: 4770 bx lr
800450c: 0008fb7f .word 0x0008fb7f
08004510 <FMC_NORSRAM_Timing_Init>:
* @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
{
8004510: b480 push {r7}
8004512: b087 sub sp, #28
8004514: af00 add r7, sp, #0
8004516: 60f8 str r0, [r7, #12]
8004518: 60b9 str r1, [r7, #8]
800451a: 607a str r2, [r7, #4]
assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
/* Set FMC_NORSRAM device timing parameters */
Device->BTCR[Bank + 1U] =
(Timing->AddressSetupTime << FMC_BTR1_ADDSET_Pos) |
800451c: 68bb ldr r3, [r7, #8]
800451e: 681a ldr r2, [r3, #0]
(Timing->AddressHoldTime << FMC_BTR1_ADDHLD_Pos) |
8004520: 68bb ldr r3, [r7, #8]
8004522: 685b ldr r3, [r3, #4]
8004524: 011b lsls r3, r3, #4
(Timing->AddressSetupTime << FMC_BTR1_ADDSET_Pos) |
8004526: 431a orrs r2, r3
(Timing->DataSetupTime << FMC_BTR1_DATAST_Pos) |
8004528: 68bb ldr r3, [r7, #8]
800452a: 689b ldr r3, [r3, #8]
800452c: 021b lsls r3, r3, #8
(Timing->AddressHoldTime << FMC_BTR1_ADDHLD_Pos) |
800452e: 431a orrs r2, r3
(Timing->BusTurnAroundDuration << FMC_BTR1_BUSTURN_Pos) |
8004530: 68bb ldr r3, [r7, #8]
8004532: 68db ldr r3, [r3, #12]
8004534: 041b lsls r3, r3, #16
(Timing->DataSetupTime << FMC_BTR1_DATAST_Pos) |
8004536: 431a orrs r2, r3
((Timing->CLKDivision - 1U) << FMC_BTR1_CLKDIV_Pos) |
8004538: 68bb ldr r3, [r7, #8]
800453a: 691b ldr r3, [r3, #16]
800453c: 3b01 subs r3, #1
800453e: 051b lsls r3, r3, #20
(Timing->BusTurnAroundDuration << FMC_BTR1_BUSTURN_Pos) |
8004540: 431a orrs r2, r3
((Timing->DataLatency - 2U) << FMC_BTR1_DATLAT_Pos) |
8004542: 68bb ldr r3, [r7, #8]
8004544: 695b ldr r3, [r3, #20]
8004546: 3b02 subs r3, #2
8004548: 061b lsls r3, r3, #24
((Timing->CLKDivision - 1U) << FMC_BTR1_CLKDIV_Pos) |
800454a: ea42 0103 orr.w r1, r2, r3
Timing->AccessMode;
800454e: 68bb ldr r3, [r7, #8]
8004550: 699b ldr r3, [r3, #24]
Device->BTCR[Bank + 1U] =
8004552: 687a ldr r2, [r7, #4]
8004554: 3201 adds r2, #1
((Timing->DataLatency - 2U) << FMC_BTR1_DATLAT_Pos) |
8004556: 4319 orrs r1, r3
Device->BTCR[Bank + 1U] =
8004558: 68fb ldr r3, [r7, #12]
800455a: f843 1022 str.w r1, [r3, r2, lsl #2]
/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
800455e: 68fb ldr r3, [r7, #12]
8004560: 681b ldr r3, [r3, #0]
8004562: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8004566: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
800456a: d113 bne.n 8004594 <FMC_NORSRAM_Timing_Init+0x84>
{
tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos));
800456c: 68fb ldr r3, [r7, #12]
800456e: 685b ldr r3, [r3, #4]
8004570: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
8004574: 617b str r3, [r7, #20]
tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos);
8004576: 68bb ldr r3, [r7, #8]
8004578: 691b ldr r3, [r3, #16]
800457a: 3b01 subs r3, #1
800457c: 051b lsls r3, r3, #20
800457e: 697a ldr r2, [r7, #20]
8004580: 4313 orrs r3, r2
8004582: 617b str r3, [r7, #20]
MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr);
8004584: 68fb ldr r3, [r7, #12]
8004586: 685b ldr r3, [r3, #4]
8004588: f423 0270 bic.w r2, r3, #15728640 @ 0xf00000
800458c: 697b ldr r3, [r7, #20]
800458e: 431a orrs r2, r3
8004590: 68fb ldr r3, [r7, #12]
8004592: 605a str r2, [r3, #4]
}
return HAL_OK;
8004594: 2300 movs r3, #0
}
8004596: 4618 mov r0, r3
8004598: 371c adds r7, #28
800459a: 46bd mov sp, r7
800459c: f85d 7b04 ldr.w r7, [sp], #4
80045a0: 4770 bx lr
...
080045a4 <FMC_NORSRAM_Extended_Timing_Init>:
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
uint32_t ExtendedMode)
{
80045a4: b480 push {r7}
80045a6: b085 sub sp, #20
80045a8: af00 add r7, sp, #0
80045aa: 60f8 str r0, [r7, #12]
80045ac: 60b9 str r1, [r7, #8]
80045ae: 607a str r2, [r7, #4]
80045b0: 603b str r3, [r7, #0]
/* Check the parameters */
assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
80045b2: 683b ldr r3, [r7, #0]
80045b4: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
80045b8: d11d bne.n 80045f6 <FMC_NORSRAM_Extended_Timing_Init+0x52>
assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
80045ba: 68fb ldr r3, [r7, #12]
80045bc: 687a ldr r2, [r7, #4]
80045be: f853 2022 ldr.w r2, [r3, r2, lsl #2]
80045c2: 4b13 ldr r3, [pc, #76] @ (8004610 <FMC_NORSRAM_Extended_Timing_Init+0x6c>)
80045c4: 4013 ands r3, r2
80045c6: 68ba ldr r2, [r7, #8]
80045c8: 6811 ldr r1, [r2, #0]
80045ca: 68ba ldr r2, [r7, #8]
80045cc: 6852 ldr r2, [r2, #4]
80045ce: 0112 lsls r2, r2, #4
80045d0: 4311 orrs r1, r2
80045d2: 68ba ldr r2, [r7, #8]
80045d4: 6892 ldr r2, [r2, #8]
80045d6: 0212 lsls r2, r2, #8
80045d8: 4311 orrs r1, r2
80045da: 68ba ldr r2, [r7, #8]
80045dc: 6992 ldr r2, [r2, #24]
80045de: 4311 orrs r1, r2
80045e0: 68ba ldr r2, [r7, #8]
80045e2: 68d2 ldr r2, [r2, #12]
80045e4: 0412 lsls r2, r2, #16
80045e6: 430a orrs r2, r1
80045e8: ea43 0102 orr.w r1, r3, r2
80045ec: 68fb ldr r3, [r7, #12]
80045ee: 687a ldr r2, [r7, #4]
80045f0: f843 1022 str.w r1, [r3, r2, lsl #2]
80045f4: e005 b.n 8004602 <FMC_NORSRAM_Extended_Timing_Init+0x5e>
Timing->AccessMode |
((Timing->BusTurnAroundDuration) << FMC_BWTR1_BUSTURN_Pos)));
}
else
{
Device->BWTR[Bank] = 0x0FFFFFFFU;
80045f6: 68fb ldr r3, [r7, #12]
80045f8: 687a ldr r2, [r7, #4]
80045fa: f06f 4170 mvn.w r1, #4026531840 @ 0xf0000000
80045fe: f843 1022 str.w r1, [r3, r2, lsl #2]
}
return HAL_OK;
8004602: 2300 movs r3, #0
}
8004604: 4618 mov r0, r3
8004606: 3714 adds r7, #20
8004608: 46bd mov sp, r7
800460a: f85d 7b04 ldr.w r7, [sp], #4
800460e: 4770 bx lr
8004610: cff00000 .word 0xcff00000
08004614 <std>:
8004614: 2300 movs r3, #0
8004616: b510 push {r4, lr}
8004618: 4604 mov r4, r0
800461a: e9c0 3300 strd r3, r3, [r0]
800461e: e9c0 3304 strd r3, r3, [r0, #16]
8004622: 6083 str r3, [r0, #8]
8004624: 8181 strh r1, [r0, #12]
8004626: 6643 str r3, [r0, #100] @ 0x64
8004628: 81c2 strh r2, [r0, #14]
800462a: 6183 str r3, [r0, #24]
800462c: 4619 mov r1, r3
800462e: 2208 movs r2, #8
8004630: 305c adds r0, #92 @ 0x5c
8004632: f000 f906 bl 8004842 <memset>
8004636: 4b0d ldr r3, [pc, #52] @ (800466c <std+0x58>)
8004638: 6263 str r3, [r4, #36] @ 0x24
800463a: 4b0d ldr r3, [pc, #52] @ (8004670 <std+0x5c>)
800463c: 62a3 str r3, [r4, #40] @ 0x28
800463e: 4b0d ldr r3, [pc, #52] @ (8004674 <std+0x60>)
8004640: 62e3 str r3, [r4, #44] @ 0x2c
8004642: 4b0d ldr r3, [pc, #52] @ (8004678 <std+0x64>)
8004644: 6323 str r3, [r4, #48] @ 0x30
8004646: 4b0d ldr r3, [pc, #52] @ (800467c <std+0x68>)
8004648: 6224 str r4, [r4, #32]
800464a: 429c cmp r4, r3
800464c: d006 beq.n 800465c <std+0x48>
800464e: f103 0268 add.w r2, r3, #104 @ 0x68
8004652: 4294 cmp r4, r2
8004654: d002 beq.n 800465c <std+0x48>
8004656: 33d0 adds r3, #208 @ 0xd0
8004658: 429c cmp r4, r3
800465a: d105 bne.n 8004668 <std+0x54>
800465c: f104 0058 add.w r0, r4, #88 @ 0x58
8004660: e8bd 4010 ldmia.w sp!, {r4, lr}
8004664: f000 b966 b.w 8004934 <__retarget_lock_init_recursive>
8004668: bd10 pop {r4, pc}
800466a: bf00 nop
800466c: 080047bd .word 0x080047bd
8004670: 080047df .word 0x080047df
8004674: 08004817 .word 0x08004817
8004678: 0800483b .word 0x0800483b
800467c: 20000204 .word 0x20000204
08004680 <stdio_exit_handler>:
8004680: 4a02 ldr r2, [pc, #8] @ (800468c <stdio_exit_handler+0xc>)
8004682: 4903 ldr r1, [pc, #12] @ (8004690 <stdio_exit_handler+0x10>)
8004684: 4803 ldr r0, [pc, #12] @ (8004694 <stdio_exit_handler+0x14>)
8004686: f000 b869 b.w 800475c <_fwalk_sglue>
800468a: bf00 nop
800468c: 2000000c .word 0x2000000c
8004690: 080051d1 .word 0x080051d1
8004694: 2000001c .word 0x2000001c
08004698 <cleanup_stdio>:
8004698: 6841 ldr r1, [r0, #4]
800469a: 4b0c ldr r3, [pc, #48] @ (80046cc <cleanup_stdio+0x34>)
800469c: 4299 cmp r1, r3
800469e: b510 push {r4, lr}
80046a0: 4604 mov r4, r0
80046a2: d001 beq.n 80046a8 <cleanup_stdio+0x10>
80046a4: f000 fd94 bl 80051d0 <_fflush_r>
80046a8: 68a1 ldr r1, [r4, #8]
80046aa: 4b09 ldr r3, [pc, #36] @ (80046d0 <cleanup_stdio+0x38>)
80046ac: 4299 cmp r1, r3
80046ae: d002 beq.n 80046b6 <cleanup_stdio+0x1e>
80046b0: 4620 mov r0, r4
80046b2: f000 fd8d bl 80051d0 <_fflush_r>
80046b6: 68e1 ldr r1, [r4, #12]
80046b8: 4b06 ldr r3, [pc, #24] @ (80046d4 <cleanup_stdio+0x3c>)
80046ba: 4299 cmp r1, r3
80046bc: d004 beq.n 80046c8 <cleanup_stdio+0x30>
80046be: 4620 mov r0, r4
80046c0: e8bd 4010 ldmia.w sp!, {r4, lr}
80046c4: f000 bd84 b.w 80051d0 <_fflush_r>
80046c8: bd10 pop {r4, pc}
80046ca: bf00 nop
80046cc: 20000204 .word 0x20000204
80046d0: 2000026c .word 0x2000026c
80046d4: 200002d4 .word 0x200002d4
080046d8 <global_stdio_init.part.0>:
80046d8: b510 push {r4, lr}
80046da: 4b0b ldr r3, [pc, #44] @ (8004708 <global_stdio_init.part.0+0x30>)
80046dc: 4c0b ldr r4, [pc, #44] @ (800470c <global_stdio_init.part.0+0x34>)
80046de: 4a0c ldr r2, [pc, #48] @ (8004710 <global_stdio_init.part.0+0x38>)
80046e0: 601a str r2, [r3, #0]
80046e2: 4620 mov r0, r4
80046e4: 2200 movs r2, #0
80046e6: 2104 movs r1, #4
80046e8: f7ff ff94 bl 8004614 <std>
80046ec: f104 0068 add.w r0, r4, #104 @ 0x68
80046f0: 2201 movs r2, #1
80046f2: 2109 movs r1, #9
80046f4: f7ff ff8e bl 8004614 <std>
80046f8: f104 00d0 add.w r0, r4, #208 @ 0xd0
80046fc: 2202 movs r2, #2
80046fe: e8bd 4010 ldmia.w sp!, {r4, lr}
8004702: 2112 movs r1, #18
8004704: f7ff bf86 b.w 8004614 <std>
8004708: 2000033c .word 0x2000033c
800470c: 20000204 .word 0x20000204
8004710: 08004681 .word 0x08004681
08004714 <__sfp_lock_acquire>:
8004714: 4801 ldr r0, [pc, #4] @ (800471c <__sfp_lock_acquire+0x8>)
8004716: f000 b90e b.w 8004936 <__retarget_lock_acquire_recursive>
800471a: bf00 nop
800471c: 20000345 .word 0x20000345
08004720 <__sfp_lock_release>:
8004720: 4801 ldr r0, [pc, #4] @ (8004728 <__sfp_lock_release+0x8>)
8004722: f000 b909 b.w 8004938 <__retarget_lock_release_recursive>
8004726: bf00 nop
8004728: 20000345 .word 0x20000345
0800472c <__sinit>:
800472c: b510 push {r4, lr}
800472e: 4604 mov r4, r0
8004730: f7ff fff0 bl 8004714 <__sfp_lock_acquire>
8004734: 6a23 ldr r3, [r4, #32]
8004736: b11b cbz r3, 8004740 <__sinit+0x14>
8004738: e8bd 4010 ldmia.w sp!, {r4, lr}
800473c: f7ff bff0 b.w 8004720 <__sfp_lock_release>
8004740: 4b04 ldr r3, [pc, #16] @ (8004754 <__sinit+0x28>)
8004742: 6223 str r3, [r4, #32]
8004744: 4b04 ldr r3, [pc, #16] @ (8004758 <__sinit+0x2c>)
8004746: 681b ldr r3, [r3, #0]
8004748: 2b00 cmp r3, #0
800474a: d1f5 bne.n 8004738 <__sinit+0xc>
800474c: f7ff ffc4 bl 80046d8 <global_stdio_init.part.0>
8004750: e7f2 b.n 8004738 <__sinit+0xc>
8004752: bf00 nop
8004754: 08004699 .word 0x08004699
8004758: 2000033c .word 0x2000033c
0800475c <_fwalk_sglue>:
800475c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
8004760: 4607 mov r7, r0
8004762: 4688 mov r8, r1
8004764: 4614 mov r4, r2
8004766: 2600 movs r6, #0
8004768: e9d4 9501 ldrd r9, r5, [r4, #4]
800476c: f1b9 0901 subs.w r9, r9, #1
8004770: d505 bpl.n 800477e <_fwalk_sglue+0x22>
8004772: 6824 ldr r4, [r4, #0]
8004774: 2c00 cmp r4, #0
8004776: d1f7 bne.n 8004768 <_fwalk_sglue+0xc>
8004778: 4630 mov r0, r6
800477a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
800477e: 89ab ldrh r3, [r5, #12]
8004780: 2b01 cmp r3, #1
8004782: d907 bls.n 8004794 <_fwalk_sglue+0x38>
8004784: f9b5 300e ldrsh.w r3, [r5, #14]
8004788: 3301 adds r3, #1
800478a: d003 beq.n 8004794 <_fwalk_sglue+0x38>
800478c: 4629 mov r1, r5
800478e: 4638 mov r0, r7
8004790: 47c0 blx r8
8004792: 4306 orrs r6, r0
8004794: 3568 adds r5, #104 @ 0x68
8004796: e7e9 b.n 800476c <_fwalk_sglue+0x10>
08004798 <iprintf>:
8004798: b40f push {r0, r1, r2, r3}
800479a: b507 push {r0, r1, r2, lr}
800479c: 4906 ldr r1, [pc, #24] @ (80047b8 <iprintf+0x20>)
800479e: ab04 add r3, sp, #16
80047a0: 6808 ldr r0, [r1, #0]
80047a2: f853 2b04 ldr.w r2, [r3], #4
80047a6: 6881 ldr r1, [r0, #8]
80047a8: 9301 str r3, [sp, #4]
80047aa: f000 f9e9 bl 8004b80 <_vfiprintf_r>
80047ae: b003 add sp, #12
80047b0: f85d eb04 ldr.w lr, [sp], #4
80047b4: b004 add sp, #16
80047b6: 4770 bx lr
80047b8: 20000018 .word 0x20000018
080047bc <__sread>:
80047bc: b510 push {r4, lr}
80047be: 460c mov r4, r1
80047c0: f9b1 100e ldrsh.w r1, [r1, #14]
80047c4: f000 f868 bl 8004898 <_read_r>
80047c8: 2800 cmp r0, #0
80047ca: bfab itete ge
80047cc: 6d63 ldrge r3, [r4, #84] @ 0x54
80047ce: 89a3 ldrhlt r3, [r4, #12]
80047d0: 181b addge r3, r3, r0
80047d2: f423 5380 biclt.w r3, r3, #4096 @ 0x1000
80047d6: bfac ite ge
80047d8: 6563 strge r3, [r4, #84] @ 0x54
80047da: 81a3 strhlt r3, [r4, #12]
80047dc: bd10 pop {r4, pc}
080047de <__swrite>:
80047de: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
80047e2: 461f mov r7, r3
80047e4: 898b ldrh r3, [r1, #12]
80047e6: 05db lsls r3, r3, #23
80047e8: 4605 mov r5, r0
80047ea: 460c mov r4, r1
80047ec: 4616 mov r6, r2
80047ee: d505 bpl.n 80047fc <__swrite+0x1e>
80047f0: f9b1 100e ldrsh.w r1, [r1, #14]
80047f4: 2302 movs r3, #2
80047f6: 2200 movs r2, #0
80047f8: f000 f83c bl 8004874 <_lseek_r>
80047fc: 89a3 ldrh r3, [r4, #12]
80047fe: f9b4 100e ldrsh.w r1, [r4, #14]
8004802: f423 5380 bic.w r3, r3, #4096 @ 0x1000
8004806: 81a3 strh r3, [r4, #12]
8004808: 4632 mov r2, r6
800480a: 463b mov r3, r7
800480c: 4628 mov r0, r5
800480e: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
8004812: f000 b853 b.w 80048bc <_write_r>
08004816 <__sseek>:
8004816: b510 push {r4, lr}
8004818: 460c mov r4, r1
800481a: f9b1 100e ldrsh.w r1, [r1, #14]
800481e: f000 f829 bl 8004874 <_lseek_r>
8004822: 1c43 adds r3, r0, #1
8004824: 89a3 ldrh r3, [r4, #12]
8004826: bf15 itete ne
8004828: 6560 strne r0, [r4, #84] @ 0x54
800482a: f423 5380 biceq.w r3, r3, #4096 @ 0x1000
800482e: f443 5380 orrne.w r3, r3, #4096 @ 0x1000
8004832: 81a3 strheq r3, [r4, #12]
8004834: bf18 it ne
8004836: 81a3 strhne r3, [r4, #12]
8004838: bd10 pop {r4, pc}
0800483a <__sclose>:
800483a: f9b1 100e ldrsh.w r1, [r1, #14]
800483e: f000 b809 b.w 8004854 <_close_r>
08004842 <memset>:
8004842: 4402 add r2, r0
8004844: 4603 mov r3, r0
8004846: 4293 cmp r3, r2
8004848: d100 bne.n 800484c <memset+0xa>
800484a: 4770 bx lr
800484c: f803 1b01 strb.w r1, [r3], #1
8004850: e7f9 b.n 8004846 <memset+0x4>
...
08004854 <_close_r>:
8004854: b538 push {r3, r4, r5, lr}
8004856: 4d06 ldr r5, [pc, #24] @ (8004870 <_close_r+0x1c>)
8004858: 2300 movs r3, #0
800485a: 4604 mov r4, r0
800485c: 4608 mov r0, r1
800485e: 602b str r3, [r5, #0]
8004860: f7fd f84f bl 8001902 <_close>
8004864: 1c43 adds r3, r0, #1
8004866: d102 bne.n 800486e <_close_r+0x1a>
8004868: 682b ldr r3, [r5, #0]
800486a: b103 cbz r3, 800486e <_close_r+0x1a>
800486c: 6023 str r3, [r4, #0]
800486e: bd38 pop {r3, r4, r5, pc}
8004870: 20000340 .word 0x20000340
08004874 <_lseek_r>:
8004874: b538 push {r3, r4, r5, lr}
8004876: 4d07 ldr r5, [pc, #28] @ (8004894 <_lseek_r+0x20>)
8004878: 4604 mov r4, r0
800487a: 4608 mov r0, r1
800487c: 4611 mov r1, r2
800487e: 2200 movs r2, #0
8004880: 602a str r2, [r5, #0]
8004882: 461a mov r2, r3
8004884: f7fd f864 bl 8001950 <_lseek>
8004888: 1c43 adds r3, r0, #1
800488a: d102 bne.n 8004892 <_lseek_r+0x1e>
800488c: 682b ldr r3, [r5, #0]
800488e: b103 cbz r3, 8004892 <_lseek_r+0x1e>
8004890: 6023 str r3, [r4, #0]
8004892: bd38 pop {r3, r4, r5, pc}
8004894: 20000340 .word 0x20000340
08004898 <_read_r>:
8004898: b538 push {r3, r4, r5, lr}
800489a: 4d07 ldr r5, [pc, #28] @ (80048b8 <_read_r+0x20>)
800489c: 4604 mov r4, r0
800489e: 4608 mov r0, r1
80048a0: 4611 mov r1, r2
80048a2: 2200 movs r2, #0
80048a4: 602a str r2, [r5, #0]
80048a6: 461a mov r2, r3
80048a8: f7fd f80e bl 80018c8 <_read>
80048ac: 1c43 adds r3, r0, #1
80048ae: d102 bne.n 80048b6 <_read_r+0x1e>
80048b0: 682b ldr r3, [r5, #0]
80048b2: b103 cbz r3, 80048b6 <_read_r+0x1e>
80048b4: 6023 str r3, [r4, #0]
80048b6: bd38 pop {r3, r4, r5, pc}
80048b8: 20000340 .word 0x20000340
080048bc <_write_r>:
80048bc: b538 push {r3, r4, r5, lr}
80048be: 4d07 ldr r5, [pc, #28] @ (80048dc <_write_r+0x20>)
80048c0: 4604 mov r4, r0
80048c2: 4608 mov r0, r1
80048c4: 4611 mov r1, r2
80048c6: 2200 movs r2, #0
80048c8: 602a str r2, [r5, #0]
80048ca: 461a mov r2, r3
80048cc: f7fc f862 bl 8000994 <_write>
80048d0: 1c43 adds r3, r0, #1
80048d2: d102 bne.n 80048da <_write_r+0x1e>
80048d4: 682b ldr r3, [r5, #0]
80048d6: b103 cbz r3, 80048da <_write_r+0x1e>
80048d8: 6023 str r3, [r4, #0]
80048da: bd38 pop {r3, r4, r5, pc}
80048dc: 20000340 .word 0x20000340
080048e0 <__errno>:
80048e0: 4b01 ldr r3, [pc, #4] @ (80048e8 <__errno+0x8>)
80048e2: 6818 ldr r0, [r3, #0]
80048e4: 4770 bx lr
80048e6: bf00 nop
80048e8: 20000018 .word 0x20000018
080048ec <__libc_init_array>:
80048ec: b570 push {r4, r5, r6, lr}
80048ee: 4d0d ldr r5, [pc, #52] @ (8004924 <__libc_init_array+0x38>)
80048f0: 4c0d ldr r4, [pc, #52] @ (8004928 <__libc_init_array+0x3c>)
80048f2: 1b64 subs r4, r4, r5
80048f4: 10a4 asrs r4, r4, #2
80048f6: 2600 movs r6, #0
80048f8: 42a6 cmp r6, r4
80048fa: d109 bne.n 8004910 <__libc_init_array+0x24>
80048fc: 4d0b ldr r5, [pc, #44] @ (800492c <__libc_init_array+0x40>)
80048fe: 4c0c ldr r4, [pc, #48] @ (8004930 <__libc_init_array+0x44>)
8004900: f000 fdb6 bl 8005470 <_init>
8004904: 1b64 subs r4, r4, r5
8004906: 10a4 asrs r4, r4, #2
8004908: 2600 movs r6, #0
800490a: 42a6 cmp r6, r4
800490c: d105 bne.n 800491a <__libc_init_array+0x2e>
800490e: bd70 pop {r4, r5, r6, pc}
8004910: f855 3b04 ldr.w r3, [r5], #4
8004914: 4798 blx r3
8004916: 3601 adds r6, #1
8004918: e7ee b.n 80048f8 <__libc_init_array+0xc>
800491a: f855 3b04 ldr.w r3, [r5], #4
800491e: 4798 blx r3
8004920: 3601 adds r6, #1
8004922: e7f2 b.n 800490a <__libc_init_array+0x1e>
8004924: 08005550 .word 0x08005550
8004928: 08005550 .word 0x08005550
800492c: 08005550 .word 0x08005550
8004930: 08005554 .word 0x08005554
08004934 <__retarget_lock_init_recursive>:
8004934: 4770 bx lr
08004936 <__retarget_lock_acquire_recursive>:
8004936: 4770 bx lr
08004938 <__retarget_lock_release_recursive>:
8004938: 4770 bx lr
...
0800493c <_free_r>:
800493c: b538 push {r3, r4, r5, lr}
800493e: 4605 mov r5, r0
8004940: 2900 cmp r1, #0
8004942: d041 beq.n 80049c8 <_free_r+0x8c>
8004944: f851 3c04 ldr.w r3, [r1, #-4]
8004948: 1f0c subs r4, r1, #4
800494a: 2b00 cmp r3, #0
800494c: bfb8 it lt
800494e: 18e4 addlt r4, r4, r3
8004950: f000 f8e0 bl 8004b14 <__malloc_lock>
8004954: 4a1d ldr r2, [pc, #116] @ (80049cc <_free_r+0x90>)
8004956: 6813 ldr r3, [r2, #0]
8004958: b933 cbnz r3, 8004968 <_free_r+0x2c>
800495a: 6063 str r3, [r4, #4]
800495c: 6014 str r4, [r2, #0]
800495e: 4628 mov r0, r5
8004960: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
8004964: f000 b8dc b.w 8004b20 <__malloc_unlock>
8004968: 42a3 cmp r3, r4
800496a: d908 bls.n 800497e <_free_r+0x42>
800496c: 6820 ldr r0, [r4, #0]
800496e: 1821 adds r1, r4, r0
8004970: 428b cmp r3, r1
8004972: bf01 itttt eq
8004974: 6819 ldreq r1, [r3, #0]
8004976: 685b ldreq r3, [r3, #4]
8004978: 1809 addeq r1, r1, r0
800497a: 6021 streq r1, [r4, #0]
800497c: e7ed b.n 800495a <_free_r+0x1e>
800497e: 461a mov r2, r3
8004980: 685b ldr r3, [r3, #4]
8004982: b10b cbz r3, 8004988 <_free_r+0x4c>
8004984: 42a3 cmp r3, r4
8004986: d9fa bls.n 800497e <_free_r+0x42>
8004988: 6811 ldr r1, [r2, #0]
800498a: 1850 adds r0, r2, r1
800498c: 42a0 cmp r0, r4
800498e: d10b bne.n 80049a8 <_free_r+0x6c>
8004990: 6820 ldr r0, [r4, #0]
8004992: 4401 add r1, r0
8004994: 1850 adds r0, r2, r1
8004996: 4283 cmp r3, r0
8004998: 6011 str r1, [r2, #0]
800499a: d1e0 bne.n 800495e <_free_r+0x22>
800499c: 6818 ldr r0, [r3, #0]
800499e: 685b ldr r3, [r3, #4]
80049a0: 6053 str r3, [r2, #4]
80049a2: 4408 add r0, r1
80049a4: 6010 str r0, [r2, #0]
80049a6: e7da b.n 800495e <_free_r+0x22>
80049a8: d902 bls.n 80049b0 <_free_r+0x74>
80049aa: 230c movs r3, #12
80049ac: 602b str r3, [r5, #0]
80049ae: e7d6 b.n 800495e <_free_r+0x22>
80049b0: 6820 ldr r0, [r4, #0]
80049b2: 1821 adds r1, r4, r0
80049b4: 428b cmp r3, r1
80049b6: bf04 itt eq
80049b8: 6819 ldreq r1, [r3, #0]
80049ba: 685b ldreq r3, [r3, #4]
80049bc: 6063 str r3, [r4, #4]
80049be: bf04 itt eq
80049c0: 1809 addeq r1, r1, r0
80049c2: 6021 streq r1, [r4, #0]
80049c4: 6054 str r4, [r2, #4]
80049c6: e7ca b.n 800495e <_free_r+0x22>
80049c8: bd38 pop {r3, r4, r5, pc}
80049ca: bf00 nop
80049cc: 2000034c .word 0x2000034c
080049d0 <sbrk_aligned>:
80049d0: b570 push {r4, r5, r6, lr}
80049d2: 4e0f ldr r6, [pc, #60] @ (8004a10 <sbrk_aligned+0x40>)
80049d4: 460c mov r4, r1
80049d6: 6831 ldr r1, [r6, #0]
80049d8: 4605 mov r5, r0
80049da: b911 cbnz r1, 80049e2 <sbrk_aligned+0x12>
80049dc: f000 fcb4 bl 8005348 <_sbrk_r>
80049e0: 6030 str r0, [r6, #0]
80049e2: 4621 mov r1, r4
80049e4: 4628 mov r0, r5
80049e6: f000 fcaf bl 8005348 <_sbrk_r>
80049ea: 1c43 adds r3, r0, #1
80049ec: d103 bne.n 80049f6 <sbrk_aligned+0x26>
80049ee: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff
80049f2: 4620 mov r0, r4
80049f4: bd70 pop {r4, r5, r6, pc}
80049f6: 1cc4 adds r4, r0, #3
80049f8: f024 0403 bic.w r4, r4, #3
80049fc: 42a0 cmp r0, r4
80049fe: d0f8 beq.n 80049f2 <sbrk_aligned+0x22>
8004a00: 1a21 subs r1, r4, r0
8004a02: 4628 mov r0, r5
8004a04: f000 fca0 bl 8005348 <_sbrk_r>
8004a08: 3001 adds r0, #1
8004a0a: d1f2 bne.n 80049f2 <sbrk_aligned+0x22>
8004a0c: e7ef b.n 80049ee <sbrk_aligned+0x1e>
8004a0e: bf00 nop
8004a10: 20000348 .word 0x20000348
08004a14 <_malloc_r>:
8004a14: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
8004a18: 1ccd adds r5, r1, #3
8004a1a: f025 0503 bic.w r5, r5, #3
8004a1e: 3508 adds r5, #8
8004a20: 2d0c cmp r5, #12
8004a22: bf38 it cc
8004a24: 250c movcc r5, #12
8004a26: 2d00 cmp r5, #0
8004a28: 4606 mov r6, r0
8004a2a: db01 blt.n 8004a30 <_malloc_r+0x1c>
8004a2c: 42a9 cmp r1, r5
8004a2e: d904 bls.n 8004a3a <_malloc_r+0x26>
8004a30: 230c movs r3, #12
8004a32: 6033 str r3, [r6, #0]
8004a34: 2000 movs r0, #0
8004a36: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
8004a3a: f8df 80d4 ldr.w r8, [pc, #212] @ 8004b10 <_malloc_r+0xfc>
8004a3e: f000 f869 bl 8004b14 <__malloc_lock>
8004a42: f8d8 3000 ldr.w r3, [r8]
8004a46: 461c mov r4, r3
8004a48: bb44 cbnz r4, 8004a9c <_malloc_r+0x88>
8004a4a: 4629 mov r1, r5
8004a4c: 4630 mov r0, r6
8004a4e: f7ff ffbf bl 80049d0 <sbrk_aligned>
8004a52: 1c43 adds r3, r0, #1
8004a54: 4604 mov r4, r0
8004a56: d158 bne.n 8004b0a <_malloc_r+0xf6>
8004a58: f8d8 4000 ldr.w r4, [r8]
8004a5c: 4627 mov r7, r4
8004a5e: 2f00 cmp r7, #0
8004a60: d143 bne.n 8004aea <_malloc_r+0xd6>
8004a62: 2c00 cmp r4, #0
8004a64: d04b beq.n 8004afe <_malloc_r+0xea>
8004a66: 6823 ldr r3, [r4, #0]
8004a68: 4639 mov r1, r7
8004a6a: 4630 mov r0, r6
8004a6c: eb04 0903 add.w r9, r4, r3
8004a70: f000 fc6a bl 8005348 <_sbrk_r>
8004a74: 4581 cmp r9, r0
8004a76: d142 bne.n 8004afe <_malloc_r+0xea>
8004a78: 6821 ldr r1, [r4, #0]
8004a7a: 1a6d subs r5, r5, r1
8004a7c: 4629 mov r1, r5
8004a7e: 4630 mov r0, r6
8004a80: f7ff ffa6 bl 80049d0 <sbrk_aligned>
8004a84: 3001 adds r0, #1
8004a86: d03a beq.n 8004afe <_malloc_r+0xea>
8004a88: 6823 ldr r3, [r4, #0]
8004a8a: 442b add r3, r5
8004a8c: 6023 str r3, [r4, #0]
8004a8e: f8d8 3000 ldr.w r3, [r8]
8004a92: 685a ldr r2, [r3, #4]
8004a94: bb62 cbnz r2, 8004af0 <_malloc_r+0xdc>
8004a96: f8c8 7000 str.w r7, [r8]
8004a9a: e00f b.n 8004abc <_malloc_r+0xa8>
8004a9c: 6822 ldr r2, [r4, #0]
8004a9e: 1b52 subs r2, r2, r5
8004aa0: d420 bmi.n 8004ae4 <_malloc_r+0xd0>
8004aa2: 2a0b cmp r2, #11
8004aa4: d917 bls.n 8004ad6 <_malloc_r+0xc2>
8004aa6: 1961 adds r1, r4, r5
8004aa8: 42a3 cmp r3, r4
8004aaa: 6025 str r5, [r4, #0]
8004aac: bf18 it ne
8004aae: 6059 strne r1, [r3, #4]
8004ab0: 6863 ldr r3, [r4, #4]
8004ab2: bf08 it eq
8004ab4: f8c8 1000 streq.w r1, [r8]
8004ab8: 5162 str r2, [r4, r5]
8004aba: 604b str r3, [r1, #4]
8004abc: 4630 mov r0, r6
8004abe: f000 f82f bl 8004b20 <__malloc_unlock>
8004ac2: f104 000b add.w r0, r4, #11
8004ac6: 1d23 adds r3, r4, #4
8004ac8: f020 0007 bic.w r0, r0, #7
8004acc: 1ac2 subs r2, r0, r3
8004ace: bf1c itt ne
8004ad0: 1a1b subne r3, r3, r0
8004ad2: 50a3 strne r3, [r4, r2]
8004ad4: e7af b.n 8004a36 <_malloc_r+0x22>
8004ad6: 6862 ldr r2, [r4, #4]
8004ad8: 42a3 cmp r3, r4
8004ada: bf0c ite eq
8004adc: f8c8 2000 streq.w r2, [r8]
8004ae0: 605a strne r2, [r3, #4]
8004ae2: e7eb b.n 8004abc <_malloc_r+0xa8>
8004ae4: 4623 mov r3, r4
8004ae6: 6864 ldr r4, [r4, #4]
8004ae8: e7ae b.n 8004a48 <_malloc_r+0x34>
8004aea: 463c mov r4, r7
8004aec: 687f ldr r7, [r7, #4]
8004aee: e7b6 b.n 8004a5e <_malloc_r+0x4a>
8004af0: 461a mov r2, r3
8004af2: 685b ldr r3, [r3, #4]
8004af4: 42a3 cmp r3, r4
8004af6: d1fb bne.n 8004af0 <_malloc_r+0xdc>
8004af8: 2300 movs r3, #0
8004afa: 6053 str r3, [r2, #4]
8004afc: e7de b.n 8004abc <_malloc_r+0xa8>
8004afe: 230c movs r3, #12
8004b00: 6033 str r3, [r6, #0]
8004b02: 4630 mov r0, r6
8004b04: f000 f80c bl 8004b20 <__malloc_unlock>
8004b08: e794 b.n 8004a34 <_malloc_r+0x20>
8004b0a: 6005 str r5, [r0, #0]
8004b0c: e7d6 b.n 8004abc <_malloc_r+0xa8>
8004b0e: bf00 nop
8004b10: 2000034c .word 0x2000034c
08004b14 <__malloc_lock>:
8004b14: 4801 ldr r0, [pc, #4] @ (8004b1c <__malloc_lock+0x8>)
8004b16: f7ff bf0e b.w 8004936 <__retarget_lock_acquire_recursive>
8004b1a: bf00 nop
8004b1c: 20000344 .word 0x20000344
08004b20 <__malloc_unlock>:
8004b20: 4801 ldr r0, [pc, #4] @ (8004b28 <__malloc_unlock+0x8>)
8004b22: f7ff bf09 b.w 8004938 <__retarget_lock_release_recursive>
8004b26: bf00 nop
8004b28: 20000344 .word 0x20000344
08004b2c <__sfputc_r>:
8004b2c: 6893 ldr r3, [r2, #8]
8004b2e: 3b01 subs r3, #1
8004b30: 2b00 cmp r3, #0
8004b32: b410 push {r4}
8004b34: 6093 str r3, [r2, #8]
8004b36: da08 bge.n 8004b4a <__sfputc_r+0x1e>
8004b38: 6994 ldr r4, [r2, #24]
8004b3a: 42a3 cmp r3, r4
8004b3c: db01 blt.n 8004b42 <__sfputc_r+0x16>
8004b3e: 290a cmp r1, #10
8004b40: d103 bne.n 8004b4a <__sfputc_r+0x1e>
8004b42: f85d 4b04 ldr.w r4, [sp], #4
8004b46: f000 bb6b b.w 8005220 <__swbuf_r>
8004b4a: 6813 ldr r3, [r2, #0]
8004b4c: 1c58 adds r0, r3, #1
8004b4e: 6010 str r0, [r2, #0]
8004b50: 7019 strb r1, [r3, #0]
8004b52: 4608 mov r0, r1
8004b54: f85d 4b04 ldr.w r4, [sp], #4
8004b58: 4770 bx lr
08004b5a <__sfputs_r>:
8004b5a: b5f8 push {r3, r4, r5, r6, r7, lr}
8004b5c: 4606 mov r6, r0
8004b5e: 460f mov r7, r1
8004b60: 4614 mov r4, r2
8004b62: 18d5 adds r5, r2, r3
8004b64: 42ac cmp r4, r5
8004b66: d101 bne.n 8004b6c <__sfputs_r+0x12>
8004b68: 2000 movs r0, #0
8004b6a: e007 b.n 8004b7c <__sfputs_r+0x22>
8004b6c: f814 1b01 ldrb.w r1, [r4], #1
8004b70: 463a mov r2, r7
8004b72: 4630 mov r0, r6
8004b74: f7ff ffda bl 8004b2c <__sfputc_r>
8004b78: 1c43 adds r3, r0, #1
8004b7a: d1f3 bne.n 8004b64 <__sfputs_r+0xa>
8004b7c: bdf8 pop {r3, r4, r5, r6, r7, pc}
...
08004b80 <_vfiprintf_r>:
8004b80: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8004b84: 460d mov r5, r1
8004b86: b09d sub sp, #116 @ 0x74
8004b88: 4614 mov r4, r2
8004b8a: 4698 mov r8, r3
8004b8c: 4606 mov r6, r0
8004b8e: b118 cbz r0, 8004b98 <_vfiprintf_r+0x18>
8004b90: 6a03 ldr r3, [r0, #32]
8004b92: b90b cbnz r3, 8004b98 <_vfiprintf_r+0x18>
8004b94: f7ff fdca bl 800472c <__sinit>
8004b98: 6e6b ldr r3, [r5, #100] @ 0x64
8004b9a: 07d9 lsls r1, r3, #31
8004b9c: d405 bmi.n 8004baa <_vfiprintf_r+0x2a>
8004b9e: 89ab ldrh r3, [r5, #12]
8004ba0: 059a lsls r2, r3, #22
8004ba2: d402 bmi.n 8004baa <_vfiprintf_r+0x2a>
8004ba4: 6da8 ldr r0, [r5, #88] @ 0x58
8004ba6: f7ff fec6 bl 8004936 <__retarget_lock_acquire_recursive>
8004baa: 89ab ldrh r3, [r5, #12]
8004bac: 071b lsls r3, r3, #28
8004bae: d501 bpl.n 8004bb4 <_vfiprintf_r+0x34>
8004bb0: 692b ldr r3, [r5, #16]
8004bb2: b99b cbnz r3, 8004bdc <_vfiprintf_r+0x5c>
8004bb4: 4629 mov r1, r5
8004bb6: 4630 mov r0, r6
8004bb8: f000 fb70 bl 800529c <__swsetup_r>
8004bbc: b170 cbz r0, 8004bdc <_vfiprintf_r+0x5c>
8004bbe: 6e6b ldr r3, [r5, #100] @ 0x64
8004bc0: 07dc lsls r4, r3, #31
8004bc2: d504 bpl.n 8004bce <_vfiprintf_r+0x4e>
8004bc4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8004bc8: b01d add sp, #116 @ 0x74
8004bca: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8004bce: 89ab ldrh r3, [r5, #12]
8004bd0: 0598 lsls r0, r3, #22
8004bd2: d4f7 bmi.n 8004bc4 <_vfiprintf_r+0x44>
8004bd4: 6da8 ldr r0, [r5, #88] @ 0x58
8004bd6: f7ff feaf bl 8004938 <__retarget_lock_release_recursive>
8004bda: e7f3 b.n 8004bc4 <_vfiprintf_r+0x44>
8004bdc: 2300 movs r3, #0
8004bde: 9309 str r3, [sp, #36] @ 0x24
8004be0: 2320 movs r3, #32
8004be2: f88d 3029 strb.w r3, [sp, #41] @ 0x29
8004be6: f8cd 800c str.w r8, [sp, #12]
8004bea: 2330 movs r3, #48 @ 0x30
8004bec: f8df 81ac ldr.w r8, [pc, #428] @ 8004d9c <_vfiprintf_r+0x21c>
8004bf0: f88d 302a strb.w r3, [sp, #42] @ 0x2a
8004bf4: f04f 0901 mov.w r9, #1
8004bf8: 4623 mov r3, r4
8004bfa: 469a mov sl, r3
8004bfc: f813 2b01 ldrb.w r2, [r3], #1
8004c00: b10a cbz r2, 8004c06 <_vfiprintf_r+0x86>
8004c02: 2a25 cmp r2, #37 @ 0x25
8004c04: d1f9 bne.n 8004bfa <_vfiprintf_r+0x7a>
8004c06: ebba 0b04 subs.w fp, sl, r4
8004c0a: d00b beq.n 8004c24 <_vfiprintf_r+0xa4>
8004c0c: 465b mov r3, fp
8004c0e: 4622 mov r2, r4
8004c10: 4629 mov r1, r5
8004c12: 4630 mov r0, r6
8004c14: f7ff ffa1 bl 8004b5a <__sfputs_r>
8004c18: 3001 adds r0, #1
8004c1a: f000 80a7 beq.w 8004d6c <_vfiprintf_r+0x1ec>
8004c1e: 9a09 ldr r2, [sp, #36] @ 0x24
8004c20: 445a add r2, fp
8004c22: 9209 str r2, [sp, #36] @ 0x24
8004c24: f89a 3000 ldrb.w r3, [sl]
8004c28: 2b00 cmp r3, #0
8004c2a: f000 809f beq.w 8004d6c <_vfiprintf_r+0x1ec>
8004c2e: 2300 movs r3, #0
8004c30: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8004c34: e9cd 2305 strd r2, r3, [sp, #20]
8004c38: f10a 0a01 add.w sl, sl, #1
8004c3c: 9304 str r3, [sp, #16]
8004c3e: 9307 str r3, [sp, #28]
8004c40: f88d 3053 strb.w r3, [sp, #83] @ 0x53
8004c44: 931a str r3, [sp, #104] @ 0x68
8004c46: 4654 mov r4, sl
8004c48: 2205 movs r2, #5
8004c4a: f814 1b01 ldrb.w r1, [r4], #1
8004c4e: 4853 ldr r0, [pc, #332] @ (8004d9c <_vfiprintf_r+0x21c>)
8004c50: f7fb fae6 bl 8000220 <memchr>
8004c54: 9a04 ldr r2, [sp, #16]
8004c56: b9d8 cbnz r0, 8004c90 <_vfiprintf_r+0x110>
8004c58: 06d1 lsls r1, r2, #27
8004c5a: bf44 itt mi
8004c5c: 2320 movmi r3, #32
8004c5e: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
8004c62: 0713 lsls r3, r2, #28
8004c64: bf44 itt mi
8004c66: 232b movmi r3, #43 @ 0x2b
8004c68: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
8004c6c: f89a 3000 ldrb.w r3, [sl]
8004c70: 2b2a cmp r3, #42 @ 0x2a
8004c72: d015 beq.n 8004ca0 <_vfiprintf_r+0x120>
8004c74: 9a07 ldr r2, [sp, #28]
8004c76: 4654 mov r4, sl
8004c78: 2000 movs r0, #0
8004c7a: f04f 0c0a mov.w ip, #10
8004c7e: 4621 mov r1, r4
8004c80: f811 3b01 ldrb.w r3, [r1], #1
8004c84: 3b30 subs r3, #48 @ 0x30
8004c86: 2b09 cmp r3, #9
8004c88: d94b bls.n 8004d22 <_vfiprintf_r+0x1a2>
8004c8a: b1b0 cbz r0, 8004cba <_vfiprintf_r+0x13a>
8004c8c: 9207 str r2, [sp, #28]
8004c8e: e014 b.n 8004cba <_vfiprintf_r+0x13a>
8004c90: eba0 0308 sub.w r3, r0, r8
8004c94: fa09 f303 lsl.w r3, r9, r3
8004c98: 4313 orrs r3, r2
8004c9a: 9304 str r3, [sp, #16]
8004c9c: 46a2 mov sl, r4
8004c9e: e7d2 b.n 8004c46 <_vfiprintf_r+0xc6>
8004ca0: 9b03 ldr r3, [sp, #12]
8004ca2: 1d19 adds r1, r3, #4
8004ca4: 681b ldr r3, [r3, #0]
8004ca6: 9103 str r1, [sp, #12]
8004ca8: 2b00 cmp r3, #0
8004caa: bfbb ittet lt
8004cac: 425b neglt r3, r3
8004cae: f042 0202 orrlt.w r2, r2, #2
8004cb2: 9307 strge r3, [sp, #28]
8004cb4: 9307 strlt r3, [sp, #28]
8004cb6: bfb8 it lt
8004cb8: 9204 strlt r2, [sp, #16]
8004cba: 7823 ldrb r3, [r4, #0]
8004cbc: 2b2e cmp r3, #46 @ 0x2e
8004cbe: d10a bne.n 8004cd6 <_vfiprintf_r+0x156>
8004cc0: 7863 ldrb r3, [r4, #1]
8004cc2: 2b2a cmp r3, #42 @ 0x2a
8004cc4: d132 bne.n 8004d2c <_vfiprintf_r+0x1ac>
8004cc6: 9b03 ldr r3, [sp, #12]
8004cc8: 1d1a adds r2, r3, #4
8004cca: 681b ldr r3, [r3, #0]
8004ccc: 9203 str r2, [sp, #12]
8004cce: ea43 73e3 orr.w r3, r3, r3, asr #31
8004cd2: 3402 adds r4, #2
8004cd4: 9305 str r3, [sp, #20]
8004cd6: f8df a0d4 ldr.w sl, [pc, #212] @ 8004dac <_vfiprintf_r+0x22c>
8004cda: 7821 ldrb r1, [r4, #0]
8004cdc: 2203 movs r2, #3
8004cde: 4650 mov r0, sl
8004ce0: f7fb fa9e bl 8000220 <memchr>
8004ce4: b138 cbz r0, 8004cf6 <_vfiprintf_r+0x176>
8004ce6: 9b04 ldr r3, [sp, #16]
8004ce8: eba0 000a sub.w r0, r0, sl
8004cec: 2240 movs r2, #64 @ 0x40
8004cee: 4082 lsls r2, r0
8004cf0: 4313 orrs r3, r2
8004cf2: 3401 adds r4, #1
8004cf4: 9304 str r3, [sp, #16]
8004cf6: f814 1b01 ldrb.w r1, [r4], #1
8004cfa: 4829 ldr r0, [pc, #164] @ (8004da0 <_vfiprintf_r+0x220>)
8004cfc: f88d 1028 strb.w r1, [sp, #40] @ 0x28
8004d00: 2206 movs r2, #6
8004d02: f7fb fa8d bl 8000220 <memchr>
8004d06: 2800 cmp r0, #0
8004d08: d03f beq.n 8004d8a <_vfiprintf_r+0x20a>
8004d0a: 4b26 ldr r3, [pc, #152] @ (8004da4 <_vfiprintf_r+0x224>)
8004d0c: bb1b cbnz r3, 8004d56 <_vfiprintf_r+0x1d6>
8004d0e: 9b03 ldr r3, [sp, #12]
8004d10: 3307 adds r3, #7
8004d12: f023 0307 bic.w r3, r3, #7
8004d16: 3308 adds r3, #8
8004d18: 9303 str r3, [sp, #12]
8004d1a: 9b09 ldr r3, [sp, #36] @ 0x24
8004d1c: 443b add r3, r7
8004d1e: 9309 str r3, [sp, #36] @ 0x24
8004d20: e76a b.n 8004bf8 <_vfiprintf_r+0x78>
8004d22: fb0c 3202 mla r2, ip, r2, r3
8004d26: 460c mov r4, r1
8004d28: 2001 movs r0, #1
8004d2a: e7a8 b.n 8004c7e <_vfiprintf_r+0xfe>
8004d2c: 2300 movs r3, #0
8004d2e: 3401 adds r4, #1
8004d30: 9305 str r3, [sp, #20]
8004d32: 4619 mov r1, r3
8004d34: f04f 0c0a mov.w ip, #10
8004d38: 4620 mov r0, r4
8004d3a: f810 2b01 ldrb.w r2, [r0], #1
8004d3e: 3a30 subs r2, #48 @ 0x30
8004d40: 2a09 cmp r2, #9
8004d42: d903 bls.n 8004d4c <_vfiprintf_r+0x1cc>
8004d44: 2b00 cmp r3, #0
8004d46: d0c6 beq.n 8004cd6 <_vfiprintf_r+0x156>
8004d48: 9105 str r1, [sp, #20]
8004d4a: e7c4 b.n 8004cd6 <_vfiprintf_r+0x156>
8004d4c: fb0c 2101 mla r1, ip, r1, r2
8004d50: 4604 mov r4, r0
8004d52: 2301 movs r3, #1
8004d54: e7f0 b.n 8004d38 <_vfiprintf_r+0x1b8>
8004d56: ab03 add r3, sp, #12
8004d58: 9300 str r3, [sp, #0]
8004d5a: 462a mov r2, r5
8004d5c: 4b12 ldr r3, [pc, #72] @ (8004da8 <_vfiprintf_r+0x228>)
8004d5e: a904 add r1, sp, #16
8004d60: 4630 mov r0, r6
8004d62: f3af 8000 nop.w
8004d66: 4607 mov r7, r0
8004d68: 1c78 adds r0, r7, #1
8004d6a: d1d6 bne.n 8004d1a <_vfiprintf_r+0x19a>
8004d6c: 6e6b ldr r3, [r5, #100] @ 0x64
8004d6e: 07d9 lsls r1, r3, #31
8004d70: d405 bmi.n 8004d7e <_vfiprintf_r+0x1fe>
8004d72: 89ab ldrh r3, [r5, #12]
8004d74: 059a lsls r2, r3, #22
8004d76: d402 bmi.n 8004d7e <_vfiprintf_r+0x1fe>
8004d78: 6da8 ldr r0, [r5, #88] @ 0x58
8004d7a: f7ff fddd bl 8004938 <__retarget_lock_release_recursive>
8004d7e: 89ab ldrh r3, [r5, #12]
8004d80: 065b lsls r3, r3, #25
8004d82: f53f af1f bmi.w 8004bc4 <_vfiprintf_r+0x44>
8004d86: 9809 ldr r0, [sp, #36] @ 0x24
8004d88: e71e b.n 8004bc8 <_vfiprintf_r+0x48>
8004d8a: ab03 add r3, sp, #12
8004d8c: 9300 str r3, [sp, #0]
8004d8e: 462a mov r2, r5
8004d90: 4b05 ldr r3, [pc, #20] @ (8004da8 <_vfiprintf_r+0x228>)
8004d92: a904 add r1, sp, #16
8004d94: 4630 mov r0, r6
8004d96: f000 f879 bl 8004e8c <_printf_i>
8004d9a: e7e4 b.n 8004d66 <_vfiprintf_r+0x1e6>
8004d9c: 08005514 .word 0x08005514
8004da0: 0800551e .word 0x0800551e
8004da4: 00000000 .word 0x00000000
8004da8: 08004b5b .word 0x08004b5b
8004dac: 0800551a .word 0x0800551a
08004db0 <_printf_common>:
8004db0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8004db4: 4616 mov r6, r2
8004db6: 4698 mov r8, r3
8004db8: 688a ldr r2, [r1, #8]
8004dba: 690b ldr r3, [r1, #16]
8004dbc: f8dd 9020 ldr.w r9, [sp, #32]
8004dc0: 4293 cmp r3, r2
8004dc2: bfb8 it lt
8004dc4: 4613 movlt r3, r2
8004dc6: 6033 str r3, [r6, #0]
8004dc8: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
8004dcc: 4607 mov r7, r0
8004dce: 460c mov r4, r1
8004dd0: b10a cbz r2, 8004dd6 <_printf_common+0x26>
8004dd2: 3301 adds r3, #1
8004dd4: 6033 str r3, [r6, #0]
8004dd6: 6823 ldr r3, [r4, #0]
8004dd8: 0699 lsls r1, r3, #26
8004dda: bf42 ittt mi
8004ddc: 6833 ldrmi r3, [r6, #0]
8004dde: 3302 addmi r3, #2
8004de0: 6033 strmi r3, [r6, #0]
8004de2: 6825 ldr r5, [r4, #0]
8004de4: f015 0506 ands.w r5, r5, #6
8004de8: d106 bne.n 8004df8 <_printf_common+0x48>
8004dea: f104 0a19 add.w sl, r4, #25
8004dee: 68e3 ldr r3, [r4, #12]
8004df0: 6832 ldr r2, [r6, #0]
8004df2: 1a9b subs r3, r3, r2
8004df4: 42ab cmp r3, r5
8004df6: dc26 bgt.n 8004e46 <_printf_common+0x96>
8004df8: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
8004dfc: 6822 ldr r2, [r4, #0]
8004dfe: 3b00 subs r3, #0
8004e00: bf18 it ne
8004e02: 2301 movne r3, #1
8004e04: 0692 lsls r2, r2, #26
8004e06: d42b bmi.n 8004e60 <_printf_common+0xb0>
8004e08: f104 0243 add.w r2, r4, #67 @ 0x43
8004e0c: 4641 mov r1, r8
8004e0e: 4638 mov r0, r7
8004e10: 47c8 blx r9
8004e12: 3001 adds r0, #1
8004e14: d01e beq.n 8004e54 <_printf_common+0xa4>
8004e16: 6823 ldr r3, [r4, #0]
8004e18: 6922 ldr r2, [r4, #16]
8004e1a: f003 0306 and.w r3, r3, #6
8004e1e: 2b04 cmp r3, #4
8004e20: bf02 ittt eq
8004e22: 68e5 ldreq r5, [r4, #12]
8004e24: 6833 ldreq r3, [r6, #0]
8004e26: 1aed subeq r5, r5, r3
8004e28: 68a3 ldr r3, [r4, #8]
8004e2a: bf0c ite eq
8004e2c: ea25 75e5 biceq.w r5, r5, r5, asr #31
8004e30: 2500 movne r5, #0
8004e32: 4293 cmp r3, r2
8004e34: bfc4 itt gt
8004e36: 1a9b subgt r3, r3, r2
8004e38: 18ed addgt r5, r5, r3
8004e3a: 2600 movs r6, #0
8004e3c: 341a adds r4, #26
8004e3e: 42b5 cmp r5, r6
8004e40: d11a bne.n 8004e78 <_printf_common+0xc8>
8004e42: 2000 movs r0, #0
8004e44: e008 b.n 8004e58 <_printf_common+0xa8>
8004e46: 2301 movs r3, #1
8004e48: 4652 mov r2, sl
8004e4a: 4641 mov r1, r8
8004e4c: 4638 mov r0, r7
8004e4e: 47c8 blx r9
8004e50: 3001 adds r0, #1
8004e52: d103 bne.n 8004e5c <_printf_common+0xac>
8004e54: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8004e58: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8004e5c: 3501 adds r5, #1
8004e5e: e7c6 b.n 8004dee <_printf_common+0x3e>
8004e60: 18e1 adds r1, r4, r3
8004e62: 1c5a adds r2, r3, #1
8004e64: 2030 movs r0, #48 @ 0x30
8004e66: f881 0043 strb.w r0, [r1, #67] @ 0x43
8004e6a: 4422 add r2, r4
8004e6c: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
8004e70: f882 1043 strb.w r1, [r2, #67] @ 0x43
8004e74: 3302 adds r3, #2
8004e76: e7c7 b.n 8004e08 <_printf_common+0x58>
8004e78: 2301 movs r3, #1
8004e7a: 4622 mov r2, r4
8004e7c: 4641 mov r1, r8
8004e7e: 4638 mov r0, r7
8004e80: 47c8 blx r9
8004e82: 3001 adds r0, #1
8004e84: d0e6 beq.n 8004e54 <_printf_common+0xa4>
8004e86: 3601 adds r6, #1
8004e88: e7d9 b.n 8004e3e <_printf_common+0x8e>
...
08004e8c <_printf_i>:
8004e8c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
8004e90: 7e0f ldrb r7, [r1, #24]
8004e92: 9e0c ldr r6, [sp, #48] @ 0x30
8004e94: 2f78 cmp r7, #120 @ 0x78
8004e96: 4691 mov r9, r2
8004e98: 4680 mov r8, r0
8004e9a: 460c mov r4, r1
8004e9c: 469a mov sl, r3
8004e9e: f101 0243 add.w r2, r1, #67 @ 0x43
8004ea2: d807 bhi.n 8004eb4 <_printf_i+0x28>
8004ea4: 2f62 cmp r7, #98 @ 0x62
8004ea6: d80a bhi.n 8004ebe <_printf_i+0x32>
8004ea8: 2f00 cmp r7, #0
8004eaa: f000 80d1 beq.w 8005050 <_printf_i+0x1c4>
8004eae: 2f58 cmp r7, #88 @ 0x58
8004eb0: f000 80b8 beq.w 8005024 <_printf_i+0x198>
8004eb4: f104 0642 add.w r6, r4, #66 @ 0x42
8004eb8: f884 7042 strb.w r7, [r4, #66] @ 0x42
8004ebc: e03a b.n 8004f34 <_printf_i+0xa8>
8004ebe: f1a7 0363 sub.w r3, r7, #99 @ 0x63
8004ec2: 2b15 cmp r3, #21
8004ec4: d8f6 bhi.n 8004eb4 <_printf_i+0x28>
8004ec6: a101 add r1, pc, #4 @ (adr r1, 8004ecc <_printf_i+0x40>)
8004ec8: f851 f023 ldr.w pc, [r1, r3, lsl #2]
8004ecc: 08004f25 .word 0x08004f25
8004ed0: 08004f39 .word 0x08004f39
8004ed4: 08004eb5 .word 0x08004eb5
8004ed8: 08004eb5 .word 0x08004eb5
8004edc: 08004eb5 .word 0x08004eb5
8004ee0: 08004eb5 .word 0x08004eb5
8004ee4: 08004f39 .word 0x08004f39
8004ee8: 08004eb5 .word 0x08004eb5
8004eec: 08004eb5 .word 0x08004eb5
8004ef0: 08004eb5 .word 0x08004eb5
8004ef4: 08004eb5 .word 0x08004eb5
8004ef8: 08005037 .word 0x08005037
8004efc: 08004f63 .word 0x08004f63
8004f00: 08004ff1 .word 0x08004ff1
8004f04: 08004eb5 .word 0x08004eb5
8004f08: 08004eb5 .word 0x08004eb5
8004f0c: 08005059 .word 0x08005059
8004f10: 08004eb5 .word 0x08004eb5
8004f14: 08004f63 .word 0x08004f63
8004f18: 08004eb5 .word 0x08004eb5
8004f1c: 08004eb5 .word 0x08004eb5
8004f20: 08004ff9 .word 0x08004ff9
8004f24: 6833 ldr r3, [r6, #0]
8004f26: 1d1a adds r2, r3, #4
8004f28: 681b ldr r3, [r3, #0]
8004f2a: 6032 str r2, [r6, #0]
8004f2c: f104 0642 add.w r6, r4, #66 @ 0x42
8004f30: f884 3042 strb.w r3, [r4, #66] @ 0x42
8004f34: 2301 movs r3, #1
8004f36: e09c b.n 8005072 <_printf_i+0x1e6>
8004f38: 6833 ldr r3, [r6, #0]
8004f3a: 6820 ldr r0, [r4, #0]
8004f3c: 1d19 adds r1, r3, #4
8004f3e: 6031 str r1, [r6, #0]
8004f40: 0606 lsls r6, r0, #24
8004f42: d501 bpl.n 8004f48 <_printf_i+0xbc>
8004f44: 681d ldr r5, [r3, #0]
8004f46: e003 b.n 8004f50 <_printf_i+0xc4>
8004f48: 0645 lsls r5, r0, #25
8004f4a: d5fb bpl.n 8004f44 <_printf_i+0xb8>
8004f4c: f9b3 5000 ldrsh.w r5, [r3]
8004f50: 2d00 cmp r5, #0
8004f52: da03 bge.n 8004f5c <_printf_i+0xd0>
8004f54: 232d movs r3, #45 @ 0x2d
8004f56: 426d negs r5, r5
8004f58: f884 3043 strb.w r3, [r4, #67] @ 0x43
8004f5c: 4858 ldr r0, [pc, #352] @ (80050c0 <_printf_i+0x234>)
8004f5e: 230a movs r3, #10
8004f60: e011 b.n 8004f86 <_printf_i+0xfa>
8004f62: 6821 ldr r1, [r4, #0]
8004f64: 6833 ldr r3, [r6, #0]
8004f66: 0608 lsls r0, r1, #24
8004f68: f853 5b04 ldr.w r5, [r3], #4
8004f6c: d402 bmi.n 8004f74 <_printf_i+0xe8>
8004f6e: 0649 lsls r1, r1, #25
8004f70: bf48 it mi
8004f72: b2ad uxthmi r5, r5
8004f74: 2f6f cmp r7, #111 @ 0x6f
8004f76: 4852 ldr r0, [pc, #328] @ (80050c0 <_printf_i+0x234>)
8004f78: 6033 str r3, [r6, #0]
8004f7a: bf14 ite ne
8004f7c: 230a movne r3, #10
8004f7e: 2308 moveq r3, #8
8004f80: 2100 movs r1, #0
8004f82: f884 1043 strb.w r1, [r4, #67] @ 0x43
8004f86: 6866 ldr r6, [r4, #4]
8004f88: 60a6 str r6, [r4, #8]
8004f8a: 2e00 cmp r6, #0
8004f8c: db05 blt.n 8004f9a <_printf_i+0x10e>
8004f8e: 6821 ldr r1, [r4, #0]
8004f90: 432e orrs r6, r5
8004f92: f021 0104 bic.w r1, r1, #4
8004f96: 6021 str r1, [r4, #0]
8004f98: d04b beq.n 8005032 <_printf_i+0x1a6>
8004f9a: 4616 mov r6, r2
8004f9c: fbb5 f1f3 udiv r1, r5, r3
8004fa0: fb03 5711 mls r7, r3, r1, r5
8004fa4: 5dc7 ldrb r7, [r0, r7]
8004fa6: f806 7d01 strb.w r7, [r6, #-1]!
8004faa: 462f mov r7, r5
8004fac: 42bb cmp r3, r7
8004fae: 460d mov r5, r1
8004fb0: d9f4 bls.n 8004f9c <_printf_i+0x110>
8004fb2: 2b08 cmp r3, #8
8004fb4: d10b bne.n 8004fce <_printf_i+0x142>
8004fb6: 6823 ldr r3, [r4, #0]
8004fb8: 07df lsls r7, r3, #31
8004fba: d508 bpl.n 8004fce <_printf_i+0x142>
8004fbc: 6923 ldr r3, [r4, #16]
8004fbe: 6861 ldr r1, [r4, #4]
8004fc0: 4299 cmp r1, r3
8004fc2: bfde ittt le
8004fc4: 2330 movle r3, #48 @ 0x30
8004fc6: f806 3c01 strble.w r3, [r6, #-1]
8004fca: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff
8004fce: 1b92 subs r2, r2, r6
8004fd0: 6122 str r2, [r4, #16]
8004fd2: f8cd a000 str.w sl, [sp]
8004fd6: 464b mov r3, r9
8004fd8: aa03 add r2, sp, #12
8004fda: 4621 mov r1, r4
8004fdc: 4640 mov r0, r8
8004fde: f7ff fee7 bl 8004db0 <_printf_common>
8004fe2: 3001 adds r0, #1
8004fe4: d14a bne.n 800507c <_printf_i+0x1f0>
8004fe6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8004fea: b004 add sp, #16
8004fec: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8004ff0: 6823 ldr r3, [r4, #0]
8004ff2: f043 0320 orr.w r3, r3, #32
8004ff6: 6023 str r3, [r4, #0]
8004ff8: 4832 ldr r0, [pc, #200] @ (80050c4 <_printf_i+0x238>)
8004ffa: 2778 movs r7, #120 @ 0x78
8004ffc: f884 7045 strb.w r7, [r4, #69] @ 0x45
8005000: 6823 ldr r3, [r4, #0]
8005002: 6831 ldr r1, [r6, #0]
8005004: 061f lsls r7, r3, #24
8005006: f851 5b04 ldr.w r5, [r1], #4
800500a: d402 bmi.n 8005012 <_printf_i+0x186>
800500c: 065f lsls r7, r3, #25
800500e: bf48 it mi
8005010: b2ad uxthmi r5, r5
8005012: 6031 str r1, [r6, #0]
8005014: 07d9 lsls r1, r3, #31
8005016: bf44 itt mi
8005018: f043 0320 orrmi.w r3, r3, #32
800501c: 6023 strmi r3, [r4, #0]
800501e: b11d cbz r5, 8005028 <_printf_i+0x19c>
8005020: 2310 movs r3, #16
8005022: e7ad b.n 8004f80 <_printf_i+0xf4>
8005024: 4826 ldr r0, [pc, #152] @ (80050c0 <_printf_i+0x234>)
8005026: e7e9 b.n 8004ffc <_printf_i+0x170>
8005028: 6823 ldr r3, [r4, #0]
800502a: f023 0320 bic.w r3, r3, #32
800502e: 6023 str r3, [r4, #0]
8005030: e7f6 b.n 8005020 <_printf_i+0x194>
8005032: 4616 mov r6, r2
8005034: e7bd b.n 8004fb2 <_printf_i+0x126>
8005036: 6833 ldr r3, [r6, #0]
8005038: 6825 ldr r5, [r4, #0]
800503a: 6961 ldr r1, [r4, #20]
800503c: 1d18 adds r0, r3, #4
800503e: 6030 str r0, [r6, #0]
8005040: 062e lsls r6, r5, #24
8005042: 681b ldr r3, [r3, #0]
8005044: d501 bpl.n 800504a <_printf_i+0x1be>
8005046: 6019 str r1, [r3, #0]
8005048: e002 b.n 8005050 <_printf_i+0x1c4>
800504a: 0668 lsls r0, r5, #25
800504c: d5fb bpl.n 8005046 <_printf_i+0x1ba>
800504e: 8019 strh r1, [r3, #0]
8005050: 2300 movs r3, #0
8005052: 6123 str r3, [r4, #16]
8005054: 4616 mov r6, r2
8005056: e7bc b.n 8004fd2 <_printf_i+0x146>
8005058: 6833 ldr r3, [r6, #0]
800505a: 1d1a adds r2, r3, #4
800505c: 6032 str r2, [r6, #0]
800505e: 681e ldr r6, [r3, #0]
8005060: 6862 ldr r2, [r4, #4]
8005062: 2100 movs r1, #0
8005064: 4630 mov r0, r6
8005066: f7fb f8db bl 8000220 <memchr>
800506a: b108 cbz r0, 8005070 <_printf_i+0x1e4>
800506c: 1b80 subs r0, r0, r6
800506e: 6060 str r0, [r4, #4]
8005070: 6863 ldr r3, [r4, #4]
8005072: 6123 str r3, [r4, #16]
8005074: 2300 movs r3, #0
8005076: f884 3043 strb.w r3, [r4, #67] @ 0x43
800507a: e7aa b.n 8004fd2 <_printf_i+0x146>
800507c: 6923 ldr r3, [r4, #16]
800507e: 4632 mov r2, r6
8005080: 4649 mov r1, r9
8005082: 4640 mov r0, r8
8005084: 47d0 blx sl
8005086: 3001 adds r0, #1
8005088: d0ad beq.n 8004fe6 <_printf_i+0x15a>
800508a: 6823 ldr r3, [r4, #0]
800508c: 079b lsls r3, r3, #30
800508e: d413 bmi.n 80050b8 <_printf_i+0x22c>
8005090: 68e0 ldr r0, [r4, #12]
8005092: 9b03 ldr r3, [sp, #12]
8005094: 4298 cmp r0, r3
8005096: bfb8 it lt
8005098: 4618 movlt r0, r3
800509a: e7a6 b.n 8004fea <_printf_i+0x15e>
800509c: 2301 movs r3, #1
800509e: 4632 mov r2, r6
80050a0: 4649 mov r1, r9
80050a2: 4640 mov r0, r8
80050a4: 47d0 blx sl
80050a6: 3001 adds r0, #1
80050a8: d09d beq.n 8004fe6 <_printf_i+0x15a>
80050aa: 3501 adds r5, #1
80050ac: 68e3 ldr r3, [r4, #12]
80050ae: 9903 ldr r1, [sp, #12]
80050b0: 1a5b subs r3, r3, r1
80050b2: 42ab cmp r3, r5
80050b4: dcf2 bgt.n 800509c <_printf_i+0x210>
80050b6: e7eb b.n 8005090 <_printf_i+0x204>
80050b8: 2500 movs r5, #0
80050ba: f104 0619 add.w r6, r4, #25
80050be: e7f5 b.n 80050ac <_printf_i+0x220>
80050c0: 08005525 .word 0x08005525
80050c4: 08005536 .word 0x08005536
080050c8 <__sflush_r>:
80050c8: f9b1 200c ldrsh.w r2, [r1, #12]
80050cc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
80050d0: 0716 lsls r6, r2, #28
80050d2: 4605 mov r5, r0
80050d4: 460c mov r4, r1
80050d6: d454 bmi.n 8005182 <__sflush_r+0xba>
80050d8: 684b ldr r3, [r1, #4]
80050da: 2b00 cmp r3, #0
80050dc: dc02 bgt.n 80050e4 <__sflush_r+0x1c>
80050de: 6c0b ldr r3, [r1, #64] @ 0x40
80050e0: 2b00 cmp r3, #0
80050e2: dd48 ble.n 8005176 <__sflush_r+0xae>
80050e4: 6ae6 ldr r6, [r4, #44] @ 0x2c
80050e6: 2e00 cmp r6, #0
80050e8: d045 beq.n 8005176 <__sflush_r+0xae>
80050ea: 2300 movs r3, #0
80050ec: f412 5280 ands.w r2, r2, #4096 @ 0x1000
80050f0: 682f ldr r7, [r5, #0]
80050f2: 6a21 ldr r1, [r4, #32]
80050f4: 602b str r3, [r5, #0]
80050f6: d030 beq.n 800515a <__sflush_r+0x92>
80050f8: 6d62 ldr r2, [r4, #84] @ 0x54
80050fa: 89a3 ldrh r3, [r4, #12]
80050fc: 0759 lsls r1, r3, #29
80050fe: d505 bpl.n 800510c <__sflush_r+0x44>
8005100: 6863 ldr r3, [r4, #4]
8005102: 1ad2 subs r2, r2, r3
8005104: 6b63 ldr r3, [r4, #52] @ 0x34
8005106: b10b cbz r3, 800510c <__sflush_r+0x44>
8005108: 6c23 ldr r3, [r4, #64] @ 0x40
800510a: 1ad2 subs r2, r2, r3
800510c: 2300 movs r3, #0
800510e: 6ae6 ldr r6, [r4, #44] @ 0x2c
8005110: 6a21 ldr r1, [r4, #32]
8005112: 4628 mov r0, r5
8005114: 47b0 blx r6
8005116: 1c43 adds r3, r0, #1
8005118: 89a3 ldrh r3, [r4, #12]
800511a: d106 bne.n 800512a <__sflush_r+0x62>
800511c: 6829 ldr r1, [r5, #0]
800511e: 291d cmp r1, #29
8005120: d82b bhi.n 800517a <__sflush_r+0xb2>
8005122: 4a2a ldr r2, [pc, #168] @ (80051cc <__sflush_r+0x104>)
8005124: 40ca lsrs r2, r1
8005126: 07d6 lsls r6, r2, #31
8005128: d527 bpl.n 800517a <__sflush_r+0xb2>
800512a: 2200 movs r2, #0
800512c: 6062 str r2, [r4, #4]
800512e: 04d9 lsls r1, r3, #19
8005130: 6922 ldr r2, [r4, #16]
8005132: 6022 str r2, [r4, #0]
8005134: d504 bpl.n 8005140 <__sflush_r+0x78>
8005136: 1c42 adds r2, r0, #1
8005138: d101 bne.n 800513e <__sflush_r+0x76>
800513a: 682b ldr r3, [r5, #0]
800513c: b903 cbnz r3, 8005140 <__sflush_r+0x78>
800513e: 6560 str r0, [r4, #84] @ 0x54
8005140: 6b61 ldr r1, [r4, #52] @ 0x34
8005142: 602f str r7, [r5, #0]
8005144: b1b9 cbz r1, 8005176 <__sflush_r+0xae>
8005146: f104 0344 add.w r3, r4, #68 @ 0x44
800514a: 4299 cmp r1, r3
800514c: d002 beq.n 8005154 <__sflush_r+0x8c>
800514e: 4628 mov r0, r5
8005150: f7ff fbf4 bl 800493c <_free_r>
8005154: 2300 movs r3, #0
8005156: 6363 str r3, [r4, #52] @ 0x34
8005158: e00d b.n 8005176 <__sflush_r+0xae>
800515a: 2301 movs r3, #1
800515c: 4628 mov r0, r5
800515e: 47b0 blx r6
8005160: 4602 mov r2, r0
8005162: 1c50 adds r0, r2, #1
8005164: d1c9 bne.n 80050fa <__sflush_r+0x32>
8005166: 682b ldr r3, [r5, #0]
8005168: 2b00 cmp r3, #0
800516a: d0c6 beq.n 80050fa <__sflush_r+0x32>
800516c: 2b1d cmp r3, #29
800516e: d001 beq.n 8005174 <__sflush_r+0xac>
8005170: 2b16 cmp r3, #22
8005172: d11e bne.n 80051b2 <__sflush_r+0xea>
8005174: 602f str r7, [r5, #0]
8005176: 2000 movs r0, #0
8005178: e022 b.n 80051c0 <__sflush_r+0xf8>
800517a: f043 0340 orr.w r3, r3, #64 @ 0x40
800517e: b21b sxth r3, r3
8005180: e01b b.n 80051ba <__sflush_r+0xf2>
8005182: 690f ldr r7, [r1, #16]
8005184: 2f00 cmp r7, #0
8005186: d0f6 beq.n 8005176 <__sflush_r+0xae>
8005188: 0793 lsls r3, r2, #30
800518a: 680e ldr r6, [r1, #0]
800518c: bf08 it eq
800518e: 694b ldreq r3, [r1, #20]
8005190: 600f str r7, [r1, #0]
8005192: bf18 it ne
8005194: 2300 movne r3, #0
8005196: eba6 0807 sub.w r8, r6, r7
800519a: 608b str r3, [r1, #8]
800519c: f1b8 0f00 cmp.w r8, #0
80051a0: dde9 ble.n 8005176 <__sflush_r+0xae>
80051a2: 6a21 ldr r1, [r4, #32]
80051a4: 6aa6 ldr r6, [r4, #40] @ 0x28
80051a6: 4643 mov r3, r8
80051a8: 463a mov r2, r7
80051aa: 4628 mov r0, r5
80051ac: 47b0 blx r6
80051ae: 2800 cmp r0, #0
80051b0: dc08 bgt.n 80051c4 <__sflush_r+0xfc>
80051b2: f9b4 300c ldrsh.w r3, [r4, #12]
80051b6: f043 0340 orr.w r3, r3, #64 @ 0x40
80051ba: 81a3 strh r3, [r4, #12]
80051bc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
80051c0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
80051c4: 4407 add r7, r0
80051c6: eba8 0800 sub.w r8, r8, r0
80051ca: e7e7 b.n 800519c <__sflush_r+0xd4>
80051cc: 20400001 .word 0x20400001
080051d0 <_fflush_r>:
80051d0: b538 push {r3, r4, r5, lr}
80051d2: 690b ldr r3, [r1, #16]
80051d4: 4605 mov r5, r0
80051d6: 460c mov r4, r1
80051d8: b913 cbnz r3, 80051e0 <_fflush_r+0x10>
80051da: 2500 movs r5, #0
80051dc: 4628 mov r0, r5
80051de: bd38 pop {r3, r4, r5, pc}
80051e0: b118 cbz r0, 80051ea <_fflush_r+0x1a>
80051e2: 6a03 ldr r3, [r0, #32]
80051e4: b90b cbnz r3, 80051ea <_fflush_r+0x1a>
80051e6: f7ff faa1 bl 800472c <__sinit>
80051ea: f9b4 300c ldrsh.w r3, [r4, #12]
80051ee: 2b00 cmp r3, #0
80051f0: d0f3 beq.n 80051da <_fflush_r+0xa>
80051f2: 6e62 ldr r2, [r4, #100] @ 0x64
80051f4: 07d0 lsls r0, r2, #31
80051f6: d404 bmi.n 8005202 <_fflush_r+0x32>
80051f8: 0599 lsls r1, r3, #22
80051fa: d402 bmi.n 8005202 <_fflush_r+0x32>
80051fc: 6da0 ldr r0, [r4, #88] @ 0x58
80051fe: f7ff fb9a bl 8004936 <__retarget_lock_acquire_recursive>
8005202: 4628 mov r0, r5
8005204: 4621 mov r1, r4
8005206: f7ff ff5f bl 80050c8 <__sflush_r>
800520a: 6e63 ldr r3, [r4, #100] @ 0x64
800520c: 07da lsls r2, r3, #31
800520e: 4605 mov r5, r0
8005210: d4e4 bmi.n 80051dc <_fflush_r+0xc>
8005212: 89a3 ldrh r3, [r4, #12]
8005214: 059b lsls r3, r3, #22
8005216: d4e1 bmi.n 80051dc <_fflush_r+0xc>
8005218: 6da0 ldr r0, [r4, #88] @ 0x58
800521a: f7ff fb8d bl 8004938 <__retarget_lock_release_recursive>
800521e: e7dd b.n 80051dc <_fflush_r+0xc>
08005220 <__swbuf_r>:
8005220: b5f8 push {r3, r4, r5, r6, r7, lr}
8005222: 460e mov r6, r1
8005224: 4614 mov r4, r2
8005226: 4605 mov r5, r0
8005228: b118 cbz r0, 8005232 <__swbuf_r+0x12>
800522a: 6a03 ldr r3, [r0, #32]
800522c: b90b cbnz r3, 8005232 <__swbuf_r+0x12>
800522e: f7ff fa7d bl 800472c <__sinit>
8005232: 69a3 ldr r3, [r4, #24]
8005234: 60a3 str r3, [r4, #8]
8005236: 89a3 ldrh r3, [r4, #12]
8005238: 071a lsls r2, r3, #28
800523a: d501 bpl.n 8005240 <__swbuf_r+0x20>
800523c: 6923 ldr r3, [r4, #16]
800523e: b943 cbnz r3, 8005252 <__swbuf_r+0x32>
8005240: 4621 mov r1, r4
8005242: 4628 mov r0, r5
8005244: f000 f82a bl 800529c <__swsetup_r>
8005248: b118 cbz r0, 8005252 <__swbuf_r+0x32>
800524a: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff
800524e: 4638 mov r0, r7
8005250: bdf8 pop {r3, r4, r5, r6, r7, pc}
8005252: 6823 ldr r3, [r4, #0]
8005254: 6922 ldr r2, [r4, #16]
8005256: 1a98 subs r0, r3, r2
8005258: 6963 ldr r3, [r4, #20]
800525a: b2f6 uxtb r6, r6
800525c: 4283 cmp r3, r0
800525e: 4637 mov r7, r6
8005260: dc05 bgt.n 800526e <__swbuf_r+0x4e>
8005262: 4621 mov r1, r4
8005264: 4628 mov r0, r5
8005266: f7ff ffb3 bl 80051d0 <_fflush_r>
800526a: 2800 cmp r0, #0
800526c: d1ed bne.n 800524a <__swbuf_r+0x2a>
800526e: 68a3 ldr r3, [r4, #8]
8005270: 3b01 subs r3, #1
8005272: 60a3 str r3, [r4, #8]
8005274: 6823 ldr r3, [r4, #0]
8005276: 1c5a adds r2, r3, #1
8005278: 6022 str r2, [r4, #0]
800527a: 701e strb r6, [r3, #0]
800527c: 6962 ldr r2, [r4, #20]
800527e: 1c43 adds r3, r0, #1
8005280: 429a cmp r2, r3
8005282: d004 beq.n 800528e <__swbuf_r+0x6e>
8005284: 89a3 ldrh r3, [r4, #12]
8005286: 07db lsls r3, r3, #31
8005288: d5e1 bpl.n 800524e <__swbuf_r+0x2e>
800528a: 2e0a cmp r6, #10
800528c: d1df bne.n 800524e <__swbuf_r+0x2e>
800528e: 4621 mov r1, r4
8005290: 4628 mov r0, r5
8005292: f7ff ff9d bl 80051d0 <_fflush_r>
8005296: 2800 cmp r0, #0
8005298: d0d9 beq.n 800524e <__swbuf_r+0x2e>
800529a: e7d6 b.n 800524a <__swbuf_r+0x2a>
0800529c <__swsetup_r>:
800529c: b538 push {r3, r4, r5, lr}
800529e: 4b29 ldr r3, [pc, #164] @ (8005344 <__swsetup_r+0xa8>)
80052a0: 4605 mov r5, r0
80052a2: 6818 ldr r0, [r3, #0]
80052a4: 460c mov r4, r1
80052a6: b118 cbz r0, 80052b0 <__swsetup_r+0x14>
80052a8: 6a03 ldr r3, [r0, #32]
80052aa: b90b cbnz r3, 80052b0 <__swsetup_r+0x14>
80052ac: f7ff fa3e bl 800472c <__sinit>
80052b0: f9b4 300c ldrsh.w r3, [r4, #12]
80052b4: 0719 lsls r1, r3, #28
80052b6: d422 bmi.n 80052fe <__swsetup_r+0x62>
80052b8: 06da lsls r2, r3, #27
80052ba: d407 bmi.n 80052cc <__swsetup_r+0x30>
80052bc: 2209 movs r2, #9
80052be: 602a str r2, [r5, #0]
80052c0: f043 0340 orr.w r3, r3, #64 @ 0x40
80052c4: 81a3 strh r3, [r4, #12]
80052c6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
80052ca: e033 b.n 8005334 <__swsetup_r+0x98>
80052cc: 0758 lsls r0, r3, #29
80052ce: d512 bpl.n 80052f6 <__swsetup_r+0x5a>
80052d0: 6b61 ldr r1, [r4, #52] @ 0x34
80052d2: b141 cbz r1, 80052e6 <__swsetup_r+0x4a>
80052d4: f104 0344 add.w r3, r4, #68 @ 0x44
80052d8: 4299 cmp r1, r3
80052da: d002 beq.n 80052e2 <__swsetup_r+0x46>
80052dc: 4628 mov r0, r5
80052de: f7ff fb2d bl 800493c <_free_r>
80052e2: 2300 movs r3, #0
80052e4: 6363 str r3, [r4, #52] @ 0x34
80052e6: 89a3 ldrh r3, [r4, #12]
80052e8: f023 0324 bic.w r3, r3, #36 @ 0x24
80052ec: 81a3 strh r3, [r4, #12]
80052ee: 2300 movs r3, #0
80052f0: 6063 str r3, [r4, #4]
80052f2: 6923 ldr r3, [r4, #16]
80052f4: 6023 str r3, [r4, #0]
80052f6: 89a3 ldrh r3, [r4, #12]
80052f8: f043 0308 orr.w r3, r3, #8
80052fc: 81a3 strh r3, [r4, #12]
80052fe: 6923 ldr r3, [r4, #16]
8005300: b94b cbnz r3, 8005316 <__swsetup_r+0x7a>
8005302: 89a3 ldrh r3, [r4, #12]
8005304: f403 7320 and.w r3, r3, #640 @ 0x280
8005308: f5b3 7f00 cmp.w r3, #512 @ 0x200
800530c: d003 beq.n 8005316 <__swsetup_r+0x7a>
800530e: 4621 mov r1, r4
8005310: 4628 mov r0, r5
8005312: f000 f84f bl 80053b4 <__smakebuf_r>
8005316: f9b4 300c ldrsh.w r3, [r4, #12]
800531a: f013 0201 ands.w r2, r3, #1
800531e: d00a beq.n 8005336 <__swsetup_r+0x9a>
8005320: 2200 movs r2, #0
8005322: 60a2 str r2, [r4, #8]
8005324: 6962 ldr r2, [r4, #20]
8005326: 4252 negs r2, r2
8005328: 61a2 str r2, [r4, #24]
800532a: 6922 ldr r2, [r4, #16]
800532c: b942 cbnz r2, 8005340 <__swsetup_r+0xa4>
800532e: f013 0080 ands.w r0, r3, #128 @ 0x80
8005332: d1c5 bne.n 80052c0 <__swsetup_r+0x24>
8005334: bd38 pop {r3, r4, r5, pc}
8005336: 0799 lsls r1, r3, #30
8005338: bf58 it pl
800533a: 6962 ldrpl r2, [r4, #20]
800533c: 60a2 str r2, [r4, #8]
800533e: e7f4 b.n 800532a <__swsetup_r+0x8e>
8005340: 2000 movs r0, #0
8005342: e7f7 b.n 8005334 <__swsetup_r+0x98>
8005344: 20000018 .word 0x20000018
08005348 <_sbrk_r>:
8005348: b538 push {r3, r4, r5, lr}
800534a: 4d06 ldr r5, [pc, #24] @ (8005364 <_sbrk_r+0x1c>)
800534c: 2300 movs r3, #0
800534e: 4604 mov r4, r0
8005350: 4608 mov r0, r1
8005352: 602b str r3, [r5, #0]
8005354: f7fc fb0a bl 800196c <_sbrk>
8005358: 1c43 adds r3, r0, #1
800535a: d102 bne.n 8005362 <_sbrk_r+0x1a>
800535c: 682b ldr r3, [r5, #0]
800535e: b103 cbz r3, 8005362 <_sbrk_r+0x1a>
8005360: 6023 str r3, [r4, #0]
8005362: bd38 pop {r3, r4, r5, pc}
8005364: 20000340 .word 0x20000340
08005368 <__swhatbuf_r>:
8005368: b570 push {r4, r5, r6, lr}
800536a: 460c mov r4, r1
800536c: f9b1 100e ldrsh.w r1, [r1, #14]
8005370: 2900 cmp r1, #0
8005372: b096 sub sp, #88 @ 0x58
8005374: 4615 mov r5, r2
8005376: 461e mov r6, r3
8005378: da0d bge.n 8005396 <__swhatbuf_r+0x2e>
800537a: 89a3 ldrh r3, [r4, #12]
800537c: f013 0f80 tst.w r3, #128 @ 0x80
8005380: f04f 0100 mov.w r1, #0
8005384: bf14 ite ne
8005386: 2340 movne r3, #64 @ 0x40
8005388: f44f 6380 moveq.w r3, #1024 @ 0x400
800538c: 2000 movs r0, #0
800538e: 6031 str r1, [r6, #0]
8005390: 602b str r3, [r5, #0]
8005392: b016 add sp, #88 @ 0x58
8005394: bd70 pop {r4, r5, r6, pc}
8005396: 466a mov r2, sp
8005398: f000 f848 bl 800542c <_fstat_r>
800539c: 2800 cmp r0, #0
800539e: dbec blt.n 800537a <__swhatbuf_r+0x12>
80053a0: 9901 ldr r1, [sp, #4]
80053a2: f401 4170 and.w r1, r1, #61440 @ 0xf000
80053a6: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000
80053aa: 4259 negs r1, r3
80053ac: 4159 adcs r1, r3
80053ae: f44f 6380 mov.w r3, #1024 @ 0x400
80053b2: e7eb b.n 800538c <__swhatbuf_r+0x24>
080053b4 <__smakebuf_r>:
80053b4: 898b ldrh r3, [r1, #12]
80053b6: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
80053b8: 079d lsls r5, r3, #30
80053ba: 4606 mov r6, r0
80053bc: 460c mov r4, r1
80053be: d507 bpl.n 80053d0 <__smakebuf_r+0x1c>
80053c0: f104 0347 add.w r3, r4, #71 @ 0x47
80053c4: 6023 str r3, [r4, #0]
80053c6: 6123 str r3, [r4, #16]
80053c8: 2301 movs r3, #1
80053ca: 6163 str r3, [r4, #20]
80053cc: b003 add sp, #12
80053ce: bdf0 pop {r4, r5, r6, r7, pc}
80053d0: ab01 add r3, sp, #4
80053d2: 466a mov r2, sp
80053d4: f7ff ffc8 bl 8005368 <__swhatbuf_r>
80053d8: 9f00 ldr r7, [sp, #0]
80053da: 4605 mov r5, r0
80053dc: 4639 mov r1, r7
80053de: 4630 mov r0, r6
80053e0: f7ff fb18 bl 8004a14 <_malloc_r>
80053e4: b948 cbnz r0, 80053fa <__smakebuf_r+0x46>
80053e6: f9b4 300c ldrsh.w r3, [r4, #12]
80053ea: 059a lsls r2, r3, #22
80053ec: d4ee bmi.n 80053cc <__smakebuf_r+0x18>
80053ee: f023 0303 bic.w r3, r3, #3
80053f2: f043 0302 orr.w r3, r3, #2
80053f6: 81a3 strh r3, [r4, #12]
80053f8: e7e2 b.n 80053c0 <__smakebuf_r+0xc>
80053fa: 89a3 ldrh r3, [r4, #12]
80053fc: 6020 str r0, [r4, #0]
80053fe: f043 0380 orr.w r3, r3, #128 @ 0x80
8005402: 81a3 strh r3, [r4, #12]
8005404: 9b01 ldr r3, [sp, #4]
8005406: e9c4 0704 strd r0, r7, [r4, #16]
800540a: b15b cbz r3, 8005424 <__smakebuf_r+0x70>
800540c: f9b4 100e ldrsh.w r1, [r4, #14]
8005410: 4630 mov r0, r6
8005412: f000 f81d bl 8005450 <_isatty_r>
8005416: b128 cbz r0, 8005424 <__smakebuf_r+0x70>
8005418: 89a3 ldrh r3, [r4, #12]
800541a: f023 0303 bic.w r3, r3, #3
800541e: f043 0301 orr.w r3, r3, #1
8005422: 81a3 strh r3, [r4, #12]
8005424: 89a3 ldrh r3, [r4, #12]
8005426: 431d orrs r5, r3
8005428: 81a5 strh r5, [r4, #12]
800542a: e7cf b.n 80053cc <__smakebuf_r+0x18>
0800542c <_fstat_r>:
800542c: b538 push {r3, r4, r5, lr}
800542e: 4d07 ldr r5, [pc, #28] @ (800544c <_fstat_r+0x20>)
8005430: 2300 movs r3, #0
8005432: 4604 mov r4, r0
8005434: 4608 mov r0, r1
8005436: 4611 mov r1, r2
8005438: 602b str r3, [r5, #0]
800543a: f7fc fa6e bl 800191a <_fstat>
800543e: 1c43 adds r3, r0, #1
8005440: d102 bne.n 8005448 <_fstat_r+0x1c>
8005442: 682b ldr r3, [r5, #0]
8005444: b103 cbz r3, 8005448 <_fstat_r+0x1c>
8005446: 6023 str r3, [r4, #0]
8005448: bd38 pop {r3, r4, r5, pc}
800544a: bf00 nop
800544c: 20000340 .word 0x20000340
08005450 <_isatty_r>:
8005450: b538 push {r3, r4, r5, lr}
8005452: 4d06 ldr r5, [pc, #24] @ (800546c <_isatty_r+0x1c>)
8005454: 2300 movs r3, #0
8005456: 4604 mov r4, r0
8005458: 4608 mov r0, r1
800545a: 602b str r3, [r5, #0]
800545c: f7fc fa6d bl 800193a <_isatty>
8005460: 1c43 adds r3, r0, #1
8005462: d102 bne.n 800546a <_isatty_r+0x1a>
8005464: 682b ldr r3, [r5, #0]
8005466: b103 cbz r3, 800546a <_isatty_r+0x1a>
8005468: 6023 str r3, [r4, #0]
800546a: bd38 pop {r3, r4, r5, pc}
800546c: 20000340 .word 0x20000340
08005470 <_init>:
8005470: b5f8 push {r3, r4, r5, r6, r7, lr}
8005472: bf00 nop
8005474: bcf8 pop {r3, r4, r5, r6, r7}
8005476: bc08 pop {r3}
8005478: 469e mov lr, r3
800547a: 4770 bx lr
0800547c <_fini>:
800547c: b5f8 push {r3, r4, r5, r6, r7, lr}
800547e: bf00 nop
8005480: bcf8 pop {r3, r4, r5, r6, r7}
8005482: bc08 pop {r3}
8005484: 469e mov lr, r3
8005486: 4770 bx lr
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