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HAW-LA_s7-prakt-mikrocontro.../Versuch1/Debug/Versuch1.list
jonny 8c10217a89 init - V1 complete, V2 started
2025-11-16 19:48:16 +01:00

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Versuch1.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001e0 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00004710 080001e0 080001e0 000011e0 2**4
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 0000005c 080048f0 080048f0 000058f0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 0800494c 0800494c 00006068 2**0
CONTENTS, READONLY
4 .ARM 00000008 0800494c 0800494c 0000594c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08004954 08004954 00006068 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08004954 08004954 00005954 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08004958 08004958 00005958 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000068 20000000 0800495c 00006000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000244 20000068 080049c4 00006068 2**2
ALLOC
10 ._user_heap_stack 00000604 200002ac 080049c4 000062ac 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 00006068 2**0
CONTENTS, READONLY
12 .debug_info 0000fda3 00000000 00000000 00006098 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000022da 00000000 00000000 00015e3b 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000e30 00000000 00000000 00018118 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00000b05 00000000 00000000 00018f48 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00023e2c 00000000 00000000 00019a4d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00010512 00000000 00000000 0003d879 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000e02f2 00000000 00000000 0004dd8b 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 0012e07d 2**0
CONTENTS, READONLY
20 .debug_frame 00004244 00000000 00000000 0012e0c0 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 0000007e 00000000 00000000 00132304 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001e0 <__do_global_dtors_aux>:
80001e0: b510 push {r4, lr}
80001e2: 4c05 ldr r4, [pc, #20] @ (80001f8 <__do_global_dtors_aux+0x18>)
80001e4: 7823 ldrb r3, [r4, #0]
80001e6: b933 cbnz r3, 80001f6 <__do_global_dtors_aux+0x16>
80001e8: 4b04 ldr r3, [pc, #16] @ (80001fc <__do_global_dtors_aux+0x1c>)
80001ea: b113 cbz r3, 80001f2 <__do_global_dtors_aux+0x12>
80001ec: 4804 ldr r0, [pc, #16] @ (8000200 <__do_global_dtors_aux+0x20>)
80001ee: f3af 8000 nop.w
80001f2: 2301 movs r3, #1
80001f4: 7023 strb r3, [r4, #0]
80001f6: bd10 pop {r4, pc}
80001f8: 20000068 .word 0x20000068
80001fc: 00000000 .word 0x00000000
8000200: 080048d8 .word 0x080048d8
08000204 <frame_dummy>:
8000204: b508 push {r3, lr}
8000206: 4b03 ldr r3, [pc, #12] @ (8000214 <frame_dummy+0x10>)
8000208: b11b cbz r3, 8000212 <frame_dummy+0xe>
800020a: 4903 ldr r1, [pc, #12] @ (8000218 <frame_dummy+0x14>)
800020c: 4803 ldr r0, [pc, #12] @ (800021c <frame_dummy+0x18>)
800020e: f3af 8000 nop.w
8000212: bd08 pop {r3, pc}
8000214: 00000000 .word 0x00000000
8000218: 2000006c .word 0x2000006c
800021c: 080048d8 .word 0x080048d8
08000220 <memchr>:
8000220: f001 01ff and.w r1, r1, #255 @ 0xff
8000224: 2a10 cmp r2, #16
8000226: db2b blt.n 8000280 <memchr+0x60>
8000228: f010 0f07 tst.w r0, #7
800022c: d008 beq.n 8000240 <memchr+0x20>
800022e: f810 3b01 ldrb.w r3, [r0], #1
8000232: 3a01 subs r2, #1
8000234: 428b cmp r3, r1
8000236: d02d beq.n 8000294 <memchr+0x74>
8000238: f010 0f07 tst.w r0, #7
800023c: b342 cbz r2, 8000290 <memchr+0x70>
800023e: d1f6 bne.n 800022e <memchr+0xe>
8000240: b4f0 push {r4, r5, r6, r7}
8000242: ea41 2101 orr.w r1, r1, r1, lsl #8
8000246: ea41 4101 orr.w r1, r1, r1, lsl #16
800024a: f022 0407 bic.w r4, r2, #7
800024e: f07f 0700 mvns.w r7, #0
8000252: 2300 movs r3, #0
8000254: e8f0 5602 ldrd r5, r6, [r0], #8
8000258: 3c08 subs r4, #8
800025a: ea85 0501 eor.w r5, r5, r1
800025e: ea86 0601 eor.w r6, r6, r1
8000262: fa85 f547 uadd8 r5, r5, r7
8000266: faa3 f587 sel r5, r3, r7
800026a: fa86 f647 uadd8 r6, r6, r7
800026e: faa5 f687 sel r6, r5, r7
8000272: b98e cbnz r6, 8000298 <memchr+0x78>
8000274: d1ee bne.n 8000254 <memchr+0x34>
8000276: bcf0 pop {r4, r5, r6, r7}
8000278: f001 01ff and.w r1, r1, #255 @ 0xff
800027c: f002 0207 and.w r2, r2, #7
8000280: b132 cbz r2, 8000290 <memchr+0x70>
8000282: f810 3b01 ldrb.w r3, [r0], #1
8000286: 3a01 subs r2, #1
8000288: ea83 0301 eor.w r3, r3, r1
800028c: b113 cbz r3, 8000294 <memchr+0x74>
800028e: d1f8 bne.n 8000282 <memchr+0x62>
8000290: 2000 movs r0, #0
8000292: 4770 bx lr
8000294: 3801 subs r0, #1
8000296: 4770 bx lr
8000298: 2d00 cmp r5, #0
800029a: bf06 itte eq
800029c: 4635 moveq r5, r6
800029e: 3803 subeq r0, #3
80002a0: 3807 subne r0, #7
80002a2: f015 0f01 tst.w r5, #1
80002a6: d107 bne.n 80002b8 <memchr+0x98>
80002a8: 3001 adds r0, #1
80002aa: f415 7f80 tst.w r5, #256 @ 0x100
80002ae: bf02 ittt eq
80002b0: 3001 addeq r0, #1
80002b2: f415 3fc0 tsteq.w r5, #98304 @ 0x18000
80002b6: 3001 addeq r0, #1
80002b8: bcf0 pop {r4, r5, r6, r7}
80002ba: 3801 subs r0, #1
80002bc: 4770 bx lr
80002be: bf00 nop
080002c0 <__aeabi_uldivmod>:
80002c0: b953 cbnz r3, 80002d8 <__aeabi_uldivmod+0x18>
80002c2: b94a cbnz r2, 80002d8 <__aeabi_uldivmod+0x18>
80002c4: 2900 cmp r1, #0
80002c6: bf08 it eq
80002c8: 2800 cmpeq r0, #0
80002ca: bf1c itt ne
80002cc: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
80002d0: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
80002d4: f000 b988 b.w 80005e8 <__aeabi_idiv0>
80002d8: f1ad 0c08 sub.w ip, sp, #8
80002dc: e96d ce04 strd ip, lr, [sp, #-16]!
80002e0: f000 f806 bl 80002f0 <__udivmoddi4>
80002e4: f8dd e004 ldr.w lr, [sp, #4]
80002e8: e9dd 2302 ldrd r2, r3, [sp, #8]
80002ec: b004 add sp, #16
80002ee: 4770 bx lr
080002f0 <__udivmoddi4>:
80002f0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80002f4: 9d08 ldr r5, [sp, #32]
80002f6: 468e mov lr, r1
80002f8: 4604 mov r4, r0
80002fa: 4688 mov r8, r1
80002fc: 2b00 cmp r3, #0
80002fe: d14a bne.n 8000396 <__udivmoddi4+0xa6>
8000300: 428a cmp r2, r1
8000302: 4617 mov r7, r2
8000304: d962 bls.n 80003cc <__udivmoddi4+0xdc>
8000306: fab2 f682 clz r6, r2
800030a: b14e cbz r6, 8000320 <__udivmoddi4+0x30>
800030c: f1c6 0320 rsb r3, r6, #32
8000310: fa01 f806 lsl.w r8, r1, r6
8000314: fa20 f303 lsr.w r3, r0, r3
8000318: 40b7 lsls r7, r6
800031a: ea43 0808 orr.w r8, r3, r8
800031e: 40b4 lsls r4, r6
8000320: ea4f 4e17 mov.w lr, r7, lsr #16
8000324: fa1f fc87 uxth.w ip, r7
8000328: fbb8 f1fe udiv r1, r8, lr
800032c: 0c23 lsrs r3, r4, #16
800032e: fb0e 8811 mls r8, lr, r1, r8
8000332: ea43 4308 orr.w r3, r3, r8, lsl #16
8000336: fb01 f20c mul.w r2, r1, ip
800033a: 429a cmp r2, r3
800033c: d909 bls.n 8000352 <__udivmoddi4+0x62>
800033e: 18fb adds r3, r7, r3
8000340: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
8000344: f080 80ea bcs.w 800051c <__udivmoddi4+0x22c>
8000348: 429a cmp r2, r3
800034a: f240 80e7 bls.w 800051c <__udivmoddi4+0x22c>
800034e: 3902 subs r1, #2
8000350: 443b add r3, r7
8000352: 1a9a subs r2, r3, r2
8000354: b2a3 uxth r3, r4
8000356: fbb2 f0fe udiv r0, r2, lr
800035a: fb0e 2210 mls r2, lr, r0, r2
800035e: ea43 4302 orr.w r3, r3, r2, lsl #16
8000362: fb00 fc0c mul.w ip, r0, ip
8000366: 459c cmp ip, r3
8000368: d909 bls.n 800037e <__udivmoddi4+0x8e>
800036a: 18fb adds r3, r7, r3
800036c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
8000370: f080 80d6 bcs.w 8000520 <__udivmoddi4+0x230>
8000374: 459c cmp ip, r3
8000376: f240 80d3 bls.w 8000520 <__udivmoddi4+0x230>
800037a: 443b add r3, r7
800037c: 3802 subs r0, #2
800037e: ea40 4001 orr.w r0, r0, r1, lsl #16
8000382: eba3 030c sub.w r3, r3, ip
8000386: 2100 movs r1, #0
8000388: b11d cbz r5, 8000392 <__udivmoddi4+0xa2>
800038a: 40f3 lsrs r3, r6
800038c: 2200 movs r2, #0
800038e: e9c5 3200 strd r3, r2, [r5]
8000392: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000396: 428b cmp r3, r1
8000398: d905 bls.n 80003a6 <__udivmoddi4+0xb6>
800039a: b10d cbz r5, 80003a0 <__udivmoddi4+0xb0>
800039c: e9c5 0100 strd r0, r1, [r5]
80003a0: 2100 movs r1, #0
80003a2: 4608 mov r0, r1
80003a4: e7f5 b.n 8000392 <__udivmoddi4+0xa2>
80003a6: fab3 f183 clz r1, r3
80003aa: 2900 cmp r1, #0
80003ac: d146 bne.n 800043c <__udivmoddi4+0x14c>
80003ae: 4573 cmp r3, lr
80003b0: d302 bcc.n 80003b8 <__udivmoddi4+0xc8>
80003b2: 4282 cmp r2, r0
80003b4: f200 8105 bhi.w 80005c2 <__udivmoddi4+0x2d2>
80003b8: 1a84 subs r4, r0, r2
80003ba: eb6e 0203 sbc.w r2, lr, r3
80003be: 2001 movs r0, #1
80003c0: 4690 mov r8, r2
80003c2: 2d00 cmp r5, #0
80003c4: d0e5 beq.n 8000392 <__udivmoddi4+0xa2>
80003c6: e9c5 4800 strd r4, r8, [r5]
80003ca: e7e2 b.n 8000392 <__udivmoddi4+0xa2>
80003cc: 2a00 cmp r2, #0
80003ce: f000 8090 beq.w 80004f2 <__udivmoddi4+0x202>
80003d2: fab2 f682 clz r6, r2
80003d6: 2e00 cmp r6, #0
80003d8: f040 80a4 bne.w 8000524 <__udivmoddi4+0x234>
80003dc: 1a8a subs r2, r1, r2
80003de: 0c03 lsrs r3, r0, #16
80003e0: ea4f 4e17 mov.w lr, r7, lsr #16
80003e4: b280 uxth r0, r0
80003e6: b2bc uxth r4, r7
80003e8: 2101 movs r1, #1
80003ea: fbb2 fcfe udiv ip, r2, lr
80003ee: fb0e 221c mls r2, lr, ip, r2
80003f2: ea43 4302 orr.w r3, r3, r2, lsl #16
80003f6: fb04 f20c mul.w r2, r4, ip
80003fa: 429a cmp r2, r3
80003fc: d907 bls.n 800040e <__udivmoddi4+0x11e>
80003fe: 18fb adds r3, r7, r3
8000400: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
8000404: d202 bcs.n 800040c <__udivmoddi4+0x11c>
8000406: 429a cmp r2, r3
8000408: f200 80e0 bhi.w 80005cc <__udivmoddi4+0x2dc>
800040c: 46c4 mov ip, r8
800040e: 1a9b subs r3, r3, r2
8000410: fbb3 f2fe udiv r2, r3, lr
8000414: fb0e 3312 mls r3, lr, r2, r3
8000418: ea40 4303 orr.w r3, r0, r3, lsl #16
800041c: fb02 f404 mul.w r4, r2, r4
8000420: 429c cmp r4, r3
8000422: d907 bls.n 8000434 <__udivmoddi4+0x144>
8000424: 18fb adds r3, r7, r3
8000426: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
800042a: d202 bcs.n 8000432 <__udivmoddi4+0x142>
800042c: 429c cmp r4, r3
800042e: f200 80ca bhi.w 80005c6 <__udivmoddi4+0x2d6>
8000432: 4602 mov r2, r0
8000434: 1b1b subs r3, r3, r4
8000436: ea42 400c orr.w r0, r2, ip, lsl #16
800043a: e7a5 b.n 8000388 <__udivmoddi4+0x98>
800043c: f1c1 0620 rsb r6, r1, #32
8000440: 408b lsls r3, r1
8000442: fa22 f706 lsr.w r7, r2, r6
8000446: 431f orrs r7, r3
8000448: fa0e f401 lsl.w r4, lr, r1
800044c: fa20 f306 lsr.w r3, r0, r6
8000450: fa2e fe06 lsr.w lr, lr, r6
8000454: ea4f 4917 mov.w r9, r7, lsr #16
8000458: 4323 orrs r3, r4
800045a: fa00 f801 lsl.w r8, r0, r1
800045e: fa1f fc87 uxth.w ip, r7
8000462: fbbe f0f9 udiv r0, lr, r9
8000466: 0c1c lsrs r4, r3, #16
8000468: fb09 ee10 mls lr, r9, r0, lr
800046c: ea44 440e orr.w r4, r4, lr, lsl #16
8000470: fb00 fe0c mul.w lr, r0, ip
8000474: 45a6 cmp lr, r4
8000476: fa02 f201 lsl.w r2, r2, r1
800047a: d909 bls.n 8000490 <__udivmoddi4+0x1a0>
800047c: 193c adds r4, r7, r4
800047e: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
8000482: f080 809c bcs.w 80005be <__udivmoddi4+0x2ce>
8000486: 45a6 cmp lr, r4
8000488: f240 8099 bls.w 80005be <__udivmoddi4+0x2ce>
800048c: 3802 subs r0, #2
800048e: 443c add r4, r7
8000490: eba4 040e sub.w r4, r4, lr
8000494: fa1f fe83 uxth.w lr, r3
8000498: fbb4 f3f9 udiv r3, r4, r9
800049c: fb09 4413 mls r4, r9, r3, r4
80004a0: ea4e 4404 orr.w r4, lr, r4, lsl #16
80004a4: fb03 fc0c mul.w ip, r3, ip
80004a8: 45a4 cmp ip, r4
80004aa: d908 bls.n 80004be <__udivmoddi4+0x1ce>
80004ac: 193c adds r4, r7, r4
80004ae: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
80004b2: f080 8082 bcs.w 80005ba <__udivmoddi4+0x2ca>
80004b6: 45a4 cmp ip, r4
80004b8: d97f bls.n 80005ba <__udivmoddi4+0x2ca>
80004ba: 3b02 subs r3, #2
80004bc: 443c add r4, r7
80004be: ea43 4000 orr.w r0, r3, r0, lsl #16
80004c2: eba4 040c sub.w r4, r4, ip
80004c6: fba0 ec02 umull lr, ip, r0, r2
80004ca: 4564 cmp r4, ip
80004cc: 4673 mov r3, lr
80004ce: 46e1 mov r9, ip
80004d0: d362 bcc.n 8000598 <__udivmoddi4+0x2a8>
80004d2: d05f beq.n 8000594 <__udivmoddi4+0x2a4>
80004d4: b15d cbz r5, 80004ee <__udivmoddi4+0x1fe>
80004d6: ebb8 0203 subs.w r2, r8, r3
80004da: eb64 0409 sbc.w r4, r4, r9
80004de: fa04 f606 lsl.w r6, r4, r6
80004e2: fa22 f301 lsr.w r3, r2, r1
80004e6: 431e orrs r6, r3
80004e8: 40cc lsrs r4, r1
80004ea: e9c5 6400 strd r6, r4, [r5]
80004ee: 2100 movs r1, #0
80004f0: e74f b.n 8000392 <__udivmoddi4+0xa2>
80004f2: fbb1 fcf2 udiv ip, r1, r2
80004f6: 0c01 lsrs r1, r0, #16
80004f8: ea41 410e orr.w r1, r1, lr, lsl #16
80004fc: b280 uxth r0, r0
80004fe: ea40 4201 orr.w r2, r0, r1, lsl #16
8000502: 463b mov r3, r7
8000504: 4638 mov r0, r7
8000506: 463c mov r4, r7
8000508: 46b8 mov r8, r7
800050a: 46be mov lr, r7
800050c: 2620 movs r6, #32
800050e: fbb1 f1f7 udiv r1, r1, r7
8000512: eba2 0208 sub.w r2, r2, r8
8000516: ea41 410c orr.w r1, r1, ip, lsl #16
800051a: e766 b.n 80003ea <__udivmoddi4+0xfa>
800051c: 4601 mov r1, r0
800051e: e718 b.n 8000352 <__udivmoddi4+0x62>
8000520: 4610 mov r0, r2
8000522: e72c b.n 800037e <__udivmoddi4+0x8e>
8000524: f1c6 0220 rsb r2, r6, #32
8000528: fa2e f302 lsr.w r3, lr, r2
800052c: 40b7 lsls r7, r6
800052e: 40b1 lsls r1, r6
8000530: fa20 f202 lsr.w r2, r0, r2
8000534: ea4f 4e17 mov.w lr, r7, lsr #16
8000538: 430a orrs r2, r1
800053a: fbb3 f8fe udiv r8, r3, lr
800053e: b2bc uxth r4, r7
8000540: fb0e 3318 mls r3, lr, r8, r3
8000544: 0c11 lsrs r1, r2, #16
8000546: ea41 4103 orr.w r1, r1, r3, lsl #16
800054a: fb08 f904 mul.w r9, r8, r4
800054e: 40b0 lsls r0, r6
8000550: 4589 cmp r9, r1
8000552: ea4f 4310 mov.w r3, r0, lsr #16
8000556: b280 uxth r0, r0
8000558: d93e bls.n 80005d8 <__udivmoddi4+0x2e8>
800055a: 1879 adds r1, r7, r1
800055c: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
8000560: d201 bcs.n 8000566 <__udivmoddi4+0x276>
8000562: 4589 cmp r9, r1
8000564: d81f bhi.n 80005a6 <__udivmoddi4+0x2b6>
8000566: eba1 0109 sub.w r1, r1, r9
800056a: fbb1 f9fe udiv r9, r1, lr
800056e: fb09 f804 mul.w r8, r9, r4
8000572: fb0e 1119 mls r1, lr, r9, r1
8000576: b292 uxth r2, r2
8000578: ea42 4201 orr.w r2, r2, r1, lsl #16
800057c: 4542 cmp r2, r8
800057e: d229 bcs.n 80005d4 <__udivmoddi4+0x2e4>
8000580: 18ba adds r2, r7, r2
8000582: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
8000586: d2c4 bcs.n 8000512 <__udivmoddi4+0x222>
8000588: 4542 cmp r2, r8
800058a: d2c2 bcs.n 8000512 <__udivmoddi4+0x222>
800058c: f1a9 0102 sub.w r1, r9, #2
8000590: 443a add r2, r7
8000592: e7be b.n 8000512 <__udivmoddi4+0x222>
8000594: 45f0 cmp r8, lr
8000596: d29d bcs.n 80004d4 <__udivmoddi4+0x1e4>
8000598: ebbe 0302 subs.w r3, lr, r2
800059c: eb6c 0c07 sbc.w ip, ip, r7
80005a0: 3801 subs r0, #1
80005a2: 46e1 mov r9, ip
80005a4: e796 b.n 80004d4 <__udivmoddi4+0x1e4>
80005a6: eba7 0909 sub.w r9, r7, r9
80005aa: 4449 add r1, r9
80005ac: f1a8 0c02 sub.w ip, r8, #2
80005b0: fbb1 f9fe udiv r9, r1, lr
80005b4: fb09 f804 mul.w r8, r9, r4
80005b8: e7db b.n 8000572 <__udivmoddi4+0x282>
80005ba: 4673 mov r3, lr
80005bc: e77f b.n 80004be <__udivmoddi4+0x1ce>
80005be: 4650 mov r0, sl
80005c0: e766 b.n 8000490 <__udivmoddi4+0x1a0>
80005c2: 4608 mov r0, r1
80005c4: e6fd b.n 80003c2 <__udivmoddi4+0xd2>
80005c6: 443b add r3, r7
80005c8: 3a02 subs r2, #2
80005ca: e733 b.n 8000434 <__udivmoddi4+0x144>
80005cc: f1ac 0c02 sub.w ip, ip, #2
80005d0: 443b add r3, r7
80005d2: e71c b.n 800040e <__udivmoddi4+0x11e>
80005d4: 4649 mov r1, r9
80005d6: e79c b.n 8000512 <__udivmoddi4+0x222>
80005d8: eba1 0109 sub.w r1, r1, r9
80005dc: 46c4 mov ip, r8
80005de: fbb1 f9fe udiv r9, r1, lr
80005e2: fb09 f804 mul.w r8, r9, r4
80005e6: e7c4 b.n 8000572 <__udivmoddi4+0x282>
080005e8 <__aeabi_idiv0>:
80005e8: 4770 bx lr
80005ea: bf00 nop
080005ec <_write>:
int _write( int file, char *ptr, int len );
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
int _write( int file, char *ptr, int len ){
80005ec: b580 push {r7, lr}
80005ee: b084 sub sp, #16
80005f0: af00 add r7, sp, #0
80005f2: 60f8 str r0, [r7, #12]
80005f4: 60b9 str r1, [r7, #8]
80005f6: 607a str r2, [r7, #4]
HAL_UART_Transmit(&huart6, (uint8_t*)ptr, len, 1000);
80005f8: 687b ldr r3, [r7, #4]
80005fa: b29a uxth r2, r3
80005fc: f44f 737a mov.w r3, #1000 @ 0x3e8
8000600: 68b9 ldr r1, [r7, #8]
8000602: 4804 ldr r0, [pc, #16] @ (8000614 <_write+0x28>)
8000604: f002 fd82 bl 800310c <HAL_UART_Transmit>
return len;
8000608: 687b ldr r3, [r7, #4]
}
800060a: 4618 mov r0, r3
800060c: 3710 adds r7, #16
800060e: 46bd mov sp, r7
8000610: bd80 pop {r7, pc}
8000612: bf00 nop
8000614: 20000084 .word 0x20000084
08000618 <time_msPassedSince>:
// get time in ms passed since a timestamp
uint32_t time_msPassedSince(uint32_t timestampOld)
{
8000618: b580 push {r7, lr}
800061a: b082 sub sp, #8
800061c: af00 add r7, sp, #0
800061e: 6078 str r0, [r7, #4]
return (uint32_t)(HAL_GetTick() - timestampOld);
8000620: f000 ff1c bl 800145c <HAL_GetTick>
8000624: 4602 mov r2, r0
8000626: 687b ldr r3, [r7, #4]
8000628: 1ad3 subs r3, r2, r3
}
800062a: 4618 mov r0, r3
800062c: 3708 adds r7, #8
800062e: 46bd mov sp, r7
8000630: bd80 pop {r7, pc}
...
08000634 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000634: b580 push {r7, lr}
8000636: b084 sub sp, #16
8000638: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
800063a: f000 feee bl 800141a <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
800063e: f000 f847 bl 80006d0 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000642: f000 f8e5 bl 8000810 <MX_GPIO_Init>
MX_USART6_UART_Init();
8000646: f000 f8b3 bl 80007b0 <MX_USART6_UART_Init>
/* USER CODE BEGIN 2 */
// local variables
uint32_t timestamp_lastBlinked = HAL_GetTick();
800064a: f000 ff07 bl 800145c <HAL_GetTick>
800064e: 60f8 str r0, [r7, #12]
uint32_t timestamp_lastButtonPolled = timestamp_lastBlinked;
8000650: 68fb ldr r3, [r7, #12]
8000652: 60bb str r3, [r7, #8]
uint32_t timestamp_lastHelloPrinted = timestamp_lastBlinked;
8000654: 68fb ldr r3, [r7, #12]
8000656: 607b str r3, [r7, #4]
uint8_t printCount = 0;
8000658: 2300 movs r3, #0
800065a: 70fb strb r3, [r7, #3]
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
// blink blue led (toggle state every 500ms)
if (time_msPassedSince(timestamp_lastBlinked) >= 500) {
800065c: 68f8 ldr r0, [r7, #12]
800065e: f7ff ffdb bl 8000618 <time_msPassedSince>
8000662: 4603 mov r3, r0
8000664: f5b3 7ffa cmp.w r3, #500 @ 0x1f4
8000668: d306 bcc.n 8000678 <main+0x44>
HAL_GPIO_TogglePin(LED_BLUE_GPIO_PORT, LED_BLUE_GPIO_PIN);
800066a: 2105 movs r1, #5
800066c: 4816 ldr r0, [pc, #88] @ (80006c8 <main+0x94>)
800066e: f001 f9b0 bl 80019d2 <HAL_GPIO_TogglePin>
timestamp_lastBlinked = HAL_GetTick();
8000672: f000 fef3 bl 800145c <HAL_GetTick>
8000676: 60f8 str r0, [r7, #12]
}
// poll button every 25ms and set red-led accordingly
if (time_msPassedSince(timestamp_lastButtonPolled) >= 25) {
8000678: 68b8 ldr r0, [r7, #8]
800067a: f7ff ffcd bl 8000618 <time_msPassedSince>
800067e: 4603 mov r3, r0
8000680: 2b18 cmp r3, #24
8000682: d90e bls.n 80006a2 <main+0x6e>
GPIO_PinState buttonState = HAL_GPIO_ReadPin(BUTTON_GPIO_PORT, BUTTON_GPIO_PIN);
8000684: 2100 movs r1, #0
8000686: 4810 ldr r0, [pc, #64] @ (80006c8 <main+0x94>)
8000688: f001 f972 bl 8001970 <HAL_GPIO_ReadPin>
800068c: 4603 mov r3, r0
800068e: 70bb strb r3, [r7, #2]
HAL_GPIO_WritePin(LED_RED_GPIO_PORT, LED_RED_GPIO_PIN, buttonState);
8000690: 78bb ldrb r3, [r7, #2]
8000692: 461a mov r2, r3
8000694: 2107 movs r1, #7
8000696: 480c ldr r0, [pc, #48] @ (80006c8 <main+0x94>)
8000698: f001 f982 bl 80019a0 <HAL_GPIO_WritePin>
timestamp_lastButtonPolled = HAL_GetTick();
800069c: f000 fede bl 800145c <HAL_GetTick>
80006a0: 60b8 str r0, [r7, #8]
}
// print "Hallo Welt" via UART every 1000ms
if (time_msPassedSince(timestamp_lastHelloPrinted) >= 1000) {
80006a2: 6878 ldr r0, [r7, #4]
80006a4: f7ff ffb8 bl 8000618 <time_msPassedSince>
80006a8: 4603 mov r3, r0
80006aa: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
80006ae: d3d5 bcc.n 800065c <main+0x28>
printf("Hallo Welt %d\n", printCount++);
80006b0: 78fb ldrb r3, [r7, #3]
80006b2: 1c5a adds r2, r3, #1
80006b4: 70fa strb r2, [r7, #3]
80006b6: 4619 mov r1, r3
80006b8: 4804 ldr r0, [pc, #16] @ (80006cc <main+0x98>)
80006ba: f003 faa1 bl 8003c00 <iprintf>
timestamp_lastHelloPrinted = HAL_GetTick();
80006be: f000 fecd bl 800145c <HAL_GetTick>
80006c2: 6078 str r0, [r7, #4]
if (time_msPassedSince(timestamp_lastBlinked) >= 500) {
80006c4: e7ca b.n 800065c <main+0x28>
80006c6: bf00 nop
80006c8: 40020000 .word 0x40020000
80006cc: 080048f0 .word 0x080048f0
080006d0 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80006d0: b580 push {r7, lr}
80006d2: b094 sub sp, #80 @ 0x50
80006d4: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80006d6: f107 0320 add.w r3, r7, #32
80006da: 2230 movs r2, #48 @ 0x30
80006dc: 2100 movs r1, #0
80006de: 4618 mov r0, r3
80006e0: f003 fae3 bl 8003caa <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80006e4: f107 030c add.w r3, r7, #12
80006e8: 2200 movs r2, #0
80006ea: 601a str r2, [r3, #0]
80006ec: 605a str r2, [r3, #4]
80006ee: 609a str r2, [r3, #8]
80006f0: 60da str r2, [r3, #12]
80006f2: 611a str r2, [r3, #16]
/** Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess();
80006f4: f001 f988 bl 8001a08 <HAL_PWR_EnableBkUpAccess>
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
80006f8: 4b2b ldr r3, [pc, #172] @ (80007a8 <SystemClock_Config+0xd8>)
80006fa: 6c1b ldr r3, [r3, #64] @ 0x40
80006fc: 4a2a ldr r2, [pc, #168] @ (80007a8 <SystemClock_Config+0xd8>)
80006fe: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000702: 6413 str r3, [r2, #64] @ 0x40
8000704: 4b28 ldr r3, [pc, #160] @ (80007a8 <SystemClock_Config+0xd8>)
8000706: 6c1b ldr r3, [r3, #64] @ 0x40
8000708: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800070c: 60bb str r3, [r7, #8]
800070e: 68bb ldr r3, [r7, #8]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8000710: 4b26 ldr r3, [pc, #152] @ (80007ac <SystemClock_Config+0xdc>)
8000712: 681b ldr r3, [r3, #0]
8000714: 4a25 ldr r2, [pc, #148] @ (80007ac <SystemClock_Config+0xdc>)
8000716: f443 4340 orr.w r3, r3, #49152 @ 0xc000
800071a: 6013 str r3, [r2, #0]
800071c: 4b23 ldr r3, [pc, #140] @ (80007ac <SystemClock_Config+0xdc>)
800071e: 681b ldr r3, [r3, #0]
8000720: f403 4340 and.w r3, r3, #49152 @ 0xc000
8000724: 607b str r3, [r7, #4]
8000726: 687b ldr r3, [r7, #4]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8000728: 2301 movs r3, #1
800072a: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
800072c: f44f 3380 mov.w r3, #65536 @ 0x10000
8000730: 627b str r3, [r7, #36] @ 0x24
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000732: 2302 movs r3, #2
8000734: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
8000736: f44f 0380 mov.w r3, #4194304 @ 0x400000
800073a: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.PLL.PLLM = 25;
800073c: 2319 movs r3, #25
800073e: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.PLL.PLLN = 432;
8000740: f44f 73d8 mov.w r3, #432 @ 0x1b0
8000744: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8000746: 2302 movs r3, #2
8000748: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLQ = 9;
800074a: 2309 movs r3, #9
800074c: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800074e: f107 0320 add.w r3, r7, #32
8000752: 4618 mov r0, r3
8000754: f001 f9b8 bl 8001ac8 <HAL_RCC_OscConfig>
8000758: 4603 mov r3, r0
800075a: 2b00 cmp r3, #0
800075c: d001 beq.n 8000762 <SystemClock_Config+0x92>
{
Error_Handler();
800075e: f000 fc5d bl 800101c <Error_Handler>
}
/** Activate the Over-Drive mode
*/
if (HAL_PWREx_EnableOverDrive() != HAL_OK)
8000762: f001 f961 bl 8001a28 <HAL_PWREx_EnableOverDrive>
8000766: 4603 mov r3, r0
8000768: 2b00 cmp r3, #0
800076a: d001 beq.n 8000770 <SystemClock_Config+0xa0>
{
Error_Handler();
800076c: f000 fc56 bl 800101c <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000770: 230f movs r3, #15
8000772: 60fb str r3, [r7, #12]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000774: 2302 movs r3, #2
8000776: 613b str r3, [r7, #16]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000778: 2300 movs r3, #0
800077a: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
800077c: f44f 53a0 mov.w r3, #5120 @ 0x1400
8000780: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
8000782: f44f 5380 mov.w r3, #4096 @ 0x1000
8000786: 61fb str r3, [r7, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
8000788: f107 030c add.w r3, r7, #12
800078c: 2107 movs r1, #7
800078e: 4618 mov r0, r3
8000790: f001 fc3e bl 8002010 <HAL_RCC_ClockConfig>
8000794: 4603 mov r3, r0
8000796: 2b00 cmp r3, #0
8000798: d001 beq.n 800079e <SystemClock_Config+0xce>
{
Error_Handler();
800079a: f000 fc3f bl 800101c <Error_Handler>
}
}
800079e: bf00 nop
80007a0: 3750 adds r7, #80 @ 0x50
80007a2: 46bd mov sp, r7
80007a4: bd80 pop {r7, pc}
80007a6: bf00 nop
80007a8: 40023800 .word 0x40023800
80007ac: 40007000 .word 0x40007000
080007b0 <MX_USART6_UART_Init>:
* @brief USART6 Initialization Function
* @param None
* @retval None
*/
static void MX_USART6_UART_Init(void)
{
80007b0: b580 push {r7, lr}
80007b2: af00 add r7, sp, #0
/* USER CODE END USART6_Init 0 */
/* USER CODE BEGIN USART6_Init 1 */
/* USER CODE END USART6_Init 1 */
huart6.Instance = USART6;
80007b4: 4b14 ldr r3, [pc, #80] @ (8000808 <MX_USART6_UART_Init+0x58>)
80007b6: 4a15 ldr r2, [pc, #84] @ (800080c <MX_USART6_UART_Init+0x5c>)
80007b8: 601a str r2, [r3, #0]
huart6.Init.BaudRate = 115200;
80007ba: 4b13 ldr r3, [pc, #76] @ (8000808 <MX_USART6_UART_Init+0x58>)
80007bc: f44f 32e1 mov.w r2, #115200 @ 0x1c200
80007c0: 605a str r2, [r3, #4]
huart6.Init.WordLength = UART_WORDLENGTH_8B;
80007c2: 4b11 ldr r3, [pc, #68] @ (8000808 <MX_USART6_UART_Init+0x58>)
80007c4: 2200 movs r2, #0
80007c6: 609a str r2, [r3, #8]
huart6.Init.StopBits = UART_STOPBITS_1;
80007c8: 4b0f ldr r3, [pc, #60] @ (8000808 <MX_USART6_UART_Init+0x58>)
80007ca: 2200 movs r2, #0
80007cc: 60da str r2, [r3, #12]
huart6.Init.Parity = UART_PARITY_NONE;
80007ce: 4b0e ldr r3, [pc, #56] @ (8000808 <MX_USART6_UART_Init+0x58>)
80007d0: 2200 movs r2, #0
80007d2: 611a str r2, [r3, #16]
huart6.Init.Mode = UART_MODE_TX_RX;
80007d4: 4b0c ldr r3, [pc, #48] @ (8000808 <MX_USART6_UART_Init+0x58>)
80007d6: 220c movs r2, #12
80007d8: 615a str r2, [r3, #20]
huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80007da: 4b0b ldr r3, [pc, #44] @ (8000808 <MX_USART6_UART_Init+0x58>)
80007dc: 2200 movs r2, #0
80007de: 619a str r2, [r3, #24]
huart6.Init.OverSampling = UART_OVERSAMPLING_16;
80007e0: 4b09 ldr r3, [pc, #36] @ (8000808 <MX_USART6_UART_Init+0x58>)
80007e2: 2200 movs r2, #0
80007e4: 61da str r2, [r3, #28]
huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
80007e6: 4b08 ldr r3, [pc, #32] @ (8000808 <MX_USART6_UART_Init+0x58>)
80007e8: 2200 movs r2, #0
80007ea: 621a str r2, [r3, #32]
huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
80007ec: 4b06 ldr r3, [pc, #24] @ (8000808 <MX_USART6_UART_Init+0x58>)
80007ee: 2200 movs r2, #0
80007f0: 625a str r2, [r3, #36] @ 0x24
if (HAL_UART_Init(&huart6) != HAL_OK)
80007f2: 4805 ldr r0, [pc, #20] @ (8000808 <MX_USART6_UART_Init+0x58>)
80007f4: f002 fc3c bl 8003070 <HAL_UART_Init>
80007f8: 4603 mov r3, r0
80007fa: 2b00 cmp r3, #0
80007fc: d001 beq.n 8000802 <MX_USART6_UART_Init+0x52>
{
Error_Handler();
80007fe: f000 fc0d bl 800101c <Error_Handler>
}
/* USER CODE BEGIN USART6_Init 2 */
/* USER CODE END USART6_Init 2 */
}
8000802: bf00 nop
8000804: bd80 pop {r7, pc}
8000806: bf00 nop
8000808: 20000084 .word 0x20000084
800080c: 40011400 .word 0x40011400
08000810 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000810: b580 push {r7, lr}
8000812: b08e sub sp, #56 @ 0x38
8000814: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000816: f107 0324 add.w r3, r7, #36 @ 0x24
800081a: 2200 movs r2, #0
800081c: 601a str r2, [r3, #0]
800081e: 605a str r2, [r3, #4]
8000820: 609a str r2, [r3, #8]
8000822: 60da str r2, [r3, #12]
8000824: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
8000826: 4bb2 ldr r3, [pc, #712] @ (8000af0 <MX_GPIO_Init+0x2e0>)
8000828: 6b1b ldr r3, [r3, #48] @ 0x30
800082a: 4ab1 ldr r2, [pc, #708] @ (8000af0 <MX_GPIO_Init+0x2e0>)
800082c: f043 0310 orr.w r3, r3, #16
8000830: 6313 str r3, [r2, #48] @ 0x30
8000832: 4baf ldr r3, [pc, #700] @ (8000af0 <MX_GPIO_Init+0x2e0>)
8000834: 6b1b ldr r3, [r3, #48] @ 0x30
8000836: f003 0310 and.w r3, r3, #16
800083a: 623b str r3, [r7, #32]
800083c: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOB_CLK_ENABLE();
800083e: 4bac ldr r3, [pc, #688] @ (8000af0 <MX_GPIO_Init+0x2e0>)
8000840: 6b1b ldr r3, [r3, #48] @ 0x30
8000842: 4aab ldr r2, [pc, #684] @ (8000af0 <MX_GPIO_Init+0x2e0>)
8000844: f043 0302 orr.w r3, r3, #2
8000848: 6313 str r3, [r2, #48] @ 0x30
800084a: 4ba9 ldr r3, [pc, #676] @ (8000af0 <MX_GPIO_Init+0x2e0>)
800084c: 6b1b ldr r3, [r3, #48] @ 0x30
800084e: f003 0302 and.w r3, r3, #2
8000852: 61fb str r3, [r7, #28]
8000854: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOG_CLK_ENABLE();
8000856: 4ba6 ldr r3, [pc, #664] @ (8000af0 <MX_GPIO_Init+0x2e0>)
8000858: 6b1b ldr r3, [r3, #48] @ 0x30
800085a: 4aa5 ldr r2, [pc, #660] @ (8000af0 <MX_GPIO_Init+0x2e0>)
800085c: f043 0340 orr.w r3, r3, #64 @ 0x40
8000860: 6313 str r3, [r2, #48] @ 0x30
8000862: 4ba3 ldr r3, [pc, #652] @ (8000af0 <MX_GPIO_Init+0x2e0>)
8000864: 6b1b ldr r3, [r3, #48] @ 0x30
8000866: f003 0340 and.w r3, r3, #64 @ 0x40
800086a: 61bb str r3, [r7, #24]
800086c: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOD_CLK_ENABLE();
800086e: 4ba0 ldr r3, [pc, #640] @ (8000af0 <MX_GPIO_Init+0x2e0>)
8000870: 6b1b ldr r3, [r3, #48] @ 0x30
8000872: 4a9f ldr r2, [pc, #636] @ (8000af0 <MX_GPIO_Init+0x2e0>)
8000874: f043 0308 orr.w r3, r3, #8
8000878: 6313 str r3, [r2, #48] @ 0x30
800087a: 4b9d ldr r3, [pc, #628] @ (8000af0 <MX_GPIO_Init+0x2e0>)
800087c: 6b1b ldr r3, [r3, #48] @ 0x30
800087e: f003 0308 and.w r3, r3, #8
8000882: 617b str r3, [r7, #20]
8000884: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOC_CLK_ENABLE();
8000886: 4b9a ldr r3, [pc, #616] @ (8000af0 <MX_GPIO_Init+0x2e0>)
8000888: 6b1b ldr r3, [r3, #48] @ 0x30
800088a: 4a99 ldr r2, [pc, #612] @ (8000af0 <MX_GPIO_Init+0x2e0>)
800088c: f043 0304 orr.w r3, r3, #4
8000890: 6313 str r3, [r2, #48] @ 0x30
8000892: 4b97 ldr r3, [pc, #604] @ (8000af0 <MX_GPIO_Init+0x2e0>)
8000894: 6b1b ldr r3, [r3, #48] @ 0x30
8000896: f003 0304 and.w r3, r3, #4
800089a: 613b str r3, [r7, #16]
800089c: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800089e: 4b94 ldr r3, [pc, #592] @ (8000af0 <MX_GPIO_Init+0x2e0>)
80008a0: 6b1b ldr r3, [r3, #48] @ 0x30
80008a2: 4a93 ldr r2, [pc, #588] @ (8000af0 <MX_GPIO_Init+0x2e0>)
80008a4: f043 0301 orr.w r3, r3, #1
80008a8: 6313 str r3, [r2, #48] @ 0x30
80008aa: 4b91 ldr r3, [pc, #580] @ (8000af0 <MX_GPIO_Init+0x2e0>)
80008ac: 6b1b ldr r3, [r3, #48] @ 0x30
80008ae: f003 0301 and.w r3, r3, #1
80008b2: 60fb str r3, [r7, #12]
80008b4: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOI_CLK_ENABLE();
80008b6: 4b8e ldr r3, [pc, #568] @ (8000af0 <MX_GPIO_Init+0x2e0>)
80008b8: 6b1b ldr r3, [r3, #48] @ 0x30
80008ba: 4a8d ldr r2, [pc, #564] @ (8000af0 <MX_GPIO_Init+0x2e0>)
80008bc: f443 7380 orr.w r3, r3, #256 @ 0x100
80008c0: 6313 str r3, [r2, #48] @ 0x30
80008c2: 4b8b ldr r3, [pc, #556] @ (8000af0 <MX_GPIO_Init+0x2e0>)
80008c4: 6b1b ldr r3, [r3, #48] @ 0x30
80008c6: f403 7380 and.w r3, r3, #256 @ 0x100
80008ca: 60bb str r3, [r7, #8]
80008cc: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOH_CLK_ENABLE();
80008ce: 4b88 ldr r3, [pc, #544] @ (8000af0 <MX_GPIO_Init+0x2e0>)
80008d0: 6b1b ldr r3, [r3, #48] @ 0x30
80008d2: 4a87 ldr r2, [pc, #540] @ (8000af0 <MX_GPIO_Init+0x2e0>)
80008d4: f043 0380 orr.w r3, r3, #128 @ 0x80
80008d8: 6313 str r3, [r2, #48] @ 0x30
80008da: 4b85 ldr r3, [pc, #532] @ (8000af0 <MX_GPIO_Init+0x2e0>)
80008dc: 6b1b ldr r3, [r3, #48] @ 0x30
80008de: f003 0380 and.w r3, r3, #128 @ 0x80
80008e2: 607b str r3, [r7, #4]
80008e4: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOF_CLK_ENABLE();
80008e6: 4b82 ldr r3, [pc, #520] @ (8000af0 <MX_GPIO_Init+0x2e0>)
80008e8: 6b1b ldr r3, [r3, #48] @ 0x30
80008ea: 4a81 ldr r2, [pc, #516] @ (8000af0 <MX_GPIO_Init+0x2e0>)
80008ec: f043 0320 orr.w r3, r3, #32
80008f0: 6313 str r3, [r2, #48] @ 0x30
80008f2: 4b7f ldr r3, [pc, #508] @ (8000af0 <MX_GPIO_Init+0x2e0>)
80008f4: 6b1b ldr r3, [r3, #48] @ 0x30
80008f6: f003 0320 and.w r3, r3, #32
80008fa: 603b str r3, [r7, #0]
80008fc: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, ARD_D7_GPIO_Pin|ARD_D8_GPIO_Pin, GPIO_PIN_RESET);
80008fe: 2200 movs r2, #0
8000900: 2118 movs r1, #24
8000902: 487c ldr r0, [pc, #496] @ (8000af4 <MX_GPIO_Init+0x2e4>)
8000904: f001 f84c bl 80019a0 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOG, WIFI_RST_Pin|WIFI_GPIO_0_Pin|PMOD_GPIO_0_Pin|USB_OTGFS_PPWR_EN_Pin, GPIO_PIN_RESET);
8000908: 2200 movs r2, #0
800090a: f44f 41e2 mov.w r1, #28928 @ 0x7100
800090e: 487a ldr r0, [pc, #488] @ (8000af8 <MX_GPIO_Init+0x2e8>)
8000910: f001 f846 bl 80019a0 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, WIFI_GPIO_2_Pin|WIFI_CH_PD_Pin, GPIO_PIN_RESET);
8000914: 2200 movs r2, #0
8000916: 2148 movs r1, #72 @ 0x48
8000918: 4878 ldr r0, [pc, #480] @ (8000afc <MX_GPIO_Init+0x2ec>)
800091a: f001 f841 bl 80019a0 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, STMOD_UART4_RXD_s_Pin|ARD_D2_GPIO_Pin, GPIO_PIN_RESET);
800091e: 2200 movs r2, #0
8000920: f44f 6102 mov.w r1, #2080 @ 0x820
8000924: 4876 ldr r0, [pc, #472] @ (8000b00 <MX_GPIO_Init+0x2f0>)
8000926: f001 f83b bl 80019a0 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOI, PMOD_SPI2_MOSI_Pin|PMOD_SPI2_MISO_Pin|GPIO_PIN_10, GPIO_PIN_RESET);
800092a: 2200 movs r2, #0
800092c: f240 410c movw r1, #1036 @ 0x40c
8000930: 4874 ldr r0, [pc, #464] @ (8000b04 <MX_GPIO_Init+0x2f4>)
8000932: f001 f835 bl 80019a0 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOH, PMOD_SEL_0_Pin|CTP_RST_Pin, GPIO_PIN_SET);
8000936: 2201 movs r2, #1
8000938: f44f 4102 mov.w r1, #33280 @ 0x8200
800093c: 4872 ldr r0, [pc, #456] @ (8000b08 <MX_GPIO_Init+0x2f8>)
800093e: f001 f82f bl 80019a0 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, USB_OTG_FS_ID_Pin|SYS_LD_USER1_Pin, GPIO_PIN_RESET);
8000942: 2200 movs r2, #0
8000944: f44f 6190 mov.w r1, #1152 @ 0x480
8000948: 4870 ldr r0, [pc, #448] @ (8000b0c <MX_GPIO_Init+0x2fc>)
800094a: f001 f829 bl 80019a0 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOH, PMOD_GPIO_1_Pin|ARD_D4_GPIO_Pin|USB_OTGHS_PPWR_EN_Pin|LCD_RST_Pin, GPIO_PIN_RESET);
800094e: 2200 movs r2, #0
8000950: f241 018c movw r1, #4236 @ 0x108c
8000954: 486c ldr r0, [pc, #432] @ (8000b08 <MX_GPIO_Init+0x2f8>)
8000956: f001 f823 bl 80019a0 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, USB_OTG_HS_ID_Pin|SYS_LD_USER2_Pin, GPIO_PIN_RESET);
800095a: 2200 movs r2, #0
800095c: f241 0102 movw r1, #4098 @ 0x1002
8000960: 486b ldr r0, [pc, #428] @ (8000b10 <MX_GPIO_Init+0x300>)
8000962: f001 f81d bl 80019a0 <HAL_GPIO_WritePin>
/*Configure GPIO pins : ARD_D7_GPIO_Pin ARD_D8_GPIO_Pin */
GPIO_InitStruct.Pin = ARD_D7_GPIO_Pin|ARD_D8_GPIO_Pin;
8000966: 2318 movs r3, #24
8000968: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800096a: 2301 movs r3, #1
800096c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800096e: 2300 movs r3, #0
8000970: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000972: 2300 movs r3, #0
8000974: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8000976: f107 0324 add.w r3, r7, #36 @ 0x24
800097a: 4619 mov r1, r3
800097c: 485d ldr r0, [pc, #372] @ (8000af4 <MX_GPIO_Init+0x2e4>)
800097e: f000 fe5b bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : QSPI_D2_Pin */
GPIO_InitStruct.Pin = QSPI_D2_Pin;
8000982: 2304 movs r3, #4
8000984: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000986: 2302 movs r3, #2
8000988: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800098a: 2300 movs r3, #0
800098c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800098e: 2303 movs r3, #3
8000990: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
8000992: 2309 movs r3, #9
8000994: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(QSPI_D2_GPIO_Port, &GPIO_InitStruct);
8000996: f107 0324 add.w r3, r7, #36 @ 0x24
800099a: 4619 mov r1, r3
800099c: 4855 ldr r0, [pc, #340] @ (8000af4 <MX_GPIO_Init+0x2e4>)
800099e: f000 fe4b bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : PSRAM_NBL1_Pin PSRAM_NBL0_Pin LCD_PSRAM_D10_Pin LCD_PSRAM_D5_Pin
LCD_PSRAM_D6_Pin LCD_PSRAM_D8_Pin LCD_PSRAM_D11_Pin LCD_PSRAM_D4_Pin
LCD_PSRAM_D7_Pin LCD_PSRAM_D9_Pin LCD_PSRAM_D12_Pin */
GPIO_InitStruct.Pin = PSRAM_NBL1_Pin|PSRAM_NBL0_Pin|LCD_PSRAM_D10_Pin|LCD_PSRAM_D5_Pin
80009a2: f64f 7383 movw r3, #65411 @ 0xff83
80009a6: 627b str r3, [r7, #36] @ 0x24
|LCD_PSRAM_D6_Pin|LCD_PSRAM_D8_Pin|LCD_PSRAM_D11_Pin|LCD_PSRAM_D4_Pin
|LCD_PSRAM_D7_Pin|LCD_PSRAM_D9_Pin|LCD_PSRAM_D12_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80009a8: 2302 movs r3, #2
80009aa: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80009ac: 2300 movs r3, #0
80009ae: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80009b0: 2303 movs r3, #3
80009b2: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80009b4: 230c movs r3, #12
80009b6: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
80009b8: f107 0324 add.w r3, r7, #36 @ 0x24
80009bc: 4619 mov r1, r3
80009be: 484d ldr r0, [pc, #308] @ (8000af4 <MX_GPIO_Init+0x2e4>)
80009c0: f000 fe3a bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : SAI2_I2C1_SCL_Pin SAI2_I2C1_SDA_Pin */
GPIO_InitStruct.Pin = SAI2_I2C1_SCL_Pin|SAI2_I2C1_SDA_Pin;
80009c4: f44f 7340 mov.w r3, #768 @ 0x300
80009c8: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
80009ca: 2312 movs r3, #18
80009cc: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80009ce: 2300 movs r3, #0
80009d0: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80009d2: 2303 movs r3, #3
80009d4: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
80009d6: 2304 movs r3, #4
80009d8: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80009da: f107 0324 add.w r3, r7, #36 @ 0x24
80009de: 4619 mov r1, r3
80009e0: 484b ldr r0, [pc, #300] @ (8000b10 <MX_GPIO_Init+0x300>)
80009e2: f000 fe29 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D11_TIM3_CH2_SPI1_MOSI_Pin ARD_D12_SPI1_MISO_Pin */
GPIO_InitStruct.Pin = ARD_D11_TIM3_CH2_SPI1_MOSI_Pin|ARD_D12_SPI1_MISO_Pin;
80009e6: 2330 movs r3, #48 @ 0x30
80009e8: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80009ea: 2302 movs r3, #2
80009ec: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80009ee: 2300 movs r3, #0
80009f0: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80009f2: 2303 movs r3, #3
80009f4: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
80009f6: 2305 movs r3, #5
80009f8: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80009fa: f107 0324 add.w r3, r7, #36 @ 0x24
80009fe: 4619 mov r1, r3
8000a00: 4843 ldr r0, [pc, #268] @ (8000b10 <MX_GPIO_Init+0x300>)
8000a02: f000 fe19 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : WIFI_RST_Pin WIFI_GPIO_0_Pin PMOD_GPIO_0_Pin USB_OTGFS_PPWR_EN_Pin */
GPIO_InitStruct.Pin = WIFI_RST_Pin|WIFI_GPIO_0_Pin|PMOD_GPIO_0_Pin|USB_OTGFS_PPWR_EN_Pin;
8000a06: f44f 43e2 mov.w r3, #28928 @ 0x7100
8000a0a: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000a0c: 2301 movs r3, #1
8000a0e: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a10: 2300 movs r3, #0
8000a12: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000a14: 2300 movs r3, #0
8000a16: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8000a18: f107 0324 add.w r3, r7, #36 @ 0x24
8000a1c: 4619 mov r1, r3
8000a1e: 4836 ldr r0, [pc, #216] @ (8000af8 <MX_GPIO_Init+0x2e8>)
8000a20: f000 fe0a bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : PSRAM_NE1_Pin LCD_PSRAM_D2_Pin LCD_PSRAM_NWE_Pin LCD_PSRAM_D3_Pin
LCD_PSRAM_NWED4_Pin LCD_PSRAM_D1_Pin LCD_PSRAM_D0_Pin PSRAM_A17_Pin
PSRAM_A16_Pin LCD_PSRAM_D15_Pin LCD_PSRAM_D14_Pin LCD_PSRAM_D13_Pin */
GPIO_InitStruct.Pin = PSRAM_NE1_Pin|LCD_PSRAM_D2_Pin|LCD_PSRAM_NWE_Pin|LCD_PSRAM_D3_Pin
8000a24: f64d 73b3 movw r3, #57267 @ 0xdfb3
8000a28: 627b str r3, [r7, #36] @ 0x24
|LCD_PSRAM_NWED4_Pin|LCD_PSRAM_D1_Pin|LCD_PSRAM_D0_Pin|PSRAM_A17_Pin
|PSRAM_A16_Pin|LCD_PSRAM_D15_Pin|LCD_PSRAM_D14_Pin|LCD_PSRAM_D13_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a2a: 2302 movs r3, #2
8000a2c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a2e: 2300 movs r3, #0
8000a30: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000a32: 2303 movs r3, #3
8000a34: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8000a36: 230c movs r3, #12
8000a38: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000a3a: f107 0324 add.w r3, r7, #36 @ 0x24
8000a3e: 4619 mov r1, r3
8000a40: 482e ldr r0, [pc, #184] @ (8000afc <MX_GPIO_Init+0x2ec>)
8000a42: f000 fdf9 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : UART_TXD_WIFI_RX_Pin */
GPIO_InitStruct.Pin = UART_TXD_WIFI_RX_Pin;
8000a46: f44f 5380 mov.w r3, #4096 @ 0x1000
8000a4a: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a4c: 2302 movs r3, #2
8000a4e: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a50: 2300 movs r3, #0
8000a52: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000a54: 2303 movs r3, #3
8000a56: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
8000a58: 2308 movs r3, #8
8000a5a: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(UART_TXD_WIFI_RX_GPIO_Port, &GPIO_InitStruct);
8000a5c: f107 0324 add.w r3, r7, #36 @ 0x24
8000a60: 4619 mov r1, r3
8000a62: 4827 ldr r0, [pc, #156] @ (8000b00 <MX_GPIO_Init+0x2f0>)
8000a64: f000 fde8 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : STMOD_TIM2_CH1_2_ETR_Pin ARD_D10_TIM2_CH2_SPI1_NSS_Pin */
GPIO_InitStruct.Pin = STMOD_TIM2_CH1_2_ETR_Pin|ARD_D10_TIM2_CH2_SPI1_NSS_Pin;
8000a68: f248 0302 movw r3, #32770 @ 0x8002
8000a6c: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a6e: 2302 movs r3, #2
8000a70: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a72: 2300 movs r3, #0
8000a74: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000a76: 2300 movs r3, #0
8000a78: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
8000a7a: 2301 movs r3, #1
8000a7c: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000a7e: f107 0324 add.w r3, r7, #36 @ 0x24
8000a82: 4619 mov r1, r3
8000a84: 4821 ldr r0, [pc, #132] @ (8000b0c <MX_GPIO_Init+0x2fc>)
8000a86: f000 fdd7 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D3_TIM9_CH1_Pin ARD_D6_TIM9_CH2_Pin */
GPIO_InitStruct.Pin = ARD_D3_TIM9_CH1_Pin|ARD_D6_TIM9_CH2_Pin;
8000a8a: 2360 movs r3, #96 @ 0x60
8000a8c: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a8e: 2302 movs r3, #2
8000a90: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a92: 2300 movs r3, #0
8000a94: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000a96: 2300 movs r3, #0
8000a98: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF3_TIM9;
8000a9a: 2303 movs r3, #3
8000a9c: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8000a9e: f107 0324 add.w r3, r7, #36 @ 0x24
8000aa2: 4619 mov r1, r3
8000aa4: 4813 ldr r0, [pc, #76] @ (8000af4 <MX_GPIO_Init+0x2e4>)
8000aa6: f000 fdc7 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : NC1_Pin */
GPIO_InitStruct.Pin = NC1_Pin;
8000aaa: 2380 movs r3, #128 @ 0x80
8000aac: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000aae: 2302 movs r3, #2
8000ab0: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ab2: 2300 movs r3, #0
8000ab4: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000ab6: 2303 movs r3, #3
8000ab8: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8000aba: 230c movs r3, #12
8000abc: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(NC1_GPIO_Port, &GPIO_InitStruct);
8000abe: f107 0324 add.w r3, r7, #36 @ 0x24
8000ac2: 4619 mov r1, r3
8000ac4: 4812 ldr r0, [pc, #72] @ (8000b10 <MX_GPIO_Init+0x300>)
8000ac6: f000 fdb7 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : QSPI_NCS_Pin */
GPIO_InitStruct.Pin = QSPI_NCS_Pin;
8000aca: 2340 movs r3, #64 @ 0x40
8000acc: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000ace: 2302 movs r3, #2
8000ad0: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ad2: 2300 movs r3, #0
8000ad4: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000ad6: 2303 movs r3, #3
8000ad8: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
8000ada: 230a movs r3, #10
8000adc: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(QSPI_NCS_GPIO_Port, &GPIO_InitStruct);
8000ade: f107 0324 add.w r3, r7, #36 @ 0x24
8000ae2: 4619 mov r1, r3
8000ae4: 480a ldr r0, [pc, #40] @ (8000b10 <MX_GPIO_Init+0x300>)
8000ae6: f000 fda7 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : SAI2_INT_Pin */
GPIO_InitStruct.Pin = SAI2_INT_Pin;
8000aea: f44f 4300 mov.w r3, #32768 @ 0x8000
8000aee: e011 b.n 8000b14 <MX_GPIO_Init+0x304>
8000af0: 40023800 .word 0x40023800
8000af4: 40021000 .word 0x40021000
8000af8: 40021800 .word 0x40021800
8000afc: 40020c00 .word 0x40020c00
8000b00: 40020800 .word 0x40020800
8000b04: 40022000 .word 0x40022000
8000b08: 40021c00 .word 0x40021c00
8000b0c: 40020000 .word 0x40020000
8000b10: 40020400 .word 0x40020400
8000b14: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000b16: f44f 1388 mov.w r3, #1114112 @ 0x110000
8000b1a: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b1c: 2300 movs r3, #0
8000b1e: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(SAI2_INT_GPIO_Port, &GPIO_InitStruct);
8000b20: f107 0324 add.w r3, r7, #36 @ 0x24
8000b24: 4619 mov r1, r3
8000b26: 48bd ldr r0, [pc, #756] @ (8000e1c <MX_GPIO_Init+0x60c>)
8000b28: f000 fd86 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : SAI2_SD_B_Pin */
GPIO_InitStruct.Pin = SAI2_SD_B_Pin;
8000b2c: f44f 6380 mov.w r3, #1024 @ 0x400
8000b30: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000b32: 2302 movs r3, #2
8000b34: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b36: 2300 movs r3, #0
8000b38: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000b3a: 2300 movs r3, #0
8000b3c: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF10_SAI2;
8000b3e: 230a movs r3, #10
8000b40: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(SAI2_SD_B_GPIO_Port, &GPIO_InitStruct);
8000b42: f107 0324 add.w r3, r7, #36 @ 0x24
8000b46: 4619 mov r1, r3
8000b48: 48b4 ldr r0, [pc, #720] @ (8000e1c <MX_GPIO_Init+0x60c>)
8000b4a: f000 fd75 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : WIFI_GPIO_2_Pin WIFI_CH_PD_Pin */
GPIO_InitStruct.Pin = WIFI_GPIO_2_Pin|WIFI_CH_PD_Pin;
8000b4e: 2348 movs r3, #72 @ 0x48
8000b50: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000b52: 2301 movs r3, #1
8000b54: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b56: 2300 movs r3, #0
8000b58: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000b5a: 2300 movs r3, #0
8000b5c: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000b5e: f107 0324 add.w r3, r7, #36 @ 0x24
8000b62: 4619 mov r1, r3
8000b64: 48ae ldr r0, [pc, #696] @ (8000e20 <MX_GPIO_Init+0x610>)
8000b66: f000 fd67 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : STMOD_UART4_RXD_s_Pin ARD_D2_GPIO_Pin */
GPIO_InitStruct.Pin = STMOD_UART4_RXD_s_Pin|ARD_D2_GPIO_Pin;
8000b6a: f44f 6302 mov.w r3, #2080 @ 0x820
8000b6e: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000b70: 2301 movs r3, #1
8000b72: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b74: 2300 movs r3, #0
8000b76: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000b78: 2300 movs r3, #0
8000b7a: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000b7c: f107 0324 add.w r3, r7, #36 @ 0x24
8000b80: 4619 mov r1, r3
8000b82: 48a8 ldr r0, [pc, #672] @ (8000e24 <MX_GPIO_Init+0x614>)
8000b84: f000 fd58 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : QSPI_D1_Pin QSPI_D0_Pin */
GPIO_InitStruct.Pin = QSPI_D1_Pin|QSPI_D0_Pin;
8000b88: f44f 63c0 mov.w r3, #1536 @ 0x600
8000b8c: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000b8e: 2302 movs r3, #2
8000b90: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b92: 2300 movs r3, #0
8000b94: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000b96: 2303 movs r3, #3
8000b98: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
8000b9a: 2309 movs r3, #9
8000b9c: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000b9e: f107 0324 add.w r3, r7, #36 @ 0x24
8000ba2: 4619 mov r1, r3
8000ba4: 489f ldr r0, [pc, #636] @ (8000e24 <MX_GPIO_Init+0x614>)
8000ba6: f000 fd47 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : PA12 PA11 */
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11;
8000baa: f44f 53c0 mov.w r3, #6144 @ 0x1800
8000bae: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000bb0: 2302 movs r3, #2
8000bb2: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000bb4: 2300 movs r3, #0
8000bb6: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000bb8: 2303 movs r3, #3
8000bba: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
8000bbc: 230a movs r3, #10
8000bbe: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000bc0: f107 0324 add.w r3, r7, #36 @ 0x24
8000bc4: 4619 mov r1, r3
8000bc6: 4898 ldr r0, [pc, #608] @ (8000e28 <MX_GPIO_Init+0x618>)
8000bc8: f000 fd36 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : SAI2_FS_A_Pin SAI2_SD_A_Pin SAI2_SCK_A_Pin SAI2_MCLK_A_Pin */
GPIO_InitStruct.Pin = SAI2_FS_A_Pin|SAI2_SD_A_Pin|SAI2_SCK_A_Pin|SAI2_MCLK_A_Pin;
8000bcc: 23f0 movs r3, #240 @ 0xf0
8000bce: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000bd0: 2302 movs r3, #2
8000bd2: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000bd4: 2300 movs r3, #0
8000bd6: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000bd8: 2300 movs r3, #0
8000bda: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF10_SAI2;
8000bdc: 230a movs r3, #10
8000bde: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8000be0: f107 0324 add.w r3, r7, #36 @ 0x24
8000be4: 4619 mov r1, r3
8000be6: 4891 ldr r0, [pc, #580] @ (8000e2c <MX_GPIO_Init+0x61c>)
8000be8: f000 fd26 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : LCD_NE_Pin PSRAM_A15_Pin PSRAM_A14_Pin PSRAM_A13_Pin
PSRAM_A12_Pin PSRAM_A11_Pin PSRAM_A10_Pin */
GPIO_InitStruct.Pin = LCD_NE_Pin|PSRAM_A15_Pin|PSRAM_A14_Pin|PSRAM_A13_Pin
8000bec: f240 233f movw r3, #575 @ 0x23f
8000bf0: 627b str r3, [r7, #36] @ 0x24
|PSRAM_A12_Pin|PSRAM_A11_Pin|PSRAM_A10_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000bf2: 2302 movs r3, #2
8000bf4: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000bf6: 2300 movs r3, #0
8000bf8: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000bfa: 2303 movs r3, #3
8000bfc: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8000bfe: 230c movs r3, #12
8000c00: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8000c02: f107 0324 add.w r3, r7, #36 @ 0x24
8000c06: 4619 mov r1, r3
8000c08: 4884 ldr r0, [pc, #528] @ (8000e1c <MX_GPIO_Init+0x60c>)
8000c0a: f000 fd15 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_SPI2_MOSI_Pin PMOD_SPI2_MISO_Pin PI10 */
GPIO_InitStruct.Pin = PMOD_SPI2_MOSI_Pin|PMOD_SPI2_MISO_Pin|GPIO_PIN_10;
8000c0e: f240 430c movw r3, #1036 @ 0x40c
8000c12: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000c14: 2301 movs r3, #1
8000c16: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c18: 2300 movs r3, #0
8000c1a: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c1c: 2300 movs r3, #0
8000c1e: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8000c20: f107 0324 add.w r3, r7, #36 @ 0x24
8000c24: 4619 mov r1, r3
8000c26: 4881 ldr r0, [pc, #516] @ (8000e2c <MX_GPIO_Init+0x61c>)
8000c28: f000 fd06 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : CTP_INT_Pin */
GPIO_InitStruct.Pin = CTP_INT_Pin;
8000c2c: f44f 7300 mov.w r3, #512 @ 0x200
8000c30: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000c32: f44f 1388 mov.w r3, #1114112 @ 0x110000
8000c36: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c38: 2300 movs r3, #0
8000c3a: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(CTP_INT_GPIO_Port, &GPIO_InitStruct);
8000c3c: f107 0324 add.w r3, r7, #36 @ 0x24
8000c40: 4619 mov r1, r3
8000c42: 487a ldr r0, [pc, #488] @ (8000e2c <MX_GPIO_Init+0x61c>)
8000c44: f000 fcf8 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : UART_RXD_WIFI_TX_Pin */
GPIO_InitStruct.Pin = UART_RXD_WIFI_TX_Pin;
8000c48: 2304 movs r3, #4
8000c4a: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c4c: 2302 movs r3, #2
8000c4e: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c50: 2300 movs r3, #0
8000c52: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000c54: 2303 movs r3, #3
8000c56: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
8000c58: 2308 movs r3, #8
8000c5a: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(UART_RXD_WIFI_TX_GPIO_Port, &GPIO_InitStruct);
8000c5c: f107 0324 add.w r3, r7, #36 @ 0x24
8000c60: 4619 mov r1, r3
8000c62: 486f ldr r0, [pc, #444] @ (8000e20 <MX_GPIO_Init+0x610>)
8000c64: f000 fce8 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_SEL_0_Pin PMOD_GPIO_1_Pin ARD_D4_GPIO_Pin USB_OTGHS_PPWR_EN_Pin
CTP_RST_Pin LCD_RST_Pin */
GPIO_InitStruct.Pin = PMOD_SEL_0_Pin|PMOD_GPIO_1_Pin|ARD_D4_GPIO_Pin|USB_OTGHS_PPWR_EN_Pin
8000c68: f249 238c movw r3, #37516 @ 0x928c
8000c6c: 627b str r3, [r7, #36] @ 0x24
|CTP_RST_Pin|LCD_RST_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000c6e: 2301 movs r3, #1
8000c70: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c72: 2300 movs r3, #0
8000c74: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c76: 2300 movs r3, #0
8000c78: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8000c7a: f107 0324 add.w r3, r7, #36 @ 0x24
8000c7e: 4619 mov r1, r3
8000c80: 486b ldr r0, [pc, #428] @ (8000e30 <MX_GPIO_Init+0x620>)
8000c82: f000 fcd9 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_SPI2_SCK_Pin PMOD_SPI2_NSS_Pin */
GPIO_InitStruct.Pin = PMOD_SPI2_SCK_Pin|PMOD_SPI2_NSS_Pin;
8000c86: 2303 movs r3, #3
8000c88: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c8a: 2302 movs r3, #2
8000c8c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c8e: 2300 movs r3, #0
8000c90: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000c92: 2303 movs r3, #3
8000c94: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8000c96: 2305 movs r3, #5
8000c98: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8000c9a: f107 0324 add.w r3, r7, #36 @ 0x24
8000c9e: 4619 mov r1, r3
8000ca0: 4862 ldr r0, [pc, #392] @ (8000e2c <MX_GPIO_Init+0x61c>)
8000ca2: f000 fcc9 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : USB_OTG_FS_ID_Pin SYS_LD_USER1_Pin */
GPIO_InitStruct.Pin = USB_OTG_FS_ID_Pin|SYS_LD_USER1_Pin;
8000ca6: f44f 6390 mov.w r3, #1152 @ 0x480
8000caa: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000cac: 2301 movs r3, #1
8000cae: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000cb0: 2300 movs r3, #0
8000cb2: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000cb4: 2300 movs r3, #0
8000cb6: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000cb8: f107 0324 add.w r3, r7, #36 @ 0x24
8000cbc: 4619 mov r1, r3
8000cbe: 485a ldr r0, [pc, #360] @ (8000e28 <MX_GPIO_Init+0x618>)
8000cc0: f000 fcba bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : PSRAM_A0_Pin PSRAM_A2_Pin PSRAM_A1_Pin PSRAM_A3_Pin
PSRAM_A4_Pin PSRAM_A5_Pin PSRAM_A7_Pin PSRAM_A6_Pin
PSRAM_A9_Pin PSRAM_A8_Pin */
GPIO_InitStruct.Pin = PSRAM_A0_Pin|PSRAM_A2_Pin|PSRAM_A1_Pin|PSRAM_A3_Pin
8000cc4: f24f 033f movw r3, #61503 @ 0xf03f
8000cc8: 627b str r3, [r7, #36] @ 0x24
|PSRAM_A4_Pin|PSRAM_A5_Pin|PSRAM_A7_Pin|PSRAM_A6_Pin
|PSRAM_A9_Pin|PSRAM_A8_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000cca: 2302 movs r3, #2
8000ccc: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000cce: 2300 movs r3, #0
8000cd0: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000cd2: 2303 movs r3, #3
8000cd4: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8000cd6: 230c movs r3, #12
8000cd8: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8000cda: f107 0324 add.w r3, r7, #36 @ 0x24
8000cde: 4619 mov r1, r3
8000ce0: 4854 ldr r0, [pc, #336] @ (8000e34 <MX_GPIO_Init+0x624>)
8000ce2: f000 fca9 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : STMOD_UART4_TXD_Pin STMOD_UART4_RXD_Pin */
GPIO_InitStruct.Pin = STMOD_UART4_TXD_Pin|STMOD_UART4_RXD_Pin;
8000ce6: f44f 43c0 mov.w r3, #24576 @ 0x6000
8000cea: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000cec: 2302 movs r3, #2
8000cee: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000cf0: 2300 movs r3, #0
8000cf2: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000cf4: 2303 movs r3, #3
8000cf6: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
8000cf8: 2308 movs r3, #8
8000cfa: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8000cfc: f107 0324 add.w r3, r7, #36 @ 0x24
8000d00: 4619 mov r1, r3
8000d02: 484b ldr r0, [pc, #300] @ (8000e30 <MX_GPIO_Init+0x620>)
8000d04: f000 fc98 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : PA9 */
GPIO_InitStruct.Pin = GPIO_PIN_9;
8000d08: f44f 7300 mov.w r3, #512 @ 0x200
8000d0c: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000d0e: 2300 movs r3, #0
8000d10: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d12: 2300 movs r3, #0
8000d14: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000d16: f107 0324 add.w r3, r7, #36 @ 0x24
8000d1a: 4619 mov r1, r3
8000d1c: 4842 ldr r0, [pc, #264] @ (8000e28 <MX_GPIO_Init+0x618>)
8000d1e: f000 fc8b bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : CTP_SCL_Pin */
GPIO_InitStruct.Pin = CTP_SCL_Pin;
8000d22: f44f 7380 mov.w r3, #256 @ 0x100
8000d26: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000d28: 2312 movs r3, #18
8000d2a: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d2c: 2300 movs r3, #0
8000d2e: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000d30: 2303 movs r3, #3
8000d32: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
8000d34: 2304 movs r3, #4
8000d36: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(CTP_SCL_GPIO_Port, &GPIO_InitStruct);
8000d38: f107 0324 add.w r3, r7, #36 @ 0x24
8000d3c: 4619 mov r1, r3
8000d3e: 483a ldr r0, [pc, #232] @ (8000e28 <MX_GPIO_Init+0x618>)
8000d40: f000 fc7a bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : LCD_TE_INT_Pin */
GPIO_InitStruct.Pin = LCD_TE_INT_Pin;
8000d44: f44f 7380 mov.w r3, #256 @ 0x100
8000d48: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000d4a: f44f 1388 mov.w r3, #1114112 @ 0x110000
8000d4e: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d50: 2300 movs r3, #0
8000d52: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(LCD_TE_INT_GPIO_Port, &GPIO_InitStruct);
8000d54: f107 0324 add.w r3, r7, #36 @ 0x24
8000d58: 4619 mov r1, r3
8000d5a: 4832 ldr r0, [pc, #200] @ (8000e24 <MX_GPIO_Init+0x614>)
8000d5c: f000 fc6c bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D15_STMOD_I2C2_SCL_Pin ARD_D14_STMOD_I2C2_SDA_Pin */
GPIO_InitStruct.Pin = ARD_D15_STMOD_I2C2_SCL_Pin|ARD_D14_STMOD_I2C2_SDA_Pin;
8000d60: 2330 movs r3, #48 @ 0x30
8000d62: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000d64: 2312 movs r3, #18
8000d66: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d68: 2300 movs r3, #0
8000d6a: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000d6c: 2303 movs r3, #3
8000d6e: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
8000d70: 2304 movs r3, #4
8000d72: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8000d74: f107 0324 add.w r3, r7, #36 @ 0x24
8000d78: 4619 mov r1, r3
8000d7a: 482d ldr r0, [pc, #180] @ (8000e30 <MX_GPIO_Init+0x620>)
8000d7c: f000 fc5c bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_UART7_TXD_Pin PMOD_UART7_RXD_Pin PMOD_UART7_CTS_Pin PMOD_UART7_RTS_Pin */
GPIO_InitStruct.Pin = PMOD_UART7_TXD_Pin|PMOD_UART7_RXD_Pin|PMOD_UART7_CTS_Pin|PMOD_UART7_RTS_Pin;
8000d80: f44f 7370 mov.w r3, #960 @ 0x3c0
8000d84: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000d86: 2302 movs r3, #2
8000d88: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d8a: 2300 movs r3, #0
8000d8c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000d8e: 2303 movs r3, #3
8000d90: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART7;
8000d92: 2308 movs r3, #8
8000d94: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8000d96: f107 0324 add.w r3, r7, #36 @ 0x24
8000d9a: 4619 mov r1, r3
8000d9c: 4825 ldr r0, [pc, #148] @ (8000e34 <MX_GPIO_Init+0x624>)
8000d9e: f000 fc4b bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_A3_ADC3_IN8_Pin */
GPIO_InitStruct.Pin = ARD_A3_ADC3_IN8_Pin;
8000da2: f44f 6380 mov.w r3, #1024 @ 0x400
8000da6: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000da8: 2303 movs r3, #3
8000daa: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000dac: 2300 movs r3, #0
8000dae: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(ARD_A3_ADC3_IN8_GPIO_Port, &GPIO_InitStruct);
8000db0: f107 0324 add.w r3, r7, #36 @ 0x24
8000db4: 4619 mov r1, r3
8000db6: 481f ldr r0, [pc, #124] @ (8000e34 <MX_GPIO_Init+0x624>)
8000db8: f000 fc3e bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : LCD_BL_Pin */
GPIO_InitStruct.Pin = LCD_BL_Pin;
8000dbc: f44f 6300 mov.w r3, #2048 @ 0x800
8000dc0: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000dc2: 2302 movs r3, #2
8000dc4: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000dc6: 2300 movs r3, #0
8000dc8: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000dca: 2300 movs r3, #0
8000dcc: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF2_TIM5;
8000dce: 2302 movs r3, #2
8000dd0: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(LCD_BL_GPIO_Port, &GPIO_InitStruct);
8000dd2: f107 0324 add.w r3, r7, #36 @ 0x24
8000dd6: 4619 mov r1, r3
8000dd8: 4815 ldr r0, [pc, #84] @ (8000e30 <MX_GPIO_Init+0x620>)
8000dda: f000 fc2d bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : USB_OTGHS_OVCR_INT_Pin */
GPIO_InitStruct.Pin = USB_OTGHS_OVCR_INT_Pin;
8000dde: f44f 6380 mov.w r3, #1024 @ 0x400
8000de2: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000de4: 2300 movs r3, #0
8000de6: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000de8: 2300 movs r3, #0
8000dea: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(USB_OTGHS_OVCR_INT_GPIO_Port, &GPIO_InitStruct);
8000dec: f107 0324 add.w r3, r7, #36 @ 0x24
8000df0: 4619 mov r1, r3
8000df2: 480f ldr r0, [pc, #60] @ (8000e30 <MX_GPIO_Init+0x620>)
8000df4: f000 fc20 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_A4_Pin ARD_A5_Pin ARD_A2_Pin */
GPIO_InitStruct.Pin = ARD_A4_Pin|ARD_A5_Pin|ARD_A2_Pin;
8000df8: 2313 movs r3, #19
8000dfa: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000dfc: 2303 movs r3, #3
8000dfe: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e00: 2300 movs r3, #0
8000e02: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000e04: f107 0324 add.w r3, r7, #36 @ 0x24
8000e08: 4619 mov r1, r3
8000e0a: 4806 ldr r0, [pc, #24] @ (8000e24 <MX_GPIO_Init+0x614>)
8000e0c: f000 fc14 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : STMOD_SPI2_MISOs_Pin STMOD_SPI2_MOSIs_Pin */
GPIO_InitStruct.Pin = STMOD_SPI2_MISOs_Pin|STMOD_SPI2_MOSIs_Pin;
8000e10: 230c movs r3, #12
8000e12: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000e14: 2302 movs r3, #2
8000e16: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e18: 2300 movs r3, #0
8000e1a: e00d b.n 8000e38 <MX_GPIO_Init+0x628>
8000e1c: 40021800 .word 0x40021800
8000e20: 40020c00 .word 0x40020c00
8000e24: 40020800 .word 0x40020800
8000e28: 40020000 .word 0x40020000
8000e2c: 40022000 .word 0x40022000
8000e30: 40021c00 .word 0x40021c00
8000e34: 40021400 .word 0x40021400
8000e38: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000e3a: 2303 movs r3, #3
8000e3c: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8000e3e: 2305 movs r3, #5
8000e40: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000e42: f107 0324 add.w r3, r7, #36 @ 0x24
8000e46: 4619 mov r1, r3
8000e48: 4865 ldr r0, [pc, #404] @ (8000fe0 <MX_GPIO_Init+0x7d0>)
8000e4a: f000 fbf5 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : QSPI_CLK_Pin */
GPIO_InitStruct.Pin = QSPI_CLK_Pin;
8000e4e: 2304 movs r3, #4
8000e50: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000e52: 2302 movs r3, #2
8000e54: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e56: 2300 movs r3, #0
8000e58: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000e5a: 2303 movs r3, #3
8000e5c: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
8000e5e: 2309 movs r3, #9
8000e60: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(QSPI_CLK_GPIO_Port, &GPIO_InitStruct);
8000e62: f107 0324 add.w r3, r7, #36 @ 0x24
8000e66: 4619 mov r1, r3
8000e68: 485e ldr r0, [pc, #376] @ (8000fe4 <MX_GPIO_Init+0x7d4>)
8000e6a: f000 fbe5 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_D9_TIM12_CH1_Pin */
GPIO_InitStruct.Pin = ARD_D9_TIM12_CH1_Pin;
8000e6e: 2340 movs r3, #64 @ 0x40
8000e70: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000e72: 2302 movs r3, #2
8000e74: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e76: 2300 movs r3, #0
8000e78: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000e7a: 2300 movs r3, #0
8000e7c: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_TIM12;
8000e7e: 2309 movs r3, #9
8000e80: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(ARD_D9_TIM12_CH1_GPIO_Port, &GPIO_InitStruct);
8000e82: f107 0324 add.w r3, r7, #36 @ 0x24
8000e86: 4619 mov r1, r3
8000e88: 4857 ldr r0, [pc, #348] @ (8000fe8 <MX_GPIO_Init+0x7d8>)
8000e8a: f000 fbd5 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : CTP_SDA_Pin */
GPIO_InitStruct.Pin = CTP_SDA_Pin;
8000e8e: f44f 7380 mov.w r3, #256 @ 0x100
8000e92: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000e94: 2312 movs r3, #18
8000e96: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e98: 2300 movs r3, #0
8000e9a: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000e9c: 2303 movs r3, #3
8000e9e: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
8000ea0: 2304 movs r3, #4
8000ea2: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(CTP_SDA_GPIO_Port, &GPIO_InitStruct);
8000ea4: f107 0324 add.w r3, r7, #36 @ 0x24
8000ea8: 4619 mov r1, r3
8000eaa: 484f ldr r0, [pc, #316] @ (8000fe8 <MX_GPIO_Init+0x7d8>)
8000eac: f000 fbc4 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : QSPI_D3_Pin */
GPIO_InitStruct.Pin = QSPI_D3_Pin;
8000eb0: f44f 5300 mov.w r3, #8192 @ 0x2000
8000eb4: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000eb6: 2302 movs r3, #2
8000eb8: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000eba: 2300 movs r3, #0
8000ebc: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000ebe: 2303 movs r3, #3
8000ec0: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
8000ec2: 2309 movs r3, #9
8000ec4: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(QSPI_D3_GPIO_Port, &GPIO_InitStruct);
8000ec6: f107 0324 add.w r3, r7, #36 @ 0x24
8000eca: 4619 mov r1, r3
8000ecc: 4847 ldr r0, [pc, #284] @ (8000fec <MX_GPIO_Init+0x7dc>)
8000ece: f000 fbb3 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : PA0 */
GPIO_InitStruct.Pin = GPIO_PIN_0;
8000ed2: 2301 movs r3, #1
8000ed4: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000ed6: 2300 movs r3, #0
8000ed8: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000eda: 2300 movs r3, #0
8000edc: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000ede: f107 0324 add.w r3, r7, #36 @ 0x24
8000ee2: 4619 mov r1, r3
8000ee4: 4842 ldr r0, [pc, #264] @ (8000ff0 <MX_GPIO_Init+0x7e0>)
8000ee6: f000 fba7 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_A1_Pin ARD_A0_Pin */
GPIO_InitStruct.Pin = ARD_A1_Pin|ARD_A0_Pin;
8000eea: 2350 movs r3, #80 @ 0x50
8000eec: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000eee: 2303 movs r3, #3
8000ef0: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ef2: 2300 movs r3, #0
8000ef4: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000ef6: f107 0324 add.w r3, r7, #36 @ 0x24
8000efa: 4619 mov r1, r3
8000efc: 483c ldr r0, [pc, #240] @ (8000ff0 <MX_GPIO_Init+0x7e0>)
8000efe: f000 fb9b bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D1_USART2_TX_Pin ARD_D0_USART2_RX_Pin */
GPIO_InitStruct.Pin = ARD_D1_USART2_TX_Pin|ARD_D0_USART2_RX_Pin;
8000f02: 230c movs r3, #12
8000f04: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000f06: 2302 movs r3, #2
8000f08: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f0a: 2300 movs r3, #0
8000f0c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000f0e: 2303 movs r3, #3
8000f10: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
8000f12: 2307 movs r3, #7
8000f14: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000f16: f107 0324 add.w r3, r7, #36 @ 0x24
8000f1a: 4619 mov r1, r3
8000f1c: 4834 ldr r0, [pc, #208] @ (8000ff0 <MX_GPIO_Init+0x7e0>)
8000f1e: f000 fb8b bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_D13_SPI1_SCK_Pin */
GPIO_InitStruct.Pin = ARD_D13_SPI1_SCK_Pin;
8000f22: 2320 movs r3, #32
8000f24: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000f26: 2302 movs r3, #2
8000f28: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f2a: 2300 movs r3, #0
8000f2c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000f2e: 2303 movs r3, #3
8000f30: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
8000f32: 2305 movs r3, #5
8000f34: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(ARD_D13_SPI1_SCK_GPIO_Port, &GPIO_InitStruct);
8000f36: f107 0324 add.w r3, r7, #36 @ 0x24
8000f3a: 4619 mov r1, r3
8000f3c: 482c ldr r0, [pc, #176] @ (8000ff0 <MX_GPIO_Init+0x7e0>)
8000f3e: f000 fb7b bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : USB_OTG_HS_ID_Pin SYS_LD_USER2_Pin */
GPIO_InitStruct.Pin = USB_OTG_HS_ID_Pin|SYS_LD_USER2_Pin;
8000f42: f241 0302 movw r3, #4098 @ 0x1002
8000f46: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000f48: 2301 movs r3, #1
8000f4a: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f4c: 2300 movs r3, #0
8000f4e: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000f50: 2300 movs r3, #0
8000f52: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000f54: f107 0324 add.w r3, r7, #36 @ 0x24
8000f58: 4619 mov r1, r3
8000f5a: 4822 ldr r0, [pc, #136] @ (8000fe4 <MX_GPIO_Init+0x7d4>)
8000f5c: f000 fb6c bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : USB_OTG_HS_VBUS_Pin USB_OTGFS_OVCR_INT_Pin PMOD_INT_Pin */
GPIO_InitStruct.Pin = USB_OTG_HS_VBUS_Pin|USB_OTGFS_OVCR_INT_Pin|PMOD_INT_Pin;
8000f60: f44f 5330 mov.w r3, #11264 @ 0x2c00
8000f64: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000f66: f44f 1388 mov.w r3, #1114112 @ 0x110000
8000f6a: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f6c: 2300 movs r3, #0
8000f6e: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000f70: f107 0324 add.w r3, r7, #36 @ 0x24
8000f74: 4619 mov r1, r3
8000f76: 481b ldr r0, [pc, #108] @ (8000fe4 <MX_GPIO_Init+0x7d4>)
8000f78: f000 fb5e bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_D5_STMOD_TIM3_CH3_Pin */
GPIO_InitStruct.Pin = ARD_D5_STMOD_TIM3_CH3_Pin;
8000f7c: 2301 movs r3, #1
8000f7e: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000f80: 2302 movs r3, #2
8000f82: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f84: 2300 movs r3, #0
8000f86: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000f88: 2300 movs r3, #0
8000f8a: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
8000f8c: 2302 movs r3, #2
8000f8e: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(ARD_D5_STMOD_TIM3_CH3_GPIO_Port, &GPIO_InitStruct);
8000f90: f107 0324 add.w r3, r7, #36 @ 0x24
8000f94: 4619 mov r1, r3
8000f96: 4813 ldr r0, [pc, #76] @ (8000fe4 <MX_GPIO_Init+0x7d4>)
8000f98: f000 fb4e bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pin : PMOD_RESET_Pin */
GPIO_InitStruct.Pin = PMOD_RESET_Pin;
8000f9c: f44f 6300 mov.w r3, #2048 @ 0x800
8000fa0: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000fa2: 2300 movs r3, #0
8000fa4: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000fa6: 2300 movs r3, #0
8000fa8: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(PMOD_RESET_GPIO_Port, &GPIO_InitStruct);
8000faa: f107 0324 add.w r3, r7, #36 @ 0x24
8000fae: 4619 mov r1, r3
8000fb0: 4810 ldr r0, [pc, #64] @ (8000ff4 <MX_GPIO_Init+0x7e4>)
8000fb2: f000 fb41 bl 8001638 <HAL_GPIO_Init>
/*Configure GPIO pins : PB14 PB15 */
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
8000fb6: f44f 4340 mov.w r3, #49152 @ 0xc000
8000fba: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000fbc: 2302 movs r3, #2
8000fbe: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000fc0: 2300 movs r3, #0
8000fc2: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000fc4: 2303 movs r3, #3
8000fc6: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;
8000fc8: 230c movs r3, #12
8000fca: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000fcc: f107 0324 add.w r3, r7, #36 @ 0x24
8000fd0: 4619 mov r1, r3
8000fd2: 4804 ldr r0, [pc, #16] @ (8000fe4 <MX_GPIO_Init+0x7d4>)
8000fd4: f000 fb30 bl 8001638 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000fd8: bf00 nop
8000fda: 3738 adds r7, #56 @ 0x38
8000fdc: 46bd mov sp, r7
8000fde: bd80 pop {r7, pc}
8000fe0: 40020800 .word 0x40020800
8000fe4: 40020400 .word 0x40020400
8000fe8: 40021c00 .word 0x40021c00
8000fec: 40020c00 .word 0x40020c00
8000ff0: 40020000 .word 0x40020000
8000ff4: 40021400 .word 0x40021400
08000ff8 <HAL_TIM_PeriodElapsedCallback>:
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8000ff8: b580 push {r7, lr}
8000ffa: b082 sub sp, #8
8000ffc: af00 add r7, sp, #0
8000ffe: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM14)
8001000: 687b ldr r3, [r7, #4]
8001002: 681b ldr r3, [r3, #0]
8001004: 4a04 ldr r2, [pc, #16] @ (8001018 <HAL_TIM_PeriodElapsedCallback+0x20>)
8001006: 4293 cmp r3, r2
8001008: d101 bne.n 800100e <HAL_TIM_PeriodElapsedCallback+0x16>
{
HAL_IncTick();
800100a: f000 fa13 bl 8001434 <HAL_IncTick>
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
800100e: bf00 nop
8001010: 3708 adds r7, #8
8001012: 46bd mov sp, r7
8001014: bd80 pop {r7, pc}
8001016: bf00 nop
8001018: 40002000 .word 0x40002000
0800101c <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
800101c: b480 push {r7}
800101e: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8001020: b672 cpsid i
}
8001022: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8001024: bf00 nop
8001026: e7fd b.n 8001024 <Error_Handler+0x8>
08001028 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8001028: b480 push {r7}
800102a: b083 sub sp, #12
800102c: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_PWR_CLK_ENABLE();
800102e: 4b0f ldr r3, [pc, #60] @ (800106c <HAL_MspInit+0x44>)
8001030: 6c1b ldr r3, [r3, #64] @ 0x40
8001032: 4a0e ldr r2, [pc, #56] @ (800106c <HAL_MspInit+0x44>)
8001034: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001038: 6413 str r3, [r2, #64] @ 0x40
800103a: 4b0c ldr r3, [pc, #48] @ (800106c <HAL_MspInit+0x44>)
800103c: 6c1b ldr r3, [r3, #64] @ 0x40
800103e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001042: 607b str r3, [r7, #4]
8001044: 687b ldr r3, [r7, #4]
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001046: 4b09 ldr r3, [pc, #36] @ (800106c <HAL_MspInit+0x44>)
8001048: 6c5b ldr r3, [r3, #68] @ 0x44
800104a: 4a08 ldr r2, [pc, #32] @ (800106c <HAL_MspInit+0x44>)
800104c: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8001050: 6453 str r3, [r2, #68] @ 0x44
8001052: 4b06 ldr r3, [pc, #24] @ (800106c <HAL_MspInit+0x44>)
8001054: 6c5b ldr r3, [r3, #68] @ 0x44
8001056: f403 4380 and.w r3, r3, #16384 @ 0x4000
800105a: 603b str r3, [r7, #0]
800105c: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800105e: bf00 nop
8001060: 370c adds r7, #12
8001062: 46bd mov sp, r7
8001064: f85d 7b04 ldr.w r7, [sp], #4
8001068: 4770 bx lr
800106a: bf00 nop
800106c: 40023800 .word 0x40023800
08001070 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8001070: b580 push {r7, lr}
8001072: b0aa sub sp, #168 @ 0xa8
8001074: af00 add r7, sp, #0
8001076: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001078: f107 0394 add.w r3, r7, #148 @ 0x94
800107c: 2200 movs r2, #0
800107e: 601a str r2, [r3, #0]
8001080: 605a str r2, [r3, #4]
8001082: 609a str r2, [r3, #8]
8001084: 60da str r2, [r3, #12]
8001086: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
8001088: f107 0314 add.w r3, r7, #20
800108c: 2280 movs r2, #128 @ 0x80
800108e: 2100 movs r1, #0
8001090: 4618 mov r0, r3
8001092: f002 fe0a bl 8003caa <memset>
if(huart->Instance==USART6)
8001096: 687b ldr r3, [r7, #4]
8001098: 681b ldr r3, [r3, #0]
800109a: 4a21 ldr r2, [pc, #132] @ (8001120 <HAL_UART_MspInit+0xb0>)
800109c: 4293 cmp r3, r2
800109e: d13b bne.n 8001118 <HAL_UART_MspInit+0xa8>
/* USER CODE END USART6_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6;
80010a0: f44f 6300 mov.w r3, #2048 @ 0x800
80010a4: 617b str r3, [r7, #20]
PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
80010a6: 2300 movs r3, #0
80010a8: 667b str r3, [r7, #100] @ 0x64
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
80010aa: f107 0314 add.w r3, r7, #20
80010ae: 4618 mov r0, r3
80010b0: f001 f9c6 bl 8002440 <HAL_RCCEx_PeriphCLKConfig>
80010b4: 4603 mov r3, r0
80010b6: 2b00 cmp r3, #0
80010b8: d001 beq.n 80010be <HAL_UART_MspInit+0x4e>
{
Error_Handler();
80010ba: f7ff ffaf bl 800101c <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_USART6_CLK_ENABLE();
80010be: 4b19 ldr r3, [pc, #100] @ (8001124 <HAL_UART_MspInit+0xb4>)
80010c0: 6c5b ldr r3, [r3, #68] @ 0x44
80010c2: 4a18 ldr r2, [pc, #96] @ (8001124 <HAL_UART_MspInit+0xb4>)
80010c4: f043 0320 orr.w r3, r3, #32
80010c8: 6453 str r3, [r2, #68] @ 0x44
80010ca: 4b16 ldr r3, [pc, #88] @ (8001124 <HAL_UART_MspInit+0xb4>)
80010cc: 6c5b ldr r3, [r3, #68] @ 0x44
80010ce: f003 0320 and.w r3, r3, #32
80010d2: 613b str r3, [r7, #16]
80010d4: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
80010d6: 4b13 ldr r3, [pc, #76] @ (8001124 <HAL_UART_MspInit+0xb4>)
80010d8: 6b1b ldr r3, [r3, #48] @ 0x30
80010da: 4a12 ldr r2, [pc, #72] @ (8001124 <HAL_UART_MspInit+0xb4>)
80010dc: f043 0304 orr.w r3, r3, #4
80010e0: 6313 str r3, [r2, #48] @ 0x30
80010e2: 4b10 ldr r3, [pc, #64] @ (8001124 <HAL_UART_MspInit+0xb4>)
80010e4: 6b1b ldr r3, [r3, #48] @ 0x30
80010e6: f003 0304 and.w r3, r3, #4
80010ea: 60fb str r3, [r7, #12]
80010ec: 68fb ldr r3, [r7, #12]
/**USART6 GPIO Configuration
PC7 ------> USART6_RX
PC6 ------> USART6_TX
*/
GPIO_InitStruct.Pin = VCP_RX_Pin|VCP_TX_Pin;
80010ee: 23c0 movs r3, #192 @ 0xc0
80010f0: f8c7 3094 str.w r3, [r7, #148] @ 0x94
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80010f4: 2302 movs r3, #2
80010f6: f8c7 3098 str.w r3, [r7, #152] @ 0x98
GPIO_InitStruct.Pull = GPIO_NOPULL;
80010fa: 2300 movs r3, #0
80010fc: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001100: 2303 movs r3, #3
8001102: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
8001106: 2308 movs r3, #8
8001108: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
800110c: f107 0394 add.w r3, r7, #148 @ 0x94
8001110: 4619 mov r1, r3
8001112: 4805 ldr r0, [pc, #20] @ (8001128 <HAL_UART_MspInit+0xb8>)
8001114: f000 fa90 bl 8001638 <HAL_GPIO_Init>
/* USER CODE END USART6_MspInit 1 */
}
}
8001118: bf00 nop
800111a: 37a8 adds r7, #168 @ 0xa8
800111c: 46bd mov sp, r7
800111e: bd80 pop {r7, pc}
8001120: 40011400 .word 0x40011400
8001124: 40023800 .word 0x40023800
8001128: 40020800 .word 0x40020800
0800112c <HAL_InitTick>:
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
800112c: b580 push {r7, lr}
800112e: b08e sub sp, #56 @ 0x38
8001130: af00 add r7, sp, #0
8001132: 6078 str r0, [r7, #4]
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock, uwAPB1Prescaler = 0U;
8001134: 2300 movs r3, #0
8001136: 62fb str r3, [r7, #44] @ 0x2c
uint32_t uwPrescalerValue = 0U;
8001138: 2300 movs r3, #0
800113a: 62bb str r3, [r7, #40] @ 0x28
uint32_t pFLatency;
HAL_StatusTypeDef status;
/* Enable TIM14 clock */
__HAL_RCC_TIM14_CLK_ENABLE();
800113c: 4b33 ldr r3, [pc, #204] @ (800120c <HAL_InitTick+0xe0>)
800113e: 6c1b ldr r3, [r3, #64] @ 0x40
8001140: 4a32 ldr r2, [pc, #200] @ (800120c <HAL_InitTick+0xe0>)
8001142: f443 7380 orr.w r3, r3, #256 @ 0x100
8001146: 6413 str r3, [r2, #64] @ 0x40
8001148: 4b30 ldr r3, [pc, #192] @ (800120c <HAL_InitTick+0xe0>)
800114a: 6c1b ldr r3, [r3, #64] @ 0x40
800114c: f403 7380 and.w r3, r3, #256 @ 0x100
8001150: 60fb str r3, [r7, #12]
8001152: 68fb ldr r3, [r7, #12]
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
8001154: f107 0210 add.w r2, r7, #16
8001158: f107 0314 add.w r3, r7, #20
800115c: 4611 mov r1, r2
800115e: 4618 mov r0, r3
8001160: f001 f93c bl 80023dc <HAL_RCC_GetClockConfig>
/* Get APB1 prescaler */
uwAPB1Prescaler = clkconfig.APB1CLKDivider;
8001164: 6a3b ldr r3, [r7, #32]
8001166: 62fb str r3, [r7, #44] @ 0x2c
/* Compute TIM14 clock */
if (uwAPB1Prescaler == RCC_HCLK_DIV1)
8001168: 6afb ldr r3, [r7, #44] @ 0x2c
800116a: 2b00 cmp r3, #0
800116c: d103 bne.n 8001176 <HAL_InitTick+0x4a>
{
uwTimclock = HAL_RCC_GetPCLK1Freq();
800116e: f001 f90d bl 800238c <HAL_RCC_GetPCLK1Freq>
8001172: 6378 str r0, [r7, #52] @ 0x34
8001174: e004 b.n 8001180 <HAL_InitTick+0x54>
}
else
{
uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
8001176: f001 f909 bl 800238c <HAL_RCC_GetPCLK1Freq>
800117a: 4603 mov r3, r0
800117c: 005b lsls r3, r3, #1
800117e: 637b str r3, [r7, #52] @ 0x34
}
/* Compute the prescaler value to have TIM14 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
8001180: 6b7b ldr r3, [r7, #52] @ 0x34
8001182: 4a23 ldr r2, [pc, #140] @ (8001210 <HAL_InitTick+0xe4>)
8001184: fba2 2303 umull r2, r3, r2, r3
8001188: 0c9b lsrs r3, r3, #18
800118a: 3b01 subs r3, #1
800118c: 62bb str r3, [r7, #40] @ 0x28
/* Initialize TIM14 */
htim14.Instance = TIM14;
800118e: 4b21 ldr r3, [pc, #132] @ (8001214 <HAL_InitTick+0xe8>)
8001190: 4a21 ldr r2, [pc, #132] @ (8001218 <HAL_InitTick+0xec>)
8001192: 601a str r2, [r3, #0]
* Period = [(TIM14CLK/1000) - 1]. to have a (1/1000) s time base.
* Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
* ClockDivision = 0
* Counter direction = Up
*/
htim14.Init.Period = (1000000U / 1000U) - 1U;
8001194: 4b1f ldr r3, [pc, #124] @ (8001214 <HAL_InitTick+0xe8>)
8001196: f240 32e7 movw r2, #999 @ 0x3e7
800119a: 60da str r2, [r3, #12]
htim14.Init.Prescaler = uwPrescalerValue;
800119c: 4a1d ldr r2, [pc, #116] @ (8001214 <HAL_InitTick+0xe8>)
800119e: 6abb ldr r3, [r7, #40] @ 0x28
80011a0: 6053 str r3, [r2, #4]
htim14.Init.ClockDivision = 0;
80011a2: 4b1c ldr r3, [pc, #112] @ (8001214 <HAL_InitTick+0xe8>)
80011a4: 2200 movs r2, #0
80011a6: 611a str r2, [r3, #16]
htim14.Init.CounterMode = TIM_COUNTERMODE_UP;
80011a8: 4b1a ldr r3, [pc, #104] @ (8001214 <HAL_InitTick+0xe8>)
80011aa: 2200 movs r2, #0
80011ac: 609a str r2, [r3, #8]
htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80011ae: 4b19 ldr r3, [pc, #100] @ (8001214 <HAL_InitTick+0xe8>)
80011b0: 2200 movs r2, #0
80011b2: 619a str r2, [r3, #24]
status = HAL_TIM_Base_Init(&htim14);
80011b4: 4817 ldr r0, [pc, #92] @ (8001214 <HAL_InitTick+0xe8>)
80011b6: f001 fc8d bl 8002ad4 <HAL_TIM_Base_Init>
80011ba: 4603 mov r3, r0
80011bc: f887 3033 strb.w r3, [r7, #51] @ 0x33
if (status == HAL_OK)
80011c0: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
80011c4: 2b00 cmp r3, #0
80011c6: d11b bne.n 8001200 <HAL_InitTick+0xd4>
{
/* Start the TIM time Base generation in interrupt mode */
status = HAL_TIM_Base_Start_IT(&htim14);
80011c8: 4812 ldr r0, [pc, #72] @ (8001214 <HAL_InitTick+0xe8>)
80011ca: f001 fce5 bl 8002b98 <HAL_TIM_Base_Start_IT>
80011ce: 4603 mov r3, r0
80011d0: f887 3033 strb.w r3, [r7, #51] @ 0x33
if (status == HAL_OK)
80011d4: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
80011d8: 2b00 cmp r3, #0
80011da: d111 bne.n 8001200 <HAL_InitTick+0xd4>
{
/* Enable the TIM14 global Interrupt */
HAL_NVIC_EnableIRQ(TIM8_TRG_COM_TIM14_IRQn);
80011dc: 202d movs r0, #45 @ 0x2d
80011de: f000 fa1d bl 800161c <HAL_NVIC_EnableIRQ>
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
80011e2: 687b ldr r3, [r7, #4]
80011e4: 2b0f cmp r3, #15
80011e6: d808 bhi.n 80011fa <HAL_InitTick+0xce>
{
/* Configure the TIM IRQ priority */
HAL_NVIC_SetPriority(TIM8_TRG_COM_TIM14_IRQn, TickPriority, 0U);
80011e8: 2200 movs r2, #0
80011ea: 6879 ldr r1, [r7, #4]
80011ec: 202d movs r0, #45 @ 0x2d
80011ee: f000 f9f9 bl 80015e4 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80011f2: 4a0a ldr r2, [pc, #40] @ (800121c <HAL_InitTick+0xf0>)
80011f4: 687b ldr r3, [r7, #4]
80011f6: 6013 str r3, [r2, #0]
80011f8: e002 b.n 8001200 <HAL_InitTick+0xd4>
}
else
{
status = HAL_ERROR;
80011fa: 2301 movs r3, #1
80011fc: f887 3033 strb.w r3, [r7, #51] @ 0x33
}
}
}
/* Return function status */
return status;
8001200: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
}
8001204: 4618 mov r0, r3
8001206: 3738 adds r7, #56 @ 0x38
8001208: 46bd mov sp, r7
800120a: bd80 pop {r7, pc}
800120c: 40023800 .word 0x40023800
8001210: 431bde83 .word 0x431bde83
8001214: 2000010c .word 0x2000010c
8001218: 40002000 .word 0x40002000
800121c: 20000004 .word 0x20000004
08001220 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001220: b480 push {r7}
8001222: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001224: bf00 nop
8001226: e7fd b.n 8001224 <NMI_Handler+0x4>
08001228 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8001228: b480 push {r7}
800122a: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
800122c: bf00 nop
800122e: e7fd b.n 800122c <HardFault_Handler+0x4>
08001230 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001230: b480 push {r7}
8001232: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001234: bf00 nop
8001236: e7fd b.n 8001234 <MemManage_Handler+0x4>
08001238 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8001238: b480 push {r7}
800123a: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
800123c: bf00 nop
800123e: e7fd b.n 800123c <BusFault_Handler+0x4>
08001240 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8001240: b480 push {r7}
8001242: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001244: bf00 nop
8001246: e7fd b.n 8001244 <UsageFault_Handler+0x4>
08001248 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8001248: b480 push {r7}
800124a: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
800124c: bf00 nop
800124e: 46bd mov sp, r7
8001250: f85d 7b04 ldr.w r7, [sp], #4
8001254: 4770 bx lr
08001256 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8001256: b480 push {r7}
8001258: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
800125a: bf00 nop
800125c: 46bd mov sp, r7
800125e: f85d 7b04 ldr.w r7, [sp], #4
8001262: 4770 bx lr
08001264 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001264: b480 push {r7}
8001266: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8001268: bf00 nop
800126a: 46bd mov sp, r7
800126c: f85d 7b04 ldr.w r7, [sp], #4
8001270: 4770 bx lr
08001272 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8001272: b480 push {r7}
8001274: af00 add r7, sp, #0
/* USER CODE END SysTick_IRQn 0 */
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8001276: bf00 nop
8001278: 46bd mov sp, r7
800127a: f85d 7b04 ldr.w r7, [sp], #4
800127e: 4770 bx lr
08001280 <TIM8_TRG_COM_TIM14_IRQHandler>:
/**
* @brief This function handles TIM8 trigger and commutation interrupts and TIM14 global interrupt.
*/
void TIM8_TRG_COM_TIM14_IRQHandler(void)
{
8001280: b580 push {r7, lr}
8001282: af00 add r7, sp, #0
/* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 0 */
/* USER CODE END TIM8_TRG_COM_TIM14_IRQn 0 */
HAL_TIM_IRQHandler(&htim14);
8001284: 4802 ldr r0, [pc, #8] @ (8001290 <TIM8_TRG_COM_TIM14_IRQHandler+0x10>)
8001286: f001 fcff bl 8002c88 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 1 */
/* USER CODE END TIM8_TRG_COM_TIM14_IRQn 1 */
}
800128a: bf00 nop
800128c: bd80 pop {r7, pc}
800128e: bf00 nop
8001290: 2000010c .word 0x2000010c
08001294 <_read>:
_kill(status, -1);
while (1) {} /* Make sure we hang here */
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
8001294: b580 push {r7, lr}
8001296: b086 sub sp, #24
8001298: af00 add r7, sp, #0
800129a: 60f8 str r0, [r7, #12]
800129c: 60b9 str r1, [r7, #8]
800129e: 607a str r2, [r7, #4]
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
80012a0: 2300 movs r3, #0
80012a2: 617b str r3, [r7, #20]
80012a4: e00a b.n 80012bc <_read+0x28>
{
*ptr++ = __io_getchar();
80012a6: f3af 8000 nop.w
80012aa: 4601 mov r1, r0
80012ac: 68bb ldr r3, [r7, #8]
80012ae: 1c5a adds r2, r3, #1
80012b0: 60ba str r2, [r7, #8]
80012b2: b2ca uxtb r2, r1
80012b4: 701a strb r2, [r3, #0]
for (DataIdx = 0; DataIdx < len; DataIdx++)
80012b6: 697b ldr r3, [r7, #20]
80012b8: 3301 adds r3, #1
80012ba: 617b str r3, [r7, #20]
80012bc: 697a ldr r2, [r7, #20]
80012be: 687b ldr r3, [r7, #4]
80012c0: 429a cmp r2, r3
80012c2: dbf0 blt.n 80012a6 <_read+0x12>
}
return len;
80012c4: 687b ldr r3, [r7, #4]
}
80012c6: 4618 mov r0, r3
80012c8: 3718 adds r7, #24
80012ca: 46bd mov sp, r7
80012cc: bd80 pop {r7, pc}
080012ce <_close>:
}
return len;
}
int _close(int file)
{
80012ce: b480 push {r7}
80012d0: b083 sub sp, #12
80012d2: af00 add r7, sp, #0
80012d4: 6078 str r0, [r7, #4]
(void)file;
return -1;
80012d6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
}
80012da: 4618 mov r0, r3
80012dc: 370c adds r7, #12
80012de: 46bd mov sp, r7
80012e0: f85d 7b04 ldr.w r7, [sp], #4
80012e4: 4770 bx lr
080012e6 <_fstat>:
int _fstat(int file, struct stat *st)
{
80012e6: b480 push {r7}
80012e8: b083 sub sp, #12
80012ea: af00 add r7, sp, #0
80012ec: 6078 str r0, [r7, #4]
80012ee: 6039 str r1, [r7, #0]
(void)file;
st->st_mode = S_IFCHR;
80012f0: 683b ldr r3, [r7, #0]
80012f2: f44f 5200 mov.w r2, #8192 @ 0x2000
80012f6: 605a str r2, [r3, #4]
return 0;
80012f8: 2300 movs r3, #0
}
80012fa: 4618 mov r0, r3
80012fc: 370c adds r7, #12
80012fe: 46bd mov sp, r7
8001300: f85d 7b04 ldr.w r7, [sp], #4
8001304: 4770 bx lr
08001306 <_isatty>:
int _isatty(int file)
{
8001306: b480 push {r7}
8001308: b083 sub sp, #12
800130a: af00 add r7, sp, #0
800130c: 6078 str r0, [r7, #4]
(void)file;
return 1;
800130e: 2301 movs r3, #1
}
8001310: 4618 mov r0, r3
8001312: 370c adds r7, #12
8001314: 46bd mov sp, r7
8001316: f85d 7b04 ldr.w r7, [sp], #4
800131a: 4770 bx lr
0800131c <_lseek>:
int _lseek(int file, int ptr, int dir)
{
800131c: b480 push {r7}
800131e: b085 sub sp, #20
8001320: af00 add r7, sp, #0
8001322: 60f8 str r0, [r7, #12]
8001324: 60b9 str r1, [r7, #8]
8001326: 607a str r2, [r7, #4]
(void)file;
(void)ptr;
(void)dir;
return 0;
8001328: 2300 movs r3, #0
}
800132a: 4618 mov r0, r3
800132c: 3714 adds r7, #20
800132e: 46bd mov sp, r7
8001330: f85d 7b04 ldr.w r7, [sp], #4
8001334: 4770 bx lr
...
08001338 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
8001338: b580 push {r7, lr}
800133a: b086 sub sp, #24
800133c: af00 add r7, sp, #0
800133e: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
8001340: 4a14 ldr r2, [pc, #80] @ (8001394 <_sbrk+0x5c>)
8001342: 4b15 ldr r3, [pc, #84] @ (8001398 <_sbrk+0x60>)
8001344: 1ad3 subs r3, r2, r3
8001346: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
8001348: 697b ldr r3, [r7, #20]
800134a: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
800134c: 4b13 ldr r3, [pc, #76] @ (800139c <_sbrk+0x64>)
800134e: 681b ldr r3, [r3, #0]
8001350: 2b00 cmp r3, #0
8001352: d102 bne.n 800135a <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
8001354: 4b11 ldr r3, [pc, #68] @ (800139c <_sbrk+0x64>)
8001356: 4a12 ldr r2, [pc, #72] @ (80013a0 <_sbrk+0x68>)
8001358: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
800135a: 4b10 ldr r3, [pc, #64] @ (800139c <_sbrk+0x64>)
800135c: 681a ldr r2, [r3, #0]
800135e: 687b ldr r3, [r7, #4]
8001360: 4413 add r3, r2
8001362: 693a ldr r2, [r7, #16]
8001364: 429a cmp r2, r3
8001366: d207 bcs.n 8001378 <_sbrk+0x40>
{
errno = ENOMEM;
8001368: f002 fcee bl 8003d48 <__errno>
800136c: 4603 mov r3, r0
800136e: 220c movs r2, #12
8001370: 601a str r2, [r3, #0]
return (void *)-1;
8001372: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
8001376: e009 b.n 800138c <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
8001378: 4b08 ldr r3, [pc, #32] @ (800139c <_sbrk+0x64>)
800137a: 681b ldr r3, [r3, #0]
800137c: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
800137e: 4b07 ldr r3, [pc, #28] @ (800139c <_sbrk+0x64>)
8001380: 681a ldr r2, [r3, #0]
8001382: 687b ldr r3, [r7, #4]
8001384: 4413 add r3, r2
8001386: 4a05 ldr r2, [pc, #20] @ (800139c <_sbrk+0x64>)
8001388: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
800138a: 68fb ldr r3, [r7, #12]
}
800138c: 4618 mov r0, r3
800138e: 3718 adds r7, #24
8001390: 46bd mov sp, r7
8001392: bd80 pop {r7, pc}
8001394: 20040000 .word 0x20040000
8001398: 00000400 .word 0x00000400
800139c: 20000158 .word 0x20000158
80013a0: 200002b0 .word 0x200002b0
080013a4 <SystemInit>:
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
80013a4: b480 push {r7}
80013a6: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
80013a8: 4b06 ldr r3, [pc, #24] @ (80013c4 <SystemInit+0x20>)
80013aa: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80013ae: 4a05 ldr r2, [pc, #20] @ (80013c4 <SystemInit+0x20>)
80013b0: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
80013b4: f8c2 3088 str.w r3, [r2, #136] @ 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
80013b8: bf00 nop
80013ba: 46bd mov sp, r7
80013bc: f85d 7b04 ldr.w r7, [sp], #4
80013c0: 4770 bx lr
80013c2: bf00 nop
80013c4: e000ed00 .word 0xe000ed00
080013c8 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
80013c8: f8df d034 ldr.w sp, [pc, #52] @ 8001400 <LoopFillZerobss+0xe>
/* Call the clock system initialization function.*/
bl SystemInit
80013cc: f7ff ffea bl 80013a4 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80013d0: 480c ldr r0, [pc, #48] @ (8001404 <LoopFillZerobss+0x12>)
ldr r1, =_edata
80013d2: 490d ldr r1, [pc, #52] @ (8001408 <LoopFillZerobss+0x16>)
ldr r2, =_sidata
80013d4: 4a0d ldr r2, [pc, #52] @ (800140c <LoopFillZerobss+0x1a>)
movs r3, #0
80013d6: 2300 movs r3, #0
b LoopCopyDataInit
80013d8: e002 b.n 80013e0 <LoopCopyDataInit>
080013da <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80013da: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80013dc: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80013de: 3304 adds r3, #4
080013e0 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80013e0: 18c4 adds r4, r0, r3
cmp r4, r1
80013e2: 428c cmp r4, r1
bcc CopyDataInit
80013e4: d3f9 bcc.n 80013da <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80013e6: 4a0a ldr r2, [pc, #40] @ (8001410 <LoopFillZerobss+0x1e>)
ldr r4, =_ebss
80013e8: 4c0a ldr r4, [pc, #40] @ (8001414 <LoopFillZerobss+0x22>)
movs r3, #0
80013ea: 2300 movs r3, #0
b LoopFillZerobss
80013ec: e001 b.n 80013f2 <LoopFillZerobss>
080013ee <FillZerobss>:
FillZerobss:
str r3, [r2]
80013ee: 6013 str r3, [r2, #0]
adds r2, r2, #4
80013f0: 3204 adds r2, #4
080013f2 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80013f2: 42a2 cmp r2, r4
bcc FillZerobss
80013f4: d3fb bcc.n 80013ee <FillZerobss>
/* Call static constructors */
bl __libc_init_array
80013f6: f002 fcad bl 8003d54 <__libc_init_array>
/* Call the application's entry point.*/
bl main
80013fa: f7ff f91b bl 8000634 <main>
bx lr
80013fe: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8001400: 20040000 .word 0x20040000
ldr r0, =_sdata
8001404: 20000000 .word 0x20000000
ldr r1, =_edata
8001408: 20000068 .word 0x20000068
ldr r2, =_sidata
800140c: 0800495c .word 0x0800495c
ldr r2, =_sbss
8001410: 20000068 .word 0x20000068
ldr r4, =_ebss
8001414: 200002ac .word 0x200002ac
08001418 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001418: e7fe b.n 8001418 <ADC_IRQHandler>
0800141a <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
800141a: b580 push {r7, lr}
800141c: af00 add r7, sp, #0
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
800141e: 2003 movs r0, #3
8001420: f000 f8d5 bl 80015ce <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8001424: 200f movs r0, #15
8001426: f7ff fe81 bl 800112c <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
800142a: f7ff fdfd bl 8001028 <HAL_MspInit>
/* Return function status */
return HAL_OK;
800142e: 2300 movs r3, #0
}
8001430: 4618 mov r0, r3
8001432: bd80 pop {r7, pc}
08001434 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001434: b480 push {r7}
8001436: af00 add r7, sp, #0
uwTick += uwTickFreq;
8001438: 4b06 ldr r3, [pc, #24] @ (8001454 <HAL_IncTick+0x20>)
800143a: 781b ldrb r3, [r3, #0]
800143c: 461a mov r2, r3
800143e: 4b06 ldr r3, [pc, #24] @ (8001458 <HAL_IncTick+0x24>)
8001440: 681b ldr r3, [r3, #0]
8001442: 4413 add r3, r2
8001444: 4a04 ldr r2, [pc, #16] @ (8001458 <HAL_IncTick+0x24>)
8001446: 6013 str r3, [r2, #0]
}
8001448: bf00 nop
800144a: 46bd mov sp, r7
800144c: f85d 7b04 ldr.w r7, [sp], #4
8001450: 4770 bx lr
8001452: bf00 nop
8001454: 20000008 .word 0x20000008
8001458: 2000015c .word 0x2000015c
0800145c <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
800145c: b480 push {r7}
800145e: af00 add r7, sp, #0
return uwTick;
8001460: 4b03 ldr r3, [pc, #12] @ (8001470 <HAL_GetTick+0x14>)
8001462: 681b ldr r3, [r3, #0]
}
8001464: 4618 mov r0, r3
8001466: 46bd mov sp, r7
8001468: f85d 7b04 ldr.w r7, [sp], #4
800146c: 4770 bx lr
800146e: bf00 nop
8001470: 2000015c .word 0x2000015c
08001474 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001474: b480 push {r7}
8001476: b085 sub sp, #20
8001478: af00 add r7, sp, #0
800147a: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
800147c: 687b ldr r3, [r7, #4]
800147e: f003 0307 and.w r3, r3, #7
8001482: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8001484: 4b0b ldr r3, [pc, #44] @ (80014b4 <__NVIC_SetPriorityGrouping+0x40>)
8001486: 68db ldr r3, [r3, #12]
8001488: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
800148a: 68ba ldr r2, [r7, #8]
800148c: f64f 03ff movw r3, #63743 @ 0xf8ff
8001490: 4013 ands r3, r2
8001492: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8001494: 68fb ldr r3, [r7, #12]
8001496: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8001498: 68bb ldr r3, [r7, #8]
800149a: 431a orrs r2, r3
reg_value = (reg_value |
800149c: 4b06 ldr r3, [pc, #24] @ (80014b8 <__NVIC_SetPriorityGrouping+0x44>)
800149e: 4313 orrs r3, r2
80014a0: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80014a2: 4a04 ldr r2, [pc, #16] @ (80014b4 <__NVIC_SetPriorityGrouping+0x40>)
80014a4: 68bb ldr r3, [r7, #8]
80014a6: 60d3 str r3, [r2, #12]
}
80014a8: bf00 nop
80014aa: 3714 adds r7, #20
80014ac: 46bd mov sp, r7
80014ae: f85d 7b04 ldr.w r7, [sp], #4
80014b2: 4770 bx lr
80014b4: e000ed00 .word 0xe000ed00
80014b8: 05fa0000 .word 0x05fa0000
080014bc <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80014bc: b480 push {r7}
80014be: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80014c0: 4b04 ldr r3, [pc, #16] @ (80014d4 <__NVIC_GetPriorityGrouping+0x18>)
80014c2: 68db ldr r3, [r3, #12]
80014c4: 0a1b lsrs r3, r3, #8
80014c6: f003 0307 and.w r3, r3, #7
}
80014ca: 4618 mov r0, r3
80014cc: 46bd mov sp, r7
80014ce: f85d 7b04 ldr.w r7, [sp], #4
80014d2: 4770 bx lr
80014d4: e000ed00 .word 0xe000ed00
080014d8 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
80014d8: b480 push {r7}
80014da: b083 sub sp, #12
80014dc: af00 add r7, sp, #0
80014de: 4603 mov r3, r0
80014e0: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80014e2: f997 3007 ldrsb.w r3, [r7, #7]
80014e6: 2b00 cmp r3, #0
80014e8: db0b blt.n 8001502 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80014ea: 79fb ldrb r3, [r7, #7]
80014ec: f003 021f and.w r2, r3, #31
80014f0: 4907 ldr r1, [pc, #28] @ (8001510 <__NVIC_EnableIRQ+0x38>)
80014f2: f997 3007 ldrsb.w r3, [r7, #7]
80014f6: 095b lsrs r3, r3, #5
80014f8: 2001 movs r0, #1
80014fa: fa00 f202 lsl.w r2, r0, r2
80014fe: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8001502: bf00 nop
8001504: 370c adds r7, #12
8001506: 46bd mov sp, r7
8001508: f85d 7b04 ldr.w r7, [sp], #4
800150c: 4770 bx lr
800150e: bf00 nop
8001510: e000e100 .word 0xe000e100
08001514 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001514: b480 push {r7}
8001516: b083 sub sp, #12
8001518: af00 add r7, sp, #0
800151a: 4603 mov r3, r0
800151c: 6039 str r1, [r7, #0]
800151e: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001520: f997 3007 ldrsb.w r3, [r7, #7]
8001524: 2b00 cmp r3, #0
8001526: db0a blt.n 800153e <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001528: 683b ldr r3, [r7, #0]
800152a: b2da uxtb r2, r3
800152c: 490c ldr r1, [pc, #48] @ (8001560 <__NVIC_SetPriority+0x4c>)
800152e: f997 3007 ldrsb.w r3, [r7, #7]
8001532: 0112 lsls r2, r2, #4
8001534: b2d2 uxtb r2, r2
8001536: 440b add r3, r1
8001538: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
800153c: e00a b.n 8001554 <__NVIC_SetPriority+0x40>
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800153e: 683b ldr r3, [r7, #0]
8001540: b2da uxtb r2, r3
8001542: 4908 ldr r1, [pc, #32] @ (8001564 <__NVIC_SetPriority+0x50>)
8001544: 79fb ldrb r3, [r7, #7]
8001546: f003 030f and.w r3, r3, #15
800154a: 3b04 subs r3, #4
800154c: 0112 lsls r2, r2, #4
800154e: b2d2 uxtb r2, r2
8001550: 440b add r3, r1
8001552: 761a strb r2, [r3, #24]
}
8001554: bf00 nop
8001556: 370c adds r7, #12
8001558: 46bd mov sp, r7
800155a: f85d 7b04 ldr.w r7, [sp], #4
800155e: 4770 bx lr
8001560: e000e100 .word 0xe000e100
8001564: e000ed00 .word 0xe000ed00
08001568 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001568: b480 push {r7}
800156a: b089 sub sp, #36 @ 0x24
800156c: af00 add r7, sp, #0
800156e: 60f8 str r0, [r7, #12]
8001570: 60b9 str r1, [r7, #8]
8001572: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8001574: 68fb ldr r3, [r7, #12]
8001576: f003 0307 and.w r3, r3, #7
800157a: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
800157c: 69fb ldr r3, [r7, #28]
800157e: f1c3 0307 rsb r3, r3, #7
8001582: 2b04 cmp r3, #4
8001584: bf28 it cs
8001586: 2304 movcs r3, #4
8001588: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
800158a: 69fb ldr r3, [r7, #28]
800158c: 3304 adds r3, #4
800158e: 2b06 cmp r3, #6
8001590: d902 bls.n 8001598 <NVIC_EncodePriority+0x30>
8001592: 69fb ldr r3, [r7, #28]
8001594: 3b03 subs r3, #3
8001596: e000 b.n 800159a <NVIC_EncodePriority+0x32>
8001598: 2300 movs r3, #0
800159a: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
800159c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
80015a0: 69bb ldr r3, [r7, #24]
80015a2: fa02 f303 lsl.w r3, r2, r3
80015a6: 43da mvns r2, r3
80015a8: 68bb ldr r3, [r7, #8]
80015aa: 401a ands r2, r3
80015ac: 697b ldr r3, [r7, #20]
80015ae: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80015b0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
80015b4: 697b ldr r3, [r7, #20]
80015b6: fa01 f303 lsl.w r3, r1, r3
80015ba: 43d9 mvns r1, r3
80015bc: 687b ldr r3, [r7, #4]
80015be: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80015c0: 4313 orrs r3, r2
);
}
80015c2: 4618 mov r0, r3
80015c4: 3724 adds r7, #36 @ 0x24
80015c6: 46bd mov sp, r7
80015c8: f85d 7b04 ldr.w r7, [sp], #4
80015cc: 4770 bx lr
080015ce <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80015ce: b580 push {r7, lr}
80015d0: b082 sub sp, #8
80015d2: af00 add r7, sp, #0
80015d4: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
80015d6: 6878 ldr r0, [r7, #4]
80015d8: f7ff ff4c bl 8001474 <__NVIC_SetPriorityGrouping>
}
80015dc: bf00 nop
80015de: 3708 adds r7, #8
80015e0: 46bd mov sp, r7
80015e2: bd80 pop {r7, pc}
080015e4 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
80015e4: b580 push {r7, lr}
80015e6: b086 sub sp, #24
80015e8: af00 add r7, sp, #0
80015ea: 4603 mov r3, r0
80015ec: 60b9 str r1, [r7, #8]
80015ee: 607a str r2, [r7, #4]
80015f0: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
80015f2: 2300 movs r3, #0
80015f4: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
80015f6: f7ff ff61 bl 80014bc <__NVIC_GetPriorityGrouping>
80015fa: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
80015fc: 687a ldr r2, [r7, #4]
80015fe: 68b9 ldr r1, [r7, #8]
8001600: 6978 ldr r0, [r7, #20]
8001602: f7ff ffb1 bl 8001568 <NVIC_EncodePriority>
8001606: 4602 mov r2, r0
8001608: f997 300f ldrsb.w r3, [r7, #15]
800160c: 4611 mov r1, r2
800160e: 4618 mov r0, r3
8001610: f7ff ff80 bl 8001514 <__NVIC_SetPriority>
}
8001614: bf00 nop
8001616: 3718 adds r7, #24
8001618: 46bd mov sp, r7
800161a: bd80 pop {r7, pc}
0800161c <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
800161c: b580 push {r7, lr}
800161e: b082 sub sp, #8
8001620: af00 add r7, sp, #0
8001622: 4603 mov r3, r0
8001624: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8001626: f997 3007 ldrsb.w r3, [r7, #7]
800162a: 4618 mov r0, r3
800162c: f7ff ff54 bl 80014d8 <__NVIC_EnableIRQ>
}
8001630: bf00 nop
8001632: 3708 adds r7, #8
8001634: 46bd mov sp, r7
8001636: bd80 pop {r7, pc}
08001638 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8001638: b480 push {r7}
800163a: b089 sub sp, #36 @ 0x24
800163c: af00 add r7, sp, #0
800163e: 6078 str r0, [r7, #4]
8001640: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
8001642: 2300 movs r3, #0
8001644: 61fb str r3, [r7, #28]
uint32_t ioposition = 0x00;
8001646: 2300 movs r3, #0
8001648: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
800164a: 2300 movs r3, #0
800164c: 613b str r3, [r7, #16]
uint32_t temp = 0x00;
800164e: 2300 movs r3, #0
8001650: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for (position = 0; position < GPIO_NUMBER; position++)
8001652: 2300 movs r3, #0
8001654: 61fb str r3, [r7, #28]
8001656: e169 b.n 800192c <HAL_GPIO_Init+0x2f4>
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
8001658: 2201 movs r2, #1
800165a: 69fb ldr r3, [r7, #28]
800165c: fa02 f303 lsl.w r3, r2, r3
8001660: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8001662: 683b ldr r3, [r7, #0]
8001664: 681b ldr r3, [r3, #0]
8001666: 697a ldr r2, [r7, #20]
8001668: 4013 ands r3, r2
800166a: 613b str r3, [r7, #16]
if (iocurrent == ioposition)
800166c: 693a ldr r2, [r7, #16]
800166e: 697b ldr r3, [r7, #20]
8001670: 429a cmp r2, r3
8001672: f040 8158 bne.w 8001926 <HAL_GPIO_Init+0x2ee>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8001676: 683b ldr r3, [r7, #0]
8001678: 685b ldr r3, [r3, #4]
800167a: f003 0303 and.w r3, r3, #3
800167e: 2b01 cmp r3, #1
8001680: d005 beq.n 800168e <HAL_GPIO_Init+0x56>
8001682: 683b ldr r3, [r7, #0]
8001684: 685b ldr r3, [r3, #4]
8001686: f003 0303 and.w r3, r3, #3
800168a: 2b02 cmp r3, #2
800168c: d130 bne.n 80016f0 <HAL_GPIO_Init+0xb8>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
800168e: 687b ldr r3, [r7, #4]
8001690: 689b ldr r3, [r3, #8]
8001692: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
8001694: 69fb ldr r3, [r7, #28]
8001696: 005b lsls r3, r3, #1
8001698: 2203 movs r2, #3
800169a: fa02 f303 lsl.w r3, r2, r3
800169e: 43db mvns r3, r3
80016a0: 69ba ldr r2, [r7, #24]
80016a2: 4013 ands r3, r2
80016a4: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2));
80016a6: 683b ldr r3, [r7, #0]
80016a8: 68da ldr r2, [r3, #12]
80016aa: 69fb ldr r3, [r7, #28]
80016ac: 005b lsls r3, r3, #1
80016ae: fa02 f303 lsl.w r3, r2, r3
80016b2: 69ba ldr r2, [r7, #24]
80016b4: 4313 orrs r3, r2
80016b6: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
80016b8: 687b ldr r3, [r7, #4]
80016ba: 69ba ldr r2, [r7, #24]
80016bc: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
80016be: 687b ldr r3, [r7, #4]
80016c0: 685b ldr r3, [r3, #4]
80016c2: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
80016c4: 2201 movs r2, #1
80016c6: 69fb ldr r3, [r7, #28]
80016c8: fa02 f303 lsl.w r3, r2, r3
80016cc: 43db mvns r3, r3
80016ce: 69ba ldr r2, [r7, #24]
80016d0: 4013 ands r3, r2
80016d2: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
80016d4: 683b ldr r3, [r7, #0]
80016d6: 685b ldr r3, [r3, #4]
80016d8: 091b lsrs r3, r3, #4
80016da: f003 0201 and.w r2, r3, #1
80016de: 69fb ldr r3, [r7, #28]
80016e0: fa02 f303 lsl.w r3, r2, r3
80016e4: 69ba ldr r2, [r7, #24]
80016e6: 4313 orrs r3, r2
80016e8: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
80016ea: 687b ldr r3, [r7, #4]
80016ec: 69ba ldr r2, [r7, #24]
80016ee: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
80016f0: 683b ldr r3, [r7, #0]
80016f2: 685b ldr r3, [r3, #4]
80016f4: f003 0303 and.w r3, r3, #3
80016f8: 2b03 cmp r3, #3
80016fa: d017 beq.n 800172c <HAL_GPIO_Init+0xf4>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80016fc: 687b ldr r3, [r7, #4]
80016fe: 68db ldr r3, [r3, #12]
8001700: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
8001702: 69fb ldr r3, [r7, #28]
8001704: 005b lsls r3, r3, #1
8001706: 2203 movs r2, #3
8001708: fa02 f303 lsl.w r3, r2, r3
800170c: 43db mvns r3, r3
800170e: 69ba ldr r2, [r7, #24]
8001710: 4013 ands r3, r2
8001712: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2));
8001714: 683b ldr r3, [r7, #0]
8001716: 689a ldr r2, [r3, #8]
8001718: 69fb ldr r3, [r7, #28]
800171a: 005b lsls r3, r3, #1
800171c: fa02 f303 lsl.w r3, r2, r3
8001720: 69ba ldr r2, [r7, #24]
8001722: 4313 orrs r3, r2
8001724: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
8001726: 687b ldr r3, [r7, #4]
8001728: 69ba ldr r2, [r7, #24]
800172a: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
800172c: 683b ldr r3, [r7, #0]
800172e: 685b ldr r3, [r3, #4]
8001730: f003 0303 and.w r3, r3, #3
8001734: 2b02 cmp r3, #2
8001736: d123 bne.n 8001780 <HAL_GPIO_Init+0x148>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
8001738: 69fb ldr r3, [r7, #28]
800173a: 08da lsrs r2, r3, #3
800173c: 687b ldr r3, [r7, #4]
800173e: 3208 adds r2, #8
8001740: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8001744: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
8001746: 69fb ldr r3, [r7, #28]
8001748: f003 0307 and.w r3, r3, #7
800174c: 009b lsls r3, r3, #2
800174e: 220f movs r2, #15
8001750: fa02 f303 lsl.w r3, r2, r3
8001754: 43db mvns r3, r3
8001756: 69ba ldr r2, [r7, #24]
8001758: 4013 ands r3, r2
800175a: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
800175c: 683b ldr r3, [r7, #0]
800175e: 691a ldr r2, [r3, #16]
8001760: 69fb ldr r3, [r7, #28]
8001762: f003 0307 and.w r3, r3, #7
8001766: 009b lsls r3, r3, #2
8001768: fa02 f303 lsl.w r3, r2, r3
800176c: 69ba ldr r2, [r7, #24]
800176e: 4313 orrs r3, r2
8001770: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3] = temp;
8001772: 69fb ldr r3, [r7, #28]
8001774: 08da lsrs r2, r3, #3
8001776: 687b ldr r3, [r7, #4]
8001778: 3208 adds r2, #8
800177a: 69b9 ldr r1, [r7, #24]
800177c: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8001780: 687b ldr r3, [r7, #4]
8001782: 681b ldr r3, [r3, #0]
8001784: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
8001786: 69fb ldr r3, [r7, #28]
8001788: 005b lsls r3, r3, #1
800178a: 2203 movs r2, #3
800178c: fa02 f303 lsl.w r3, r2, r3
8001790: 43db mvns r3, r3
8001792: 69ba ldr r2, [r7, #24]
8001794: 4013 ands r3, r2
8001796: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
8001798: 683b ldr r3, [r7, #0]
800179a: 685b ldr r3, [r3, #4]
800179c: f003 0203 and.w r2, r3, #3
80017a0: 69fb ldr r3, [r7, #28]
80017a2: 005b lsls r3, r3, #1
80017a4: fa02 f303 lsl.w r3, r2, r3
80017a8: 69ba ldr r2, [r7, #24]
80017aa: 4313 orrs r3, r2
80017ac: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
80017ae: 687b ldr r3, [r7, #4]
80017b0: 69ba ldr r2, [r7, #24]
80017b2: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
80017b4: 683b ldr r3, [r7, #0]
80017b6: 685b ldr r3, [r3, #4]
80017b8: f403 3340 and.w r3, r3, #196608 @ 0x30000
80017bc: 2b00 cmp r3, #0
80017be: f000 80b2 beq.w 8001926 <HAL_GPIO_Init+0x2ee>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80017c2: 4b60 ldr r3, [pc, #384] @ (8001944 <HAL_GPIO_Init+0x30c>)
80017c4: 6c5b ldr r3, [r3, #68] @ 0x44
80017c6: 4a5f ldr r2, [pc, #380] @ (8001944 <HAL_GPIO_Init+0x30c>)
80017c8: f443 4380 orr.w r3, r3, #16384 @ 0x4000
80017cc: 6453 str r3, [r2, #68] @ 0x44
80017ce: 4b5d ldr r3, [pc, #372] @ (8001944 <HAL_GPIO_Init+0x30c>)
80017d0: 6c5b ldr r3, [r3, #68] @ 0x44
80017d2: f403 4380 and.w r3, r3, #16384 @ 0x4000
80017d6: 60fb str r3, [r7, #12]
80017d8: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2];
80017da: 4a5b ldr r2, [pc, #364] @ (8001948 <HAL_GPIO_Init+0x310>)
80017dc: 69fb ldr r3, [r7, #28]
80017de: 089b lsrs r3, r3, #2
80017e0: 3302 adds r3, #2
80017e2: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80017e6: 61bb str r3, [r7, #24]
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
80017e8: 69fb ldr r3, [r7, #28]
80017ea: f003 0303 and.w r3, r3, #3
80017ee: 009b lsls r3, r3, #2
80017f0: 220f movs r2, #15
80017f2: fa02 f303 lsl.w r3, r2, r3
80017f6: 43db mvns r3, r3
80017f8: 69ba ldr r2, [r7, #24]
80017fa: 4013 ands r3, r2
80017fc: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
80017fe: 687b ldr r3, [r7, #4]
8001800: 4a52 ldr r2, [pc, #328] @ (800194c <HAL_GPIO_Init+0x314>)
8001802: 4293 cmp r3, r2
8001804: d02b beq.n 800185e <HAL_GPIO_Init+0x226>
8001806: 687b ldr r3, [r7, #4]
8001808: 4a51 ldr r2, [pc, #324] @ (8001950 <HAL_GPIO_Init+0x318>)
800180a: 4293 cmp r3, r2
800180c: d025 beq.n 800185a <HAL_GPIO_Init+0x222>
800180e: 687b ldr r3, [r7, #4]
8001810: 4a50 ldr r2, [pc, #320] @ (8001954 <HAL_GPIO_Init+0x31c>)
8001812: 4293 cmp r3, r2
8001814: d01f beq.n 8001856 <HAL_GPIO_Init+0x21e>
8001816: 687b ldr r3, [r7, #4]
8001818: 4a4f ldr r2, [pc, #316] @ (8001958 <HAL_GPIO_Init+0x320>)
800181a: 4293 cmp r3, r2
800181c: d019 beq.n 8001852 <HAL_GPIO_Init+0x21a>
800181e: 687b ldr r3, [r7, #4]
8001820: 4a4e ldr r2, [pc, #312] @ (800195c <HAL_GPIO_Init+0x324>)
8001822: 4293 cmp r3, r2
8001824: d013 beq.n 800184e <HAL_GPIO_Init+0x216>
8001826: 687b ldr r3, [r7, #4]
8001828: 4a4d ldr r2, [pc, #308] @ (8001960 <HAL_GPIO_Init+0x328>)
800182a: 4293 cmp r3, r2
800182c: d00d beq.n 800184a <HAL_GPIO_Init+0x212>
800182e: 687b ldr r3, [r7, #4]
8001830: 4a4c ldr r2, [pc, #304] @ (8001964 <HAL_GPIO_Init+0x32c>)
8001832: 4293 cmp r3, r2
8001834: d007 beq.n 8001846 <HAL_GPIO_Init+0x20e>
8001836: 687b ldr r3, [r7, #4]
8001838: 4a4b ldr r2, [pc, #300] @ (8001968 <HAL_GPIO_Init+0x330>)
800183a: 4293 cmp r3, r2
800183c: d101 bne.n 8001842 <HAL_GPIO_Init+0x20a>
800183e: 2307 movs r3, #7
8001840: e00e b.n 8001860 <HAL_GPIO_Init+0x228>
8001842: 2308 movs r3, #8
8001844: e00c b.n 8001860 <HAL_GPIO_Init+0x228>
8001846: 2306 movs r3, #6
8001848: e00a b.n 8001860 <HAL_GPIO_Init+0x228>
800184a: 2305 movs r3, #5
800184c: e008 b.n 8001860 <HAL_GPIO_Init+0x228>
800184e: 2304 movs r3, #4
8001850: e006 b.n 8001860 <HAL_GPIO_Init+0x228>
8001852: 2303 movs r3, #3
8001854: e004 b.n 8001860 <HAL_GPIO_Init+0x228>
8001856: 2302 movs r3, #2
8001858: e002 b.n 8001860 <HAL_GPIO_Init+0x228>
800185a: 2301 movs r3, #1
800185c: e000 b.n 8001860 <HAL_GPIO_Init+0x228>
800185e: 2300 movs r3, #0
8001860: 69fa ldr r2, [r7, #28]
8001862: f002 0203 and.w r2, r2, #3
8001866: 0092 lsls r2, r2, #2
8001868: 4093 lsls r3, r2
800186a: 69ba ldr r2, [r7, #24]
800186c: 4313 orrs r3, r2
800186e: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2] = temp;
8001870: 4935 ldr r1, [pc, #212] @ (8001948 <HAL_GPIO_Init+0x310>)
8001872: 69fb ldr r3, [r7, #28]
8001874: 089b lsrs r3, r3, #2
8001876: 3302 adds r3, #2
8001878: 69ba ldr r2, [r7, #24]
800187a: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
800187e: 4b3b ldr r3, [pc, #236] @ (800196c <HAL_GPIO_Init+0x334>)
8001880: 689b ldr r3, [r3, #8]
8001882: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001884: 693b ldr r3, [r7, #16]
8001886: 43db mvns r3, r3
8001888: 69ba ldr r2, [r7, #24]
800188a: 4013 ands r3, r2
800188c: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
800188e: 683b ldr r3, [r7, #0]
8001890: 685b ldr r3, [r3, #4]
8001892: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8001896: 2b00 cmp r3, #0
8001898: d003 beq.n 80018a2 <HAL_GPIO_Init+0x26a>
{
temp |= iocurrent;
800189a: 69ba ldr r2, [r7, #24]
800189c: 693b ldr r3, [r7, #16]
800189e: 4313 orrs r3, r2
80018a0: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
80018a2: 4a32 ldr r2, [pc, #200] @ (800196c <HAL_GPIO_Init+0x334>)
80018a4: 69bb ldr r3, [r7, #24]
80018a6: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
80018a8: 4b30 ldr r3, [pc, #192] @ (800196c <HAL_GPIO_Init+0x334>)
80018aa: 68db ldr r3, [r3, #12]
80018ac: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80018ae: 693b ldr r3, [r7, #16]
80018b0: 43db mvns r3, r3
80018b2: 69ba ldr r2, [r7, #24]
80018b4: 4013 ands r3, r2
80018b6: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
80018b8: 683b ldr r3, [r7, #0]
80018ba: 685b ldr r3, [r3, #4]
80018bc: f403 1300 and.w r3, r3, #2097152 @ 0x200000
80018c0: 2b00 cmp r3, #0
80018c2: d003 beq.n 80018cc <HAL_GPIO_Init+0x294>
{
temp |= iocurrent;
80018c4: 69ba ldr r2, [r7, #24]
80018c6: 693b ldr r3, [r7, #16]
80018c8: 4313 orrs r3, r2
80018ca: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
80018cc: 4a27 ldr r2, [pc, #156] @ (800196c <HAL_GPIO_Init+0x334>)
80018ce: 69bb ldr r3, [r7, #24]
80018d0: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
80018d2: 4b26 ldr r3, [pc, #152] @ (800196c <HAL_GPIO_Init+0x334>)
80018d4: 685b ldr r3, [r3, #4]
80018d6: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80018d8: 693b ldr r3, [r7, #16]
80018da: 43db mvns r3, r3
80018dc: 69ba ldr r2, [r7, #24]
80018de: 4013 ands r3, r2
80018e0: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
80018e2: 683b ldr r3, [r7, #0]
80018e4: 685b ldr r3, [r3, #4]
80018e6: f403 3300 and.w r3, r3, #131072 @ 0x20000
80018ea: 2b00 cmp r3, #0
80018ec: d003 beq.n 80018f6 <HAL_GPIO_Init+0x2be>
{
temp |= iocurrent;
80018ee: 69ba ldr r2, [r7, #24]
80018f0: 693b ldr r3, [r7, #16]
80018f2: 4313 orrs r3, r2
80018f4: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
80018f6: 4a1d ldr r2, [pc, #116] @ (800196c <HAL_GPIO_Init+0x334>)
80018f8: 69bb ldr r3, [r7, #24]
80018fa: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
80018fc: 4b1b ldr r3, [pc, #108] @ (800196c <HAL_GPIO_Init+0x334>)
80018fe: 681b ldr r3, [r3, #0]
8001900: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001902: 693b ldr r3, [r7, #16]
8001904: 43db mvns r3, r3
8001906: 69ba ldr r2, [r7, #24]
8001908: 4013 ands r3, r2
800190a: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
800190c: 683b ldr r3, [r7, #0]
800190e: 685b ldr r3, [r3, #4]
8001910: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001914: 2b00 cmp r3, #0
8001916: d003 beq.n 8001920 <HAL_GPIO_Init+0x2e8>
{
temp |= iocurrent;
8001918: 69ba ldr r2, [r7, #24]
800191a: 693b ldr r3, [r7, #16]
800191c: 4313 orrs r3, r2
800191e: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
8001920: 4a12 ldr r2, [pc, #72] @ (800196c <HAL_GPIO_Init+0x334>)
8001922: 69bb ldr r3, [r7, #24]
8001924: 6013 str r3, [r2, #0]
for (position = 0; position < GPIO_NUMBER; position++)
8001926: 69fb ldr r3, [r7, #28]
8001928: 3301 adds r3, #1
800192a: 61fb str r3, [r7, #28]
800192c: 69fb ldr r3, [r7, #28]
800192e: 2b0f cmp r3, #15
8001930: f67f ae92 bls.w 8001658 <HAL_GPIO_Init+0x20>
}
}
}
}
8001934: bf00 nop
8001936: bf00 nop
8001938: 3724 adds r7, #36 @ 0x24
800193a: 46bd mov sp, r7
800193c: f85d 7b04 ldr.w r7, [sp], #4
8001940: 4770 bx lr
8001942: bf00 nop
8001944: 40023800 .word 0x40023800
8001948: 40013800 .word 0x40013800
800194c: 40020000 .word 0x40020000
8001950: 40020400 .word 0x40020400
8001954: 40020800 .word 0x40020800
8001958: 40020c00 .word 0x40020c00
800195c: 40021000 .word 0x40021000
8001960: 40021400 .word 0x40021400
8001964: 40021800 .word 0x40021800
8001968: 40021c00 .word 0x40021c00
800196c: 40013c00 .word 0x40013c00
08001970 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
8001970: b480 push {r7}
8001972: b085 sub sp, #20
8001974: af00 add r7, sp, #0
8001976: 6078 str r0, [r7, #4]
8001978: 460b mov r3, r1
800197a: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
800197c: 687b ldr r3, [r7, #4]
800197e: 691a ldr r2, [r3, #16]
8001980: 887b ldrh r3, [r7, #2]
8001982: 4013 ands r3, r2
8001984: 2b00 cmp r3, #0
8001986: d002 beq.n 800198e <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8001988: 2301 movs r3, #1
800198a: 73fb strb r3, [r7, #15]
800198c: e001 b.n 8001992 <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
800198e: 2300 movs r3, #0
8001990: 73fb strb r3, [r7, #15]
}
return bitstatus;
8001992: 7bfb ldrb r3, [r7, #15]
}
8001994: 4618 mov r0, r3
8001996: 3714 adds r7, #20
8001998: 46bd mov sp, r7
800199a: f85d 7b04 ldr.w r7, [sp], #4
800199e: 4770 bx lr
080019a0 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
80019a0: b480 push {r7}
80019a2: b083 sub sp, #12
80019a4: af00 add r7, sp, #0
80019a6: 6078 str r0, [r7, #4]
80019a8: 460b mov r3, r1
80019aa: 807b strh r3, [r7, #2]
80019ac: 4613 mov r3, r2
80019ae: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
80019b0: 787b ldrb r3, [r7, #1]
80019b2: 2b00 cmp r3, #0
80019b4: d003 beq.n 80019be <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
80019b6: 887a ldrh r2, [r7, #2]
80019b8: 687b ldr r3, [r7, #4]
80019ba: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
}
}
80019bc: e003 b.n 80019c6 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
80019be: 887b ldrh r3, [r7, #2]
80019c0: 041a lsls r2, r3, #16
80019c2: 687b ldr r3, [r7, #4]
80019c4: 619a str r2, [r3, #24]
}
80019c6: bf00 nop
80019c8: 370c adds r7, #12
80019ca: 46bd mov sp, r7
80019cc: f85d 7b04 ldr.w r7, [sp], #4
80019d0: 4770 bx lr
080019d2 <HAL_GPIO_TogglePin>:
* @param GPIO_Pin Specifies the pins to be toggled.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
80019d2: b480 push {r7}
80019d4: b085 sub sp, #20
80019d6: af00 add r7, sp, #0
80019d8: 6078 str r0, [r7, #4]
80019da: 460b mov r3, r1
80019dc: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
80019de: 687b ldr r3, [r7, #4]
80019e0: 695b ldr r3, [r3, #20]
80019e2: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
80019e4: 887a ldrh r2, [r7, #2]
80019e6: 68fb ldr r3, [r7, #12]
80019e8: 4013 ands r3, r2
80019ea: 041a lsls r2, r3, #16
80019ec: 68fb ldr r3, [r7, #12]
80019ee: 43d9 mvns r1, r3
80019f0: 887b ldrh r3, [r7, #2]
80019f2: 400b ands r3, r1
80019f4: 431a orrs r2, r3
80019f6: 687b ldr r3, [r7, #4]
80019f8: 619a str r2, [r3, #24]
}
80019fa: bf00 nop
80019fc: 3714 adds r7, #20
80019fe: 46bd mov sp, r7
8001a00: f85d 7b04 ldr.w r7, [sp], #4
8001a04: 4770 bx lr
...
08001a08 <HAL_PWR_EnableBkUpAccess>:
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
8001a08: b480 push {r7}
8001a0a: af00 add r7, sp, #0
/* Enable access to RTC and backup registers */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8001a0c: 4b05 ldr r3, [pc, #20] @ (8001a24 <HAL_PWR_EnableBkUpAccess+0x1c>)
8001a0e: 681b ldr r3, [r3, #0]
8001a10: 4a04 ldr r2, [pc, #16] @ (8001a24 <HAL_PWR_EnableBkUpAccess+0x1c>)
8001a12: f443 7380 orr.w r3, r3, #256 @ 0x100
8001a16: 6013 str r3, [r2, #0]
}
8001a18: bf00 nop
8001a1a: 46bd mov sp, r7
8001a1c: f85d 7b04 ldr.w r7, [sp], #4
8001a20: 4770 bx lr
8001a22: bf00 nop
8001a24: 40007000 .word 0x40007000
08001a28 <HAL_PWREx_EnableOverDrive>:
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
{
8001a28: b580 push {r7, lr}
8001a2a: b082 sub sp, #8
8001a2c: af00 add r7, sp, #0
uint32_t tickstart = 0;
8001a2e: 2300 movs r3, #0
8001a30: 607b str r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8001a32: 4b23 ldr r3, [pc, #140] @ (8001ac0 <HAL_PWREx_EnableOverDrive+0x98>)
8001a34: 6c1b ldr r3, [r3, #64] @ 0x40
8001a36: 4a22 ldr r2, [pc, #136] @ (8001ac0 <HAL_PWREx_EnableOverDrive+0x98>)
8001a38: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001a3c: 6413 str r3, [r2, #64] @ 0x40
8001a3e: 4b20 ldr r3, [pc, #128] @ (8001ac0 <HAL_PWREx_EnableOverDrive+0x98>)
8001a40: 6c1b ldr r3, [r3, #64] @ 0x40
8001a42: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001a46: 603b str r3, [r7, #0]
8001a48: 683b ldr r3, [r7, #0]
/* Enable the Over-drive to extend the clock frequency to 216 MHz */
__HAL_PWR_OVERDRIVE_ENABLE();
8001a4a: 4b1e ldr r3, [pc, #120] @ (8001ac4 <HAL_PWREx_EnableOverDrive+0x9c>)
8001a4c: 681b ldr r3, [r3, #0]
8001a4e: 4a1d ldr r2, [pc, #116] @ (8001ac4 <HAL_PWREx_EnableOverDrive+0x9c>)
8001a50: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001a54: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8001a56: f7ff fd01 bl 800145c <HAL_GetTick>
8001a5a: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
8001a5c: e009 b.n 8001a72 <HAL_PWREx_EnableOverDrive+0x4a>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8001a5e: f7ff fcfd bl 800145c <HAL_GetTick>
8001a62: 4602 mov r2, r0
8001a64: 687b ldr r3, [r7, #4]
8001a66: 1ad3 subs r3, r2, r3
8001a68: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
8001a6c: d901 bls.n 8001a72 <HAL_PWREx_EnableOverDrive+0x4a>
{
return HAL_TIMEOUT;
8001a6e: 2303 movs r3, #3
8001a70: e022 b.n 8001ab8 <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
8001a72: 4b14 ldr r3, [pc, #80] @ (8001ac4 <HAL_PWREx_EnableOverDrive+0x9c>)
8001a74: 685b ldr r3, [r3, #4]
8001a76: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001a7a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8001a7e: d1ee bne.n 8001a5e <HAL_PWREx_EnableOverDrive+0x36>
}
}
/* Enable the Over-drive switch */
__HAL_PWR_OVERDRIVESWITCHING_ENABLE();
8001a80: 4b10 ldr r3, [pc, #64] @ (8001ac4 <HAL_PWREx_EnableOverDrive+0x9c>)
8001a82: 681b ldr r3, [r3, #0]
8001a84: 4a0f ldr r2, [pc, #60] @ (8001ac4 <HAL_PWREx_EnableOverDrive+0x9c>)
8001a86: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8001a8a: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8001a8c: f7ff fce6 bl 800145c <HAL_GetTick>
8001a90: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
8001a92: e009 b.n 8001aa8 <HAL_PWREx_EnableOverDrive+0x80>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8001a94: f7ff fce2 bl 800145c <HAL_GetTick>
8001a98: 4602 mov r2, r0
8001a9a: 687b ldr r3, [r7, #4]
8001a9c: 1ad3 subs r3, r2, r3
8001a9e: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
8001aa2: d901 bls.n 8001aa8 <HAL_PWREx_EnableOverDrive+0x80>
{
return HAL_TIMEOUT;
8001aa4: 2303 movs r3, #3
8001aa6: e007 b.n 8001ab8 <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
8001aa8: 4b06 ldr r3, [pc, #24] @ (8001ac4 <HAL_PWREx_EnableOverDrive+0x9c>)
8001aaa: 685b ldr r3, [r3, #4]
8001aac: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001ab0: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
8001ab4: d1ee bne.n 8001a94 <HAL_PWREx_EnableOverDrive+0x6c>
}
}
return HAL_OK;
8001ab6: 2300 movs r3, #0
}
8001ab8: 4618 mov r0, r3
8001aba: 3708 adds r7, #8
8001abc: 46bd mov sp, r7
8001abe: bd80 pop {r7, pc}
8001ac0: 40023800 .word 0x40023800
8001ac4: 40007000 .word 0x40007000
08001ac8 <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8001ac8: b580 push {r7, lr}
8001aca: b086 sub sp, #24
8001acc: af00 add r7, sp, #0
8001ace: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
FlagStatus pwrclkchanged = RESET;
8001ad0: 2300 movs r3, #0
8001ad2: 75fb strb r3, [r7, #23]
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8001ad4: 687b ldr r3, [r7, #4]
8001ad6: 2b00 cmp r3, #0
8001ad8: d101 bne.n 8001ade <HAL_RCC_OscConfig+0x16>
{
return HAL_ERROR;
8001ada: 2301 movs r3, #1
8001adc: e291 b.n 8002002 <HAL_RCC_OscConfig+0x53a>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8001ade: 687b ldr r3, [r7, #4]
8001ae0: 681b ldr r3, [r3, #0]
8001ae2: f003 0301 and.w r3, r3, #1
8001ae6: 2b00 cmp r3, #0
8001ae8: f000 8087 beq.w 8001bfa <HAL_RCC_OscConfig+0x132>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8001aec: 4b96 ldr r3, [pc, #600] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001aee: 689b ldr r3, [r3, #8]
8001af0: f003 030c and.w r3, r3, #12
8001af4: 2b04 cmp r3, #4
8001af6: d00c beq.n 8001b12 <HAL_RCC_OscConfig+0x4a>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8001af8: 4b93 ldr r3, [pc, #588] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001afa: 689b ldr r3, [r3, #8]
8001afc: f003 030c and.w r3, r3, #12
8001b00: 2b08 cmp r3, #8
8001b02: d112 bne.n 8001b2a <HAL_RCC_OscConfig+0x62>
8001b04: 4b90 ldr r3, [pc, #576] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001b06: 685b ldr r3, [r3, #4]
8001b08: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8001b0c: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8001b10: d10b bne.n 8001b2a <HAL_RCC_OscConfig+0x62>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001b12: 4b8d ldr r3, [pc, #564] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001b14: 681b ldr r3, [r3, #0]
8001b16: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001b1a: 2b00 cmp r3, #0
8001b1c: d06c beq.n 8001bf8 <HAL_RCC_OscConfig+0x130>
8001b1e: 687b ldr r3, [r7, #4]
8001b20: 685b ldr r3, [r3, #4]
8001b22: 2b00 cmp r3, #0
8001b24: d168 bne.n 8001bf8 <HAL_RCC_OscConfig+0x130>
{
return HAL_ERROR;
8001b26: 2301 movs r3, #1
8001b28: e26b b.n 8002002 <HAL_RCC_OscConfig+0x53a>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8001b2a: 687b ldr r3, [r7, #4]
8001b2c: 685b ldr r3, [r3, #4]
8001b2e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8001b32: d106 bne.n 8001b42 <HAL_RCC_OscConfig+0x7a>
8001b34: 4b84 ldr r3, [pc, #528] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001b36: 681b ldr r3, [r3, #0]
8001b38: 4a83 ldr r2, [pc, #524] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001b3a: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001b3e: 6013 str r3, [r2, #0]
8001b40: e02e b.n 8001ba0 <HAL_RCC_OscConfig+0xd8>
8001b42: 687b ldr r3, [r7, #4]
8001b44: 685b ldr r3, [r3, #4]
8001b46: 2b00 cmp r3, #0
8001b48: d10c bne.n 8001b64 <HAL_RCC_OscConfig+0x9c>
8001b4a: 4b7f ldr r3, [pc, #508] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001b4c: 681b ldr r3, [r3, #0]
8001b4e: 4a7e ldr r2, [pc, #504] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001b50: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8001b54: 6013 str r3, [r2, #0]
8001b56: 4b7c ldr r3, [pc, #496] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001b58: 681b ldr r3, [r3, #0]
8001b5a: 4a7b ldr r2, [pc, #492] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001b5c: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8001b60: 6013 str r3, [r2, #0]
8001b62: e01d b.n 8001ba0 <HAL_RCC_OscConfig+0xd8>
8001b64: 687b ldr r3, [r7, #4]
8001b66: 685b ldr r3, [r3, #4]
8001b68: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8001b6c: d10c bne.n 8001b88 <HAL_RCC_OscConfig+0xc0>
8001b6e: 4b76 ldr r3, [pc, #472] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001b70: 681b ldr r3, [r3, #0]
8001b72: 4a75 ldr r2, [pc, #468] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001b74: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8001b78: 6013 str r3, [r2, #0]
8001b7a: 4b73 ldr r3, [pc, #460] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001b7c: 681b ldr r3, [r3, #0]
8001b7e: 4a72 ldr r2, [pc, #456] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001b80: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001b84: 6013 str r3, [r2, #0]
8001b86: e00b b.n 8001ba0 <HAL_RCC_OscConfig+0xd8>
8001b88: 4b6f ldr r3, [pc, #444] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001b8a: 681b ldr r3, [r3, #0]
8001b8c: 4a6e ldr r2, [pc, #440] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001b8e: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8001b92: 6013 str r3, [r2, #0]
8001b94: 4b6c ldr r3, [pc, #432] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001b96: 681b ldr r3, [r3, #0]
8001b98: 4a6b ldr r2, [pc, #428] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001b9a: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8001b9e: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8001ba0: 687b ldr r3, [r7, #4]
8001ba2: 685b ldr r3, [r3, #4]
8001ba4: 2b00 cmp r3, #0
8001ba6: d013 beq.n 8001bd0 <HAL_RCC_OscConfig+0x108>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001ba8: f7ff fc58 bl 800145c <HAL_GetTick>
8001bac: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001bae: e008 b.n 8001bc2 <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8001bb0: f7ff fc54 bl 800145c <HAL_GetTick>
8001bb4: 4602 mov r2, r0
8001bb6: 693b ldr r3, [r7, #16]
8001bb8: 1ad3 subs r3, r2, r3
8001bba: 2b64 cmp r3, #100 @ 0x64
8001bbc: d901 bls.n 8001bc2 <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
8001bbe: 2303 movs r3, #3
8001bc0: e21f b.n 8002002 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001bc2: 4b61 ldr r3, [pc, #388] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001bc4: 681b ldr r3, [r3, #0]
8001bc6: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001bca: 2b00 cmp r3, #0
8001bcc: d0f0 beq.n 8001bb0 <HAL_RCC_OscConfig+0xe8>
8001bce: e014 b.n 8001bfa <HAL_RCC_OscConfig+0x132>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001bd0: f7ff fc44 bl 800145c <HAL_GetTick>
8001bd4: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8001bd6: e008 b.n 8001bea <HAL_RCC_OscConfig+0x122>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8001bd8: f7ff fc40 bl 800145c <HAL_GetTick>
8001bdc: 4602 mov r2, r0
8001bde: 693b ldr r3, [r7, #16]
8001be0: 1ad3 subs r3, r2, r3
8001be2: 2b64 cmp r3, #100 @ 0x64
8001be4: d901 bls.n 8001bea <HAL_RCC_OscConfig+0x122>
{
return HAL_TIMEOUT;
8001be6: 2303 movs r3, #3
8001be8: e20b b.n 8002002 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8001bea: 4b57 ldr r3, [pc, #348] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001bec: 681b ldr r3, [r3, #0]
8001bee: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001bf2: 2b00 cmp r3, #0
8001bf4: d1f0 bne.n 8001bd8 <HAL_RCC_OscConfig+0x110>
8001bf6: e000 b.n 8001bfa <HAL_RCC_OscConfig+0x132>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001bf8: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8001bfa: 687b ldr r3, [r7, #4]
8001bfc: 681b ldr r3, [r3, #0]
8001bfe: f003 0302 and.w r3, r3, #2
8001c02: 2b00 cmp r3, #0
8001c04: d069 beq.n 8001cda <HAL_RCC_OscConfig+0x212>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8001c06: 4b50 ldr r3, [pc, #320] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001c08: 689b ldr r3, [r3, #8]
8001c0a: f003 030c and.w r3, r3, #12
8001c0e: 2b00 cmp r3, #0
8001c10: d00b beq.n 8001c2a <HAL_RCC_OscConfig+0x162>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
8001c12: 4b4d ldr r3, [pc, #308] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001c14: 689b ldr r3, [r3, #8]
8001c16: f003 030c and.w r3, r3, #12
8001c1a: 2b08 cmp r3, #8
8001c1c: d11c bne.n 8001c58 <HAL_RCC_OscConfig+0x190>
8001c1e: 4b4a ldr r3, [pc, #296] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001c20: 685b ldr r3, [r3, #4]
8001c22: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8001c26: 2b00 cmp r3, #0
8001c28: d116 bne.n 8001c58 <HAL_RCC_OscConfig+0x190>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001c2a: 4b47 ldr r3, [pc, #284] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001c2c: 681b ldr r3, [r3, #0]
8001c2e: f003 0302 and.w r3, r3, #2
8001c32: 2b00 cmp r3, #0
8001c34: d005 beq.n 8001c42 <HAL_RCC_OscConfig+0x17a>
8001c36: 687b ldr r3, [r7, #4]
8001c38: 68db ldr r3, [r3, #12]
8001c3a: 2b01 cmp r3, #1
8001c3c: d001 beq.n 8001c42 <HAL_RCC_OscConfig+0x17a>
{
return HAL_ERROR;
8001c3e: 2301 movs r3, #1
8001c40: e1df b.n 8002002 <HAL_RCC_OscConfig+0x53a>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001c42: 4b41 ldr r3, [pc, #260] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001c44: 681b ldr r3, [r3, #0]
8001c46: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8001c4a: 687b ldr r3, [r7, #4]
8001c4c: 691b ldr r3, [r3, #16]
8001c4e: 00db lsls r3, r3, #3
8001c50: 493d ldr r1, [pc, #244] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001c52: 4313 orrs r3, r2
8001c54: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001c56: e040 b.n 8001cda <HAL_RCC_OscConfig+0x212>
}
}
else
{
/* Check the HSI State */
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
8001c58: 687b ldr r3, [r7, #4]
8001c5a: 68db ldr r3, [r3, #12]
8001c5c: 2b00 cmp r3, #0
8001c5e: d023 beq.n 8001ca8 <HAL_RCC_OscConfig+0x1e0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8001c60: 4b39 ldr r3, [pc, #228] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001c62: 681b ldr r3, [r3, #0]
8001c64: 4a38 ldr r2, [pc, #224] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001c66: f043 0301 orr.w r3, r3, #1
8001c6a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001c6c: f7ff fbf6 bl 800145c <HAL_GetTick>
8001c70: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001c72: e008 b.n 8001c86 <HAL_RCC_OscConfig+0x1be>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8001c74: f7ff fbf2 bl 800145c <HAL_GetTick>
8001c78: 4602 mov r2, r0
8001c7a: 693b ldr r3, [r7, #16]
8001c7c: 1ad3 subs r3, r2, r3
8001c7e: 2b02 cmp r3, #2
8001c80: d901 bls.n 8001c86 <HAL_RCC_OscConfig+0x1be>
{
return HAL_TIMEOUT;
8001c82: 2303 movs r3, #3
8001c84: e1bd b.n 8002002 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001c86: 4b30 ldr r3, [pc, #192] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001c88: 681b ldr r3, [r3, #0]
8001c8a: f003 0302 and.w r3, r3, #2
8001c8e: 2b00 cmp r3, #0
8001c90: d0f0 beq.n 8001c74 <HAL_RCC_OscConfig+0x1ac>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001c92: 4b2d ldr r3, [pc, #180] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001c94: 681b ldr r3, [r3, #0]
8001c96: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8001c9a: 687b ldr r3, [r7, #4]
8001c9c: 691b ldr r3, [r3, #16]
8001c9e: 00db lsls r3, r3, #3
8001ca0: 4929 ldr r1, [pc, #164] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001ca2: 4313 orrs r3, r2
8001ca4: 600b str r3, [r1, #0]
8001ca6: e018 b.n 8001cda <HAL_RCC_OscConfig+0x212>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001ca8: 4b27 ldr r3, [pc, #156] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001caa: 681b ldr r3, [r3, #0]
8001cac: 4a26 ldr r2, [pc, #152] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001cae: f023 0301 bic.w r3, r3, #1
8001cb2: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001cb4: f7ff fbd2 bl 800145c <HAL_GetTick>
8001cb8: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001cba: e008 b.n 8001cce <HAL_RCC_OscConfig+0x206>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8001cbc: f7ff fbce bl 800145c <HAL_GetTick>
8001cc0: 4602 mov r2, r0
8001cc2: 693b ldr r3, [r7, #16]
8001cc4: 1ad3 subs r3, r2, r3
8001cc6: 2b02 cmp r3, #2
8001cc8: d901 bls.n 8001cce <HAL_RCC_OscConfig+0x206>
{
return HAL_TIMEOUT;
8001cca: 2303 movs r3, #3
8001ccc: e199 b.n 8002002 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001cce: 4b1e ldr r3, [pc, #120] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001cd0: 681b ldr r3, [r3, #0]
8001cd2: f003 0302 and.w r3, r3, #2
8001cd6: 2b00 cmp r3, #0
8001cd8: d1f0 bne.n 8001cbc <HAL_RCC_OscConfig+0x1f4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8001cda: 687b ldr r3, [r7, #4]
8001cdc: 681b ldr r3, [r3, #0]
8001cde: f003 0308 and.w r3, r3, #8
8001ce2: 2b00 cmp r3, #0
8001ce4: d038 beq.n 8001d58 <HAL_RCC_OscConfig+0x290>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
8001ce6: 687b ldr r3, [r7, #4]
8001ce8: 695b ldr r3, [r3, #20]
8001cea: 2b00 cmp r3, #0
8001cec: d019 beq.n 8001d22 <HAL_RCC_OscConfig+0x25a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001cee: 4b16 ldr r3, [pc, #88] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001cf0: 6f5b ldr r3, [r3, #116] @ 0x74
8001cf2: 4a15 ldr r2, [pc, #84] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001cf4: f043 0301 orr.w r3, r3, #1
8001cf8: 6753 str r3, [r2, #116] @ 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001cfa: f7ff fbaf bl 800145c <HAL_GetTick>
8001cfe: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001d00: e008 b.n 8001d14 <HAL_RCC_OscConfig+0x24c>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8001d02: f7ff fbab bl 800145c <HAL_GetTick>
8001d06: 4602 mov r2, r0
8001d08: 693b ldr r3, [r7, #16]
8001d0a: 1ad3 subs r3, r2, r3
8001d0c: 2b02 cmp r3, #2
8001d0e: d901 bls.n 8001d14 <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
8001d10: 2303 movs r3, #3
8001d12: e176 b.n 8002002 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001d14: 4b0c ldr r3, [pc, #48] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001d16: 6f5b ldr r3, [r3, #116] @ 0x74
8001d18: f003 0302 and.w r3, r3, #2
8001d1c: 2b00 cmp r3, #0
8001d1e: d0f0 beq.n 8001d02 <HAL_RCC_OscConfig+0x23a>
8001d20: e01a b.n 8001d58 <HAL_RCC_OscConfig+0x290>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001d22: 4b09 ldr r3, [pc, #36] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001d24: 6f5b ldr r3, [r3, #116] @ 0x74
8001d26: 4a08 ldr r2, [pc, #32] @ (8001d48 <HAL_RCC_OscConfig+0x280>)
8001d28: f023 0301 bic.w r3, r3, #1
8001d2c: 6753 str r3, [r2, #116] @ 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001d2e: f7ff fb95 bl 800145c <HAL_GetTick>
8001d32: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001d34: e00a b.n 8001d4c <HAL_RCC_OscConfig+0x284>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8001d36: f7ff fb91 bl 800145c <HAL_GetTick>
8001d3a: 4602 mov r2, r0
8001d3c: 693b ldr r3, [r7, #16]
8001d3e: 1ad3 subs r3, r2, r3
8001d40: 2b02 cmp r3, #2
8001d42: d903 bls.n 8001d4c <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
8001d44: 2303 movs r3, #3
8001d46: e15c b.n 8002002 <HAL_RCC_OscConfig+0x53a>
8001d48: 40023800 .word 0x40023800
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001d4c: 4b91 ldr r3, [pc, #580] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001d4e: 6f5b ldr r3, [r3, #116] @ 0x74
8001d50: f003 0302 and.w r3, r3, #2
8001d54: 2b00 cmp r3, #0
8001d56: d1ee bne.n 8001d36 <HAL_RCC_OscConfig+0x26e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8001d58: 687b ldr r3, [r7, #4]
8001d5a: 681b ldr r3, [r3, #0]
8001d5c: f003 0304 and.w r3, r3, #4
8001d60: 2b00 cmp r3, #0
8001d62: f000 80a4 beq.w 8001eae <HAL_RCC_OscConfig+0x3e6>
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8001d66: 4b8b ldr r3, [pc, #556] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001d68: 6c1b ldr r3, [r3, #64] @ 0x40
8001d6a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001d6e: 2b00 cmp r3, #0
8001d70: d10d bne.n 8001d8e <HAL_RCC_OscConfig+0x2c6>
{
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
8001d72: 4b88 ldr r3, [pc, #544] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001d74: 6c1b ldr r3, [r3, #64] @ 0x40
8001d76: 4a87 ldr r2, [pc, #540] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001d78: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001d7c: 6413 str r3, [r2, #64] @ 0x40
8001d7e: 4b85 ldr r3, [pc, #532] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001d80: 6c1b ldr r3, [r3, #64] @ 0x40
8001d82: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001d86: 60bb str r3, [r7, #8]
8001d88: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8001d8a: 2301 movs r3, #1
8001d8c: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001d8e: 4b82 ldr r3, [pc, #520] @ (8001f98 <HAL_RCC_OscConfig+0x4d0>)
8001d90: 681b ldr r3, [r3, #0]
8001d92: f403 7380 and.w r3, r3, #256 @ 0x100
8001d96: 2b00 cmp r3, #0
8001d98: d118 bne.n 8001dcc <HAL_RCC_OscConfig+0x304>
{
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
8001d9a: 4b7f ldr r3, [pc, #508] @ (8001f98 <HAL_RCC_OscConfig+0x4d0>)
8001d9c: 681b ldr r3, [r3, #0]
8001d9e: 4a7e ldr r2, [pc, #504] @ (8001f98 <HAL_RCC_OscConfig+0x4d0>)
8001da0: f443 7380 orr.w r3, r3, #256 @ 0x100
8001da4: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8001da6: f7ff fb59 bl 800145c <HAL_GetTick>
8001daa: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001dac: e008 b.n 8001dc0 <HAL_RCC_OscConfig+0x2f8>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001dae: f7ff fb55 bl 800145c <HAL_GetTick>
8001db2: 4602 mov r2, r0
8001db4: 693b ldr r3, [r7, #16]
8001db6: 1ad3 subs r3, r2, r3
8001db8: 2b64 cmp r3, #100 @ 0x64
8001dba: d901 bls.n 8001dc0 <HAL_RCC_OscConfig+0x2f8>
{
return HAL_TIMEOUT;
8001dbc: 2303 movs r3, #3
8001dbe: e120 b.n 8002002 <HAL_RCC_OscConfig+0x53a>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001dc0: 4b75 ldr r3, [pc, #468] @ (8001f98 <HAL_RCC_OscConfig+0x4d0>)
8001dc2: 681b ldr r3, [r3, #0]
8001dc4: f403 7380 and.w r3, r3, #256 @ 0x100
8001dc8: 2b00 cmp r3, #0
8001dca: d0f0 beq.n 8001dae <HAL_RCC_OscConfig+0x2e6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001dcc: 687b ldr r3, [r7, #4]
8001dce: 689b ldr r3, [r3, #8]
8001dd0: 2b01 cmp r3, #1
8001dd2: d106 bne.n 8001de2 <HAL_RCC_OscConfig+0x31a>
8001dd4: 4b6f ldr r3, [pc, #444] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001dd6: 6f1b ldr r3, [r3, #112] @ 0x70
8001dd8: 4a6e ldr r2, [pc, #440] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001dda: f043 0301 orr.w r3, r3, #1
8001dde: 6713 str r3, [r2, #112] @ 0x70
8001de0: e02d b.n 8001e3e <HAL_RCC_OscConfig+0x376>
8001de2: 687b ldr r3, [r7, #4]
8001de4: 689b ldr r3, [r3, #8]
8001de6: 2b00 cmp r3, #0
8001de8: d10c bne.n 8001e04 <HAL_RCC_OscConfig+0x33c>
8001dea: 4b6a ldr r3, [pc, #424] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001dec: 6f1b ldr r3, [r3, #112] @ 0x70
8001dee: 4a69 ldr r2, [pc, #420] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001df0: f023 0301 bic.w r3, r3, #1
8001df4: 6713 str r3, [r2, #112] @ 0x70
8001df6: 4b67 ldr r3, [pc, #412] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001df8: 6f1b ldr r3, [r3, #112] @ 0x70
8001dfa: 4a66 ldr r2, [pc, #408] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001dfc: f023 0304 bic.w r3, r3, #4
8001e00: 6713 str r3, [r2, #112] @ 0x70
8001e02: e01c b.n 8001e3e <HAL_RCC_OscConfig+0x376>
8001e04: 687b ldr r3, [r7, #4]
8001e06: 689b ldr r3, [r3, #8]
8001e08: 2b05 cmp r3, #5
8001e0a: d10c bne.n 8001e26 <HAL_RCC_OscConfig+0x35e>
8001e0c: 4b61 ldr r3, [pc, #388] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001e0e: 6f1b ldr r3, [r3, #112] @ 0x70
8001e10: 4a60 ldr r2, [pc, #384] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001e12: f043 0304 orr.w r3, r3, #4
8001e16: 6713 str r3, [r2, #112] @ 0x70
8001e18: 4b5e ldr r3, [pc, #376] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001e1a: 6f1b ldr r3, [r3, #112] @ 0x70
8001e1c: 4a5d ldr r2, [pc, #372] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001e1e: f043 0301 orr.w r3, r3, #1
8001e22: 6713 str r3, [r2, #112] @ 0x70
8001e24: e00b b.n 8001e3e <HAL_RCC_OscConfig+0x376>
8001e26: 4b5b ldr r3, [pc, #364] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001e28: 6f1b ldr r3, [r3, #112] @ 0x70
8001e2a: 4a5a ldr r2, [pc, #360] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001e2c: f023 0301 bic.w r3, r3, #1
8001e30: 6713 str r3, [r2, #112] @ 0x70
8001e32: 4b58 ldr r3, [pc, #352] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001e34: 6f1b ldr r3, [r3, #112] @ 0x70
8001e36: 4a57 ldr r2, [pc, #348] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001e38: f023 0304 bic.w r3, r3, #4
8001e3c: 6713 str r3, [r2, #112] @ 0x70
/* Check the LSE State */
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8001e3e: 687b ldr r3, [r7, #4]
8001e40: 689b ldr r3, [r3, #8]
8001e42: 2b00 cmp r3, #0
8001e44: d015 beq.n 8001e72 <HAL_RCC_OscConfig+0x3aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001e46: f7ff fb09 bl 800145c <HAL_GetTick>
8001e4a: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001e4c: e00a b.n 8001e64 <HAL_RCC_OscConfig+0x39c>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8001e4e: f7ff fb05 bl 800145c <HAL_GetTick>
8001e52: 4602 mov r2, r0
8001e54: 693b ldr r3, [r7, #16]
8001e56: 1ad3 subs r3, r2, r3
8001e58: f241 3288 movw r2, #5000 @ 0x1388
8001e5c: 4293 cmp r3, r2
8001e5e: d901 bls.n 8001e64 <HAL_RCC_OscConfig+0x39c>
{
return HAL_TIMEOUT;
8001e60: 2303 movs r3, #3
8001e62: e0ce b.n 8002002 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001e64: 4b4b ldr r3, [pc, #300] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001e66: 6f1b ldr r3, [r3, #112] @ 0x70
8001e68: f003 0302 and.w r3, r3, #2
8001e6c: 2b00 cmp r3, #0
8001e6e: d0ee beq.n 8001e4e <HAL_RCC_OscConfig+0x386>
8001e70: e014 b.n 8001e9c <HAL_RCC_OscConfig+0x3d4>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001e72: f7ff faf3 bl 800145c <HAL_GetTick>
8001e76: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001e78: e00a b.n 8001e90 <HAL_RCC_OscConfig+0x3c8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8001e7a: f7ff faef bl 800145c <HAL_GetTick>
8001e7e: 4602 mov r2, r0
8001e80: 693b ldr r3, [r7, #16]
8001e82: 1ad3 subs r3, r2, r3
8001e84: f241 3288 movw r2, #5000 @ 0x1388
8001e88: 4293 cmp r3, r2
8001e8a: d901 bls.n 8001e90 <HAL_RCC_OscConfig+0x3c8>
{
return HAL_TIMEOUT;
8001e8c: 2303 movs r3, #3
8001e8e: e0b8 b.n 8002002 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001e90: 4b40 ldr r3, [pc, #256] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001e92: 6f1b ldr r3, [r3, #112] @ 0x70
8001e94: f003 0302 and.w r3, r3, #2
8001e98: 2b00 cmp r3, #0
8001e9a: d1ee bne.n 8001e7a <HAL_RCC_OscConfig+0x3b2>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
8001e9c: 7dfb ldrb r3, [r7, #23]
8001e9e: 2b01 cmp r3, #1
8001ea0: d105 bne.n 8001eae <HAL_RCC_OscConfig+0x3e6>
{
__HAL_RCC_PWR_CLK_DISABLE();
8001ea2: 4b3c ldr r3, [pc, #240] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001ea4: 6c1b ldr r3, [r3, #64] @ 0x40
8001ea6: 4a3b ldr r2, [pc, #236] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001ea8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8001eac: 6413 str r3, [r2, #64] @ 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8001eae: 687b ldr r3, [r7, #4]
8001eb0: 699b ldr r3, [r3, #24]
8001eb2: 2b00 cmp r3, #0
8001eb4: f000 80a4 beq.w 8002000 <HAL_RCC_OscConfig+0x538>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8001eb8: 4b36 ldr r3, [pc, #216] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001eba: 689b ldr r3, [r3, #8]
8001ebc: f003 030c and.w r3, r3, #12
8001ec0: 2b08 cmp r3, #8
8001ec2: d06b beq.n 8001f9c <HAL_RCC_OscConfig+0x4d4>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8001ec4: 687b ldr r3, [r7, #4]
8001ec6: 699b ldr r3, [r3, #24]
8001ec8: 2b02 cmp r3, #2
8001eca: d149 bne.n 8001f60 <HAL_RCC_OscConfig+0x498>
#if defined (RCC_PLLCFGR_PLLR)
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001ecc: 4b31 ldr r3, [pc, #196] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001ece: 681b ldr r3, [r3, #0]
8001ed0: 4a30 ldr r2, [pc, #192] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001ed2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8001ed6: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001ed8: f7ff fac0 bl 800145c <HAL_GetTick>
8001edc: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001ede: e008 b.n 8001ef2 <HAL_RCC_OscConfig+0x42a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001ee0: f7ff fabc bl 800145c <HAL_GetTick>
8001ee4: 4602 mov r2, r0
8001ee6: 693b ldr r3, [r7, #16]
8001ee8: 1ad3 subs r3, r2, r3
8001eea: 2b02 cmp r3, #2
8001eec: d901 bls.n 8001ef2 <HAL_RCC_OscConfig+0x42a>
{
return HAL_TIMEOUT;
8001eee: 2303 movs r3, #3
8001ef0: e087 b.n 8002002 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001ef2: 4b28 ldr r3, [pc, #160] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001ef4: 681b ldr r3, [r3, #0]
8001ef6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8001efa: 2b00 cmp r3, #0
8001efc: d1f0 bne.n 8001ee0 <HAL_RCC_OscConfig+0x418>
RCC_OscInitStruct->PLL.PLLN,
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#else
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001efe: 687b ldr r3, [r7, #4]
8001f00: 69da ldr r2, [r3, #28]
8001f02: 687b ldr r3, [r7, #4]
8001f04: 6a1b ldr r3, [r3, #32]
8001f06: 431a orrs r2, r3
8001f08: 687b ldr r3, [r7, #4]
8001f0a: 6a5b ldr r3, [r3, #36] @ 0x24
8001f0c: 019b lsls r3, r3, #6
8001f0e: 431a orrs r2, r3
8001f10: 687b ldr r3, [r7, #4]
8001f12: 6a9b ldr r3, [r3, #40] @ 0x28
8001f14: 085b lsrs r3, r3, #1
8001f16: 3b01 subs r3, #1
8001f18: 041b lsls r3, r3, #16
8001f1a: 431a orrs r2, r3
8001f1c: 687b ldr r3, [r7, #4]
8001f1e: 6adb ldr r3, [r3, #44] @ 0x2c
8001f20: 061b lsls r3, r3, #24
8001f22: 4313 orrs r3, r2
8001f24: 4a1b ldr r2, [pc, #108] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001f26: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
8001f2a: 6053 str r3, [r2, #4]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001f2c: 4b19 ldr r3, [pc, #100] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001f2e: 681b ldr r3, [r3, #0]
8001f30: 4a18 ldr r2, [pc, #96] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001f32: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8001f36: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001f38: f7ff fa90 bl 800145c <HAL_GetTick>
8001f3c: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001f3e: e008 b.n 8001f52 <HAL_RCC_OscConfig+0x48a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001f40: f7ff fa8c bl 800145c <HAL_GetTick>
8001f44: 4602 mov r2, r0
8001f46: 693b ldr r3, [r7, #16]
8001f48: 1ad3 subs r3, r2, r3
8001f4a: 2b02 cmp r3, #2
8001f4c: d901 bls.n 8001f52 <HAL_RCC_OscConfig+0x48a>
{
return HAL_TIMEOUT;
8001f4e: 2303 movs r3, #3
8001f50: e057 b.n 8002002 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001f52: 4b10 ldr r3, [pc, #64] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001f54: 681b ldr r3, [r3, #0]
8001f56: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8001f5a: 2b00 cmp r3, #0
8001f5c: d0f0 beq.n 8001f40 <HAL_RCC_OscConfig+0x478>
8001f5e: e04f b.n 8002000 <HAL_RCC_OscConfig+0x538>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001f60: 4b0c ldr r3, [pc, #48] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001f62: 681b ldr r3, [r3, #0]
8001f64: 4a0b ldr r2, [pc, #44] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001f66: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8001f6a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001f6c: f7ff fa76 bl 800145c <HAL_GetTick>
8001f70: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001f72: e008 b.n 8001f86 <HAL_RCC_OscConfig+0x4be>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001f74: f7ff fa72 bl 800145c <HAL_GetTick>
8001f78: 4602 mov r2, r0
8001f7a: 693b ldr r3, [r7, #16]
8001f7c: 1ad3 subs r3, r2, r3
8001f7e: 2b02 cmp r3, #2
8001f80: d901 bls.n 8001f86 <HAL_RCC_OscConfig+0x4be>
{
return HAL_TIMEOUT;
8001f82: 2303 movs r3, #3
8001f84: e03d b.n 8002002 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001f86: 4b03 ldr r3, [pc, #12] @ (8001f94 <HAL_RCC_OscConfig+0x4cc>)
8001f88: 681b ldr r3, [r3, #0]
8001f8a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8001f8e: 2b00 cmp r3, #0
8001f90: d1f0 bne.n 8001f74 <HAL_RCC_OscConfig+0x4ac>
8001f92: e035 b.n 8002000 <HAL_RCC_OscConfig+0x538>
8001f94: 40023800 .word 0x40023800
8001f98: 40007000 .word 0x40007000
}
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
8001f9c: 4b1b ldr r3, [pc, #108] @ (800200c <HAL_RCC_OscConfig+0x544>)
8001f9e: 685b ldr r3, [r3, #4]
8001fa0: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8001fa2: 687b ldr r3, [r7, #4]
8001fa4: 699b ldr r3, [r3, #24]
8001fa6: 2b01 cmp r3, #1
8001fa8: d028 beq.n 8001ffc <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001faa: 68fb ldr r3, [r7, #12]
8001fac: f403 0280 and.w r2, r3, #4194304 @ 0x400000
8001fb0: 687b ldr r3, [r7, #4]
8001fb2: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8001fb4: 429a cmp r2, r3
8001fb6: d121 bne.n 8001ffc <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8001fb8: 68fb ldr r3, [r7, #12]
8001fba: f003 023f and.w r2, r3, #63 @ 0x3f
8001fbe: 687b ldr r3, [r7, #4]
8001fc0: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001fc2: 429a cmp r2, r3
8001fc4: d11a bne.n 8001ffc <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8001fc6: 68fa ldr r2, [r7, #12]
8001fc8: f647 73c0 movw r3, #32704 @ 0x7fc0
8001fcc: 4013 ands r3, r2
8001fce: 687a ldr r2, [r7, #4]
8001fd0: 6a52 ldr r2, [r2, #36] @ 0x24
8001fd2: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8001fd4: 4293 cmp r3, r2
8001fd6: d111 bne.n 8001ffc <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
8001fd8: 68fb ldr r3, [r7, #12]
8001fda: f403 3240 and.w r2, r3, #196608 @ 0x30000
8001fde: 687b ldr r3, [r7, #4]
8001fe0: 6a9b ldr r3, [r3, #40] @ 0x28
8001fe2: 085b lsrs r3, r3, #1
8001fe4: 3b01 subs r3, #1
8001fe6: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8001fe8: 429a cmp r2, r3
8001fea: d107 bne.n 8001ffc <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
8001fec: 68fb ldr r3, [r7, #12]
8001fee: f003 6270 and.w r2, r3, #251658240 @ 0xf000000
8001ff2: 687b ldr r3, [r7, #4]
8001ff4: 6adb ldr r3, [r3, #44] @ 0x2c
8001ff6: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
8001ff8: 429a cmp r2, r3
8001ffa: d001 beq.n 8002000 <HAL_RCC_OscConfig+0x538>
#endif
{
return HAL_ERROR;
8001ffc: 2301 movs r3, #1
8001ffe: e000 b.n 8002002 <HAL_RCC_OscConfig+0x53a>
}
}
}
return HAL_OK;
8002000: 2300 movs r3, #0
}
8002002: 4618 mov r0, r3
8002004: 3718 adds r7, #24
8002006: 46bd mov sp, r7
8002008: bd80 pop {r7, pc}
800200a: bf00 nop
800200c: 40023800 .word 0x40023800
08002010 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8002010: b580 push {r7, lr}
8002012: b084 sub sp, #16
8002014: af00 add r7, sp, #0
8002016: 6078 str r0, [r7, #4]
8002018: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
800201a: 2300 movs r3, #0
800201c: 60fb str r3, [r7, #12]
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
800201e: 687b ldr r3, [r7, #4]
8002020: 2b00 cmp r3, #0
8002022: d101 bne.n 8002028 <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8002024: 2301 movs r3, #1
8002026: e0d0 b.n 80021ca <HAL_RCC_ClockConfig+0x1ba>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8002028: 4b6a ldr r3, [pc, #424] @ (80021d4 <HAL_RCC_ClockConfig+0x1c4>)
800202a: 681b ldr r3, [r3, #0]
800202c: f003 030f and.w r3, r3, #15
8002030: 683a ldr r2, [r7, #0]
8002032: 429a cmp r2, r3
8002034: d910 bls.n 8002058 <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002036: 4b67 ldr r3, [pc, #412] @ (80021d4 <HAL_RCC_ClockConfig+0x1c4>)
8002038: 681b ldr r3, [r3, #0]
800203a: f023 020f bic.w r2, r3, #15
800203e: 4965 ldr r1, [pc, #404] @ (80021d4 <HAL_RCC_ClockConfig+0x1c4>)
8002040: 683b ldr r3, [r7, #0]
8002042: 4313 orrs r3, r2
8002044: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8002046: 4b63 ldr r3, [pc, #396] @ (80021d4 <HAL_RCC_ClockConfig+0x1c4>)
8002048: 681b ldr r3, [r3, #0]
800204a: f003 030f and.w r3, r3, #15
800204e: 683a ldr r2, [r7, #0]
8002050: 429a cmp r2, r3
8002052: d001 beq.n 8002058 <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
8002054: 2301 movs r3, #1
8002056: e0b8 b.n 80021ca <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002058: 687b ldr r3, [r7, #4]
800205a: 681b ldr r3, [r3, #0]
800205c: f003 0302 and.w r3, r3, #2
8002060: 2b00 cmp r3, #0
8002062: d020 beq.n 80020a6 <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002064: 687b ldr r3, [r7, #4]
8002066: 681b ldr r3, [r3, #0]
8002068: f003 0304 and.w r3, r3, #4
800206c: 2b00 cmp r3, #0
800206e: d005 beq.n 800207c <HAL_RCC_ClockConfig+0x6c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8002070: 4b59 ldr r3, [pc, #356] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
8002072: 689b ldr r3, [r3, #8]
8002074: 4a58 ldr r2, [pc, #352] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
8002076: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00
800207a: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
800207c: 687b ldr r3, [r7, #4]
800207e: 681b ldr r3, [r3, #0]
8002080: f003 0308 and.w r3, r3, #8
8002084: 2b00 cmp r3, #0
8002086: d005 beq.n 8002094 <HAL_RCC_ClockConfig+0x84>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8002088: 4b53 ldr r3, [pc, #332] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
800208a: 689b ldr r3, [r3, #8]
800208c: 4a52 ldr r2, [pc, #328] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
800208e: f443 4360 orr.w r3, r3, #57344 @ 0xe000
8002092: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002094: 4b50 ldr r3, [pc, #320] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
8002096: 689b ldr r3, [r3, #8]
8002098: f023 02f0 bic.w r2, r3, #240 @ 0xf0
800209c: 687b ldr r3, [r7, #4]
800209e: 689b ldr r3, [r3, #8]
80020a0: 494d ldr r1, [pc, #308] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
80020a2: 4313 orrs r3, r2
80020a4: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
80020a6: 687b ldr r3, [r7, #4]
80020a8: 681b ldr r3, [r3, #0]
80020aa: f003 0301 and.w r3, r3, #1
80020ae: 2b00 cmp r3, #0
80020b0: d040 beq.n 8002134 <HAL_RCC_ClockConfig+0x124>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
80020b2: 687b ldr r3, [r7, #4]
80020b4: 685b ldr r3, [r3, #4]
80020b6: 2b01 cmp r3, #1
80020b8: d107 bne.n 80020ca <HAL_RCC_ClockConfig+0xba>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80020ba: 4b47 ldr r3, [pc, #284] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
80020bc: 681b ldr r3, [r3, #0]
80020be: f403 3300 and.w r3, r3, #131072 @ 0x20000
80020c2: 2b00 cmp r3, #0
80020c4: d115 bne.n 80020f2 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
80020c6: 2301 movs r3, #1
80020c8: e07f b.n 80021ca <HAL_RCC_ClockConfig+0x1ba>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
80020ca: 687b ldr r3, [r7, #4]
80020cc: 685b ldr r3, [r3, #4]
80020ce: 2b02 cmp r3, #2
80020d0: d107 bne.n 80020e2 <HAL_RCC_ClockConfig+0xd2>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80020d2: 4b41 ldr r3, [pc, #260] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
80020d4: 681b ldr r3, [r3, #0]
80020d6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80020da: 2b00 cmp r3, #0
80020dc: d109 bne.n 80020f2 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
80020de: 2301 movs r3, #1
80020e0: e073 b.n 80021ca <HAL_RCC_ClockConfig+0x1ba>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80020e2: 4b3d ldr r3, [pc, #244] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
80020e4: 681b ldr r3, [r3, #0]
80020e6: f003 0302 and.w r3, r3, #2
80020ea: 2b00 cmp r3, #0
80020ec: d101 bne.n 80020f2 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
80020ee: 2301 movs r3, #1
80020f0: e06b b.n 80021ca <HAL_RCC_ClockConfig+0x1ba>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
80020f2: 4b39 ldr r3, [pc, #228] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
80020f4: 689b ldr r3, [r3, #8]
80020f6: f023 0203 bic.w r2, r3, #3
80020fa: 687b ldr r3, [r7, #4]
80020fc: 685b ldr r3, [r3, #4]
80020fe: 4936 ldr r1, [pc, #216] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
8002100: 4313 orrs r3, r2
8002102: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002104: f7ff f9aa bl 800145c <HAL_GetTick>
8002108: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800210a: e00a b.n 8002122 <HAL_RCC_ClockConfig+0x112>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
800210c: f7ff f9a6 bl 800145c <HAL_GetTick>
8002110: 4602 mov r2, r0
8002112: 68fb ldr r3, [r7, #12]
8002114: 1ad3 subs r3, r2, r3
8002116: f241 3288 movw r2, #5000 @ 0x1388
800211a: 4293 cmp r3, r2
800211c: d901 bls.n 8002122 <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
800211e: 2303 movs r3, #3
8002120: e053 b.n 80021ca <HAL_RCC_ClockConfig+0x1ba>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002122: 4b2d ldr r3, [pc, #180] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
8002124: 689b ldr r3, [r3, #8]
8002126: f003 020c and.w r2, r3, #12
800212a: 687b ldr r3, [r7, #4]
800212c: 685b ldr r3, [r3, #4]
800212e: 009b lsls r3, r3, #2
8002130: 429a cmp r2, r3
8002132: d1eb bne.n 800210c <HAL_RCC_ClockConfig+0xfc>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8002134: 4b27 ldr r3, [pc, #156] @ (80021d4 <HAL_RCC_ClockConfig+0x1c4>)
8002136: 681b ldr r3, [r3, #0]
8002138: f003 030f and.w r3, r3, #15
800213c: 683a ldr r2, [r7, #0]
800213e: 429a cmp r2, r3
8002140: d210 bcs.n 8002164 <HAL_RCC_ClockConfig+0x154>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002142: 4b24 ldr r3, [pc, #144] @ (80021d4 <HAL_RCC_ClockConfig+0x1c4>)
8002144: 681b ldr r3, [r3, #0]
8002146: f023 020f bic.w r2, r3, #15
800214a: 4922 ldr r1, [pc, #136] @ (80021d4 <HAL_RCC_ClockConfig+0x1c4>)
800214c: 683b ldr r3, [r7, #0]
800214e: 4313 orrs r3, r2
8002150: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8002152: 4b20 ldr r3, [pc, #128] @ (80021d4 <HAL_RCC_ClockConfig+0x1c4>)
8002154: 681b ldr r3, [r3, #0]
8002156: f003 030f and.w r3, r3, #15
800215a: 683a ldr r2, [r7, #0]
800215c: 429a cmp r2, r3
800215e: d001 beq.n 8002164 <HAL_RCC_ClockConfig+0x154>
{
return HAL_ERROR;
8002160: 2301 movs r3, #1
8002162: e032 b.n 80021ca <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002164: 687b ldr r3, [r7, #4]
8002166: 681b ldr r3, [r3, #0]
8002168: f003 0304 and.w r3, r3, #4
800216c: 2b00 cmp r3, #0
800216e: d008 beq.n 8002182 <HAL_RCC_ClockConfig+0x172>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8002170: 4b19 ldr r3, [pc, #100] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
8002172: 689b ldr r3, [r3, #8]
8002174: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00
8002178: 687b ldr r3, [r7, #4]
800217a: 68db ldr r3, [r3, #12]
800217c: 4916 ldr r1, [pc, #88] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
800217e: 4313 orrs r3, r2
8002180: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002182: 687b ldr r3, [r7, #4]
8002184: 681b ldr r3, [r3, #0]
8002186: f003 0308 and.w r3, r3, #8
800218a: 2b00 cmp r3, #0
800218c: d009 beq.n 80021a2 <HAL_RCC_ClockConfig+0x192>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
800218e: 4b12 ldr r3, [pc, #72] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
8002190: 689b ldr r3, [r3, #8]
8002192: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8002196: 687b ldr r3, [r7, #4]
8002198: 691b ldr r3, [r3, #16]
800219a: 00db lsls r3, r3, #3
800219c: 490e ldr r1, [pc, #56] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
800219e: 4313 orrs r3, r2
80021a0: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
80021a2: f000 f821 bl 80021e8 <HAL_RCC_GetSysClockFreq>
80021a6: 4602 mov r2, r0
80021a8: 4b0b ldr r3, [pc, #44] @ (80021d8 <HAL_RCC_ClockConfig+0x1c8>)
80021aa: 689b ldr r3, [r3, #8]
80021ac: 091b lsrs r3, r3, #4
80021ae: f003 030f and.w r3, r3, #15
80021b2: 490a ldr r1, [pc, #40] @ (80021dc <HAL_RCC_ClockConfig+0x1cc>)
80021b4: 5ccb ldrb r3, [r1, r3]
80021b6: fa22 f303 lsr.w r3, r2, r3
80021ba: 4a09 ldr r2, [pc, #36] @ (80021e0 <HAL_RCC_ClockConfig+0x1d0>)
80021bc: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
80021be: 4b09 ldr r3, [pc, #36] @ (80021e4 <HAL_RCC_ClockConfig+0x1d4>)
80021c0: 681b ldr r3, [r3, #0]
80021c2: 4618 mov r0, r3
80021c4: f7fe ffb2 bl 800112c <HAL_InitTick>
return HAL_OK;
80021c8: 2300 movs r3, #0
}
80021ca: 4618 mov r0, r3
80021cc: 3710 adds r7, #16
80021ce: 46bd mov sp, r7
80021d0: bd80 pop {r7, pc}
80021d2: bf00 nop
80021d4: 40023c00 .word 0x40023c00
80021d8: 40023800 .word 0x40023800
80021dc: 08004900 .word 0x08004900
80021e0: 20000000 .word 0x20000000
80021e4: 20000004 .word 0x20000004
080021e8 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
80021e8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
80021ec: b090 sub sp, #64 @ 0x40
80021ee: af00 add r7, sp, #0
uint32_t pllm = 0, pllvco = 0, pllp = 0;
80021f0: 2300 movs r3, #0
80021f2: 637b str r3, [r7, #52] @ 0x34
80021f4: 2300 movs r3, #0
80021f6: 63fb str r3, [r7, #60] @ 0x3c
80021f8: 2300 movs r3, #0
80021fa: 633b str r3, [r7, #48] @ 0x30
uint32_t sysclockfreq = 0;
80021fc: 2300 movs r3, #0
80021fe: 63bb str r3, [r7, #56] @ 0x38
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8002200: 4b59 ldr r3, [pc, #356] @ (8002368 <HAL_RCC_GetSysClockFreq+0x180>)
8002202: 689b ldr r3, [r3, #8]
8002204: f003 030c and.w r3, r3, #12
8002208: 2b08 cmp r3, #8
800220a: d00d beq.n 8002228 <HAL_RCC_GetSysClockFreq+0x40>
800220c: 2b08 cmp r3, #8
800220e: f200 80a1 bhi.w 8002354 <HAL_RCC_GetSysClockFreq+0x16c>
8002212: 2b00 cmp r3, #0
8002214: d002 beq.n 800221c <HAL_RCC_GetSysClockFreq+0x34>
8002216: 2b04 cmp r3, #4
8002218: d003 beq.n 8002222 <HAL_RCC_GetSysClockFreq+0x3a>
800221a: e09b b.n 8002354 <HAL_RCC_GetSysClockFreq+0x16c>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
800221c: 4b53 ldr r3, [pc, #332] @ (800236c <HAL_RCC_GetSysClockFreq+0x184>)
800221e: 63bb str r3, [r7, #56] @ 0x38
break;
8002220: e09b b.n 800235a <HAL_RCC_GetSysClockFreq+0x172>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8002222: 4b53 ldr r3, [pc, #332] @ (8002370 <HAL_RCC_GetSysClockFreq+0x188>)
8002224: 63bb str r3, [r7, #56] @ 0x38
break;
8002226: e098 b.n 800235a <HAL_RCC_GetSysClockFreq+0x172>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8002228: 4b4f ldr r3, [pc, #316] @ (8002368 <HAL_RCC_GetSysClockFreq+0x180>)
800222a: 685b ldr r3, [r3, #4]
800222c: f003 033f and.w r3, r3, #63 @ 0x3f
8002230: 637b str r3, [r7, #52] @ 0x34
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
8002232: 4b4d ldr r3, [pc, #308] @ (8002368 <HAL_RCC_GetSysClockFreq+0x180>)
8002234: 685b ldr r3, [r3, #4]
8002236: f403 0380 and.w r3, r3, #4194304 @ 0x400000
800223a: 2b00 cmp r3, #0
800223c: d028 beq.n 8002290 <HAL_RCC_GetSysClockFreq+0xa8>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
800223e: 4b4a ldr r3, [pc, #296] @ (8002368 <HAL_RCC_GetSysClockFreq+0x180>)
8002240: 685b ldr r3, [r3, #4]
8002242: 099b lsrs r3, r3, #6
8002244: 2200 movs r2, #0
8002246: 623b str r3, [r7, #32]
8002248: 627a str r2, [r7, #36] @ 0x24
800224a: 6a3b ldr r3, [r7, #32]
800224c: f3c3 0008 ubfx r0, r3, #0, #9
8002250: 2100 movs r1, #0
8002252: 4b47 ldr r3, [pc, #284] @ (8002370 <HAL_RCC_GetSysClockFreq+0x188>)
8002254: fb03 f201 mul.w r2, r3, r1
8002258: 2300 movs r3, #0
800225a: fb00 f303 mul.w r3, r0, r3
800225e: 4413 add r3, r2
8002260: 4a43 ldr r2, [pc, #268] @ (8002370 <HAL_RCC_GetSysClockFreq+0x188>)
8002262: fba0 1202 umull r1, r2, r0, r2
8002266: 62fa str r2, [r7, #44] @ 0x2c
8002268: 460a mov r2, r1
800226a: 62ba str r2, [r7, #40] @ 0x28
800226c: 6afa ldr r2, [r7, #44] @ 0x2c
800226e: 4413 add r3, r2
8002270: 62fb str r3, [r7, #44] @ 0x2c
8002272: 6b7b ldr r3, [r7, #52] @ 0x34
8002274: 2200 movs r2, #0
8002276: 61bb str r3, [r7, #24]
8002278: 61fa str r2, [r7, #28]
800227a: e9d7 2306 ldrd r2, r3, [r7, #24]
800227e: e9d7 010a ldrd r0, r1, [r7, #40] @ 0x28
8002282: f7fe f81d bl 80002c0 <__aeabi_uldivmod>
8002286: 4602 mov r2, r0
8002288: 460b mov r3, r1
800228a: 4613 mov r3, r2
800228c: 63fb str r3, [r7, #60] @ 0x3c
800228e: e053 b.n 8002338 <HAL_RCC_GetSysClockFreq+0x150>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8002290: 4b35 ldr r3, [pc, #212] @ (8002368 <HAL_RCC_GetSysClockFreq+0x180>)
8002292: 685b ldr r3, [r3, #4]
8002294: 099b lsrs r3, r3, #6
8002296: 2200 movs r2, #0
8002298: 613b str r3, [r7, #16]
800229a: 617a str r2, [r7, #20]
800229c: 693b ldr r3, [r7, #16]
800229e: f3c3 0a08 ubfx sl, r3, #0, #9
80022a2: f04f 0b00 mov.w fp, #0
80022a6: 4652 mov r2, sl
80022a8: 465b mov r3, fp
80022aa: f04f 0000 mov.w r0, #0
80022ae: f04f 0100 mov.w r1, #0
80022b2: 0159 lsls r1, r3, #5
80022b4: ea41 61d2 orr.w r1, r1, r2, lsr #27
80022b8: 0150 lsls r0, r2, #5
80022ba: 4602 mov r2, r0
80022bc: 460b mov r3, r1
80022be: ebb2 080a subs.w r8, r2, sl
80022c2: eb63 090b sbc.w r9, r3, fp
80022c6: f04f 0200 mov.w r2, #0
80022ca: f04f 0300 mov.w r3, #0
80022ce: ea4f 1389 mov.w r3, r9, lsl #6
80022d2: ea43 6398 orr.w r3, r3, r8, lsr #26
80022d6: ea4f 1288 mov.w r2, r8, lsl #6
80022da: ebb2 0408 subs.w r4, r2, r8
80022de: eb63 0509 sbc.w r5, r3, r9
80022e2: f04f 0200 mov.w r2, #0
80022e6: f04f 0300 mov.w r3, #0
80022ea: 00eb lsls r3, r5, #3
80022ec: ea43 7354 orr.w r3, r3, r4, lsr #29
80022f0: 00e2 lsls r2, r4, #3
80022f2: 4614 mov r4, r2
80022f4: 461d mov r5, r3
80022f6: eb14 030a adds.w r3, r4, sl
80022fa: 603b str r3, [r7, #0]
80022fc: eb45 030b adc.w r3, r5, fp
8002300: 607b str r3, [r7, #4]
8002302: f04f 0200 mov.w r2, #0
8002306: f04f 0300 mov.w r3, #0
800230a: e9d7 4500 ldrd r4, r5, [r7]
800230e: 4629 mov r1, r5
8002310: 028b lsls r3, r1, #10
8002312: 4621 mov r1, r4
8002314: ea43 5391 orr.w r3, r3, r1, lsr #22
8002318: 4621 mov r1, r4
800231a: 028a lsls r2, r1, #10
800231c: 4610 mov r0, r2
800231e: 4619 mov r1, r3
8002320: 6b7b ldr r3, [r7, #52] @ 0x34
8002322: 2200 movs r2, #0
8002324: 60bb str r3, [r7, #8]
8002326: 60fa str r2, [r7, #12]
8002328: e9d7 2302 ldrd r2, r3, [r7, #8]
800232c: f7fd ffc8 bl 80002c0 <__aeabi_uldivmod>
8002330: 4602 mov r2, r0
8002332: 460b mov r3, r1
8002334: 4613 mov r3, r2
8002336: 63fb str r3, [r7, #60] @ 0x3c
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
8002338: 4b0b ldr r3, [pc, #44] @ (8002368 <HAL_RCC_GetSysClockFreq+0x180>)
800233a: 685b ldr r3, [r3, #4]
800233c: 0c1b lsrs r3, r3, #16
800233e: f003 0303 and.w r3, r3, #3
8002342: 3301 adds r3, #1
8002344: 005b lsls r3, r3, #1
8002346: 633b str r3, [r7, #48] @ 0x30
sysclockfreq = pllvco / pllp;
8002348: 6bfa ldr r2, [r7, #60] @ 0x3c
800234a: 6b3b ldr r3, [r7, #48] @ 0x30
800234c: fbb2 f3f3 udiv r3, r2, r3
8002350: 63bb str r3, [r7, #56] @ 0x38
break;
8002352: e002 b.n 800235a <HAL_RCC_GetSysClockFreq+0x172>
}
default:
{
sysclockfreq = HSI_VALUE;
8002354: 4b05 ldr r3, [pc, #20] @ (800236c <HAL_RCC_GetSysClockFreq+0x184>)
8002356: 63bb str r3, [r7, #56] @ 0x38
break;
8002358: bf00 nop
}
}
return sysclockfreq;
800235a: 6bbb ldr r3, [r7, #56] @ 0x38
}
800235c: 4618 mov r0, r3
800235e: 3740 adds r7, #64 @ 0x40
8002360: 46bd mov sp, r7
8002362: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8002366: bf00 nop
8002368: 40023800 .word 0x40023800
800236c: 00f42400 .word 0x00f42400
8002370: 017d7840 .word 0x017d7840
08002374 <HAL_RCC_GetHCLKFreq>:
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8002374: b480 push {r7}
8002376: af00 add r7, sp, #0
return SystemCoreClock;
8002378: 4b03 ldr r3, [pc, #12] @ (8002388 <HAL_RCC_GetHCLKFreq+0x14>)
800237a: 681b ldr r3, [r3, #0]
}
800237c: 4618 mov r0, r3
800237e: 46bd mov sp, r7
8002380: f85d 7b04 ldr.w r7, [sp], #4
8002384: 4770 bx lr
8002386: bf00 nop
8002388: 20000000 .word 0x20000000
0800238c <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
800238c: b580 push {r7, lr}
800238e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8002390: f7ff fff0 bl 8002374 <HAL_RCC_GetHCLKFreq>
8002394: 4602 mov r2, r0
8002396: 4b05 ldr r3, [pc, #20] @ (80023ac <HAL_RCC_GetPCLK1Freq+0x20>)
8002398: 689b ldr r3, [r3, #8]
800239a: 0a9b lsrs r3, r3, #10
800239c: f003 0307 and.w r3, r3, #7
80023a0: 4903 ldr r1, [pc, #12] @ (80023b0 <HAL_RCC_GetPCLK1Freq+0x24>)
80023a2: 5ccb ldrb r3, [r1, r3]
80023a4: fa22 f303 lsr.w r3, r2, r3
}
80023a8: 4618 mov r0, r3
80023aa: bd80 pop {r7, pc}
80023ac: 40023800 .word 0x40023800
80023b0: 08004910 .word 0x08004910
080023b4 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
80023b4: b580 push {r7, lr}
80023b6: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
80023b8: f7ff ffdc bl 8002374 <HAL_RCC_GetHCLKFreq>
80023bc: 4602 mov r2, r0
80023be: 4b05 ldr r3, [pc, #20] @ (80023d4 <HAL_RCC_GetPCLK2Freq+0x20>)
80023c0: 689b ldr r3, [r3, #8]
80023c2: 0b5b lsrs r3, r3, #13
80023c4: f003 0307 and.w r3, r3, #7
80023c8: 4903 ldr r1, [pc, #12] @ (80023d8 <HAL_RCC_GetPCLK2Freq+0x24>)
80023ca: 5ccb ldrb r3, [r1, r3]
80023cc: fa22 f303 lsr.w r3, r2, r3
}
80023d0: 4618 mov r0, r3
80023d2: bd80 pop {r7, pc}
80023d4: 40023800 .word 0x40023800
80023d8: 08004910 .word 0x08004910
080023dc <HAL_RCC_GetClockConfig>:
* will be configured.
* @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
80023dc: b480 push {r7}
80023de: b083 sub sp, #12
80023e0: af00 add r7, sp, #0
80023e2: 6078 str r0, [r7, #4]
80023e4: 6039 str r1, [r7, #0]
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
80023e6: 687b ldr r3, [r7, #4]
80023e8: 220f movs r2, #15
80023ea: 601a str r2, [r3, #0]
/* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
80023ec: 4b12 ldr r3, [pc, #72] @ (8002438 <HAL_RCC_GetClockConfig+0x5c>)
80023ee: 689b ldr r3, [r3, #8]
80023f0: f003 0203 and.w r2, r3, #3
80023f4: 687b ldr r3, [r7, #4]
80023f6: 605a str r2, [r3, #4]
/* Get the HCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
80023f8: 4b0f ldr r3, [pc, #60] @ (8002438 <HAL_RCC_GetClockConfig+0x5c>)
80023fa: 689b ldr r3, [r3, #8]
80023fc: f003 02f0 and.w r2, r3, #240 @ 0xf0
8002400: 687b ldr r3, [r7, #4]
8002402: 609a str r2, [r3, #8]
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
8002404: 4b0c ldr r3, [pc, #48] @ (8002438 <HAL_RCC_GetClockConfig+0x5c>)
8002406: 689b ldr r3, [r3, #8]
8002408: f403 52e0 and.w r2, r3, #7168 @ 0x1c00
800240c: 687b ldr r3, [r7, #4]
800240e: 60da str r2, [r3, #12]
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
8002410: 4b09 ldr r3, [pc, #36] @ (8002438 <HAL_RCC_GetClockConfig+0x5c>)
8002412: 689b ldr r3, [r3, #8]
8002414: 08db lsrs r3, r3, #3
8002416: f403 52e0 and.w r2, r3, #7168 @ 0x1c00
800241a: 687b ldr r3, [r7, #4]
800241c: 611a str r2, [r3, #16]
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
800241e: 4b07 ldr r3, [pc, #28] @ (800243c <HAL_RCC_GetClockConfig+0x60>)
8002420: 681b ldr r3, [r3, #0]
8002422: f003 020f and.w r2, r3, #15
8002426: 683b ldr r3, [r7, #0]
8002428: 601a str r2, [r3, #0]
}
800242a: bf00 nop
800242c: 370c adds r7, #12
800242e: 46bd mov sp, r7
8002430: f85d 7b04 ldr.w r7, [sp], #4
8002434: 4770 bx lr
8002436: bf00 nop
8002438: 40023800 .word 0x40023800
800243c: 40023c00 .word 0x40023c00
08002440 <HAL_RCCEx_PeriphCLKConfig>:
* the backup registers) are set to their reset values.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8002440: b580 push {r7, lr}
8002442: b088 sub sp, #32
8002444: af00 add r7, sp, #0
8002446: 6078 str r0, [r7, #4]
uint32_t tickstart = 0;
8002448: 2300 movs r3, #0
800244a: 617b str r3, [r7, #20]
uint32_t tmpreg0 = 0;
800244c: 2300 movs r3, #0
800244e: 613b str r3, [r7, #16]
uint32_t plli2sused = 0;
8002450: 2300 movs r3, #0
8002452: 61fb str r3, [r7, #28]
uint32_t pllsaiused = 0;
8002454: 2300 movs r3, #0
8002456: 61bb str r3, [r7, #24]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*----------------------------------- I2S configuration ----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
8002458: 687b ldr r3, [r7, #4]
800245a: 681b ldr r3, [r3, #0]
800245c: f003 0301 and.w r3, r3, #1
8002460: 2b00 cmp r3, #0
8002462: d012 beq.n 800248a <HAL_RCCEx_PeriphCLKConfig+0x4a>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure I2S Clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
8002464: 4b65 ldr r3, [pc, #404] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002466: 689b ldr r3, [r3, #8]
8002468: 4a64 ldr r2, [pc, #400] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
800246a: f423 0300 bic.w r3, r3, #8388608 @ 0x800000
800246e: 6093 str r3, [r2, #8]
8002470: 4b62 ldr r3, [pc, #392] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002472: 689a ldr r2, [r3, #8]
8002474: 687b ldr r3, [r7, #4]
8002476: 6adb ldr r3, [r3, #44] @ 0x2c
8002478: 4960 ldr r1, [pc, #384] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
800247a: 4313 orrs r3, r2
800247c: 608b str r3, [r1, #8]
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
800247e: 687b ldr r3, [r7, #4]
8002480: 6adb ldr r3, [r3, #44] @ 0x2c
8002482: 2b00 cmp r3, #0
8002484: d101 bne.n 800248a <HAL_RCCEx_PeriphCLKConfig+0x4a>
{
plli2sused = 1;
8002486: 2301 movs r3, #1
8002488: 61fb str r3, [r7, #28]
}
}
/*------------------------------------ SAI1 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
800248a: 687b ldr r3, [r7, #4]
800248c: 681b ldr r3, [r3, #0]
800248e: f403 2300 and.w r3, r3, #524288 @ 0x80000
8002492: 2b00 cmp r3, #0
8002494: d017 beq.n 80024c6 <HAL_RCCEx_PeriphCLKConfig+0x86>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure SAI1 Clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
8002496: 4b59 ldr r3, [pc, #356] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002498: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
800249c: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
80024a0: 687b ldr r3, [r7, #4]
80024a2: 6b5b ldr r3, [r3, #52] @ 0x34
80024a4: 4955 ldr r1, [pc, #340] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80024a6: 4313 orrs r3, r2
80024a8: f8c1 308c str.w r3, [r1, #140] @ 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
80024ac: 687b ldr r3, [r7, #4]
80024ae: 6b5b ldr r3, [r3, #52] @ 0x34
80024b0: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
80024b4: d101 bne.n 80024ba <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
plli2sused = 1;
80024b6: 2301 movs r3, #1
80024b8: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
80024ba: 687b ldr r3, [r7, #4]
80024bc: 6b5b ldr r3, [r3, #52] @ 0x34
80024be: 2b00 cmp r3, #0
80024c0: d101 bne.n 80024c6 <HAL_RCCEx_PeriphCLKConfig+0x86>
{
pllsaiused = 1;
80024c2: 2301 movs r3, #1
80024c4: 61bb str r3, [r7, #24]
}
}
/*------------------------------------ SAI2 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
80024c6: 687b ldr r3, [r7, #4]
80024c8: 681b ldr r3, [r3, #0]
80024ca: f403 1380 and.w r3, r3, #1048576 @ 0x100000
80024ce: 2b00 cmp r3, #0
80024d0: d017 beq.n 8002502 <HAL_RCCEx_PeriphCLKConfig+0xc2>
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
/* Configure SAI2 Clock source */
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
80024d2: 4b4a ldr r3, [pc, #296] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80024d4: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
80024d8: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
80024dc: 687b ldr r3, [r7, #4]
80024de: 6b9b ldr r3, [r3, #56] @ 0x38
80024e0: 4946 ldr r1, [pc, #280] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80024e2: 4313 orrs r3, r2
80024e4: f8c1 308c str.w r3, [r1, #140] @ 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
80024e8: 687b ldr r3, [r7, #4]
80024ea: 6b9b ldr r3, [r3, #56] @ 0x38
80024ec: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
80024f0: d101 bne.n 80024f6 <HAL_RCCEx_PeriphCLKConfig+0xb6>
{
plli2sused = 1;
80024f2: 2301 movs r3, #1
80024f4: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
80024f6: 687b ldr r3, [r7, #4]
80024f8: 6b9b ldr r3, [r3, #56] @ 0x38
80024fa: 2b00 cmp r3, #0
80024fc: d101 bne.n 8002502 <HAL_RCCEx_PeriphCLKConfig+0xc2>
{
pllsaiused = 1;
80024fe: 2301 movs r3, #1
8002500: 61bb str r3, [r7, #24]
}
}
/*------------------------------------ RTC configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
8002502: 687b ldr r3, [r7, #4]
8002504: 681b ldr r3, [r3, #0]
8002506: f003 0320 and.w r3, r3, #32
800250a: 2b00 cmp r3, #0
800250c: f000 808b beq.w 8002626 <HAL_RCCEx_PeriphCLKConfig+0x1e6>
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
8002510: 4b3a ldr r3, [pc, #232] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002512: 6c1b ldr r3, [r3, #64] @ 0x40
8002514: 4a39 ldr r2, [pc, #228] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002516: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800251a: 6413 str r3, [r2, #64] @ 0x40
800251c: 4b37 ldr r3, [pc, #220] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
800251e: 6c1b ldr r3, [r3, #64] @ 0x40
8002520: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002524: 60fb str r3, [r7, #12]
8002526: 68fb ldr r3, [r7, #12]
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
8002528: 4b35 ldr r3, [pc, #212] @ (8002600 <HAL_RCCEx_PeriphCLKConfig+0x1c0>)
800252a: 681b ldr r3, [r3, #0]
800252c: 4a34 ldr r2, [pc, #208] @ (8002600 <HAL_RCCEx_PeriphCLKConfig+0x1c0>)
800252e: f443 7380 orr.w r3, r3, #256 @ 0x100
8002532: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002534: f7fe ff92 bl 800145c <HAL_GetTick>
8002538: 6178 str r0, [r7, #20]
/* Wait for Backup domain Write protection disable */
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
800253a: e008 b.n 800254e <HAL_RCCEx_PeriphCLKConfig+0x10e>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
800253c: f7fe ff8e bl 800145c <HAL_GetTick>
8002540: 4602 mov r2, r0
8002542: 697b ldr r3, [r7, #20]
8002544: 1ad3 subs r3, r2, r3
8002546: 2b64 cmp r3, #100 @ 0x64
8002548: d901 bls.n 800254e <HAL_RCCEx_PeriphCLKConfig+0x10e>
{
return HAL_TIMEOUT;
800254a: 2303 movs r3, #3
800254c: e2bc b.n 8002ac8 <HAL_RCCEx_PeriphCLKConfig+0x688>
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
800254e: 4b2c ldr r3, [pc, #176] @ (8002600 <HAL_RCCEx_PeriphCLKConfig+0x1c0>)
8002550: 681b ldr r3, [r3, #0]
8002552: f403 7380 and.w r3, r3, #256 @ 0x100
8002556: 2b00 cmp r3, #0
8002558: d0f0 beq.n 800253c <HAL_RCCEx_PeriphCLKConfig+0xfc>
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified */
tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
800255a: 4b28 ldr r3, [pc, #160] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
800255c: 6f1b ldr r3, [r3, #112] @ 0x70
800255e: f403 7340 and.w r3, r3, #768 @ 0x300
8002562: 613b str r3, [r7, #16]
if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
8002564: 693b ldr r3, [r7, #16]
8002566: 2b00 cmp r3, #0
8002568: d035 beq.n 80025d6 <HAL_RCCEx_PeriphCLKConfig+0x196>
800256a: 687b ldr r3, [r7, #4]
800256c: 6a9b ldr r3, [r3, #40] @ 0x28
800256e: f403 7340 and.w r3, r3, #768 @ 0x300
8002572: 693a ldr r2, [r7, #16]
8002574: 429a cmp r2, r3
8002576: d02e beq.n 80025d6 <HAL_RCCEx_PeriphCLKConfig+0x196>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8002578: 4b20 ldr r3, [pc, #128] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
800257a: 6f1b ldr r3, [r3, #112] @ 0x70
800257c: f423 7340 bic.w r3, r3, #768 @ 0x300
8002580: 613b str r3, [r7, #16]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8002582: 4b1e ldr r3, [pc, #120] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002584: 6f1b ldr r3, [r3, #112] @ 0x70
8002586: 4a1d ldr r2, [pc, #116] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002588: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800258c: 6713 str r3, [r2, #112] @ 0x70
__HAL_RCC_BACKUPRESET_RELEASE();
800258e: 4b1b ldr r3, [pc, #108] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002590: 6f1b ldr r3, [r3, #112] @ 0x70
8002592: 4a1a ldr r2, [pc, #104] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
8002594: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8002598: 6713 str r3, [r2, #112] @ 0x70
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg0;
800259a: 4a18 ldr r2, [pc, #96] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
800259c: 693b ldr r3, [r7, #16]
800259e: 6713 str r3, [r2, #112] @ 0x70
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
80025a0: 4b16 ldr r3, [pc, #88] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80025a2: 6f1b ldr r3, [r3, #112] @ 0x70
80025a4: f003 0301 and.w r3, r3, #1
80025a8: 2b01 cmp r3, #1
80025aa: d114 bne.n 80025d6 <HAL_RCCEx_PeriphCLKConfig+0x196>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80025ac: f7fe ff56 bl 800145c <HAL_GetTick>
80025b0: 6178 str r0, [r7, #20]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80025b2: e00a b.n 80025ca <HAL_RCCEx_PeriphCLKConfig+0x18a>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80025b4: f7fe ff52 bl 800145c <HAL_GetTick>
80025b8: 4602 mov r2, r0
80025ba: 697b ldr r3, [r7, #20]
80025bc: 1ad3 subs r3, r2, r3
80025be: f241 3288 movw r2, #5000 @ 0x1388
80025c2: 4293 cmp r3, r2
80025c4: d901 bls.n 80025ca <HAL_RCCEx_PeriphCLKConfig+0x18a>
{
return HAL_TIMEOUT;
80025c6: 2303 movs r3, #3
80025c8: e27e b.n 8002ac8 <HAL_RCCEx_PeriphCLKConfig+0x688>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80025ca: 4b0c ldr r3, [pc, #48] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80025cc: 6f1b ldr r3, [r3, #112] @ 0x70
80025ce: f003 0302 and.w r3, r3, #2
80025d2: 2b00 cmp r3, #0
80025d4: d0ee beq.n 80025b4 <HAL_RCCEx_PeriphCLKConfig+0x174>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
80025d6: 687b ldr r3, [r7, #4]
80025d8: 6a9b ldr r3, [r3, #40] @ 0x28
80025da: f403 7340 and.w r3, r3, #768 @ 0x300
80025de: f5b3 7f40 cmp.w r3, #768 @ 0x300
80025e2: d111 bne.n 8002608 <HAL_RCCEx_PeriphCLKConfig+0x1c8>
80025e4: 4b05 ldr r3, [pc, #20] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80025e6: 689b ldr r3, [r3, #8]
80025e8: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000
80025ec: 687b ldr r3, [r7, #4]
80025ee: 6a99 ldr r1, [r3, #40] @ 0x28
80025f0: 4b04 ldr r3, [pc, #16] @ (8002604 <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
80025f2: 400b ands r3, r1
80025f4: 4901 ldr r1, [pc, #4] @ (80025fc <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
80025f6: 4313 orrs r3, r2
80025f8: 608b str r3, [r1, #8]
80025fa: e00b b.n 8002614 <HAL_RCCEx_PeriphCLKConfig+0x1d4>
80025fc: 40023800 .word 0x40023800
8002600: 40007000 .word 0x40007000
8002604: 0ffffcff .word 0x0ffffcff
8002608: 4ba4 ldr r3, [pc, #656] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800260a: 689b ldr r3, [r3, #8]
800260c: 4aa3 ldr r2, [pc, #652] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800260e: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000
8002612: 6093 str r3, [r2, #8]
8002614: 4ba1 ldr r3, [pc, #644] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002616: 6f1a ldr r2, [r3, #112] @ 0x70
8002618: 687b ldr r3, [r7, #4]
800261a: 6a9b ldr r3, [r3, #40] @ 0x28
800261c: f3c3 030b ubfx r3, r3, #0, #12
8002620: 499e ldr r1, [pc, #632] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002622: 4313 orrs r3, r2
8002624: 670b str r3, [r1, #112] @ 0x70
}
/*------------------------------------ TIM configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
8002626: 687b ldr r3, [r7, #4]
8002628: 681b ldr r3, [r3, #0]
800262a: f003 0310 and.w r3, r3, #16
800262e: 2b00 cmp r3, #0
8002630: d010 beq.n 8002654 <HAL_RCCEx_PeriphCLKConfig+0x214>
{
/* Check the parameters */
assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
/* Configure Timer Prescaler */
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
8002632: 4b9a ldr r3, [pc, #616] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002634: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8002638: 4a98 ldr r2, [pc, #608] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800263a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
800263e: f8c2 308c str.w r3, [r2, #140] @ 0x8c
8002642: 4b96 ldr r3, [pc, #600] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002644: f8d3 208c ldr.w r2, [r3, #140] @ 0x8c
8002648: 687b ldr r3, [r7, #4]
800264a: 6b1b ldr r3, [r3, #48] @ 0x30
800264c: 4993 ldr r1, [pc, #588] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800264e: 4313 orrs r3, r2
8002650: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*-------------------------------------- I2C1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
8002654: 687b ldr r3, [r7, #4]
8002656: 681b ldr r3, [r3, #0]
8002658: f403 4380 and.w r3, r3, #16384 @ 0x4000
800265c: 2b00 cmp r3, #0
800265e: d00a beq.n 8002676 <HAL_RCCEx_PeriphCLKConfig+0x236>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
8002660: 4b8e ldr r3, [pc, #568] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002662: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002666: f423 3240 bic.w r2, r3, #196608 @ 0x30000
800266a: 687b ldr r3, [r7, #4]
800266c: 6ddb ldr r3, [r3, #92] @ 0x5c
800266e: 498b ldr r1, [pc, #556] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002670: 4313 orrs r3, r2
8002672: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- I2C2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
8002676: 687b ldr r3, [r7, #4]
8002678: 681b ldr r3, [r3, #0]
800267a: f403 4300 and.w r3, r3, #32768 @ 0x8000
800267e: 2b00 cmp r3, #0
8002680: d00a beq.n 8002698 <HAL_RCCEx_PeriphCLKConfig+0x258>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
8002682: 4b86 ldr r3, [pc, #536] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002684: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002688: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
800268c: 687b ldr r3, [r7, #4]
800268e: 6e1b ldr r3, [r3, #96] @ 0x60
8002690: 4982 ldr r1, [pc, #520] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002692: 4313 orrs r3, r2
8002694: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- I2C3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
8002698: 687b ldr r3, [r7, #4]
800269a: 681b ldr r3, [r3, #0]
800269c: f403 3380 and.w r3, r3, #65536 @ 0x10000
80026a0: 2b00 cmp r3, #0
80026a2: d00a beq.n 80026ba <HAL_RCCEx_PeriphCLKConfig+0x27a>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
80026a4: 4b7d ldr r3, [pc, #500] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80026a6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80026aa: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
80026ae: 687b ldr r3, [r7, #4]
80026b0: 6e5b ldr r3, [r3, #100] @ 0x64
80026b2: 497a ldr r1, [pc, #488] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80026b4: 4313 orrs r3, r2
80026b6: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
80026ba: 687b ldr r3, [r7, #4]
80026bc: 681b ldr r3, [r3, #0]
80026be: f003 0340 and.w r3, r3, #64 @ 0x40
80026c2: 2b00 cmp r3, #0
80026c4: d00a beq.n 80026dc <HAL_RCCEx_PeriphCLKConfig+0x29c>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
80026c6: 4b75 ldr r3, [pc, #468] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80026c8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80026cc: f023 0203 bic.w r2, r3, #3
80026d0: 687b ldr r3, [r7, #4]
80026d2: 6bdb ldr r3, [r3, #60] @ 0x3c
80026d4: 4971 ldr r1, [pc, #452] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80026d6: 4313 orrs r3, r2
80026d8: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
80026dc: 687b ldr r3, [r7, #4]
80026de: 681b ldr r3, [r3, #0]
80026e0: f003 0380 and.w r3, r3, #128 @ 0x80
80026e4: 2b00 cmp r3, #0
80026e6: d00a beq.n 80026fe <HAL_RCCEx_PeriphCLKConfig+0x2be>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
80026e8: 4b6c ldr r3, [pc, #432] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80026ea: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80026ee: f023 020c bic.w r2, r3, #12
80026f2: 687b ldr r3, [r7, #4]
80026f4: 6c1b ldr r3, [r3, #64] @ 0x40
80026f6: 4969 ldr r1, [pc, #420] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80026f8: 4313 orrs r3, r2
80026fa: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
80026fe: 687b ldr r3, [r7, #4]
8002700: 681b ldr r3, [r3, #0]
8002702: f403 7380 and.w r3, r3, #256 @ 0x100
8002706: 2b00 cmp r3, #0
8002708: d00a beq.n 8002720 <HAL_RCCEx_PeriphCLKConfig+0x2e0>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
800270a: 4b64 ldr r3, [pc, #400] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800270c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002710: f023 0230 bic.w r2, r3, #48 @ 0x30
8002714: 687b ldr r3, [r7, #4]
8002716: 6c5b ldr r3, [r3, #68] @ 0x44
8002718: 4960 ldr r1, [pc, #384] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800271a: 4313 orrs r3, r2
800271c: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
8002720: 687b ldr r3, [r7, #4]
8002722: 681b ldr r3, [r3, #0]
8002724: f403 7300 and.w r3, r3, #512 @ 0x200
8002728: 2b00 cmp r3, #0
800272a: d00a beq.n 8002742 <HAL_RCCEx_PeriphCLKConfig+0x302>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
800272c: 4b5b ldr r3, [pc, #364] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800272e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002732: f023 02c0 bic.w r2, r3, #192 @ 0xc0
8002736: 687b ldr r3, [r7, #4]
8002738: 6c9b ldr r3, [r3, #72] @ 0x48
800273a: 4958 ldr r1, [pc, #352] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800273c: 4313 orrs r3, r2
800273e: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART5 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
8002742: 687b ldr r3, [r7, #4]
8002744: 681b ldr r3, [r3, #0]
8002746: f403 6380 and.w r3, r3, #1024 @ 0x400
800274a: 2b00 cmp r3, #0
800274c: d00a beq.n 8002764 <HAL_RCCEx_PeriphCLKConfig+0x324>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
800274e: 4b53 ldr r3, [pc, #332] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002750: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002754: f423 7240 bic.w r2, r3, #768 @ 0x300
8002758: 687b ldr r3, [r7, #4]
800275a: 6cdb ldr r3, [r3, #76] @ 0x4c
800275c: 494f ldr r1, [pc, #316] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800275e: 4313 orrs r3, r2
8002760: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART6 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
8002764: 687b ldr r3, [r7, #4]
8002766: 681b ldr r3, [r3, #0]
8002768: f403 6300 and.w r3, r3, #2048 @ 0x800
800276c: 2b00 cmp r3, #0
800276e: d00a beq.n 8002786 <HAL_RCCEx_PeriphCLKConfig+0x346>
{
/* Check the parameters */
assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
/* Configure the USART6 clock source */
__HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
8002770: 4b4a ldr r3, [pc, #296] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002772: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002776: f423 6240 bic.w r2, r3, #3072 @ 0xc00
800277a: 687b ldr r3, [r7, #4]
800277c: 6d1b ldr r3, [r3, #80] @ 0x50
800277e: 4947 ldr r1, [pc, #284] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002780: 4313 orrs r3, r2
8002782: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART7 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
8002786: 687b ldr r3, [r7, #4]
8002788: 681b ldr r3, [r3, #0]
800278a: f403 5380 and.w r3, r3, #4096 @ 0x1000
800278e: 2b00 cmp r3, #0
8002790: d00a beq.n 80027a8 <HAL_RCCEx_PeriphCLKConfig+0x368>
{
/* Check the parameters */
assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
/* Configure the UART7 clock source */
__HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
8002792: 4b42 ldr r3, [pc, #264] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002794: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002798: f423 5240 bic.w r2, r3, #12288 @ 0x3000
800279c: 687b ldr r3, [r7, #4]
800279e: 6d5b ldr r3, [r3, #84] @ 0x54
80027a0: 493e ldr r1, [pc, #248] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80027a2: 4313 orrs r3, r2
80027a4: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART8 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
80027a8: 687b ldr r3, [r7, #4]
80027aa: 681b ldr r3, [r3, #0]
80027ac: f403 5300 and.w r3, r3, #8192 @ 0x2000
80027b0: 2b00 cmp r3, #0
80027b2: d00a beq.n 80027ca <HAL_RCCEx_PeriphCLKConfig+0x38a>
{
/* Check the parameters */
assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
/* Configure the UART8 clock source */
__HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
80027b4: 4b39 ldr r3, [pc, #228] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80027b6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80027ba: f423 4240 bic.w r2, r3, #49152 @ 0xc000
80027be: 687b ldr r3, [r7, #4]
80027c0: 6d9b ldr r3, [r3, #88] @ 0x58
80027c2: 4936 ldr r1, [pc, #216] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80027c4: 4313 orrs r3, r2
80027c6: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- CK48 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
80027ca: 687b ldr r3, [r7, #4]
80027cc: 681b ldr r3, [r3, #0]
80027ce: f403 1300 and.w r3, r3, #2097152 @ 0x200000
80027d2: 2b00 cmp r3, #0
80027d4: d011 beq.n 80027fa <HAL_RCCEx_PeriphCLKConfig+0x3ba>
{
/* Check the parameters */
assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
/* Configure the CLK48 source */
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
80027d6: 4b31 ldr r3, [pc, #196] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80027d8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80027dc: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000
80027e0: 687b ldr r3, [r7, #4]
80027e2: 6f5b ldr r3, [r3, #116] @ 0x74
80027e4: 492d ldr r1, [pc, #180] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
80027e6: 4313 orrs r3, r2
80027e8: f8c1 3090 str.w r3, [r1, #144] @ 0x90
/* Enable the PLLSAI when it's used as clock source for CK48 */
if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
80027ec: 687b ldr r3, [r7, #4]
80027ee: 6f5b ldr r3, [r3, #116] @ 0x74
80027f0: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
80027f4: d101 bne.n 80027fa <HAL_RCCEx_PeriphCLKConfig+0x3ba>
{
pllsaiused = 1;
80027f6: 2301 movs r3, #1
80027f8: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
80027fa: 687b ldr r3, [r7, #4]
80027fc: 681b ldr r3, [r3, #0]
80027fe: f403 2380 and.w r3, r3, #262144 @ 0x40000
8002802: 2b00 cmp r3, #0
8002804: d00a beq.n 800281c <HAL_RCCEx_PeriphCLKConfig+0x3dc>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LTPIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
8002806: 4b25 ldr r3, [pc, #148] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002808: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800280c: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
8002810: 687b ldr r3, [r7, #4]
8002812: 6edb ldr r3, [r3, #108] @ 0x6c
8002814: 4921 ldr r1, [pc, #132] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002816: 4313 orrs r3, r2
8002818: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*------------------------------------- SDMMC1 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
800281c: 687b ldr r3, [r7, #4]
800281e: 681b ldr r3, [r3, #0]
8002820: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8002824: 2b00 cmp r3, #0
8002826: d00a beq.n 800283e <HAL_RCCEx_PeriphCLKConfig+0x3fe>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
/* Configure the SDMMC1 clock source */
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
8002828: 4b1c ldr r3, [pc, #112] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800282a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800282e: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000
8002832: 687b ldr r3, [r7, #4]
8002834: 6f9b ldr r3, [r3, #120] @ 0x78
8002836: 4919 ldr r1, [pc, #100] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002838: 4313 orrs r3, r2
800283a: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*------------------------------------- SDMMC2 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
800283e: 687b ldr r3, [r7, #4]
8002840: 681b ldr r3, [r3, #0]
8002842: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
8002846: 2b00 cmp r3, #0
8002848: d00a beq.n 8002860 <HAL_RCCEx_PeriphCLKConfig+0x420>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
/* Configure the SDMMC2 clock source */
__HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
800284a: 4b14 ldr r3, [pc, #80] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800284c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002850: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000
8002854: 687b ldr r3, [r7, #4]
8002856: 6fdb ldr r3, [r3, #124] @ 0x7c
8002858: 4910 ldr r1, [pc, #64] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800285a: 4313 orrs r3, r2
800285c: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */
if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
8002860: 69fb ldr r3, [r7, #28]
8002862: 2b01 cmp r3, #1
8002864: d006 beq.n 8002874 <HAL_RCCEx_PeriphCLKConfig+0x434>
8002866: 687b ldr r3, [r7, #4]
8002868: 681b ldr r3, [r3, #0]
800286a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800286e: 2b00 cmp r3, #0
8002870: f000 809d beq.w 80029ae <HAL_RCCEx_PeriphCLKConfig+0x56e>
{
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
8002874: 4b09 ldr r3, [pc, #36] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
8002876: 681b ldr r3, [r3, #0]
8002878: 4a08 ldr r2, [pc, #32] @ (800289c <HAL_RCCEx_PeriphCLKConfig+0x45c>)
800287a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
800287e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002880: f7fe fdec bl 800145c <HAL_GetTick>
8002884: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8002886: e00b b.n 80028a0 <HAL_RCCEx_PeriphCLKConfig+0x460>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
8002888: f7fe fde8 bl 800145c <HAL_GetTick>
800288c: 4602 mov r2, r0
800288e: 697b ldr r3, [r7, #20]
8002890: 1ad3 subs r3, r2, r3
8002892: 2b64 cmp r3, #100 @ 0x64
8002894: d904 bls.n 80028a0 <HAL_RCCEx_PeriphCLKConfig+0x460>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8002896: 2303 movs r3, #3
8002898: e116 b.n 8002ac8 <HAL_RCCEx_PeriphCLKConfig+0x688>
800289a: bf00 nop
800289c: 40023800 .word 0x40023800
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
80028a0: 4b8b ldr r3, [pc, #556] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80028a2: 681b ldr r3, [r3, #0]
80028a4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
80028a8: 2b00 cmp r3, #0
80028aa: d1ed bne.n 8002888 <HAL_RCCEx_PeriphCLKConfig+0x448>
/* check for common PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
/*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
80028ac: 687b ldr r3, [r7, #4]
80028ae: 681b ldr r3, [r3, #0]
80028b0: f003 0301 and.w r3, r3, #1
80028b4: 2b00 cmp r3, #0
80028b6: d017 beq.n 80028e8 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
80028b8: 687b ldr r3, [r7, #4]
80028ba: 6adb ldr r3, [r3, #44] @ 0x2c
80028bc: 2b00 cmp r3, #0
80028be: d113 bne.n 80028e8 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
80028c0: 4b83 ldr r3, [pc, #524] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80028c2: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
80028c6: 0e1b lsrs r3, r3, #24
80028c8: f003 030f and.w r3, r3, #15
80028cc: 613b str r3, [r7, #16]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2SR);
80028ce: 687b ldr r3, [r7, #4]
80028d0: 685b ldr r3, [r3, #4]
80028d2: 019a lsls r2, r3, #6
80028d4: 693b ldr r3, [r7, #16]
80028d6: 061b lsls r3, r3, #24
80028d8: 431a orrs r2, r3
80028da: 687b ldr r3, [r7, #4]
80028dc: 689b ldr r3, [r3, #8]
80028de: 071b lsls r3, r3, #28
80028e0: 497b ldr r1, [pc, #492] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80028e2: 4313 orrs r3, r2
80028e4: f8c1 3084 str.w r3, [r1, #132] @ 0x84
}
/*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
80028e8: 687b ldr r3, [r7, #4]
80028ea: 681b ldr r3, [r3, #0]
80028ec: f403 2300 and.w r3, r3, #524288 @ 0x80000
80028f0: 2b00 cmp r3, #0
80028f2: d004 beq.n 80028fe <HAL_RCCEx_PeriphCLKConfig+0x4be>
80028f4: 687b ldr r3, [r7, #4]
80028f6: 6b5b ldr r3, [r3, #52] @ 0x34
80028f8: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
80028fc: d00a beq.n 8002914 <HAL_RCCEx_PeriphCLKConfig+0x4d4>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
80028fe: 687b ldr r3, [r7, #4]
8002900: 681b ldr r3, [r3, #0]
8002902: f403 1380 and.w r3, r3, #1048576 @ 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
8002906: 2b00 cmp r3, #0
8002908: d024 beq.n 8002954 <HAL_RCCEx_PeriphCLKConfig+0x514>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
800290a: 687b ldr r3, [r7, #4]
800290c: 6b9b ldr r3, [r3, #56] @ 0x38
800290e: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8002912: d11f bne.n 8002954 <HAL_RCCEx_PeriphCLKConfig+0x514>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Check for PLLI2S/DIVQ parameters */
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
8002914: 4b6e ldr r3, [pc, #440] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002916: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
800291a: 0f1b lsrs r3, r3, #28
800291c: f003 0307 and.w r3, r3, #7
8002920: 613b str r3, [r7, #16]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0);
8002922: 687b ldr r3, [r7, #4]
8002924: 685b ldr r3, [r3, #4]
8002926: 019a lsls r2, r3, #6
8002928: 687b ldr r3, [r7, #4]
800292a: 68db ldr r3, [r3, #12]
800292c: 061b lsls r3, r3, #24
800292e: 431a orrs r2, r3
8002930: 693b ldr r3, [r7, #16]
8002932: 071b lsls r3, r3, #28
8002934: 4966 ldr r1, [pc, #408] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002936: 4313 orrs r3, r2
8002938: f8c1 3084 str.w r3, [r1, #132] @ 0x84
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
800293c: 4b64 ldr r3, [pc, #400] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800293e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8002942: f023 021f bic.w r2, r3, #31
8002946: 687b ldr r3, [r7, #4]
8002948: 69db ldr r3, [r3, #28]
800294a: 3b01 subs r3, #1
800294c: 4960 ldr r1, [pc, #384] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800294e: 4313 orrs r3, r2
8002950: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
8002954: 687b ldr r3, [r7, #4]
8002956: 681b ldr r3, [r3, #0]
8002958: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800295c: 2b00 cmp r3, #0
800295e: d00d beq.n 800297c <HAL_RCCEx_PeriphCLKConfig+0x53c>
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
8002960: 687b ldr r3, [r7, #4]
8002962: 685b ldr r3, [r3, #4]
8002964: 019a lsls r2, r3, #6
8002966: 687b ldr r3, [r7, #4]
8002968: 68db ldr r3, [r3, #12]
800296a: 061b lsls r3, r3, #24
800296c: 431a orrs r2, r3
800296e: 687b ldr r3, [r7, #4]
8002970: 689b ldr r3, [r3, #8]
8002972: 071b lsls r3, r3, #28
8002974: 4956 ldr r1, [pc, #344] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002976: 4313 orrs r3, r2
8002978: f8c1 3084 str.w r3, [r1, #132] @ 0x84
}
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
800297c: 4b54 ldr r3, [pc, #336] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
800297e: 681b ldr r3, [r3, #0]
8002980: 4a53 ldr r2, [pc, #332] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002982: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
8002986: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002988: f7fe fd68 bl 800145c <HAL_GetTick>
800298c: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
800298e: e008 b.n 80029a2 <HAL_RCCEx_PeriphCLKConfig+0x562>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
8002990: f7fe fd64 bl 800145c <HAL_GetTick>
8002994: 4602 mov r2, r0
8002996: 697b ldr r3, [r7, #20]
8002998: 1ad3 subs r3, r2, r3
800299a: 2b64 cmp r3, #100 @ 0x64
800299c: d901 bls.n 80029a2 <HAL_RCCEx_PeriphCLKConfig+0x562>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
800299e: 2303 movs r3, #3
80029a0: e092 b.n 8002ac8 <HAL_RCCEx_PeriphCLKConfig+0x688>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
80029a2: 4b4b ldr r3, [pc, #300] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80029a4: 681b ldr r3, [r3, #0]
80029a6: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
80029aa: 2b00 cmp r3, #0
80029ac: d0f0 beq.n 8002990 <HAL_RCCEx_PeriphCLKConfig+0x550>
}
}
/*-------------------------------------- PLLSAI Configuration ---------------------------------*/
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
if(pllsaiused == 1)
80029ae: 69bb ldr r3, [r7, #24]
80029b0: 2b01 cmp r3, #1
80029b2: f040 8088 bne.w 8002ac6 <HAL_RCCEx_PeriphCLKConfig+0x686>
{
/* Disable PLLSAI Clock */
__HAL_RCC_PLLSAI_DISABLE();
80029b6: 4b46 ldr r3, [pc, #280] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80029b8: 681b ldr r3, [r3, #0]
80029ba: 4a45 ldr r2, [pc, #276] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80029bc: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80029c0: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80029c2: f7fe fd4b bl 800145c <HAL_GetTick>
80029c6: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
80029c8: e008 b.n 80029dc <HAL_RCCEx_PeriphCLKConfig+0x59c>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
80029ca: f7fe fd47 bl 800145c <HAL_GetTick>
80029ce: 4602 mov r2, r0
80029d0: 697b ldr r3, [r7, #20]
80029d2: 1ad3 subs r3, r2, r3
80029d4: 2b64 cmp r3, #100 @ 0x64
80029d6: d901 bls.n 80029dc <HAL_RCCEx_PeriphCLKConfig+0x59c>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
80029d8: 2303 movs r3, #3
80029da: e075 b.n 8002ac8 <HAL_RCCEx_PeriphCLKConfig+0x688>
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
80029dc: 4b3c ldr r3, [pc, #240] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
80029de: 681b ldr r3, [r3, #0]
80029e0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
80029e4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
80029e8: d0ef beq.n 80029ca <HAL_RCCEx_PeriphCLKConfig+0x58a>
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
/*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
80029ea: 687b ldr r3, [r7, #4]
80029ec: 681b ldr r3, [r3, #0]
80029ee: f403 2300 and.w r3, r3, #524288 @ 0x80000
80029f2: 2b00 cmp r3, #0
80029f4: d003 beq.n 80029fe <HAL_RCCEx_PeriphCLKConfig+0x5be>
80029f6: 687b ldr r3, [r7, #4]
80029f8: 6b5b ldr r3, [r3, #52] @ 0x34
80029fa: 2b00 cmp r3, #0
80029fc: d009 beq.n 8002a12 <HAL_RCCEx_PeriphCLKConfig+0x5d2>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
80029fe: 687b ldr r3, [r7, #4]
8002a00: 681b ldr r3, [r3, #0]
8002a02: f403 1380 and.w r3, r3, #1048576 @ 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
8002a06: 2b00 cmp r3, #0
8002a08: d024 beq.n 8002a54 <HAL_RCCEx_PeriphCLKConfig+0x614>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
8002a0a: 687b ldr r3, [r7, #4]
8002a0c: 6b9b ldr r3, [r3, #56] @ 0x38
8002a0e: 2b00 cmp r3, #0
8002a10: d120 bne.n 8002a54 <HAL_RCCEx_PeriphCLKConfig+0x614>
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
/* check for PLLSAI/DIVQ Parameter */
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
8002a12: 4b2f ldr r3, [pc, #188] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002a14: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8002a18: 0c1b lsrs r3, r3, #16
8002a1a: f003 0303 and.w r3, r3, #3
8002a1e: 613b str r3, [r7, #16]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ);
8002a20: 687b ldr r3, [r7, #4]
8002a22: 691b ldr r3, [r3, #16]
8002a24: 019a lsls r2, r3, #6
8002a26: 693b ldr r3, [r7, #16]
8002a28: 041b lsls r3, r3, #16
8002a2a: 431a orrs r2, r3
8002a2c: 687b ldr r3, [r7, #4]
8002a2e: 695b ldr r3, [r3, #20]
8002a30: 061b lsls r3, r3, #24
8002a32: 4927 ldr r1, [pc, #156] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002a34: 4313 orrs r3, r2
8002a36: f8c1 3088 str.w r3, [r1, #136] @ 0x88
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
8002a3a: 4b25 ldr r3, [pc, #148] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002a3c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8002a40: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
8002a44: 687b ldr r3, [r7, #4]
8002a46: 6a1b ldr r3, [r3, #32]
8002a48: 3b01 subs r3, #1
8002a4a: 021b lsls r3, r3, #8
8002a4c: 4920 ldr r1, [pc, #128] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002a4e: 4313 orrs r3, r2
8002a50: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
/* In Case of PLLI2S is selected as source clock for CK48 */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
8002a54: 687b ldr r3, [r7, #4]
8002a56: 681b ldr r3, [r3, #0]
8002a58: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8002a5c: 2b00 cmp r3, #0
8002a5e: d018 beq.n 8002a92 <HAL_RCCEx_PeriphCLKConfig+0x652>
8002a60: 687b ldr r3, [r7, #4]
8002a62: 6f5b ldr r3, [r3, #116] @ 0x74
8002a64: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
8002a68: d113 bne.n 8002a92 <HAL_RCCEx_PeriphCLKConfig+0x652>
{
/* check for Parameters */
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
8002a6a: 4b19 ldr r3, [pc, #100] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002a6c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8002a70: 0e1b lsrs r3, r3, #24
8002a72: f003 030f and.w r3, r3, #15
8002a76: 613b str r3, [r7, #16]
/* Configure the PLLSAI division factors */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0);
8002a78: 687b ldr r3, [r7, #4]
8002a7a: 691b ldr r3, [r3, #16]
8002a7c: 019a lsls r2, r3, #6
8002a7e: 687b ldr r3, [r7, #4]
8002a80: 699b ldr r3, [r3, #24]
8002a82: 041b lsls r3, r3, #16
8002a84: 431a orrs r2, r3
8002a86: 693b ldr r3, [r7, #16]
8002a88: 061b lsls r3, r3, #24
8002a8a: 4911 ldr r1, [pc, #68] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002a8c: 4313 orrs r3, r2
8002a8e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
8002a92: 4b0f ldr r3, [pc, #60] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002a94: 681b ldr r3, [r3, #0]
8002a96: 4a0e ldr r2, [pc, #56] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002a98: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002a9c: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002a9e: f7fe fcdd bl 800145c <HAL_GetTick>
8002aa2: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is ready */
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
8002aa4: e008 b.n 8002ab8 <HAL_RCCEx_PeriphCLKConfig+0x678>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
8002aa6: f7fe fcd9 bl 800145c <HAL_GetTick>
8002aaa: 4602 mov r2, r0
8002aac: 697b ldr r3, [r7, #20]
8002aae: 1ad3 subs r3, r2, r3
8002ab0: 2b64 cmp r3, #100 @ 0x64
8002ab2: d901 bls.n 8002ab8 <HAL_RCCEx_PeriphCLKConfig+0x678>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8002ab4: 2303 movs r3, #3
8002ab6: e007 b.n 8002ac8 <HAL_RCCEx_PeriphCLKConfig+0x688>
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
8002ab8: 4b05 ldr r3, [pc, #20] @ (8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x690>)
8002aba: 681b ldr r3, [r3, #0]
8002abc: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
8002ac0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8002ac4: d1ef bne.n 8002aa6 <HAL_RCCEx_PeriphCLKConfig+0x666>
}
}
}
return HAL_OK;
8002ac6: 2300 movs r3, #0
}
8002ac8: 4618 mov r0, r3
8002aca: 3720 adds r7, #32
8002acc: 46bd mov sp, r7
8002ace: bd80 pop {r7, pc}
8002ad0: 40023800 .word 0x40023800
08002ad4 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8002ad4: b580 push {r7, lr}
8002ad6: b082 sub sp, #8
8002ad8: af00 add r7, sp, #0
8002ada: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8002adc: 687b ldr r3, [r7, #4]
8002ade: 2b00 cmp r3, #0
8002ae0: d101 bne.n 8002ae6 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8002ae2: 2301 movs r3, #1
8002ae4: e049 b.n 8002b7a <HAL_TIM_Base_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8002ae6: 687b ldr r3, [r7, #4]
8002ae8: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8002aec: b2db uxtb r3, r3
8002aee: 2b00 cmp r3, #0
8002af0: d106 bne.n 8002b00 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8002af2: 687b ldr r3, [r7, #4]
8002af4: 2200 movs r2, #0
8002af6: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8002afa: 6878 ldr r0, [r7, #4]
8002afc: f000 f841 bl 8002b82 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002b00: 687b ldr r3, [r7, #4]
8002b02: 2202 movs r2, #2
8002b04: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8002b08: 687b ldr r3, [r7, #4]
8002b0a: 681a ldr r2, [r3, #0]
8002b0c: 687b ldr r3, [r7, #4]
8002b0e: 3304 adds r3, #4
8002b10: 4619 mov r1, r3
8002b12: 4610 mov r0, r2
8002b14: f000 f9e8 bl 8002ee8 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8002b18: 687b ldr r3, [r7, #4]
8002b1a: 2201 movs r2, #1
8002b1c: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002b20: 687b ldr r3, [r7, #4]
8002b22: 2201 movs r2, #1
8002b24: f883 203e strb.w r2, [r3, #62] @ 0x3e
8002b28: 687b ldr r3, [r7, #4]
8002b2a: 2201 movs r2, #1
8002b2c: f883 203f strb.w r2, [r3, #63] @ 0x3f
8002b30: 687b ldr r3, [r7, #4]
8002b32: 2201 movs r2, #1
8002b34: f883 2040 strb.w r2, [r3, #64] @ 0x40
8002b38: 687b ldr r3, [r7, #4]
8002b3a: 2201 movs r2, #1
8002b3c: f883 2041 strb.w r2, [r3, #65] @ 0x41
8002b40: 687b ldr r3, [r7, #4]
8002b42: 2201 movs r2, #1
8002b44: f883 2042 strb.w r2, [r3, #66] @ 0x42
8002b48: 687b ldr r3, [r7, #4]
8002b4a: 2201 movs r2, #1
8002b4c: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002b50: 687b ldr r3, [r7, #4]
8002b52: 2201 movs r2, #1
8002b54: f883 2044 strb.w r2, [r3, #68] @ 0x44
8002b58: 687b ldr r3, [r7, #4]
8002b5a: 2201 movs r2, #1
8002b5c: f883 2045 strb.w r2, [r3, #69] @ 0x45
8002b60: 687b ldr r3, [r7, #4]
8002b62: 2201 movs r2, #1
8002b64: f883 2046 strb.w r2, [r3, #70] @ 0x46
8002b68: 687b ldr r3, [r7, #4]
8002b6a: 2201 movs r2, #1
8002b6c: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8002b70: 687b ldr r3, [r7, #4]
8002b72: 2201 movs r2, #1
8002b74: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8002b78: 2300 movs r3, #0
}
8002b7a: 4618 mov r0, r3
8002b7c: 3708 adds r7, #8
8002b7e: 46bd mov sp, r7
8002b80: bd80 pop {r7, pc}
08002b82 <HAL_TIM_Base_MspInit>:
* @brief Initializes the TIM Base MSP.
* @param htim TIM Base handle
* @retval None
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
8002b82: b480 push {r7}
8002b84: b083 sub sp, #12
8002b86: af00 add r7, sp, #0
8002b88: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Base_MspInit could be implemented in the user file
*/
}
8002b8a: bf00 nop
8002b8c: 370c adds r7, #12
8002b8e: 46bd mov sp, r7
8002b90: f85d 7b04 ldr.w r7, [sp], #4
8002b94: 4770 bx lr
...
08002b98 <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8002b98: b480 push {r7}
8002b9a: b085 sub sp, #20
8002b9c: af00 add r7, sp, #0
8002b9e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
8002ba0: 687b ldr r3, [r7, #4]
8002ba2: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8002ba6: b2db uxtb r3, r3
8002ba8: 2b01 cmp r3, #1
8002baa: d001 beq.n 8002bb0 <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
8002bac: 2301 movs r3, #1
8002bae: e054 b.n 8002c5a <HAL_TIM_Base_Start_IT+0xc2>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002bb0: 687b ldr r3, [r7, #4]
8002bb2: 2202 movs r2, #2
8002bb4: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8002bb8: 687b ldr r3, [r7, #4]
8002bba: 681b ldr r3, [r3, #0]
8002bbc: 68da ldr r2, [r3, #12]
8002bbe: 687b ldr r3, [r7, #4]
8002bc0: 681b ldr r3, [r3, #0]
8002bc2: f042 0201 orr.w r2, r2, #1
8002bc6: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8002bc8: 687b ldr r3, [r7, #4]
8002bca: 681b ldr r3, [r3, #0]
8002bcc: 4a26 ldr r2, [pc, #152] @ (8002c68 <HAL_TIM_Base_Start_IT+0xd0>)
8002bce: 4293 cmp r3, r2
8002bd0: d022 beq.n 8002c18 <HAL_TIM_Base_Start_IT+0x80>
8002bd2: 687b ldr r3, [r7, #4]
8002bd4: 681b ldr r3, [r3, #0]
8002bd6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8002bda: d01d beq.n 8002c18 <HAL_TIM_Base_Start_IT+0x80>
8002bdc: 687b ldr r3, [r7, #4]
8002bde: 681b ldr r3, [r3, #0]
8002be0: 4a22 ldr r2, [pc, #136] @ (8002c6c <HAL_TIM_Base_Start_IT+0xd4>)
8002be2: 4293 cmp r3, r2
8002be4: d018 beq.n 8002c18 <HAL_TIM_Base_Start_IT+0x80>
8002be6: 687b ldr r3, [r7, #4]
8002be8: 681b ldr r3, [r3, #0]
8002bea: 4a21 ldr r2, [pc, #132] @ (8002c70 <HAL_TIM_Base_Start_IT+0xd8>)
8002bec: 4293 cmp r3, r2
8002bee: d013 beq.n 8002c18 <HAL_TIM_Base_Start_IT+0x80>
8002bf0: 687b ldr r3, [r7, #4]
8002bf2: 681b ldr r3, [r3, #0]
8002bf4: 4a1f ldr r2, [pc, #124] @ (8002c74 <HAL_TIM_Base_Start_IT+0xdc>)
8002bf6: 4293 cmp r3, r2
8002bf8: d00e beq.n 8002c18 <HAL_TIM_Base_Start_IT+0x80>
8002bfa: 687b ldr r3, [r7, #4]
8002bfc: 681b ldr r3, [r3, #0]
8002bfe: 4a1e ldr r2, [pc, #120] @ (8002c78 <HAL_TIM_Base_Start_IT+0xe0>)
8002c00: 4293 cmp r3, r2
8002c02: d009 beq.n 8002c18 <HAL_TIM_Base_Start_IT+0x80>
8002c04: 687b ldr r3, [r7, #4]
8002c06: 681b ldr r3, [r3, #0]
8002c08: 4a1c ldr r2, [pc, #112] @ (8002c7c <HAL_TIM_Base_Start_IT+0xe4>)
8002c0a: 4293 cmp r3, r2
8002c0c: d004 beq.n 8002c18 <HAL_TIM_Base_Start_IT+0x80>
8002c0e: 687b ldr r3, [r7, #4]
8002c10: 681b ldr r3, [r3, #0]
8002c12: 4a1b ldr r2, [pc, #108] @ (8002c80 <HAL_TIM_Base_Start_IT+0xe8>)
8002c14: 4293 cmp r3, r2
8002c16: d115 bne.n 8002c44 <HAL_TIM_Base_Start_IT+0xac>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8002c18: 687b ldr r3, [r7, #4]
8002c1a: 681b ldr r3, [r3, #0]
8002c1c: 689a ldr r2, [r3, #8]
8002c1e: 4b19 ldr r3, [pc, #100] @ (8002c84 <HAL_TIM_Base_Start_IT+0xec>)
8002c20: 4013 ands r3, r2
8002c22: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002c24: 68fb ldr r3, [r7, #12]
8002c26: 2b06 cmp r3, #6
8002c28: d015 beq.n 8002c56 <HAL_TIM_Base_Start_IT+0xbe>
8002c2a: 68fb ldr r3, [r7, #12]
8002c2c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8002c30: d011 beq.n 8002c56 <HAL_TIM_Base_Start_IT+0xbe>
{
__HAL_TIM_ENABLE(htim);
8002c32: 687b ldr r3, [r7, #4]
8002c34: 681b ldr r3, [r3, #0]
8002c36: 681a ldr r2, [r3, #0]
8002c38: 687b ldr r3, [r7, #4]
8002c3a: 681b ldr r3, [r3, #0]
8002c3c: f042 0201 orr.w r2, r2, #1
8002c40: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002c42: e008 b.n 8002c56 <HAL_TIM_Base_Start_IT+0xbe>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8002c44: 687b ldr r3, [r7, #4]
8002c46: 681b ldr r3, [r3, #0]
8002c48: 681a ldr r2, [r3, #0]
8002c4a: 687b ldr r3, [r7, #4]
8002c4c: 681b ldr r3, [r3, #0]
8002c4e: f042 0201 orr.w r2, r2, #1
8002c52: 601a str r2, [r3, #0]
8002c54: e000 b.n 8002c58 <HAL_TIM_Base_Start_IT+0xc0>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002c56: bf00 nop
}
/* Return function status */
return HAL_OK;
8002c58: 2300 movs r3, #0
}
8002c5a: 4618 mov r0, r3
8002c5c: 3714 adds r7, #20
8002c5e: 46bd mov sp, r7
8002c60: f85d 7b04 ldr.w r7, [sp], #4
8002c64: 4770 bx lr
8002c66: bf00 nop
8002c68: 40010000 .word 0x40010000
8002c6c: 40000400 .word 0x40000400
8002c70: 40000800 .word 0x40000800
8002c74: 40000c00 .word 0x40000c00
8002c78: 40010400 .word 0x40010400
8002c7c: 40014000 .word 0x40014000
8002c80: 40001800 .word 0x40001800
8002c84: 00010007 .word 0x00010007
08002c88 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8002c88: b580 push {r7, lr}
8002c8a: b084 sub sp, #16
8002c8c: af00 add r7, sp, #0
8002c8e: 6078 str r0, [r7, #4]
uint32_t itsource = htim->Instance->DIER;
8002c90: 687b ldr r3, [r7, #4]
8002c92: 681b ldr r3, [r3, #0]
8002c94: 68db ldr r3, [r3, #12]
8002c96: 60fb str r3, [r7, #12]
uint32_t itflag = htim->Instance->SR;
8002c98: 687b ldr r3, [r7, #4]
8002c9a: 681b ldr r3, [r3, #0]
8002c9c: 691b ldr r3, [r3, #16]
8002c9e: 60bb str r3, [r7, #8]
/* Capture compare 1 event */
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
8002ca0: 68bb ldr r3, [r7, #8]
8002ca2: f003 0302 and.w r3, r3, #2
8002ca6: 2b00 cmp r3, #0
8002ca8: d020 beq.n 8002cec <HAL_TIM_IRQHandler+0x64>
{
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
8002caa: 68fb ldr r3, [r7, #12]
8002cac: f003 0302 and.w r3, r3, #2
8002cb0: 2b00 cmp r3, #0
8002cb2: d01b beq.n 8002cec <HAL_TIM_IRQHandler+0x64>
{
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
8002cb4: 687b ldr r3, [r7, #4]
8002cb6: 681b ldr r3, [r3, #0]
8002cb8: f06f 0202 mvn.w r2, #2
8002cbc: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8002cbe: 687b ldr r3, [r7, #4]
8002cc0: 2201 movs r2, #1
8002cc2: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8002cc4: 687b ldr r3, [r7, #4]
8002cc6: 681b ldr r3, [r3, #0]
8002cc8: 699b ldr r3, [r3, #24]
8002cca: f003 0303 and.w r3, r3, #3
8002cce: 2b00 cmp r3, #0
8002cd0: d003 beq.n 8002cda <HAL_TIM_IRQHandler+0x52>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002cd2: 6878 ldr r0, [r7, #4]
8002cd4: f000 f8e9 bl 8002eaa <HAL_TIM_IC_CaptureCallback>
8002cd8: e005 b.n 8002ce6 <HAL_TIM_IRQHandler+0x5e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002cda: 6878 ldr r0, [r7, #4]
8002cdc: f000 f8db bl 8002e96 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002ce0: 6878 ldr r0, [r7, #4]
8002ce2: f000 f8ec bl 8002ebe <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002ce6: 687b ldr r3, [r7, #4]
8002ce8: 2200 movs r2, #0
8002cea: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
8002cec: 68bb ldr r3, [r7, #8]
8002cee: f003 0304 and.w r3, r3, #4
8002cf2: 2b00 cmp r3, #0
8002cf4: d020 beq.n 8002d38 <HAL_TIM_IRQHandler+0xb0>
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
8002cf6: 68fb ldr r3, [r7, #12]
8002cf8: f003 0304 and.w r3, r3, #4
8002cfc: 2b00 cmp r3, #0
8002cfe: d01b beq.n 8002d38 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
8002d00: 687b ldr r3, [r7, #4]
8002d02: 681b ldr r3, [r3, #0]
8002d04: f06f 0204 mvn.w r2, #4
8002d08: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8002d0a: 687b ldr r3, [r7, #4]
8002d0c: 2202 movs r2, #2
8002d0e: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8002d10: 687b ldr r3, [r7, #4]
8002d12: 681b ldr r3, [r3, #0]
8002d14: 699b ldr r3, [r3, #24]
8002d16: f403 7340 and.w r3, r3, #768 @ 0x300
8002d1a: 2b00 cmp r3, #0
8002d1c: d003 beq.n 8002d26 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002d1e: 6878 ldr r0, [r7, #4]
8002d20: f000 f8c3 bl 8002eaa <HAL_TIM_IC_CaptureCallback>
8002d24: e005 b.n 8002d32 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002d26: 6878 ldr r0, [r7, #4]
8002d28: f000 f8b5 bl 8002e96 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002d2c: 6878 ldr r0, [r7, #4]
8002d2e: f000 f8c6 bl 8002ebe <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002d32: 687b ldr r3, [r7, #4]
8002d34: 2200 movs r2, #0
8002d36: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
8002d38: 68bb ldr r3, [r7, #8]
8002d3a: f003 0308 and.w r3, r3, #8
8002d3e: 2b00 cmp r3, #0
8002d40: d020 beq.n 8002d84 <HAL_TIM_IRQHandler+0xfc>
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
8002d42: 68fb ldr r3, [r7, #12]
8002d44: f003 0308 and.w r3, r3, #8
8002d48: 2b00 cmp r3, #0
8002d4a: d01b beq.n 8002d84 <HAL_TIM_IRQHandler+0xfc>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
8002d4c: 687b ldr r3, [r7, #4]
8002d4e: 681b ldr r3, [r3, #0]
8002d50: f06f 0208 mvn.w r2, #8
8002d54: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8002d56: 687b ldr r3, [r7, #4]
8002d58: 2204 movs r2, #4
8002d5a: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8002d5c: 687b ldr r3, [r7, #4]
8002d5e: 681b ldr r3, [r3, #0]
8002d60: 69db ldr r3, [r3, #28]
8002d62: f003 0303 and.w r3, r3, #3
8002d66: 2b00 cmp r3, #0
8002d68: d003 beq.n 8002d72 <HAL_TIM_IRQHandler+0xea>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002d6a: 6878 ldr r0, [r7, #4]
8002d6c: f000 f89d bl 8002eaa <HAL_TIM_IC_CaptureCallback>
8002d70: e005 b.n 8002d7e <HAL_TIM_IRQHandler+0xf6>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002d72: 6878 ldr r0, [r7, #4]
8002d74: f000 f88f bl 8002e96 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002d78: 6878 ldr r0, [r7, #4]
8002d7a: f000 f8a0 bl 8002ebe <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002d7e: 687b ldr r3, [r7, #4]
8002d80: 2200 movs r2, #0
8002d82: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
8002d84: 68bb ldr r3, [r7, #8]
8002d86: f003 0310 and.w r3, r3, #16
8002d8a: 2b00 cmp r3, #0
8002d8c: d020 beq.n 8002dd0 <HAL_TIM_IRQHandler+0x148>
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
8002d8e: 68fb ldr r3, [r7, #12]
8002d90: f003 0310 and.w r3, r3, #16
8002d94: 2b00 cmp r3, #0
8002d96: d01b beq.n 8002dd0 <HAL_TIM_IRQHandler+0x148>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
8002d98: 687b ldr r3, [r7, #4]
8002d9a: 681b ldr r3, [r3, #0]
8002d9c: f06f 0210 mvn.w r2, #16
8002da0: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8002da2: 687b ldr r3, [r7, #4]
8002da4: 2208 movs r2, #8
8002da6: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8002da8: 687b ldr r3, [r7, #4]
8002daa: 681b ldr r3, [r3, #0]
8002dac: 69db ldr r3, [r3, #28]
8002dae: f403 7340 and.w r3, r3, #768 @ 0x300
8002db2: 2b00 cmp r3, #0
8002db4: d003 beq.n 8002dbe <HAL_TIM_IRQHandler+0x136>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002db6: 6878 ldr r0, [r7, #4]
8002db8: f000 f877 bl 8002eaa <HAL_TIM_IC_CaptureCallback>
8002dbc: e005 b.n 8002dca <HAL_TIM_IRQHandler+0x142>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002dbe: 6878 ldr r0, [r7, #4]
8002dc0: f000 f869 bl 8002e96 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002dc4: 6878 ldr r0, [r7, #4]
8002dc6: f000 f87a bl 8002ebe <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002dca: 687b ldr r3, [r7, #4]
8002dcc: 2200 movs r2, #0
8002dce: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
8002dd0: 68bb ldr r3, [r7, #8]
8002dd2: f003 0301 and.w r3, r3, #1
8002dd6: 2b00 cmp r3, #0
8002dd8: d00c beq.n 8002df4 <HAL_TIM_IRQHandler+0x16c>
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
8002dda: 68fb ldr r3, [r7, #12]
8002ddc: f003 0301 and.w r3, r3, #1
8002de0: 2b00 cmp r3, #0
8002de2: d007 beq.n 8002df4 <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
8002de4: 687b ldr r3, [r7, #4]
8002de6: 681b ldr r3, [r3, #0]
8002de8: f06f 0201 mvn.w r2, #1
8002dec: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8002dee: 6878 ldr r0, [r7, #4]
8002df0: f7fe f902 bl 8000ff8 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
8002df4: 68bb ldr r3, [r7, #8]
8002df6: f003 0380 and.w r3, r3, #128 @ 0x80
8002dfa: 2b00 cmp r3, #0
8002dfc: d104 bne.n 8002e08 <HAL_TIM_IRQHandler+0x180>
((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
8002dfe: 68bb ldr r3, [r7, #8]
8002e00: f403 5300 and.w r3, r3, #8192 @ 0x2000
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
8002e04: 2b00 cmp r3, #0
8002e06: d00c beq.n 8002e22 <HAL_TIM_IRQHandler+0x19a>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
8002e08: 68fb ldr r3, [r7, #12]
8002e0a: f003 0380 and.w r3, r3, #128 @ 0x80
8002e0e: 2b00 cmp r3, #0
8002e10: d007 beq.n 8002e22 <HAL_TIM_IRQHandler+0x19a>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
8002e12: 687b ldr r3, [r7, #4]
8002e14: 681b ldr r3, [r3, #0]
8002e16: f46f 5202 mvn.w r2, #8320 @ 0x2080
8002e1a: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8002e1c: 6878 ldr r0, [r7, #4]
8002e1e: f000 f913 bl 8003048 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
8002e22: 68bb ldr r3, [r7, #8]
8002e24: f403 7380 and.w r3, r3, #256 @ 0x100
8002e28: 2b00 cmp r3, #0
8002e2a: d00c beq.n 8002e46 <HAL_TIM_IRQHandler+0x1be>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
8002e2c: 68fb ldr r3, [r7, #12]
8002e2e: f003 0380 and.w r3, r3, #128 @ 0x80
8002e32: 2b00 cmp r3, #0
8002e34: d007 beq.n 8002e46 <HAL_TIM_IRQHandler+0x1be>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
8002e36: 687b ldr r3, [r7, #4]
8002e38: 681b ldr r3, [r3, #0]
8002e3a: f46f 7280 mvn.w r2, #256 @ 0x100
8002e3e: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
8002e40: 6878 ldr r0, [r7, #4]
8002e42: f000 f90b bl 800305c <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
8002e46: 68bb ldr r3, [r7, #8]
8002e48: f003 0340 and.w r3, r3, #64 @ 0x40
8002e4c: 2b00 cmp r3, #0
8002e4e: d00c beq.n 8002e6a <HAL_TIM_IRQHandler+0x1e2>
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
8002e50: 68fb ldr r3, [r7, #12]
8002e52: f003 0340 and.w r3, r3, #64 @ 0x40
8002e56: 2b00 cmp r3, #0
8002e58: d007 beq.n 8002e6a <HAL_TIM_IRQHandler+0x1e2>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
8002e5a: 687b ldr r3, [r7, #4]
8002e5c: 681b ldr r3, [r3, #0]
8002e5e: f06f 0240 mvn.w r2, #64 @ 0x40
8002e62: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8002e64: 6878 ldr r0, [r7, #4]
8002e66: f000 f834 bl 8002ed2 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
8002e6a: 68bb ldr r3, [r7, #8]
8002e6c: f003 0320 and.w r3, r3, #32
8002e70: 2b00 cmp r3, #0
8002e72: d00c beq.n 8002e8e <HAL_TIM_IRQHandler+0x206>
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
8002e74: 68fb ldr r3, [r7, #12]
8002e76: f003 0320 and.w r3, r3, #32
8002e7a: 2b00 cmp r3, #0
8002e7c: d007 beq.n 8002e8e <HAL_TIM_IRQHandler+0x206>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
8002e7e: 687b ldr r3, [r7, #4]
8002e80: 681b ldr r3, [r3, #0]
8002e82: f06f 0220 mvn.w r2, #32
8002e86: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8002e88: 6878 ldr r0, [r7, #4]
8002e8a: f000 f8d3 bl 8003034 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8002e8e: bf00 nop
8002e90: 3710 adds r7, #16
8002e92: 46bd mov sp, r7
8002e94: bd80 pop {r7, pc}
08002e96 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8002e96: b480 push {r7}
8002e98: b083 sub sp, #12
8002e9a: af00 add r7, sp, #0
8002e9c: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8002e9e: bf00 nop
8002ea0: 370c adds r7, #12
8002ea2: 46bd mov sp, r7
8002ea4: f85d 7b04 ldr.w r7, [sp], #4
8002ea8: 4770 bx lr
08002eaa <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8002eaa: b480 push {r7}
8002eac: b083 sub sp, #12
8002eae: af00 add r7, sp, #0
8002eb0: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8002eb2: bf00 nop
8002eb4: 370c adds r7, #12
8002eb6: 46bd mov sp, r7
8002eb8: f85d 7b04 ldr.w r7, [sp], #4
8002ebc: 4770 bx lr
08002ebe <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8002ebe: b480 push {r7}
8002ec0: b083 sub sp, #12
8002ec2: af00 add r7, sp, #0
8002ec4: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8002ec6: bf00 nop
8002ec8: 370c adds r7, #12
8002eca: 46bd mov sp, r7
8002ecc: f85d 7b04 ldr.w r7, [sp], #4
8002ed0: 4770 bx lr
08002ed2 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8002ed2: b480 push {r7}
8002ed4: b083 sub sp, #12
8002ed6: af00 add r7, sp, #0
8002ed8: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8002eda: bf00 nop
8002edc: 370c adds r7, #12
8002ede: 46bd mov sp, r7
8002ee0: f85d 7b04 ldr.w r7, [sp], #4
8002ee4: 4770 bx lr
...
08002ee8 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8002ee8: b480 push {r7}
8002eea: b085 sub sp, #20
8002eec: af00 add r7, sp, #0
8002eee: 6078 str r0, [r7, #4]
8002ef0: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8002ef2: 687b ldr r3, [r7, #4]
8002ef4: 681b ldr r3, [r3, #0]
8002ef6: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8002ef8: 687b ldr r3, [r7, #4]
8002efa: 4a43 ldr r2, [pc, #268] @ (8003008 <TIM_Base_SetConfig+0x120>)
8002efc: 4293 cmp r3, r2
8002efe: d013 beq.n 8002f28 <TIM_Base_SetConfig+0x40>
8002f00: 687b ldr r3, [r7, #4]
8002f02: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8002f06: d00f beq.n 8002f28 <TIM_Base_SetConfig+0x40>
8002f08: 687b ldr r3, [r7, #4]
8002f0a: 4a40 ldr r2, [pc, #256] @ (800300c <TIM_Base_SetConfig+0x124>)
8002f0c: 4293 cmp r3, r2
8002f0e: d00b beq.n 8002f28 <TIM_Base_SetConfig+0x40>
8002f10: 687b ldr r3, [r7, #4]
8002f12: 4a3f ldr r2, [pc, #252] @ (8003010 <TIM_Base_SetConfig+0x128>)
8002f14: 4293 cmp r3, r2
8002f16: d007 beq.n 8002f28 <TIM_Base_SetConfig+0x40>
8002f18: 687b ldr r3, [r7, #4]
8002f1a: 4a3e ldr r2, [pc, #248] @ (8003014 <TIM_Base_SetConfig+0x12c>)
8002f1c: 4293 cmp r3, r2
8002f1e: d003 beq.n 8002f28 <TIM_Base_SetConfig+0x40>
8002f20: 687b ldr r3, [r7, #4]
8002f22: 4a3d ldr r2, [pc, #244] @ (8003018 <TIM_Base_SetConfig+0x130>)
8002f24: 4293 cmp r3, r2
8002f26: d108 bne.n 8002f3a <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8002f28: 68fb ldr r3, [r7, #12]
8002f2a: f023 0370 bic.w r3, r3, #112 @ 0x70
8002f2e: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8002f30: 683b ldr r3, [r7, #0]
8002f32: 685b ldr r3, [r3, #4]
8002f34: 68fa ldr r2, [r7, #12]
8002f36: 4313 orrs r3, r2
8002f38: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8002f3a: 687b ldr r3, [r7, #4]
8002f3c: 4a32 ldr r2, [pc, #200] @ (8003008 <TIM_Base_SetConfig+0x120>)
8002f3e: 4293 cmp r3, r2
8002f40: d02b beq.n 8002f9a <TIM_Base_SetConfig+0xb2>
8002f42: 687b ldr r3, [r7, #4]
8002f44: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8002f48: d027 beq.n 8002f9a <TIM_Base_SetConfig+0xb2>
8002f4a: 687b ldr r3, [r7, #4]
8002f4c: 4a2f ldr r2, [pc, #188] @ (800300c <TIM_Base_SetConfig+0x124>)
8002f4e: 4293 cmp r3, r2
8002f50: d023 beq.n 8002f9a <TIM_Base_SetConfig+0xb2>
8002f52: 687b ldr r3, [r7, #4]
8002f54: 4a2e ldr r2, [pc, #184] @ (8003010 <TIM_Base_SetConfig+0x128>)
8002f56: 4293 cmp r3, r2
8002f58: d01f beq.n 8002f9a <TIM_Base_SetConfig+0xb2>
8002f5a: 687b ldr r3, [r7, #4]
8002f5c: 4a2d ldr r2, [pc, #180] @ (8003014 <TIM_Base_SetConfig+0x12c>)
8002f5e: 4293 cmp r3, r2
8002f60: d01b beq.n 8002f9a <TIM_Base_SetConfig+0xb2>
8002f62: 687b ldr r3, [r7, #4]
8002f64: 4a2c ldr r2, [pc, #176] @ (8003018 <TIM_Base_SetConfig+0x130>)
8002f66: 4293 cmp r3, r2
8002f68: d017 beq.n 8002f9a <TIM_Base_SetConfig+0xb2>
8002f6a: 687b ldr r3, [r7, #4]
8002f6c: 4a2b ldr r2, [pc, #172] @ (800301c <TIM_Base_SetConfig+0x134>)
8002f6e: 4293 cmp r3, r2
8002f70: d013 beq.n 8002f9a <TIM_Base_SetConfig+0xb2>
8002f72: 687b ldr r3, [r7, #4]
8002f74: 4a2a ldr r2, [pc, #168] @ (8003020 <TIM_Base_SetConfig+0x138>)
8002f76: 4293 cmp r3, r2
8002f78: d00f beq.n 8002f9a <TIM_Base_SetConfig+0xb2>
8002f7a: 687b ldr r3, [r7, #4]
8002f7c: 4a29 ldr r2, [pc, #164] @ (8003024 <TIM_Base_SetConfig+0x13c>)
8002f7e: 4293 cmp r3, r2
8002f80: d00b beq.n 8002f9a <TIM_Base_SetConfig+0xb2>
8002f82: 687b ldr r3, [r7, #4]
8002f84: 4a28 ldr r2, [pc, #160] @ (8003028 <TIM_Base_SetConfig+0x140>)
8002f86: 4293 cmp r3, r2
8002f88: d007 beq.n 8002f9a <TIM_Base_SetConfig+0xb2>
8002f8a: 687b ldr r3, [r7, #4]
8002f8c: 4a27 ldr r2, [pc, #156] @ (800302c <TIM_Base_SetConfig+0x144>)
8002f8e: 4293 cmp r3, r2
8002f90: d003 beq.n 8002f9a <TIM_Base_SetConfig+0xb2>
8002f92: 687b ldr r3, [r7, #4]
8002f94: 4a26 ldr r2, [pc, #152] @ (8003030 <TIM_Base_SetConfig+0x148>)
8002f96: 4293 cmp r3, r2
8002f98: d108 bne.n 8002fac <TIM_Base_SetConfig+0xc4>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8002f9a: 68fb ldr r3, [r7, #12]
8002f9c: f423 7340 bic.w r3, r3, #768 @ 0x300
8002fa0: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8002fa2: 683b ldr r3, [r7, #0]
8002fa4: 68db ldr r3, [r3, #12]
8002fa6: 68fa ldr r2, [r7, #12]
8002fa8: 4313 orrs r3, r2
8002faa: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8002fac: 68fb ldr r3, [r7, #12]
8002fae: f023 0280 bic.w r2, r3, #128 @ 0x80
8002fb2: 683b ldr r3, [r7, #0]
8002fb4: 695b ldr r3, [r3, #20]
8002fb6: 4313 orrs r3, r2
8002fb8: 60fb str r3, [r7, #12]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8002fba: 683b ldr r3, [r7, #0]
8002fbc: 689a ldr r2, [r3, #8]
8002fbe: 687b ldr r3, [r7, #4]
8002fc0: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8002fc2: 683b ldr r3, [r7, #0]
8002fc4: 681a ldr r2, [r3, #0]
8002fc6: 687b ldr r3, [r7, #4]
8002fc8: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8002fca: 687b ldr r3, [r7, #4]
8002fcc: 4a0e ldr r2, [pc, #56] @ (8003008 <TIM_Base_SetConfig+0x120>)
8002fce: 4293 cmp r3, r2
8002fd0: d003 beq.n 8002fda <TIM_Base_SetConfig+0xf2>
8002fd2: 687b ldr r3, [r7, #4]
8002fd4: 4a10 ldr r2, [pc, #64] @ (8003018 <TIM_Base_SetConfig+0x130>)
8002fd6: 4293 cmp r3, r2
8002fd8: d103 bne.n 8002fe2 <TIM_Base_SetConfig+0xfa>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8002fda: 683b ldr r3, [r7, #0]
8002fdc: 691a ldr r2, [r3, #16]
8002fde: 687b ldr r3, [r7, #4]
8002fe0: 631a str r2, [r3, #48] @ 0x30
}
/* Disable Update Event (UEV) with Update Generation (UG)
by changing Update Request Source (URS) to avoid Update flag (UIF) */
SET_BIT(TIMx->CR1, TIM_CR1_URS);
8002fe2: 687b ldr r3, [r7, #4]
8002fe4: 681b ldr r3, [r3, #0]
8002fe6: f043 0204 orr.w r2, r3, #4
8002fea: 687b ldr r3, [r7, #4]
8002fec: 601a str r2, [r3, #0]
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8002fee: 687b ldr r3, [r7, #4]
8002ff0: 2201 movs r2, #1
8002ff2: 615a str r2, [r3, #20]
TIMx->CR1 = tmpcr1;
8002ff4: 687b ldr r3, [r7, #4]
8002ff6: 68fa ldr r2, [r7, #12]
8002ff8: 601a str r2, [r3, #0]
}
8002ffa: bf00 nop
8002ffc: 3714 adds r7, #20
8002ffe: 46bd mov sp, r7
8003000: f85d 7b04 ldr.w r7, [sp], #4
8003004: 4770 bx lr
8003006: bf00 nop
8003008: 40010000 .word 0x40010000
800300c: 40000400 .word 0x40000400
8003010: 40000800 .word 0x40000800
8003014: 40000c00 .word 0x40000c00
8003018: 40010400 .word 0x40010400
800301c: 40014000 .word 0x40014000
8003020: 40014400 .word 0x40014400
8003024: 40014800 .word 0x40014800
8003028: 40001800 .word 0x40001800
800302c: 40001c00 .word 0x40001c00
8003030: 40002000 .word 0x40002000
08003034 <HAL_TIMEx_CommutCallback>:
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8003034: b480 push {r7}
8003036: b083 sub sp, #12
8003038: af00 add r7, sp, #0
800303a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
800303c: bf00 nop
800303e: 370c adds r7, #12
8003040: 46bd mov sp, r7
8003042: f85d 7b04 ldr.w r7, [sp], #4
8003046: 4770 bx lr
08003048 <HAL_TIMEx_BreakCallback>:
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8003048: b480 push {r7}
800304a: b083 sub sp, #12
800304c: af00 add r7, sp, #0
800304e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
8003050: bf00 nop
8003052: 370c adds r7, #12
8003054: 46bd mov sp, r7
8003056: f85d 7b04 ldr.w r7, [sp], #4
800305a: 4770 bx lr
0800305c <HAL_TIMEx_Break2Callback>:
* @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
800305c: b480 push {r7}
800305e: b083 sub sp, #12
8003060: af00 add r7, sp, #0
8003062: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
8003064: bf00 nop
8003066: 370c adds r7, #12
8003068: 46bd mov sp, r7
800306a: f85d 7b04 ldr.w r7, [sp], #4
800306e: 4770 bx lr
08003070 <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8003070: b580 push {r7, lr}
8003072: b082 sub sp, #8
8003074: af00 add r7, sp, #0
8003076: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8003078: 687b ldr r3, [r7, #4]
800307a: 2b00 cmp r3, #0
800307c: d101 bne.n 8003082 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
800307e: 2301 movs r3, #1
8003080: e040 b.n 8003104 <HAL_UART_Init+0x94>
{
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
}
if (huart->gState == HAL_UART_STATE_RESET)
8003082: 687b ldr r3, [r7, #4]
8003084: 6fdb ldr r3, [r3, #124] @ 0x7c
8003086: 2b00 cmp r3, #0
8003088: d106 bne.n 8003098 <HAL_UART_Init+0x28>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
800308a: 687b ldr r3, [r7, #4]
800308c: 2200 movs r2, #0
800308e: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8003092: 6878 ldr r0, [r7, #4]
8003094: f7fd ffec bl 8001070 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8003098: 687b ldr r3, [r7, #4]
800309a: 2224 movs r2, #36 @ 0x24
800309c: 67da str r2, [r3, #124] @ 0x7c
__HAL_UART_DISABLE(huart);
800309e: 687b ldr r3, [r7, #4]
80030a0: 681b ldr r3, [r3, #0]
80030a2: 681a ldr r2, [r3, #0]
80030a4: 687b ldr r3, [r7, #4]
80030a6: 681b ldr r3, [r3, #0]
80030a8: f022 0201 bic.w r2, r2, #1
80030ac: 601a str r2, [r3, #0]
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
80030ae: 687b ldr r3, [r7, #4]
80030b0: 6a5b ldr r3, [r3, #36] @ 0x24
80030b2: 2b00 cmp r3, #0
80030b4: d002 beq.n 80030bc <HAL_UART_Init+0x4c>
{
UART_AdvFeatureConfig(huart);
80030b6: 6878 ldr r0, [r7, #4]
80030b8: f000 fb16 bl 80036e8 <UART_AdvFeatureConfig>
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
80030bc: 6878 ldr r0, [r7, #4]
80030be: f000 f8af bl 8003220 <UART_SetConfig>
80030c2: 4603 mov r3, r0
80030c4: 2b01 cmp r3, #1
80030c6: d101 bne.n 80030cc <HAL_UART_Init+0x5c>
{
return HAL_ERROR;
80030c8: 2301 movs r3, #1
80030ca: e01b b.n 8003104 <HAL_UART_Init+0x94>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
80030cc: 687b ldr r3, [r7, #4]
80030ce: 681b ldr r3, [r3, #0]
80030d0: 685a ldr r2, [r3, #4]
80030d2: 687b ldr r3, [r7, #4]
80030d4: 681b ldr r3, [r3, #0]
80030d6: f422 4290 bic.w r2, r2, #18432 @ 0x4800
80030da: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
80030dc: 687b ldr r3, [r7, #4]
80030de: 681b ldr r3, [r3, #0]
80030e0: 689a ldr r2, [r3, #8]
80030e2: 687b ldr r3, [r7, #4]
80030e4: 681b ldr r3, [r3, #0]
80030e6: f022 022a bic.w r2, r2, #42 @ 0x2a
80030ea: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
80030ec: 687b ldr r3, [r7, #4]
80030ee: 681b ldr r3, [r3, #0]
80030f0: 681a ldr r2, [r3, #0]
80030f2: 687b ldr r3, [r7, #4]
80030f4: 681b ldr r3, [r3, #0]
80030f6: f042 0201 orr.w r2, r2, #1
80030fa: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
80030fc: 6878 ldr r0, [r7, #4]
80030fe: f000 fb95 bl 800382c <UART_CheckIdleState>
8003102: 4603 mov r3, r0
}
8003104: 4618 mov r0, r3
8003106: 3708 adds r7, #8
8003108: 46bd mov sp, r7
800310a: bd80 pop {r7, pc}
0800310c <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
800310c: b580 push {r7, lr}
800310e: b08a sub sp, #40 @ 0x28
8003110: af02 add r7, sp, #8
8003112: 60f8 str r0, [r7, #12]
8003114: 60b9 str r1, [r7, #8]
8003116: 603b str r3, [r7, #0]
8003118: 4613 mov r3, r2
800311a: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
800311c: 68fb ldr r3, [r7, #12]
800311e: 6fdb ldr r3, [r3, #124] @ 0x7c
8003120: 2b20 cmp r3, #32
8003122: d177 bne.n 8003214 <HAL_UART_Transmit+0x108>
{
if ((pData == NULL) || (Size == 0U))
8003124: 68bb ldr r3, [r7, #8]
8003126: 2b00 cmp r3, #0
8003128: d002 beq.n 8003130 <HAL_UART_Transmit+0x24>
800312a: 88fb ldrh r3, [r7, #6]
800312c: 2b00 cmp r3, #0
800312e: d101 bne.n 8003134 <HAL_UART_Transmit+0x28>
{
return HAL_ERROR;
8003130: 2301 movs r3, #1
8003132: e070 b.n 8003216 <HAL_UART_Transmit+0x10a>
}
huart->ErrorCode = HAL_UART_ERROR_NONE;
8003134: 68fb ldr r3, [r7, #12]
8003136: 2200 movs r2, #0
8003138: f8c3 2084 str.w r2, [r3, #132] @ 0x84
huart->gState = HAL_UART_STATE_BUSY_TX;
800313c: 68fb ldr r3, [r7, #12]
800313e: 2221 movs r2, #33 @ 0x21
8003140: 67da str r2, [r3, #124] @ 0x7c
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8003142: f7fe f98b bl 800145c <HAL_GetTick>
8003146: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
8003148: 68fb ldr r3, [r7, #12]
800314a: 88fa ldrh r2, [r7, #6]
800314c: f8a3 2050 strh.w r2, [r3, #80] @ 0x50
huart->TxXferCount = Size;
8003150: 68fb ldr r3, [r7, #12]
8003152: 88fa ldrh r2, [r7, #6]
8003154: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8003158: 68fb ldr r3, [r7, #12]
800315a: 689b ldr r3, [r3, #8]
800315c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8003160: d108 bne.n 8003174 <HAL_UART_Transmit+0x68>
8003162: 68fb ldr r3, [r7, #12]
8003164: 691b ldr r3, [r3, #16]
8003166: 2b00 cmp r3, #0
8003168: d104 bne.n 8003174 <HAL_UART_Transmit+0x68>
{
pdata8bits = NULL;
800316a: 2300 movs r3, #0
800316c: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
800316e: 68bb ldr r3, [r7, #8]
8003170: 61bb str r3, [r7, #24]
8003172: e003 b.n 800317c <HAL_UART_Transmit+0x70>
}
else
{
pdata8bits = pData;
8003174: 68bb ldr r3, [r7, #8]
8003176: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8003178: 2300 movs r3, #0
800317a: 61bb str r3, [r7, #24]
}
while (huart->TxXferCount > 0U)
800317c: e02f b.n 80031de <HAL_UART_Transmit+0xd2>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
800317e: 683b ldr r3, [r7, #0]
8003180: 9300 str r3, [sp, #0]
8003182: 697b ldr r3, [r7, #20]
8003184: 2200 movs r2, #0
8003186: 2180 movs r1, #128 @ 0x80
8003188: 68f8 ldr r0, [r7, #12]
800318a: f000 fba6 bl 80038da <UART_WaitOnFlagUntilTimeout>
800318e: 4603 mov r3, r0
8003190: 2b00 cmp r3, #0
8003192: d004 beq.n 800319e <HAL_UART_Transmit+0x92>
{
huart->gState = HAL_UART_STATE_READY;
8003194: 68fb ldr r3, [r7, #12]
8003196: 2220 movs r2, #32
8003198: 67da str r2, [r3, #124] @ 0x7c
return HAL_TIMEOUT;
800319a: 2303 movs r3, #3
800319c: e03b b.n 8003216 <HAL_UART_Transmit+0x10a>
}
if (pdata8bits == NULL)
800319e: 69fb ldr r3, [r7, #28]
80031a0: 2b00 cmp r3, #0
80031a2: d10b bne.n 80031bc <HAL_UART_Transmit+0xb0>
{
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
80031a4: 69bb ldr r3, [r7, #24]
80031a6: 881b ldrh r3, [r3, #0]
80031a8: 461a mov r2, r3
80031aa: 68fb ldr r3, [r7, #12]
80031ac: 681b ldr r3, [r3, #0]
80031ae: f3c2 0208 ubfx r2, r2, #0, #9
80031b2: 629a str r2, [r3, #40] @ 0x28
pdata16bits++;
80031b4: 69bb ldr r3, [r7, #24]
80031b6: 3302 adds r3, #2
80031b8: 61bb str r3, [r7, #24]
80031ba: e007 b.n 80031cc <HAL_UART_Transmit+0xc0>
}
else
{
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
80031bc: 69fb ldr r3, [r7, #28]
80031be: 781a ldrb r2, [r3, #0]
80031c0: 68fb ldr r3, [r7, #12]
80031c2: 681b ldr r3, [r3, #0]
80031c4: 629a str r2, [r3, #40] @ 0x28
pdata8bits++;
80031c6: 69fb ldr r3, [r7, #28]
80031c8: 3301 adds r3, #1
80031ca: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
80031cc: 68fb ldr r3, [r7, #12]
80031ce: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
80031d2: b29b uxth r3, r3
80031d4: 3b01 subs r3, #1
80031d6: b29a uxth r2, r3
80031d8: 68fb ldr r3, [r7, #12]
80031da: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
while (huart->TxXferCount > 0U)
80031de: 68fb ldr r3, [r7, #12]
80031e0: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
80031e4: b29b uxth r3, r3
80031e6: 2b00 cmp r3, #0
80031e8: d1c9 bne.n 800317e <HAL_UART_Transmit+0x72>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
80031ea: 683b ldr r3, [r7, #0]
80031ec: 9300 str r3, [sp, #0]
80031ee: 697b ldr r3, [r7, #20]
80031f0: 2200 movs r2, #0
80031f2: 2140 movs r1, #64 @ 0x40
80031f4: 68f8 ldr r0, [r7, #12]
80031f6: f000 fb70 bl 80038da <UART_WaitOnFlagUntilTimeout>
80031fa: 4603 mov r3, r0
80031fc: 2b00 cmp r3, #0
80031fe: d004 beq.n 800320a <HAL_UART_Transmit+0xfe>
{
huart->gState = HAL_UART_STATE_READY;
8003200: 68fb ldr r3, [r7, #12]
8003202: 2220 movs r2, #32
8003204: 67da str r2, [r3, #124] @ 0x7c
return HAL_TIMEOUT;
8003206: 2303 movs r3, #3
8003208: e005 b.n 8003216 <HAL_UART_Transmit+0x10a>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
800320a: 68fb ldr r3, [r7, #12]
800320c: 2220 movs r2, #32
800320e: 67da str r2, [r3, #124] @ 0x7c
return HAL_OK;
8003210: 2300 movs r3, #0
8003212: e000 b.n 8003216 <HAL_UART_Transmit+0x10a>
}
else
{
return HAL_BUSY;
8003214: 2302 movs r3, #2
}
}
8003216: 4618 mov r0, r3
8003218: 3720 adds r7, #32
800321a: 46bd mov sp, r7
800321c: bd80 pop {r7, pc}
...
08003220 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8003220: b580 push {r7, lr}
8003222: b088 sub sp, #32
8003224: af00 add r7, sp, #0
8003226: 6078 str r0, [r7, #4]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
8003228: 2300 movs r3, #0
800322a: 77bb strb r3, [r7, #30]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
800322c: 687b ldr r3, [r7, #4]
800322e: 689a ldr r2, [r3, #8]
8003230: 687b ldr r3, [r7, #4]
8003232: 691b ldr r3, [r3, #16]
8003234: 431a orrs r2, r3
8003236: 687b ldr r3, [r7, #4]
8003238: 695b ldr r3, [r3, #20]
800323a: 431a orrs r2, r3
800323c: 687b ldr r3, [r7, #4]
800323e: 69db ldr r3, [r3, #28]
8003240: 4313 orrs r3, r2
8003242: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8003244: 687b ldr r3, [r7, #4]
8003246: 681b ldr r3, [r3, #0]
8003248: 681a ldr r2, [r3, #0]
800324a: 4ba6 ldr r3, [pc, #664] @ (80034e4 <UART_SetConfig+0x2c4>)
800324c: 4013 ands r3, r2
800324e: 687a ldr r2, [r7, #4]
8003250: 6812 ldr r2, [r2, #0]
8003252: 6979 ldr r1, [r7, #20]
8003254: 430b orrs r3, r1
8003256: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8003258: 687b ldr r3, [r7, #4]
800325a: 681b ldr r3, [r3, #0]
800325c: 685b ldr r3, [r3, #4]
800325e: f423 5140 bic.w r1, r3, #12288 @ 0x3000
8003262: 687b ldr r3, [r7, #4]
8003264: 68da ldr r2, [r3, #12]
8003266: 687b ldr r3, [r7, #4]
8003268: 681b ldr r3, [r3, #0]
800326a: 430a orrs r2, r1
800326c: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
800326e: 687b ldr r3, [r7, #4]
8003270: 699b ldr r3, [r3, #24]
8003272: 617b str r3, [r7, #20]
tmpreg |= huart->Init.OneBitSampling;
8003274: 687b ldr r3, [r7, #4]
8003276: 6a1b ldr r3, [r3, #32]
8003278: 697a ldr r2, [r7, #20]
800327a: 4313 orrs r3, r2
800327c: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
800327e: 687b ldr r3, [r7, #4]
8003280: 681b ldr r3, [r3, #0]
8003282: 689b ldr r3, [r3, #8]
8003284: f423 6130 bic.w r1, r3, #2816 @ 0xb00
8003288: 687b ldr r3, [r7, #4]
800328a: 681b ldr r3, [r3, #0]
800328c: 697a ldr r2, [r7, #20]
800328e: 430a orrs r2, r1
8003290: 609a str r2, [r3, #8]
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
8003292: 687b ldr r3, [r7, #4]
8003294: 681b ldr r3, [r3, #0]
8003296: 4a94 ldr r2, [pc, #592] @ (80034e8 <UART_SetConfig+0x2c8>)
8003298: 4293 cmp r3, r2
800329a: d120 bne.n 80032de <UART_SetConfig+0xbe>
800329c: 4b93 ldr r3, [pc, #588] @ (80034ec <UART_SetConfig+0x2cc>)
800329e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80032a2: f003 0303 and.w r3, r3, #3
80032a6: 2b03 cmp r3, #3
80032a8: d816 bhi.n 80032d8 <UART_SetConfig+0xb8>
80032aa: a201 add r2, pc, #4 @ (adr r2, 80032b0 <UART_SetConfig+0x90>)
80032ac: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80032b0: 080032c1 .word 0x080032c1
80032b4: 080032cd .word 0x080032cd
80032b8: 080032c7 .word 0x080032c7
80032bc: 080032d3 .word 0x080032d3
80032c0: 2301 movs r3, #1
80032c2: 77fb strb r3, [r7, #31]
80032c4: e150 b.n 8003568 <UART_SetConfig+0x348>
80032c6: 2302 movs r3, #2
80032c8: 77fb strb r3, [r7, #31]
80032ca: e14d b.n 8003568 <UART_SetConfig+0x348>
80032cc: 2304 movs r3, #4
80032ce: 77fb strb r3, [r7, #31]
80032d0: e14a b.n 8003568 <UART_SetConfig+0x348>
80032d2: 2308 movs r3, #8
80032d4: 77fb strb r3, [r7, #31]
80032d6: e147 b.n 8003568 <UART_SetConfig+0x348>
80032d8: 2310 movs r3, #16
80032da: 77fb strb r3, [r7, #31]
80032dc: e144 b.n 8003568 <UART_SetConfig+0x348>
80032de: 687b ldr r3, [r7, #4]
80032e0: 681b ldr r3, [r3, #0]
80032e2: 4a83 ldr r2, [pc, #524] @ (80034f0 <UART_SetConfig+0x2d0>)
80032e4: 4293 cmp r3, r2
80032e6: d132 bne.n 800334e <UART_SetConfig+0x12e>
80032e8: 4b80 ldr r3, [pc, #512] @ (80034ec <UART_SetConfig+0x2cc>)
80032ea: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80032ee: f003 030c and.w r3, r3, #12
80032f2: 2b0c cmp r3, #12
80032f4: d828 bhi.n 8003348 <UART_SetConfig+0x128>
80032f6: a201 add r2, pc, #4 @ (adr r2, 80032fc <UART_SetConfig+0xdc>)
80032f8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80032fc: 08003331 .word 0x08003331
8003300: 08003349 .word 0x08003349
8003304: 08003349 .word 0x08003349
8003308: 08003349 .word 0x08003349
800330c: 0800333d .word 0x0800333d
8003310: 08003349 .word 0x08003349
8003314: 08003349 .word 0x08003349
8003318: 08003349 .word 0x08003349
800331c: 08003337 .word 0x08003337
8003320: 08003349 .word 0x08003349
8003324: 08003349 .word 0x08003349
8003328: 08003349 .word 0x08003349
800332c: 08003343 .word 0x08003343
8003330: 2300 movs r3, #0
8003332: 77fb strb r3, [r7, #31]
8003334: e118 b.n 8003568 <UART_SetConfig+0x348>
8003336: 2302 movs r3, #2
8003338: 77fb strb r3, [r7, #31]
800333a: e115 b.n 8003568 <UART_SetConfig+0x348>
800333c: 2304 movs r3, #4
800333e: 77fb strb r3, [r7, #31]
8003340: e112 b.n 8003568 <UART_SetConfig+0x348>
8003342: 2308 movs r3, #8
8003344: 77fb strb r3, [r7, #31]
8003346: e10f b.n 8003568 <UART_SetConfig+0x348>
8003348: 2310 movs r3, #16
800334a: 77fb strb r3, [r7, #31]
800334c: e10c b.n 8003568 <UART_SetConfig+0x348>
800334e: 687b ldr r3, [r7, #4]
8003350: 681b ldr r3, [r3, #0]
8003352: 4a68 ldr r2, [pc, #416] @ (80034f4 <UART_SetConfig+0x2d4>)
8003354: 4293 cmp r3, r2
8003356: d120 bne.n 800339a <UART_SetConfig+0x17a>
8003358: 4b64 ldr r3, [pc, #400] @ (80034ec <UART_SetConfig+0x2cc>)
800335a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800335e: f003 0330 and.w r3, r3, #48 @ 0x30
8003362: 2b30 cmp r3, #48 @ 0x30
8003364: d013 beq.n 800338e <UART_SetConfig+0x16e>
8003366: 2b30 cmp r3, #48 @ 0x30
8003368: d814 bhi.n 8003394 <UART_SetConfig+0x174>
800336a: 2b20 cmp r3, #32
800336c: d009 beq.n 8003382 <UART_SetConfig+0x162>
800336e: 2b20 cmp r3, #32
8003370: d810 bhi.n 8003394 <UART_SetConfig+0x174>
8003372: 2b00 cmp r3, #0
8003374: d002 beq.n 800337c <UART_SetConfig+0x15c>
8003376: 2b10 cmp r3, #16
8003378: d006 beq.n 8003388 <UART_SetConfig+0x168>
800337a: e00b b.n 8003394 <UART_SetConfig+0x174>
800337c: 2300 movs r3, #0
800337e: 77fb strb r3, [r7, #31]
8003380: e0f2 b.n 8003568 <UART_SetConfig+0x348>
8003382: 2302 movs r3, #2
8003384: 77fb strb r3, [r7, #31]
8003386: e0ef b.n 8003568 <UART_SetConfig+0x348>
8003388: 2304 movs r3, #4
800338a: 77fb strb r3, [r7, #31]
800338c: e0ec b.n 8003568 <UART_SetConfig+0x348>
800338e: 2308 movs r3, #8
8003390: 77fb strb r3, [r7, #31]
8003392: e0e9 b.n 8003568 <UART_SetConfig+0x348>
8003394: 2310 movs r3, #16
8003396: 77fb strb r3, [r7, #31]
8003398: e0e6 b.n 8003568 <UART_SetConfig+0x348>
800339a: 687b ldr r3, [r7, #4]
800339c: 681b ldr r3, [r3, #0]
800339e: 4a56 ldr r2, [pc, #344] @ (80034f8 <UART_SetConfig+0x2d8>)
80033a0: 4293 cmp r3, r2
80033a2: d120 bne.n 80033e6 <UART_SetConfig+0x1c6>
80033a4: 4b51 ldr r3, [pc, #324] @ (80034ec <UART_SetConfig+0x2cc>)
80033a6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80033aa: f003 03c0 and.w r3, r3, #192 @ 0xc0
80033ae: 2bc0 cmp r3, #192 @ 0xc0
80033b0: d013 beq.n 80033da <UART_SetConfig+0x1ba>
80033b2: 2bc0 cmp r3, #192 @ 0xc0
80033b4: d814 bhi.n 80033e0 <UART_SetConfig+0x1c0>
80033b6: 2b80 cmp r3, #128 @ 0x80
80033b8: d009 beq.n 80033ce <UART_SetConfig+0x1ae>
80033ba: 2b80 cmp r3, #128 @ 0x80
80033bc: d810 bhi.n 80033e0 <UART_SetConfig+0x1c0>
80033be: 2b00 cmp r3, #0
80033c0: d002 beq.n 80033c8 <UART_SetConfig+0x1a8>
80033c2: 2b40 cmp r3, #64 @ 0x40
80033c4: d006 beq.n 80033d4 <UART_SetConfig+0x1b4>
80033c6: e00b b.n 80033e0 <UART_SetConfig+0x1c0>
80033c8: 2300 movs r3, #0
80033ca: 77fb strb r3, [r7, #31]
80033cc: e0cc b.n 8003568 <UART_SetConfig+0x348>
80033ce: 2302 movs r3, #2
80033d0: 77fb strb r3, [r7, #31]
80033d2: e0c9 b.n 8003568 <UART_SetConfig+0x348>
80033d4: 2304 movs r3, #4
80033d6: 77fb strb r3, [r7, #31]
80033d8: e0c6 b.n 8003568 <UART_SetConfig+0x348>
80033da: 2308 movs r3, #8
80033dc: 77fb strb r3, [r7, #31]
80033de: e0c3 b.n 8003568 <UART_SetConfig+0x348>
80033e0: 2310 movs r3, #16
80033e2: 77fb strb r3, [r7, #31]
80033e4: e0c0 b.n 8003568 <UART_SetConfig+0x348>
80033e6: 687b ldr r3, [r7, #4]
80033e8: 681b ldr r3, [r3, #0]
80033ea: 4a44 ldr r2, [pc, #272] @ (80034fc <UART_SetConfig+0x2dc>)
80033ec: 4293 cmp r3, r2
80033ee: d125 bne.n 800343c <UART_SetConfig+0x21c>
80033f0: 4b3e ldr r3, [pc, #248] @ (80034ec <UART_SetConfig+0x2cc>)
80033f2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80033f6: f403 7340 and.w r3, r3, #768 @ 0x300
80033fa: f5b3 7f40 cmp.w r3, #768 @ 0x300
80033fe: d017 beq.n 8003430 <UART_SetConfig+0x210>
8003400: f5b3 7f40 cmp.w r3, #768 @ 0x300
8003404: d817 bhi.n 8003436 <UART_SetConfig+0x216>
8003406: f5b3 7f00 cmp.w r3, #512 @ 0x200
800340a: d00b beq.n 8003424 <UART_SetConfig+0x204>
800340c: f5b3 7f00 cmp.w r3, #512 @ 0x200
8003410: d811 bhi.n 8003436 <UART_SetConfig+0x216>
8003412: 2b00 cmp r3, #0
8003414: d003 beq.n 800341e <UART_SetConfig+0x1fe>
8003416: f5b3 7f80 cmp.w r3, #256 @ 0x100
800341a: d006 beq.n 800342a <UART_SetConfig+0x20a>
800341c: e00b b.n 8003436 <UART_SetConfig+0x216>
800341e: 2300 movs r3, #0
8003420: 77fb strb r3, [r7, #31]
8003422: e0a1 b.n 8003568 <UART_SetConfig+0x348>
8003424: 2302 movs r3, #2
8003426: 77fb strb r3, [r7, #31]
8003428: e09e b.n 8003568 <UART_SetConfig+0x348>
800342a: 2304 movs r3, #4
800342c: 77fb strb r3, [r7, #31]
800342e: e09b b.n 8003568 <UART_SetConfig+0x348>
8003430: 2308 movs r3, #8
8003432: 77fb strb r3, [r7, #31]
8003434: e098 b.n 8003568 <UART_SetConfig+0x348>
8003436: 2310 movs r3, #16
8003438: 77fb strb r3, [r7, #31]
800343a: e095 b.n 8003568 <UART_SetConfig+0x348>
800343c: 687b ldr r3, [r7, #4]
800343e: 681b ldr r3, [r3, #0]
8003440: 4a2f ldr r2, [pc, #188] @ (8003500 <UART_SetConfig+0x2e0>)
8003442: 4293 cmp r3, r2
8003444: d125 bne.n 8003492 <UART_SetConfig+0x272>
8003446: 4b29 ldr r3, [pc, #164] @ (80034ec <UART_SetConfig+0x2cc>)
8003448: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800344c: f403 6340 and.w r3, r3, #3072 @ 0xc00
8003450: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
8003454: d017 beq.n 8003486 <UART_SetConfig+0x266>
8003456: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
800345a: d817 bhi.n 800348c <UART_SetConfig+0x26c>
800345c: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8003460: d00b beq.n 800347a <UART_SetConfig+0x25a>
8003462: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8003466: d811 bhi.n 800348c <UART_SetConfig+0x26c>
8003468: 2b00 cmp r3, #0
800346a: d003 beq.n 8003474 <UART_SetConfig+0x254>
800346c: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003470: d006 beq.n 8003480 <UART_SetConfig+0x260>
8003472: e00b b.n 800348c <UART_SetConfig+0x26c>
8003474: 2301 movs r3, #1
8003476: 77fb strb r3, [r7, #31]
8003478: e076 b.n 8003568 <UART_SetConfig+0x348>
800347a: 2302 movs r3, #2
800347c: 77fb strb r3, [r7, #31]
800347e: e073 b.n 8003568 <UART_SetConfig+0x348>
8003480: 2304 movs r3, #4
8003482: 77fb strb r3, [r7, #31]
8003484: e070 b.n 8003568 <UART_SetConfig+0x348>
8003486: 2308 movs r3, #8
8003488: 77fb strb r3, [r7, #31]
800348a: e06d b.n 8003568 <UART_SetConfig+0x348>
800348c: 2310 movs r3, #16
800348e: 77fb strb r3, [r7, #31]
8003490: e06a b.n 8003568 <UART_SetConfig+0x348>
8003492: 687b ldr r3, [r7, #4]
8003494: 681b ldr r3, [r3, #0]
8003496: 4a1b ldr r2, [pc, #108] @ (8003504 <UART_SetConfig+0x2e4>)
8003498: 4293 cmp r3, r2
800349a: d138 bne.n 800350e <UART_SetConfig+0x2ee>
800349c: 4b13 ldr r3, [pc, #76] @ (80034ec <UART_SetConfig+0x2cc>)
800349e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80034a2: f403 5340 and.w r3, r3, #12288 @ 0x3000
80034a6: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
80034aa: d017 beq.n 80034dc <UART_SetConfig+0x2bc>
80034ac: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
80034b0: d82a bhi.n 8003508 <UART_SetConfig+0x2e8>
80034b2: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80034b6: d00b beq.n 80034d0 <UART_SetConfig+0x2b0>
80034b8: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80034bc: d824 bhi.n 8003508 <UART_SetConfig+0x2e8>
80034be: 2b00 cmp r3, #0
80034c0: d003 beq.n 80034ca <UART_SetConfig+0x2aa>
80034c2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80034c6: d006 beq.n 80034d6 <UART_SetConfig+0x2b6>
80034c8: e01e b.n 8003508 <UART_SetConfig+0x2e8>
80034ca: 2300 movs r3, #0
80034cc: 77fb strb r3, [r7, #31]
80034ce: e04b b.n 8003568 <UART_SetConfig+0x348>
80034d0: 2302 movs r3, #2
80034d2: 77fb strb r3, [r7, #31]
80034d4: e048 b.n 8003568 <UART_SetConfig+0x348>
80034d6: 2304 movs r3, #4
80034d8: 77fb strb r3, [r7, #31]
80034da: e045 b.n 8003568 <UART_SetConfig+0x348>
80034dc: 2308 movs r3, #8
80034de: 77fb strb r3, [r7, #31]
80034e0: e042 b.n 8003568 <UART_SetConfig+0x348>
80034e2: bf00 nop
80034e4: efff69f3 .word 0xefff69f3
80034e8: 40011000 .word 0x40011000
80034ec: 40023800 .word 0x40023800
80034f0: 40004400 .word 0x40004400
80034f4: 40004800 .word 0x40004800
80034f8: 40004c00 .word 0x40004c00
80034fc: 40005000 .word 0x40005000
8003500: 40011400 .word 0x40011400
8003504: 40007800 .word 0x40007800
8003508: 2310 movs r3, #16
800350a: 77fb strb r3, [r7, #31]
800350c: e02c b.n 8003568 <UART_SetConfig+0x348>
800350e: 687b ldr r3, [r7, #4]
8003510: 681b ldr r3, [r3, #0]
8003512: 4a72 ldr r2, [pc, #456] @ (80036dc <UART_SetConfig+0x4bc>)
8003514: 4293 cmp r3, r2
8003516: d125 bne.n 8003564 <UART_SetConfig+0x344>
8003518: 4b71 ldr r3, [pc, #452] @ (80036e0 <UART_SetConfig+0x4c0>)
800351a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800351e: f403 4340 and.w r3, r3, #49152 @ 0xc000
8003522: f5b3 4f40 cmp.w r3, #49152 @ 0xc000
8003526: d017 beq.n 8003558 <UART_SetConfig+0x338>
8003528: f5b3 4f40 cmp.w r3, #49152 @ 0xc000
800352c: d817 bhi.n 800355e <UART_SetConfig+0x33e>
800352e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8003532: d00b beq.n 800354c <UART_SetConfig+0x32c>
8003534: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8003538: d811 bhi.n 800355e <UART_SetConfig+0x33e>
800353a: 2b00 cmp r3, #0
800353c: d003 beq.n 8003546 <UART_SetConfig+0x326>
800353e: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
8003542: d006 beq.n 8003552 <UART_SetConfig+0x332>
8003544: e00b b.n 800355e <UART_SetConfig+0x33e>
8003546: 2300 movs r3, #0
8003548: 77fb strb r3, [r7, #31]
800354a: e00d b.n 8003568 <UART_SetConfig+0x348>
800354c: 2302 movs r3, #2
800354e: 77fb strb r3, [r7, #31]
8003550: e00a b.n 8003568 <UART_SetConfig+0x348>
8003552: 2304 movs r3, #4
8003554: 77fb strb r3, [r7, #31]
8003556: e007 b.n 8003568 <UART_SetConfig+0x348>
8003558: 2308 movs r3, #8
800355a: 77fb strb r3, [r7, #31]
800355c: e004 b.n 8003568 <UART_SetConfig+0x348>
800355e: 2310 movs r3, #16
8003560: 77fb strb r3, [r7, #31]
8003562: e001 b.n 8003568 <UART_SetConfig+0x348>
8003564: 2310 movs r3, #16
8003566: 77fb strb r3, [r7, #31]
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8003568: 687b ldr r3, [r7, #4]
800356a: 69db ldr r3, [r3, #28]
800356c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8003570: d15b bne.n 800362a <UART_SetConfig+0x40a>
{
switch (clocksource)
8003572: 7ffb ldrb r3, [r7, #31]
8003574: 2b08 cmp r3, #8
8003576: d828 bhi.n 80035ca <UART_SetConfig+0x3aa>
8003578: a201 add r2, pc, #4 @ (adr r2, 8003580 <UART_SetConfig+0x360>)
800357a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800357e: bf00 nop
8003580: 080035a5 .word 0x080035a5
8003584: 080035ad .word 0x080035ad
8003588: 080035b5 .word 0x080035b5
800358c: 080035cb .word 0x080035cb
8003590: 080035bb .word 0x080035bb
8003594: 080035cb .word 0x080035cb
8003598: 080035cb .word 0x080035cb
800359c: 080035cb .word 0x080035cb
80035a0: 080035c3 .word 0x080035c3
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
80035a4: f7fe fef2 bl 800238c <HAL_RCC_GetPCLK1Freq>
80035a8: 61b8 str r0, [r7, #24]
break;
80035aa: e013 b.n 80035d4 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
80035ac: f7fe ff02 bl 80023b4 <HAL_RCC_GetPCLK2Freq>
80035b0: 61b8 str r0, [r7, #24]
break;
80035b2: e00f b.n 80035d4 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
80035b4: 4b4b ldr r3, [pc, #300] @ (80036e4 <UART_SetConfig+0x4c4>)
80035b6: 61bb str r3, [r7, #24]
break;
80035b8: e00c b.n 80035d4 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80035ba: f7fe fe15 bl 80021e8 <HAL_RCC_GetSysClockFreq>
80035be: 61b8 str r0, [r7, #24]
break;
80035c0: e008 b.n 80035d4 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
80035c2: f44f 4300 mov.w r3, #32768 @ 0x8000
80035c6: 61bb str r3, [r7, #24]
break;
80035c8: e004 b.n 80035d4 <UART_SetConfig+0x3b4>
default:
pclk = 0U;
80035ca: 2300 movs r3, #0
80035cc: 61bb str r3, [r7, #24]
ret = HAL_ERROR;
80035ce: 2301 movs r3, #1
80035d0: 77bb strb r3, [r7, #30]
break;
80035d2: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
80035d4: 69bb ldr r3, [r7, #24]
80035d6: 2b00 cmp r3, #0
80035d8: d074 beq.n 80036c4 <UART_SetConfig+0x4a4>
{
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
80035da: 69bb ldr r3, [r7, #24]
80035dc: 005a lsls r2, r3, #1
80035de: 687b ldr r3, [r7, #4]
80035e0: 685b ldr r3, [r3, #4]
80035e2: 085b lsrs r3, r3, #1
80035e4: 441a add r2, r3
80035e6: 687b ldr r3, [r7, #4]
80035e8: 685b ldr r3, [r3, #4]
80035ea: fbb2 f3f3 udiv r3, r2, r3
80035ee: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
80035f0: 693b ldr r3, [r7, #16]
80035f2: 2b0f cmp r3, #15
80035f4: d916 bls.n 8003624 <UART_SetConfig+0x404>
80035f6: 693b ldr r3, [r7, #16]
80035f8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80035fc: d212 bcs.n 8003624 <UART_SetConfig+0x404>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
80035fe: 693b ldr r3, [r7, #16]
8003600: b29b uxth r3, r3
8003602: f023 030f bic.w r3, r3, #15
8003606: 81fb strh r3, [r7, #14]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8003608: 693b ldr r3, [r7, #16]
800360a: 085b lsrs r3, r3, #1
800360c: b29b uxth r3, r3
800360e: f003 0307 and.w r3, r3, #7
8003612: b29a uxth r2, r3
8003614: 89fb ldrh r3, [r7, #14]
8003616: 4313 orrs r3, r2
8003618: 81fb strh r3, [r7, #14]
huart->Instance->BRR = brrtemp;
800361a: 687b ldr r3, [r7, #4]
800361c: 681b ldr r3, [r3, #0]
800361e: 89fa ldrh r2, [r7, #14]
8003620: 60da str r2, [r3, #12]
8003622: e04f b.n 80036c4 <UART_SetConfig+0x4a4>
}
else
{
ret = HAL_ERROR;
8003624: 2301 movs r3, #1
8003626: 77bb strb r3, [r7, #30]
8003628: e04c b.n 80036c4 <UART_SetConfig+0x4a4>
}
}
}
else
{
switch (clocksource)
800362a: 7ffb ldrb r3, [r7, #31]
800362c: 2b08 cmp r3, #8
800362e: d828 bhi.n 8003682 <UART_SetConfig+0x462>
8003630: a201 add r2, pc, #4 @ (adr r2, 8003638 <UART_SetConfig+0x418>)
8003632: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003636: bf00 nop
8003638: 0800365d .word 0x0800365d
800363c: 08003665 .word 0x08003665
8003640: 0800366d .word 0x0800366d
8003644: 08003683 .word 0x08003683
8003648: 08003673 .word 0x08003673
800364c: 08003683 .word 0x08003683
8003650: 08003683 .word 0x08003683
8003654: 08003683 .word 0x08003683
8003658: 0800367b .word 0x0800367b
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
800365c: f7fe fe96 bl 800238c <HAL_RCC_GetPCLK1Freq>
8003660: 61b8 str r0, [r7, #24]
break;
8003662: e013 b.n 800368c <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8003664: f7fe fea6 bl 80023b4 <HAL_RCC_GetPCLK2Freq>
8003668: 61b8 str r0, [r7, #24]
break;
800366a: e00f b.n 800368c <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
800366c: 4b1d ldr r3, [pc, #116] @ (80036e4 <UART_SetConfig+0x4c4>)
800366e: 61bb str r3, [r7, #24]
break;
8003670: e00c b.n 800368c <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8003672: f7fe fdb9 bl 80021e8 <HAL_RCC_GetSysClockFreq>
8003676: 61b8 str r0, [r7, #24]
break;
8003678: e008 b.n 800368c <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
800367a: f44f 4300 mov.w r3, #32768 @ 0x8000
800367e: 61bb str r3, [r7, #24]
break;
8003680: e004 b.n 800368c <UART_SetConfig+0x46c>
default:
pclk = 0U;
8003682: 2300 movs r3, #0
8003684: 61bb str r3, [r7, #24]
ret = HAL_ERROR;
8003686: 2301 movs r3, #1
8003688: 77bb strb r3, [r7, #30]
break;
800368a: bf00 nop
}
if (pclk != 0U)
800368c: 69bb ldr r3, [r7, #24]
800368e: 2b00 cmp r3, #0
8003690: d018 beq.n 80036c4 <UART_SetConfig+0x4a4>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
8003692: 687b ldr r3, [r7, #4]
8003694: 685b ldr r3, [r3, #4]
8003696: 085a lsrs r2, r3, #1
8003698: 69bb ldr r3, [r7, #24]
800369a: 441a add r2, r3
800369c: 687b ldr r3, [r7, #4]
800369e: 685b ldr r3, [r3, #4]
80036a0: fbb2 f3f3 udiv r3, r2, r3
80036a4: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
80036a6: 693b ldr r3, [r7, #16]
80036a8: 2b0f cmp r3, #15
80036aa: d909 bls.n 80036c0 <UART_SetConfig+0x4a0>
80036ac: 693b ldr r3, [r7, #16]
80036ae: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80036b2: d205 bcs.n 80036c0 <UART_SetConfig+0x4a0>
{
huart->Instance->BRR = (uint16_t)usartdiv;
80036b4: 693b ldr r3, [r7, #16]
80036b6: b29a uxth r2, r3
80036b8: 687b ldr r3, [r7, #4]
80036ba: 681b ldr r3, [r3, #0]
80036bc: 60da str r2, [r3, #12]
80036be: e001 b.n 80036c4 <UART_SetConfig+0x4a4>
}
else
{
ret = HAL_ERROR;
80036c0: 2301 movs r3, #1
80036c2: 77bb strb r3, [r7, #30]
}
}
/* Clear ISR function pointers */
huart->RxISR = NULL;
80036c4: 687b ldr r3, [r7, #4]
80036c6: 2200 movs r2, #0
80036c8: 669a str r2, [r3, #104] @ 0x68
huart->TxISR = NULL;
80036ca: 687b ldr r3, [r7, #4]
80036cc: 2200 movs r2, #0
80036ce: 66da str r2, [r3, #108] @ 0x6c
return ret;
80036d0: 7fbb ldrb r3, [r7, #30]
}
80036d2: 4618 mov r0, r3
80036d4: 3720 adds r7, #32
80036d6: 46bd mov sp, r7
80036d8: bd80 pop {r7, pc}
80036da: bf00 nop
80036dc: 40007c00 .word 0x40007c00
80036e0: 40023800 .word 0x40023800
80036e4: 00f42400 .word 0x00f42400
080036e8 <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
80036e8: b480 push {r7}
80036ea: b083 sub sp, #12
80036ec: af00 add r7, sp, #0
80036ee: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
80036f0: 687b ldr r3, [r7, #4]
80036f2: 6a5b ldr r3, [r3, #36] @ 0x24
80036f4: f003 0308 and.w r3, r3, #8
80036f8: 2b00 cmp r3, #0
80036fa: d00a beq.n 8003712 <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
80036fc: 687b ldr r3, [r7, #4]
80036fe: 681b ldr r3, [r3, #0]
8003700: 685b ldr r3, [r3, #4]
8003702: f423 4100 bic.w r1, r3, #32768 @ 0x8000
8003706: 687b ldr r3, [r7, #4]
8003708: 6b5a ldr r2, [r3, #52] @ 0x34
800370a: 687b ldr r3, [r7, #4]
800370c: 681b ldr r3, [r3, #0]
800370e: 430a orrs r2, r1
8003710: 605a str r2, [r3, #4]
}
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
8003712: 687b ldr r3, [r7, #4]
8003714: 6a5b ldr r3, [r3, #36] @ 0x24
8003716: f003 0301 and.w r3, r3, #1
800371a: 2b00 cmp r3, #0
800371c: d00a beq.n 8003734 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
800371e: 687b ldr r3, [r7, #4]
8003720: 681b ldr r3, [r3, #0]
8003722: 685b ldr r3, [r3, #4]
8003724: f423 3100 bic.w r1, r3, #131072 @ 0x20000
8003728: 687b ldr r3, [r7, #4]
800372a: 6a9a ldr r2, [r3, #40] @ 0x28
800372c: 687b ldr r3, [r7, #4]
800372e: 681b ldr r3, [r3, #0]
8003730: 430a orrs r2, r1
8003732: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
8003734: 687b ldr r3, [r7, #4]
8003736: 6a5b ldr r3, [r3, #36] @ 0x24
8003738: f003 0302 and.w r3, r3, #2
800373c: 2b00 cmp r3, #0
800373e: d00a beq.n 8003756 <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
8003740: 687b ldr r3, [r7, #4]
8003742: 681b ldr r3, [r3, #0]
8003744: 685b ldr r3, [r3, #4]
8003746: f423 3180 bic.w r1, r3, #65536 @ 0x10000
800374a: 687b ldr r3, [r7, #4]
800374c: 6ada ldr r2, [r3, #44] @ 0x2c
800374e: 687b ldr r3, [r7, #4]
8003750: 681b ldr r3, [r3, #0]
8003752: 430a orrs r2, r1
8003754: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
8003756: 687b ldr r3, [r7, #4]
8003758: 6a5b ldr r3, [r3, #36] @ 0x24
800375a: f003 0304 and.w r3, r3, #4
800375e: 2b00 cmp r3, #0
8003760: d00a beq.n 8003778 <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
8003762: 687b ldr r3, [r7, #4]
8003764: 681b ldr r3, [r3, #0]
8003766: 685b ldr r3, [r3, #4]
8003768: f423 2180 bic.w r1, r3, #262144 @ 0x40000
800376c: 687b ldr r3, [r7, #4]
800376e: 6b1a ldr r2, [r3, #48] @ 0x30
8003770: 687b ldr r3, [r7, #4]
8003772: 681b ldr r3, [r3, #0]
8003774: 430a orrs r2, r1
8003776: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
8003778: 687b ldr r3, [r7, #4]
800377a: 6a5b ldr r3, [r3, #36] @ 0x24
800377c: f003 0310 and.w r3, r3, #16
8003780: 2b00 cmp r3, #0
8003782: d00a beq.n 800379a <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
8003784: 687b ldr r3, [r7, #4]
8003786: 681b ldr r3, [r3, #0]
8003788: 689b ldr r3, [r3, #8]
800378a: f423 5180 bic.w r1, r3, #4096 @ 0x1000
800378e: 687b ldr r3, [r7, #4]
8003790: 6b9a ldr r2, [r3, #56] @ 0x38
8003792: 687b ldr r3, [r7, #4]
8003794: 681b ldr r3, [r3, #0]
8003796: 430a orrs r2, r1
8003798: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
800379a: 687b ldr r3, [r7, #4]
800379c: 6a5b ldr r3, [r3, #36] @ 0x24
800379e: f003 0320 and.w r3, r3, #32
80037a2: 2b00 cmp r3, #0
80037a4: d00a beq.n 80037bc <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
80037a6: 687b ldr r3, [r7, #4]
80037a8: 681b ldr r3, [r3, #0]
80037aa: 689b ldr r3, [r3, #8]
80037ac: f423 5100 bic.w r1, r3, #8192 @ 0x2000
80037b0: 687b ldr r3, [r7, #4]
80037b2: 6bda ldr r2, [r3, #60] @ 0x3c
80037b4: 687b ldr r3, [r7, #4]
80037b6: 681b ldr r3, [r3, #0]
80037b8: 430a orrs r2, r1
80037ba: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
80037bc: 687b ldr r3, [r7, #4]
80037be: 6a5b ldr r3, [r3, #36] @ 0x24
80037c0: f003 0340 and.w r3, r3, #64 @ 0x40
80037c4: 2b00 cmp r3, #0
80037c6: d01a beq.n 80037fe <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
80037c8: 687b ldr r3, [r7, #4]
80037ca: 681b ldr r3, [r3, #0]
80037cc: 685b ldr r3, [r3, #4]
80037ce: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
80037d2: 687b ldr r3, [r7, #4]
80037d4: 6c1a ldr r2, [r3, #64] @ 0x40
80037d6: 687b ldr r3, [r7, #4]
80037d8: 681b ldr r3, [r3, #0]
80037da: 430a orrs r2, r1
80037dc: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
80037de: 687b ldr r3, [r7, #4]
80037e0: 6c1b ldr r3, [r3, #64] @ 0x40
80037e2: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
80037e6: d10a bne.n 80037fe <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
80037e8: 687b ldr r3, [r7, #4]
80037ea: 681b ldr r3, [r3, #0]
80037ec: 685b ldr r3, [r3, #4]
80037ee: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
80037f2: 687b ldr r3, [r7, #4]
80037f4: 6c5a ldr r2, [r3, #68] @ 0x44
80037f6: 687b ldr r3, [r7, #4]
80037f8: 681b ldr r3, [r3, #0]
80037fa: 430a orrs r2, r1
80037fc: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
80037fe: 687b ldr r3, [r7, #4]
8003800: 6a5b ldr r3, [r3, #36] @ 0x24
8003802: f003 0380 and.w r3, r3, #128 @ 0x80
8003806: 2b00 cmp r3, #0
8003808: d00a beq.n 8003820 <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
800380a: 687b ldr r3, [r7, #4]
800380c: 681b ldr r3, [r3, #0]
800380e: 685b ldr r3, [r3, #4]
8003810: f423 2100 bic.w r1, r3, #524288 @ 0x80000
8003814: 687b ldr r3, [r7, #4]
8003816: 6c9a ldr r2, [r3, #72] @ 0x48
8003818: 687b ldr r3, [r7, #4]
800381a: 681b ldr r3, [r3, #0]
800381c: 430a orrs r2, r1
800381e: 605a str r2, [r3, #4]
}
}
8003820: bf00 nop
8003822: 370c adds r7, #12
8003824: 46bd mov sp, r7
8003826: f85d 7b04 ldr.w r7, [sp], #4
800382a: 4770 bx lr
0800382c <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
800382c: b580 push {r7, lr}
800382e: b08c sub sp, #48 @ 0x30
8003830: af02 add r7, sp, #8
8003832: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8003834: 687b ldr r3, [r7, #4]
8003836: 2200 movs r2, #0
8003838: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
800383c: f7fd fe0e bl 800145c <HAL_GetTick>
8003840: 6278 str r0, [r7, #36] @ 0x24
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
8003842: 687b ldr r3, [r7, #4]
8003844: 681b ldr r3, [r3, #0]
8003846: 681b ldr r3, [r3, #0]
8003848: f003 0308 and.w r3, r3, #8
800384c: 2b08 cmp r3, #8
800384e: d12e bne.n 80038ae <UART_CheckIdleState+0x82>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8003850: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
8003854: 9300 str r3, [sp, #0]
8003856: 6a7b ldr r3, [r7, #36] @ 0x24
8003858: 2200 movs r2, #0
800385a: f44f 1100 mov.w r1, #2097152 @ 0x200000
800385e: 6878 ldr r0, [r7, #4]
8003860: f000 f83b bl 80038da <UART_WaitOnFlagUntilTimeout>
8003864: 4603 mov r3, r0
8003866: 2b00 cmp r3, #0
8003868: d021 beq.n 80038ae <UART_CheckIdleState+0x82>
{
/* Disable TXE interrupt for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
800386a: 687b ldr r3, [r7, #4]
800386c: 681b ldr r3, [r3, #0]
800386e: 613b str r3, [r7, #16]
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8003870: 693b ldr r3, [r7, #16]
8003872: e853 3f00 ldrex r3, [r3]
8003876: 60fb str r3, [r7, #12]
return(result);
8003878: 68fb ldr r3, [r7, #12]
800387a: f023 0380 bic.w r3, r3, #128 @ 0x80
800387e: 623b str r3, [r7, #32]
8003880: 687b ldr r3, [r7, #4]
8003882: 681b ldr r3, [r3, #0]
8003884: 461a mov r2, r3
8003886: 6a3b ldr r3, [r7, #32]
8003888: 61fb str r3, [r7, #28]
800388a: 61ba str r2, [r7, #24]
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800388c: 69b9 ldr r1, [r7, #24]
800388e: 69fa ldr r2, [r7, #28]
8003890: e841 2300 strex r3, r2, [r1]
8003894: 617b str r3, [r7, #20]
return(result);
8003896: 697b ldr r3, [r7, #20]
8003898: 2b00 cmp r3, #0
800389a: d1e6 bne.n 800386a <UART_CheckIdleState+0x3e>
huart->gState = HAL_UART_STATE_READY;
800389c: 687b ldr r3, [r7, #4]
800389e: 2220 movs r2, #32
80038a0: 67da str r2, [r3, #124] @ 0x7c
__HAL_UNLOCK(huart);
80038a2: 687b ldr r3, [r7, #4]
80038a4: 2200 movs r2, #0
80038a6: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Timeout occurred */
return HAL_TIMEOUT;
80038aa: 2303 movs r3, #3
80038ac: e011 b.n 80038d2 <UART_CheckIdleState+0xa6>
}
}
#endif /* USART_ISR_REACK */
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
80038ae: 687b ldr r3, [r7, #4]
80038b0: 2220 movs r2, #32
80038b2: 67da str r2, [r3, #124] @ 0x7c
huart->RxState = HAL_UART_STATE_READY;
80038b4: 687b ldr r3, [r7, #4]
80038b6: 2220 movs r2, #32
80038b8: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80038bc: 687b ldr r3, [r7, #4]
80038be: 2200 movs r2, #0
80038c0: 661a str r2, [r3, #96] @ 0x60
huart->RxEventType = HAL_UART_RXEVENT_TC;
80038c2: 687b ldr r3, [r7, #4]
80038c4: 2200 movs r2, #0
80038c6: 665a str r2, [r3, #100] @ 0x64
__HAL_UNLOCK(huart);
80038c8: 687b ldr r3, [r7, #4]
80038ca: 2200 movs r2, #0
80038cc: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_OK;
80038d0: 2300 movs r3, #0
}
80038d2: 4618 mov r0, r3
80038d4: 3728 adds r7, #40 @ 0x28
80038d6: 46bd mov sp, r7
80038d8: bd80 pop {r7, pc}
080038da <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
80038da: b580 push {r7, lr}
80038dc: b084 sub sp, #16
80038de: af00 add r7, sp, #0
80038e0: 60f8 str r0, [r7, #12]
80038e2: 60b9 str r1, [r7, #8]
80038e4: 603b str r3, [r7, #0]
80038e6: 4613 mov r3, r2
80038e8: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80038ea: e04f b.n 800398c <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80038ec: 69bb ldr r3, [r7, #24]
80038ee: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80038f2: d04b beq.n 800398c <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80038f4: f7fd fdb2 bl 800145c <HAL_GetTick>
80038f8: 4602 mov r2, r0
80038fa: 683b ldr r3, [r7, #0]
80038fc: 1ad3 subs r3, r2, r3
80038fe: 69ba ldr r2, [r7, #24]
8003900: 429a cmp r2, r3
8003902: d302 bcc.n 800390a <UART_WaitOnFlagUntilTimeout+0x30>
8003904: 69bb ldr r3, [r7, #24]
8003906: 2b00 cmp r3, #0
8003908: d101 bne.n 800390e <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
800390a: 2303 movs r3, #3
800390c: e04e b.n 80039ac <UART_WaitOnFlagUntilTimeout+0xd2>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
800390e: 68fb ldr r3, [r7, #12]
8003910: 681b ldr r3, [r3, #0]
8003912: 681b ldr r3, [r3, #0]
8003914: f003 0304 and.w r3, r3, #4
8003918: 2b00 cmp r3, #0
800391a: d037 beq.n 800398c <UART_WaitOnFlagUntilTimeout+0xb2>
800391c: 68bb ldr r3, [r7, #8]
800391e: 2b80 cmp r3, #128 @ 0x80
8003920: d034 beq.n 800398c <UART_WaitOnFlagUntilTimeout+0xb2>
8003922: 68bb ldr r3, [r7, #8]
8003924: 2b40 cmp r3, #64 @ 0x40
8003926: d031 beq.n 800398c <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
8003928: 68fb ldr r3, [r7, #12]
800392a: 681b ldr r3, [r3, #0]
800392c: 69db ldr r3, [r3, #28]
800392e: f003 0308 and.w r3, r3, #8
8003932: 2b08 cmp r3, #8
8003934: d110 bne.n 8003958 <UART_WaitOnFlagUntilTimeout+0x7e>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8003936: 68fb ldr r3, [r7, #12]
8003938: 681b ldr r3, [r3, #0]
800393a: 2208 movs r2, #8
800393c: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
800393e: 68f8 ldr r0, [r7, #12]
8003940: f000 f838 bl 80039b4 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
8003944: 68fb ldr r3, [r7, #12]
8003946: 2208 movs r2, #8
8003948: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
800394c: 68fb ldr r3, [r7, #12]
800394e: 2200 movs r2, #0
8003950: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_ERROR;
8003954: 2301 movs r3, #1
8003956: e029 b.n 80039ac <UART_WaitOnFlagUntilTimeout+0xd2>
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
8003958: 68fb ldr r3, [r7, #12]
800395a: 681b ldr r3, [r3, #0]
800395c: 69db ldr r3, [r3, #28]
800395e: f403 6300 and.w r3, r3, #2048 @ 0x800
8003962: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8003966: d111 bne.n 800398c <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8003968: 68fb ldr r3, [r7, #12]
800396a: 681b ldr r3, [r3, #0]
800396c: f44f 6200 mov.w r2, #2048 @ 0x800
8003970: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8003972: 68f8 ldr r0, [r7, #12]
8003974: f000 f81e bl 80039b4 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
8003978: 68fb ldr r3, [r7, #12]
800397a: 2220 movs r2, #32
800397c: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
8003980: 68fb ldr r3, [r7, #12]
8003982: 2200 movs r2, #0
8003984: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_TIMEOUT;
8003988: 2303 movs r3, #3
800398a: e00f b.n 80039ac <UART_WaitOnFlagUntilTimeout+0xd2>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
800398c: 68fb ldr r3, [r7, #12]
800398e: 681b ldr r3, [r3, #0]
8003990: 69da ldr r2, [r3, #28]
8003992: 68bb ldr r3, [r7, #8]
8003994: 4013 ands r3, r2
8003996: 68ba ldr r2, [r7, #8]
8003998: 429a cmp r2, r3
800399a: bf0c ite eq
800399c: 2301 moveq r3, #1
800399e: 2300 movne r3, #0
80039a0: b2db uxtb r3, r3
80039a2: 461a mov r2, r3
80039a4: 79fb ldrb r3, [r7, #7]
80039a6: 429a cmp r2, r3
80039a8: d0a0 beq.n 80038ec <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
80039aa: 2300 movs r3, #0
}
80039ac: 4618 mov r0, r3
80039ae: 3710 adds r7, #16
80039b0: 46bd mov sp, r7
80039b2: bd80 pop {r7, pc}
080039b4 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
80039b4: b480 push {r7}
80039b6: b095 sub sp, #84 @ 0x54
80039b8: af00 add r7, sp, #0
80039ba: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
80039bc: 687b ldr r3, [r7, #4]
80039be: 681b ldr r3, [r3, #0]
80039c0: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80039c2: 6b7b ldr r3, [r7, #52] @ 0x34
80039c4: e853 3f00 ldrex r3, [r3]
80039c8: 633b str r3, [r7, #48] @ 0x30
return(result);
80039ca: 6b3b ldr r3, [r7, #48] @ 0x30
80039cc: f423 7390 bic.w r3, r3, #288 @ 0x120
80039d0: 64fb str r3, [r7, #76] @ 0x4c
80039d2: 687b ldr r3, [r7, #4]
80039d4: 681b ldr r3, [r3, #0]
80039d6: 461a mov r2, r3
80039d8: 6cfb ldr r3, [r7, #76] @ 0x4c
80039da: 643b str r3, [r7, #64] @ 0x40
80039dc: 63fa str r2, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80039de: 6bf9 ldr r1, [r7, #60] @ 0x3c
80039e0: 6c3a ldr r2, [r7, #64] @ 0x40
80039e2: e841 2300 strex r3, r2, [r1]
80039e6: 63bb str r3, [r7, #56] @ 0x38
return(result);
80039e8: 6bbb ldr r3, [r7, #56] @ 0x38
80039ea: 2b00 cmp r3, #0
80039ec: d1e6 bne.n 80039bc <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80039ee: 687b ldr r3, [r7, #4]
80039f0: 681b ldr r3, [r3, #0]
80039f2: 3308 adds r3, #8
80039f4: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80039f6: 6a3b ldr r3, [r7, #32]
80039f8: e853 3f00 ldrex r3, [r3]
80039fc: 61fb str r3, [r7, #28]
return(result);
80039fe: 69fb ldr r3, [r7, #28]
8003a00: f023 0301 bic.w r3, r3, #1
8003a04: 64bb str r3, [r7, #72] @ 0x48
8003a06: 687b ldr r3, [r7, #4]
8003a08: 681b ldr r3, [r3, #0]
8003a0a: 3308 adds r3, #8
8003a0c: 6cba ldr r2, [r7, #72] @ 0x48
8003a0e: 62fa str r2, [r7, #44] @ 0x2c
8003a10: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003a12: 6ab9 ldr r1, [r7, #40] @ 0x28
8003a14: 6afa ldr r2, [r7, #44] @ 0x2c
8003a16: e841 2300 strex r3, r2, [r1]
8003a1a: 627b str r3, [r7, #36] @ 0x24
return(result);
8003a1c: 6a7b ldr r3, [r7, #36] @ 0x24
8003a1e: 2b00 cmp r3, #0
8003a20: d1e5 bne.n 80039ee <UART_EndRxTransfer+0x3a>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8003a22: 687b ldr r3, [r7, #4]
8003a24: 6e1b ldr r3, [r3, #96] @ 0x60
8003a26: 2b01 cmp r3, #1
8003a28: d118 bne.n 8003a5c <UART_EndRxTransfer+0xa8>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8003a2a: 687b ldr r3, [r7, #4]
8003a2c: 681b ldr r3, [r3, #0]
8003a2e: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8003a30: 68fb ldr r3, [r7, #12]
8003a32: e853 3f00 ldrex r3, [r3]
8003a36: 60bb str r3, [r7, #8]
return(result);
8003a38: 68bb ldr r3, [r7, #8]
8003a3a: f023 0310 bic.w r3, r3, #16
8003a3e: 647b str r3, [r7, #68] @ 0x44
8003a40: 687b ldr r3, [r7, #4]
8003a42: 681b ldr r3, [r3, #0]
8003a44: 461a mov r2, r3
8003a46: 6c7b ldr r3, [r7, #68] @ 0x44
8003a48: 61bb str r3, [r7, #24]
8003a4a: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003a4c: 6979 ldr r1, [r7, #20]
8003a4e: 69ba ldr r2, [r7, #24]
8003a50: e841 2300 strex r3, r2, [r1]
8003a54: 613b str r3, [r7, #16]
return(result);
8003a56: 693b ldr r3, [r7, #16]
8003a58: 2b00 cmp r3, #0
8003a5a: d1e6 bne.n 8003a2a <UART_EndRxTransfer+0x76>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8003a5c: 687b ldr r3, [r7, #4]
8003a5e: 2220 movs r2, #32
8003a60: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8003a64: 687b ldr r3, [r7, #4]
8003a66: 2200 movs r2, #0
8003a68: 661a str r2, [r3, #96] @ 0x60
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
8003a6a: 687b ldr r3, [r7, #4]
8003a6c: 2200 movs r2, #0
8003a6e: 669a str r2, [r3, #104] @ 0x68
}
8003a70: bf00 nop
8003a72: 3754 adds r7, #84 @ 0x54
8003a74: 46bd mov sp, r7
8003a76: f85d 7b04 ldr.w r7, [sp], #4
8003a7a: 4770 bx lr
08003a7c <std>:
8003a7c: 2300 movs r3, #0
8003a7e: b510 push {r4, lr}
8003a80: 4604 mov r4, r0
8003a82: e9c0 3300 strd r3, r3, [r0]
8003a86: e9c0 3304 strd r3, r3, [r0, #16]
8003a8a: 6083 str r3, [r0, #8]
8003a8c: 8181 strh r1, [r0, #12]
8003a8e: 6643 str r3, [r0, #100] @ 0x64
8003a90: 81c2 strh r2, [r0, #14]
8003a92: 6183 str r3, [r0, #24]
8003a94: 4619 mov r1, r3
8003a96: 2208 movs r2, #8
8003a98: 305c adds r0, #92 @ 0x5c
8003a9a: f000 f906 bl 8003caa <memset>
8003a9e: 4b0d ldr r3, [pc, #52] @ (8003ad4 <std+0x58>)
8003aa0: 6263 str r3, [r4, #36] @ 0x24
8003aa2: 4b0d ldr r3, [pc, #52] @ (8003ad8 <std+0x5c>)
8003aa4: 62a3 str r3, [r4, #40] @ 0x28
8003aa6: 4b0d ldr r3, [pc, #52] @ (8003adc <std+0x60>)
8003aa8: 62e3 str r3, [r4, #44] @ 0x2c
8003aaa: 4b0d ldr r3, [pc, #52] @ (8003ae0 <std+0x64>)
8003aac: 6323 str r3, [r4, #48] @ 0x30
8003aae: 4b0d ldr r3, [pc, #52] @ (8003ae4 <std+0x68>)
8003ab0: 6224 str r4, [r4, #32]
8003ab2: 429c cmp r4, r3
8003ab4: d006 beq.n 8003ac4 <std+0x48>
8003ab6: f103 0268 add.w r2, r3, #104 @ 0x68
8003aba: 4294 cmp r4, r2
8003abc: d002 beq.n 8003ac4 <std+0x48>
8003abe: 33d0 adds r3, #208 @ 0xd0
8003ac0: 429c cmp r4, r3
8003ac2: d105 bne.n 8003ad0 <std+0x54>
8003ac4: f104 0058 add.w r0, r4, #88 @ 0x58
8003ac8: e8bd 4010 ldmia.w sp!, {r4, lr}
8003acc: f000 b966 b.w 8003d9c <__retarget_lock_init_recursive>
8003ad0: bd10 pop {r4, pc}
8003ad2: bf00 nop
8003ad4: 08003c25 .word 0x08003c25
8003ad8: 08003c47 .word 0x08003c47
8003adc: 08003c7f .word 0x08003c7f
8003ae0: 08003ca3 .word 0x08003ca3
8003ae4: 20000160 .word 0x20000160
08003ae8 <stdio_exit_handler>:
8003ae8: 4a02 ldr r2, [pc, #8] @ (8003af4 <stdio_exit_handler+0xc>)
8003aea: 4903 ldr r1, [pc, #12] @ (8003af8 <stdio_exit_handler+0x10>)
8003aec: 4803 ldr r0, [pc, #12] @ (8003afc <stdio_exit_handler+0x14>)
8003aee: f000 b869 b.w 8003bc4 <_fwalk_sglue>
8003af2: bf00 nop
8003af4: 2000000c .word 0x2000000c
8003af8: 08004639 .word 0x08004639
8003afc: 2000001c .word 0x2000001c
08003b00 <cleanup_stdio>:
8003b00: 6841 ldr r1, [r0, #4]
8003b02: 4b0c ldr r3, [pc, #48] @ (8003b34 <cleanup_stdio+0x34>)
8003b04: 4299 cmp r1, r3
8003b06: b510 push {r4, lr}
8003b08: 4604 mov r4, r0
8003b0a: d001 beq.n 8003b10 <cleanup_stdio+0x10>
8003b0c: f000 fd94 bl 8004638 <_fflush_r>
8003b10: 68a1 ldr r1, [r4, #8]
8003b12: 4b09 ldr r3, [pc, #36] @ (8003b38 <cleanup_stdio+0x38>)
8003b14: 4299 cmp r1, r3
8003b16: d002 beq.n 8003b1e <cleanup_stdio+0x1e>
8003b18: 4620 mov r0, r4
8003b1a: f000 fd8d bl 8004638 <_fflush_r>
8003b1e: 68e1 ldr r1, [r4, #12]
8003b20: 4b06 ldr r3, [pc, #24] @ (8003b3c <cleanup_stdio+0x3c>)
8003b22: 4299 cmp r1, r3
8003b24: d004 beq.n 8003b30 <cleanup_stdio+0x30>
8003b26: 4620 mov r0, r4
8003b28: e8bd 4010 ldmia.w sp!, {r4, lr}
8003b2c: f000 bd84 b.w 8004638 <_fflush_r>
8003b30: bd10 pop {r4, pc}
8003b32: bf00 nop
8003b34: 20000160 .word 0x20000160
8003b38: 200001c8 .word 0x200001c8
8003b3c: 20000230 .word 0x20000230
08003b40 <global_stdio_init.part.0>:
8003b40: b510 push {r4, lr}
8003b42: 4b0b ldr r3, [pc, #44] @ (8003b70 <global_stdio_init.part.0+0x30>)
8003b44: 4c0b ldr r4, [pc, #44] @ (8003b74 <global_stdio_init.part.0+0x34>)
8003b46: 4a0c ldr r2, [pc, #48] @ (8003b78 <global_stdio_init.part.0+0x38>)
8003b48: 601a str r2, [r3, #0]
8003b4a: 4620 mov r0, r4
8003b4c: 2200 movs r2, #0
8003b4e: 2104 movs r1, #4
8003b50: f7ff ff94 bl 8003a7c <std>
8003b54: f104 0068 add.w r0, r4, #104 @ 0x68
8003b58: 2201 movs r2, #1
8003b5a: 2109 movs r1, #9
8003b5c: f7ff ff8e bl 8003a7c <std>
8003b60: f104 00d0 add.w r0, r4, #208 @ 0xd0
8003b64: 2202 movs r2, #2
8003b66: e8bd 4010 ldmia.w sp!, {r4, lr}
8003b6a: 2112 movs r1, #18
8003b6c: f7ff bf86 b.w 8003a7c <std>
8003b70: 20000298 .word 0x20000298
8003b74: 20000160 .word 0x20000160
8003b78: 08003ae9 .word 0x08003ae9
08003b7c <__sfp_lock_acquire>:
8003b7c: 4801 ldr r0, [pc, #4] @ (8003b84 <__sfp_lock_acquire+0x8>)
8003b7e: f000 b90e b.w 8003d9e <__retarget_lock_acquire_recursive>
8003b82: bf00 nop
8003b84: 200002a1 .word 0x200002a1
08003b88 <__sfp_lock_release>:
8003b88: 4801 ldr r0, [pc, #4] @ (8003b90 <__sfp_lock_release+0x8>)
8003b8a: f000 b909 b.w 8003da0 <__retarget_lock_release_recursive>
8003b8e: bf00 nop
8003b90: 200002a1 .word 0x200002a1
08003b94 <__sinit>:
8003b94: b510 push {r4, lr}
8003b96: 4604 mov r4, r0
8003b98: f7ff fff0 bl 8003b7c <__sfp_lock_acquire>
8003b9c: 6a23 ldr r3, [r4, #32]
8003b9e: b11b cbz r3, 8003ba8 <__sinit+0x14>
8003ba0: e8bd 4010 ldmia.w sp!, {r4, lr}
8003ba4: f7ff bff0 b.w 8003b88 <__sfp_lock_release>
8003ba8: 4b04 ldr r3, [pc, #16] @ (8003bbc <__sinit+0x28>)
8003baa: 6223 str r3, [r4, #32]
8003bac: 4b04 ldr r3, [pc, #16] @ (8003bc0 <__sinit+0x2c>)
8003bae: 681b ldr r3, [r3, #0]
8003bb0: 2b00 cmp r3, #0
8003bb2: d1f5 bne.n 8003ba0 <__sinit+0xc>
8003bb4: f7ff ffc4 bl 8003b40 <global_stdio_init.part.0>
8003bb8: e7f2 b.n 8003ba0 <__sinit+0xc>
8003bba: bf00 nop
8003bbc: 08003b01 .word 0x08003b01
8003bc0: 20000298 .word 0x20000298
08003bc4 <_fwalk_sglue>:
8003bc4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
8003bc8: 4607 mov r7, r0
8003bca: 4688 mov r8, r1
8003bcc: 4614 mov r4, r2
8003bce: 2600 movs r6, #0
8003bd0: e9d4 9501 ldrd r9, r5, [r4, #4]
8003bd4: f1b9 0901 subs.w r9, r9, #1
8003bd8: d505 bpl.n 8003be6 <_fwalk_sglue+0x22>
8003bda: 6824 ldr r4, [r4, #0]
8003bdc: 2c00 cmp r4, #0
8003bde: d1f7 bne.n 8003bd0 <_fwalk_sglue+0xc>
8003be0: 4630 mov r0, r6
8003be2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
8003be6: 89ab ldrh r3, [r5, #12]
8003be8: 2b01 cmp r3, #1
8003bea: d907 bls.n 8003bfc <_fwalk_sglue+0x38>
8003bec: f9b5 300e ldrsh.w r3, [r5, #14]
8003bf0: 3301 adds r3, #1
8003bf2: d003 beq.n 8003bfc <_fwalk_sglue+0x38>
8003bf4: 4629 mov r1, r5
8003bf6: 4638 mov r0, r7
8003bf8: 47c0 blx r8
8003bfa: 4306 orrs r6, r0
8003bfc: 3568 adds r5, #104 @ 0x68
8003bfe: e7e9 b.n 8003bd4 <_fwalk_sglue+0x10>
08003c00 <iprintf>:
8003c00: b40f push {r0, r1, r2, r3}
8003c02: b507 push {r0, r1, r2, lr}
8003c04: 4906 ldr r1, [pc, #24] @ (8003c20 <iprintf+0x20>)
8003c06: ab04 add r3, sp, #16
8003c08: 6808 ldr r0, [r1, #0]
8003c0a: f853 2b04 ldr.w r2, [r3], #4
8003c0e: 6881 ldr r1, [r0, #8]
8003c10: 9301 str r3, [sp, #4]
8003c12: f000 f9e9 bl 8003fe8 <_vfiprintf_r>
8003c16: b003 add sp, #12
8003c18: f85d eb04 ldr.w lr, [sp], #4
8003c1c: b004 add sp, #16
8003c1e: 4770 bx lr
8003c20: 20000018 .word 0x20000018
08003c24 <__sread>:
8003c24: b510 push {r4, lr}
8003c26: 460c mov r4, r1
8003c28: f9b1 100e ldrsh.w r1, [r1, #14]
8003c2c: f000 f868 bl 8003d00 <_read_r>
8003c30: 2800 cmp r0, #0
8003c32: bfab itete ge
8003c34: 6d63 ldrge r3, [r4, #84] @ 0x54
8003c36: 89a3 ldrhlt r3, [r4, #12]
8003c38: 181b addge r3, r3, r0
8003c3a: f423 5380 biclt.w r3, r3, #4096 @ 0x1000
8003c3e: bfac ite ge
8003c40: 6563 strge r3, [r4, #84] @ 0x54
8003c42: 81a3 strhlt r3, [r4, #12]
8003c44: bd10 pop {r4, pc}
08003c46 <__swrite>:
8003c46: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8003c4a: 461f mov r7, r3
8003c4c: 898b ldrh r3, [r1, #12]
8003c4e: 05db lsls r3, r3, #23
8003c50: 4605 mov r5, r0
8003c52: 460c mov r4, r1
8003c54: 4616 mov r6, r2
8003c56: d505 bpl.n 8003c64 <__swrite+0x1e>
8003c58: f9b1 100e ldrsh.w r1, [r1, #14]
8003c5c: 2302 movs r3, #2
8003c5e: 2200 movs r2, #0
8003c60: f000 f83c bl 8003cdc <_lseek_r>
8003c64: 89a3 ldrh r3, [r4, #12]
8003c66: f9b4 100e ldrsh.w r1, [r4, #14]
8003c6a: f423 5380 bic.w r3, r3, #4096 @ 0x1000
8003c6e: 81a3 strh r3, [r4, #12]
8003c70: 4632 mov r2, r6
8003c72: 463b mov r3, r7
8003c74: 4628 mov r0, r5
8003c76: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
8003c7a: f000 b853 b.w 8003d24 <_write_r>
08003c7e <__sseek>:
8003c7e: b510 push {r4, lr}
8003c80: 460c mov r4, r1
8003c82: f9b1 100e ldrsh.w r1, [r1, #14]
8003c86: f000 f829 bl 8003cdc <_lseek_r>
8003c8a: 1c43 adds r3, r0, #1
8003c8c: 89a3 ldrh r3, [r4, #12]
8003c8e: bf15 itete ne
8003c90: 6560 strne r0, [r4, #84] @ 0x54
8003c92: f423 5380 biceq.w r3, r3, #4096 @ 0x1000
8003c96: f443 5380 orrne.w r3, r3, #4096 @ 0x1000
8003c9a: 81a3 strheq r3, [r4, #12]
8003c9c: bf18 it ne
8003c9e: 81a3 strhne r3, [r4, #12]
8003ca0: bd10 pop {r4, pc}
08003ca2 <__sclose>:
8003ca2: f9b1 100e ldrsh.w r1, [r1, #14]
8003ca6: f000 b809 b.w 8003cbc <_close_r>
08003caa <memset>:
8003caa: 4402 add r2, r0
8003cac: 4603 mov r3, r0
8003cae: 4293 cmp r3, r2
8003cb0: d100 bne.n 8003cb4 <memset+0xa>
8003cb2: 4770 bx lr
8003cb4: f803 1b01 strb.w r1, [r3], #1
8003cb8: e7f9 b.n 8003cae <memset+0x4>
...
08003cbc <_close_r>:
8003cbc: b538 push {r3, r4, r5, lr}
8003cbe: 4d06 ldr r5, [pc, #24] @ (8003cd8 <_close_r+0x1c>)
8003cc0: 2300 movs r3, #0
8003cc2: 4604 mov r4, r0
8003cc4: 4608 mov r0, r1
8003cc6: 602b str r3, [r5, #0]
8003cc8: f7fd fb01 bl 80012ce <_close>
8003ccc: 1c43 adds r3, r0, #1
8003cce: d102 bne.n 8003cd6 <_close_r+0x1a>
8003cd0: 682b ldr r3, [r5, #0]
8003cd2: b103 cbz r3, 8003cd6 <_close_r+0x1a>
8003cd4: 6023 str r3, [r4, #0]
8003cd6: bd38 pop {r3, r4, r5, pc}
8003cd8: 2000029c .word 0x2000029c
08003cdc <_lseek_r>:
8003cdc: b538 push {r3, r4, r5, lr}
8003cde: 4d07 ldr r5, [pc, #28] @ (8003cfc <_lseek_r+0x20>)
8003ce0: 4604 mov r4, r0
8003ce2: 4608 mov r0, r1
8003ce4: 4611 mov r1, r2
8003ce6: 2200 movs r2, #0
8003ce8: 602a str r2, [r5, #0]
8003cea: 461a mov r2, r3
8003cec: f7fd fb16 bl 800131c <_lseek>
8003cf0: 1c43 adds r3, r0, #1
8003cf2: d102 bne.n 8003cfa <_lseek_r+0x1e>
8003cf4: 682b ldr r3, [r5, #0]
8003cf6: b103 cbz r3, 8003cfa <_lseek_r+0x1e>
8003cf8: 6023 str r3, [r4, #0]
8003cfa: bd38 pop {r3, r4, r5, pc}
8003cfc: 2000029c .word 0x2000029c
08003d00 <_read_r>:
8003d00: b538 push {r3, r4, r5, lr}
8003d02: 4d07 ldr r5, [pc, #28] @ (8003d20 <_read_r+0x20>)
8003d04: 4604 mov r4, r0
8003d06: 4608 mov r0, r1
8003d08: 4611 mov r1, r2
8003d0a: 2200 movs r2, #0
8003d0c: 602a str r2, [r5, #0]
8003d0e: 461a mov r2, r3
8003d10: f7fd fac0 bl 8001294 <_read>
8003d14: 1c43 adds r3, r0, #1
8003d16: d102 bne.n 8003d1e <_read_r+0x1e>
8003d18: 682b ldr r3, [r5, #0]
8003d1a: b103 cbz r3, 8003d1e <_read_r+0x1e>
8003d1c: 6023 str r3, [r4, #0]
8003d1e: bd38 pop {r3, r4, r5, pc}
8003d20: 2000029c .word 0x2000029c
08003d24 <_write_r>:
8003d24: b538 push {r3, r4, r5, lr}
8003d26: 4d07 ldr r5, [pc, #28] @ (8003d44 <_write_r+0x20>)
8003d28: 4604 mov r4, r0
8003d2a: 4608 mov r0, r1
8003d2c: 4611 mov r1, r2
8003d2e: 2200 movs r2, #0
8003d30: 602a str r2, [r5, #0]
8003d32: 461a mov r2, r3
8003d34: f7fc fc5a bl 80005ec <_write>
8003d38: 1c43 adds r3, r0, #1
8003d3a: d102 bne.n 8003d42 <_write_r+0x1e>
8003d3c: 682b ldr r3, [r5, #0]
8003d3e: b103 cbz r3, 8003d42 <_write_r+0x1e>
8003d40: 6023 str r3, [r4, #0]
8003d42: bd38 pop {r3, r4, r5, pc}
8003d44: 2000029c .word 0x2000029c
08003d48 <__errno>:
8003d48: 4b01 ldr r3, [pc, #4] @ (8003d50 <__errno+0x8>)
8003d4a: 6818 ldr r0, [r3, #0]
8003d4c: 4770 bx lr
8003d4e: bf00 nop
8003d50: 20000018 .word 0x20000018
08003d54 <__libc_init_array>:
8003d54: b570 push {r4, r5, r6, lr}
8003d56: 4d0d ldr r5, [pc, #52] @ (8003d8c <__libc_init_array+0x38>)
8003d58: 4c0d ldr r4, [pc, #52] @ (8003d90 <__libc_init_array+0x3c>)
8003d5a: 1b64 subs r4, r4, r5
8003d5c: 10a4 asrs r4, r4, #2
8003d5e: 2600 movs r6, #0
8003d60: 42a6 cmp r6, r4
8003d62: d109 bne.n 8003d78 <__libc_init_array+0x24>
8003d64: 4d0b ldr r5, [pc, #44] @ (8003d94 <__libc_init_array+0x40>)
8003d66: 4c0c ldr r4, [pc, #48] @ (8003d98 <__libc_init_array+0x44>)
8003d68: f000 fdb6 bl 80048d8 <_init>
8003d6c: 1b64 subs r4, r4, r5
8003d6e: 10a4 asrs r4, r4, #2
8003d70: 2600 movs r6, #0
8003d72: 42a6 cmp r6, r4
8003d74: d105 bne.n 8003d82 <__libc_init_array+0x2e>
8003d76: bd70 pop {r4, r5, r6, pc}
8003d78: f855 3b04 ldr.w r3, [r5], #4
8003d7c: 4798 blx r3
8003d7e: 3601 adds r6, #1
8003d80: e7ee b.n 8003d60 <__libc_init_array+0xc>
8003d82: f855 3b04 ldr.w r3, [r5], #4
8003d86: 4798 blx r3
8003d88: 3601 adds r6, #1
8003d8a: e7f2 b.n 8003d72 <__libc_init_array+0x1e>
8003d8c: 08004954 .word 0x08004954
8003d90: 08004954 .word 0x08004954
8003d94: 08004954 .word 0x08004954
8003d98: 08004958 .word 0x08004958
08003d9c <__retarget_lock_init_recursive>:
8003d9c: 4770 bx lr
08003d9e <__retarget_lock_acquire_recursive>:
8003d9e: 4770 bx lr
08003da0 <__retarget_lock_release_recursive>:
8003da0: 4770 bx lr
...
08003da4 <_free_r>:
8003da4: b538 push {r3, r4, r5, lr}
8003da6: 4605 mov r5, r0
8003da8: 2900 cmp r1, #0
8003daa: d041 beq.n 8003e30 <_free_r+0x8c>
8003dac: f851 3c04 ldr.w r3, [r1, #-4]
8003db0: 1f0c subs r4, r1, #4
8003db2: 2b00 cmp r3, #0
8003db4: bfb8 it lt
8003db6: 18e4 addlt r4, r4, r3
8003db8: f000 f8e0 bl 8003f7c <__malloc_lock>
8003dbc: 4a1d ldr r2, [pc, #116] @ (8003e34 <_free_r+0x90>)
8003dbe: 6813 ldr r3, [r2, #0]
8003dc0: b933 cbnz r3, 8003dd0 <_free_r+0x2c>
8003dc2: 6063 str r3, [r4, #4]
8003dc4: 6014 str r4, [r2, #0]
8003dc6: 4628 mov r0, r5
8003dc8: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
8003dcc: f000 b8dc b.w 8003f88 <__malloc_unlock>
8003dd0: 42a3 cmp r3, r4
8003dd2: d908 bls.n 8003de6 <_free_r+0x42>
8003dd4: 6820 ldr r0, [r4, #0]
8003dd6: 1821 adds r1, r4, r0
8003dd8: 428b cmp r3, r1
8003dda: bf01 itttt eq
8003ddc: 6819 ldreq r1, [r3, #0]
8003dde: 685b ldreq r3, [r3, #4]
8003de0: 1809 addeq r1, r1, r0
8003de2: 6021 streq r1, [r4, #0]
8003de4: e7ed b.n 8003dc2 <_free_r+0x1e>
8003de6: 461a mov r2, r3
8003de8: 685b ldr r3, [r3, #4]
8003dea: b10b cbz r3, 8003df0 <_free_r+0x4c>
8003dec: 42a3 cmp r3, r4
8003dee: d9fa bls.n 8003de6 <_free_r+0x42>
8003df0: 6811 ldr r1, [r2, #0]
8003df2: 1850 adds r0, r2, r1
8003df4: 42a0 cmp r0, r4
8003df6: d10b bne.n 8003e10 <_free_r+0x6c>
8003df8: 6820 ldr r0, [r4, #0]
8003dfa: 4401 add r1, r0
8003dfc: 1850 adds r0, r2, r1
8003dfe: 4283 cmp r3, r0
8003e00: 6011 str r1, [r2, #0]
8003e02: d1e0 bne.n 8003dc6 <_free_r+0x22>
8003e04: 6818 ldr r0, [r3, #0]
8003e06: 685b ldr r3, [r3, #4]
8003e08: 6053 str r3, [r2, #4]
8003e0a: 4408 add r0, r1
8003e0c: 6010 str r0, [r2, #0]
8003e0e: e7da b.n 8003dc6 <_free_r+0x22>
8003e10: d902 bls.n 8003e18 <_free_r+0x74>
8003e12: 230c movs r3, #12
8003e14: 602b str r3, [r5, #0]
8003e16: e7d6 b.n 8003dc6 <_free_r+0x22>
8003e18: 6820 ldr r0, [r4, #0]
8003e1a: 1821 adds r1, r4, r0
8003e1c: 428b cmp r3, r1
8003e1e: bf04 itt eq
8003e20: 6819 ldreq r1, [r3, #0]
8003e22: 685b ldreq r3, [r3, #4]
8003e24: 6063 str r3, [r4, #4]
8003e26: bf04 itt eq
8003e28: 1809 addeq r1, r1, r0
8003e2a: 6021 streq r1, [r4, #0]
8003e2c: 6054 str r4, [r2, #4]
8003e2e: e7ca b.n 8003dc6 <_free_r+0x22>
8003e30: bd38 pop {r3, r4, r5, pc}
8003e32: bf00 nop
8003e34: 200002a8 .word 0x200002a8
08003e38 <sbrk_aligned>:
8003e38: b570 push {r4, r5, r6, lr}
8003e3a: 4e0f ldr r6, [pc, #60] @ (8003e78 <sbrk_aligned+0x40>)
8003e3c: 460c mov r4, r1
8003e3e: 6831 ldr r1, [r6, #0]
8003e40: 4605 mov r5, r0
8003e42: b911 cbnz r1, 8003e4a <sbrk_aligned+0x12>
8003e44: f000 fcb4 bl 80047b0 <_sbrk_r>
8003e48: 6030 str r0, [r6, #0]
8003e4a: 4621 mov r1, r4
8003e4c: 4628 mov r0, r5
8003e4e: f000 fcaf bl 80047b0 <_sbrk_r>
8003e52: 1c43 adds r3, r0, #1
8003e54: d103 bne.n 8003e5e <sbrk_aligned+0x26>
8003e56: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff
8003e5a: 4620 mov r0, r4
8003e5c: bd70 pop {r4, r5, r6, pc}
8003e5e: 1cc4 adds r4, r0, #3
8003e60: f024 0403 bic.w r4, r4, #3
8003e64: 42a0 cmp r0, r4
8003e66: d0f8 beq.n 8003e5a <sbrk_aligned+0x22>
8003e68: 1a21 subs r1, r4, r0
8003e6a: 4628 mov r0, r5
8003e6c: f000 fca0 bl 80047b0 <_sbrk_r>
8003e70: 3001 adds r0, #1
8003e72: d1f2 bne.n 8003e5a <sbrk_aligned+0x22>
8003e74: e7ef b.n 8003e56 <sbrk_aligned+0x1e>
8003e76: bf00 nop
8003e78: 200002a4 .word 0x200002a4
08003e7c <_malloc_r>:
8003e7c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
8003e80: 1ccd adds r5, r1, #3
8003e82: f025 0503 bic.w r5, r5, #3
8003e86: 3508 adds r5, #8
8003e88: 2d0c cmp r5, #12
8003e8a: bf38 it cc
8003e8c: 250c movcc r5, #12
8003e8e: 2d00 cmp r5, #0
8003e90: 4606 mov r6, r0
8003e92: db01 blt.n 8003e98 <_malloc_r+0x1c>
8003e94: 42a9 cmp r1, r5
8003e96: d904 bls.n 8003ea2 <_malloc_r+0x26>
8003e98: 230c movs r3, #12
8003e9a: 6033 str r3, [r6, #0]
8003e9c: 2000 movs r0, #0
8003e9e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
8003ea2: f8df 80d4 ldr.w r8, [pc, #212] @ 8003f78 <_malloc_r+0xfc>
8003ea6: f000 f869 bl 8003f7c <__malloc_lock>
8003eaa: f8d8 3000 ldr.w r3, [r8]
8003eae: 461c mov r4, r3
8003eb0: bb44 cbnz r4, 8003f04 <_malloc_r+0x88>
8003eb2: 4629 mov r1, r5
8003eb4: 4630 mov r0, r6
8003eb6: f7ff ffbf bl 8003e38 <sbrk_aligned>
8003eba: 1c43 adds r3, r0, #1
8003ebc: 4604 mov r4, r0
8003ebe: d158 bne.n 8003f72 <_malloc_r+0xf6>
8003ec0: f8d8 4000 ldr.w r4, [r8]
8003ec4: 4627 mov r7, r4
8003ec6: 2f00 cmp r7, #0
8003ec8: d143 bne.n 8003f52 <_malloc_r+0xd6>
8003eca: 2c00 cmp r4, #0
8003ecc: d04b beq.n 8003f66 <_malloc_r+0xea>
8003ece: 6823 ldr r3, [r4, #0]
8003ed0: 4639 mov r1, r7
8003ed2: 4630 mov r0, r6
8003ed4: eb04 0903 add.w r9, r4, r3
8003ed8: f000 fc6a bl 80047b0 <_sbrk_r>
8003edc: 4581 cmp r9, r0
8003ede: d142 bne.n 8003f66 <_malloc_r+0xea>
8003ee0: 6821 ldr r1, [r4, #0]
8003ee2: 1a6d subs r5, r5, r1
8003ee4: 4629 mov r1, r5
8003ee6: 4630 mov r0, r6
8003ee8: f7ff ffa6 bl 8003e38 <sbrk_aligned>
8003eec: 3001 adds r0, #1
8003eee: d03a beq.n 8003f66 <_malloc_r+0xea>
8003ef0: 6823 ldr r3, [r4, #0]
8003ef2: 442b add r3, r5
8003ef4: 6023 str r3, [r4, #0]
8003ef6: f8d8 3000 ldr.w r3, [r8]
8003efa: 685a ldr r2, [r3, #4]
8003efc: bb62 cbnz r2, 8003f58 <_malloc_r+0xdc>
8003efe: f8c8 7000 str.w r7, [r8]
8003f02: e00f b.n 8003f24 <_malloc_r+0xa8>
8003f04: 6822 ldr r2, [r4, #0]
8003f06: 1b52 subs r2, r2, r5
8003f08: d420 bmi.n 8003f4c <_malloc_r+0xd0>
8003f0a: 2a0b cmp r2, #11
8003f0c: d917 bls.n 8003f3e <_malloc_r+0xc2>
8003f0e: 1961 adds r1, r4, r5
8003f10: 42a3 cmp r3, r4
8003f12: 6025 str r5, [r4, #0]
8003f14: bf18 it ne
8003f16: 6059 strne r1, [r3, #4]
8003f18: 6863 ldr r3, [r4, #4]
8003f1a: bf08 it eq
8003f1c: f8c8 1000 streq.w r1, [r8]
8003f20: 5162 str r2, [r4, r5]
8003f22: 604b str r3, [r1, #4]
8003f24: 4630 mov r0, r6
8003f26: f000 f82f bl 8003f88 <__malloc_unlock>
8003f2a: f104 000b add.w r0, r4, #11
8003f2e: 1d23 adds r3, r4, #4
8003f30: f020 0007 bic.w r0, r0, #7
8003f34: 1ac2 subs r2, r0, r3
8003f36: bf1c itt ne
8003f38: 1a1b subne r3, r3, r0
8003f3a: 50a3 strne r3, [r4, r2]
8003f3c: e7af b.n 8003e9e <_malloc_r+0x22>
8003f3e: 6862 ldr r2, [r4, #4]
8003f40: 42a3 cmp r3, r4
8003f42: bf0c ite eq
8003f44: f8c8 2000 streq.w r2, [r8]
8003f48: 605a strne r2, [r3, #4]
8003f4a: e7eb b.n 8003f24 <_malloc_r+0xa8>
8003f4c: 4623 mov r3, r4
8003f4e: 6864 ldr r4, [r4, #4]
8003f50: e7ae b.n 8003eb0 <_malloc_r+0x34>
8003f52: 463c mov r4, r7
8003f54: 687f ldr r7, [r7, #4]
8003f56: e7b6 b.n 8003ec6 <_malloc_r+0x4a>
8003f58: 461a mov r2, r3
8003f5a: 685b ldr r3, [r3, #4]
8003f5c: 42a3 cmp r3, r4
8003f5e: d1fb bne.n 8003f58 <_malloc_r+0xdc>
8003f60: 2300 movs r3, #0
8003f62: 6053 str r3, [r2, #4]
8003f64: e7de b.n 8003f24 <_malloc_r+0xa8>
8003f66: 230c movs r3, #12
8003f68: 6033 str r3, [r6, #0]
8003f6a: 4630 mov r0, r6
8003f6c: f000 f80c bl 8003f88 <__malloc_unlock>
8003f70: e794 b.n 8003e9c <_malloc_r+0x20>
8003f72: 6005 str r5, [r0, #0]
8003f74: e7d6 b.n 8003f24 <_malloc_r+0xa8>
8003f76: bf00 nop
8003f78: 200002a8 .word 0x200002a8
08003f7c <__malloc_lock>:
8003f7c: 4801 ldr r0, [pc, #4] @ (8003f84 <__malloc_lock+0x8>)
8003f7e: f7ff bf0e b.w 8003d9e <__retarget_lock_acquire_recursive>
8003f82: bf00 nop
8003f84: 200002a0 .word 0x200002a0
08003f88 <__malloc_unlock>:
8003f88: 4801 ldr r0, [pc, #4] @ (8003f90 <__malloc_unlock+0x8>)
8003f8a: f7ff bf09 b.w 8003da0 <__retarget_lock_release_recursive>
8003f8e: bf00 nop
8003f90: 200002a0 .word 0x200002a0
08003f94 <__sfputc_r>:
8003f94: 6893 ldr r3, [r2, #8]
8003f96: 3b01 subs r3, #1
8003f98: 2b00 cmp r3, #0
8003f9a: b410 push {r4}
8003f9c: 6093 str r3, [r2, #8]
8003f9e: da08 bge.n 8003fb2 <__sfputc_r+0x1e>
8003fa0: 6994 ldr r4, [r2, #24]
8003fa2: 42a3 cmp r3, r4
8003fa4: db01 blt.n 8003faa <__sfputc_r+0x16>
8003fa6: 290a cmp r1, #10
8003fa8: d103 bne.n 8003fb2 <__sfputc_r+0x1e>
8003faa: f85d 4b04 ldr.w r4, [sp], #4
8003fae: f000 bb6b b.w 8004688 <__swbuf_r>
8003fb2: 6813 ldr r3, [r2, #0]
8003fb4: 1c58 adds r0, r3, #1
8003fb6: 6010 str r0, [r2, #0]
8003fb8: 7019 strb r1, [r3, #0]
8003fba: 4608 mov r0, r1
8003fbc: f85d 4b04 ldr.w r4, [sp], #4
8003fc0: 4770 bx lr
08003fc2 <__sfputs_r>:
8003fc2: b5f8 push {r3, r4, r5, r6, r7, lr}
8003fc4: 4606 mov r6, r0
8003fc6: 460f mov r7, r1
8003fc8: 4614 mov r4, r2
8003fca: 18d5 adds r5, r2, r3
8003fcc: 42ac cmp r4, r5
8003fce: d101 bne.n 8003fd4 <__sfputs_r+0x12>
8003fd0: 2000 movs r0, #0
8003fd2: e007 b.n 8003fe4 <__sfputs_r+0x22>
8003fd4: f814 1b01 ldrb.w r1, [r4], #1
8003fd8: 463a mov r2, r7
8003fda: 4630 mov r0, r6
8003fdc: f7ff ffda bl 8003f94 <__sfputc_r>
8003fe0: 1c43 adds r3, r0, #1
8003fe2: d1f3 bne.n 8003fcc <__sfputs_r+0xa>
8003fe4: bdf8 pop {r3, r4, r5, r6, r7, pc}
...
08003fe8 <_vfiprintf_r>:
8003fe8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8003fec: 460d mov r5, r1
8003fee: b09d sub sp, #116 @ 0x74
8003ff0: 4614 mov r4, r2
8003ff2: 4698 mov r8, r3
8003ff4: 4606 mov r6, r0
8003ff6: b118 cbz r0, 8004000 <_vfiprintf_r+0x18>
8003ff8: 6a03 ldr r3, [r0, #32]
8003ffa: b90b cbnz r3, 8004000 <_vfiprintf_r+0x18>
8003ffc: f7ff fdca bl 8003b94 <__sinit>
8004000: 6e6b ldr r3, [r5, #100] @ 0x64
8004002: 07d9 lsls r1, r3, #31
8004004: d405 bmi.n 8004012 <_vfiprintf_r+0x2a>
8004006: 89ab ldrh r3, [r5, #12]
8004008: 059a lsls r2, r3, #22
800400a: d402 bmi.n 8004012 <_vfiprintf_r+0x2a>
800400c: 6da8 ldr r0, [r5, #88] @ 0x58
800400e: f7ff fec6 bl 8003d9e <__retarget_lock_acquire_recursive>
8004012: 89ab ldrh r3, [r5, #12]
8004014: 071b lsls r3, r3, #28
8004016: d501 bpl.n 800401c <_vfiprintf_r+0x34>
8004018: 692b ldr r3, [r5, #16]
800401a: b99b cbnz r3, 8004044 <_vfiprintf_r+0x5c>
800401c: 4629 mov r1, r5
800401e: 4630 mov r0, r6
8004020: f000 fb70 bl 8004704 <__swsetup_r>
8004024: b170 cbz r0, 8004044 <_vfiprintf_r+0x5c>
8004026: 6e6b ldr r3, [r5, #100] @ 0x64
8004028: 07dc lsls r4, r3, #31
800402a: d504 bpl.n 8004036 <_vfiprintf_r+0x4e>
800402c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8004030: b01d add sp, #116 @ 0x74
8004032: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8004036: 89ab ldrh r3, [r5, #12]
8004038: 0598 lsls r0, r3, #22
800403a: d4f7 bmi.n 800402c <_vfiprintf_r+0x44>
800403c: 6da8 ldr r0, [r5, #88] @ 0x58
800403e: f7ff feaf bl 8003da0 <__retarget_lock_release_recursive>
8004042: e7f3 b.n 800402c <_vfiprintf_r+0x44>
8004044: 2300 movs r3, #0
8004046: 9309 str r3, [sp, #36] @ 0x24
8004048: 2320 movs r3, #32
800404a: f88d 3029 strb.w r3, [sp, #41] @ 0x29
800404e: f8cd 800c str.w r8, [sp, #12]
8004052: 2330 movs r3, #48 @ 0x30
8004054: f8df 81ac ldr.w r8, [pc, #428] @ 8004204 <_vfiprintf_r+0x21c>
8004058: f88d 302a strb.w r3, [sp, #42] @ 0x2a
800405c: f04f 0901 mov.w r9, #1
8004060: 4623 mov r3, r4
8004062: 469a mov sl, r3
8004064: f813 2b01 ldrb.w r2, [r3], #1
8004068: b10a cbz r2, 800406e <_vfiprintf_r+0x86>
800406a: 2a25 cmp r2, #37 @ 0x25
800406c: d1f9 bne.n 8004062 <_vfiprintf_r+0x7a>
800406e: ebba 0b04 subs.w fp, sl, r4
8004072: d00b beq.n 800408c <_vfiprintf_r+0xa4>
8004074: 465b mov r3, fp
8004076: 4622 mov r2, r4
8004078: 4629 mov r1, r5
800407a: 4630 mov r0, r6
800407c: f7ff ffa1 bl 8003fc2 <__sfputs_r>
8004080: 3001 adds r0, #1
8004082: f000 80a7 beq.w 80041d4 <_vfiprintf_r+0x1ec>
8004086: 9a09 ldr r2, [sp, #36] @ 0x24
8004088: 445a add r2, fp
800408a: 9209 str r2, [sp, #36] @ 0x24
800408c: f89a 3000 ldrb.w r3, [sl]
8004090: 2b00 cmp r3, #0
8004092: f000 809f beq.w 80041d4 <_vfiprintf_r+0x1ec>
8004096: 2300 movs r3, #0
8004098: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
800409c: e9cd 2305 strd r2, r3, [sp, #20]
80040a0: f10a 0a01 add.w sl, sl, #1
80040a4: 9304 str r3, [sp, #16]
80040a6: 9307 str r3, [sp, #28]
80040a8: f88d 3053 strb.w r3, [sp, #83] @ 0x53
80040ac: 931a str r3, [sp, #104] @ 0x68
80040ae: 4654 mov r4, sl
80040b0: 2205 movs r2, #5
80040b2: f814 1b01 ldrb.w r1, [r4], #1
80040b6: 4853 ldr r0, [pc, #332] @ (8004204 <_vfiprintf_r+0x21c>)
80040b8: f7fc f8b2 bl 8000220 <memchr>
80040bc: 9a04 ldr r2, [sp, #16]
80040be: b9d8 cbnz r0, 80040f8 <_vfiprintf_r+0x110>
80040c0: 06d1 lsls r1, r2, #27
80040c2: bf44 itt mi
80040c4: 2320 movmi r3, #32
80040c6: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
80040ca: 0713 lsls r3, r2, #28
80040cc: bf44 itt mi
80040ce: 232b movmi r3, #43 @ 0x2b
80040d0: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
80040d4: f89a 3000 ldrb.w r3, [sl]
80040d8: 2b2a cmp r3, #42 @ 0x2a
80040da: d015 beq.n 8004108 <_vfiprintf_r+0x120>
80040dc: 9a07 ldr r2, [sp, #28]
80040de: 4654 mov r4, sl
80040e0: 2000 movs r0, #0
80040e2: f04f 0c0a mov.w ip, #10
80040e6: 4621 mov r1, r4
80040e8: f811 3b01 ldrb.w r3, [r1], #1
80040ec: 3b30 subs r3, #48 @ 0x30
80040ee: 2b09 cmp r3, #9
80040f0: d94b bls.n 800418a <_vfiprintf_r+0x1a2>
80040f2: b1b0 cbz r0, 8004122 <_vfiprintf_r+0x13a>
80040f4: 9207 str r2, [sp, #28]
80040f6: e014 b.n 8004122 <_vfiprintf_r+0x13a>
80040f8: eba0 0308 sub.w r3, r0, r8
80040fc: fa09 f303 lsl.w r3, r9, r3
8004100: 4313 orrs r3, r2
8004102: 9304 str r3, [sp, #16]
8004104: 46a2 mov sl, r4
8004106: e7d2 b.n 80040ae <_vfiprintf_r+0xc6>
8004108: 9b03 ldr r3, [sp, #12]
800410a: 1d19 adds r1, r3, #4
800410c: 681b ldr r3, [r3, #0]
800410e: 9103 str r1, [sp, #12]
8004110: 2b00 cmp r3, #0
8004112: bfbb ittet lt
8004114: 425b neglt r3, r3
8004116: f042 0202 orrlt.w r2, r2, #2
800411a: 9307 strge r3, [sp, #28]
800411c: 9307 strlt r3, [sp, #28]
800411e: bfb8 it lt
8004120: 9204 strlt r2, [sp, #16]
8004122: 7823 ldrb r3, [r4, #0]
8004124: 2b2e cmp r3, #46 @ 0x2e
8004126: d10a bne.n 800413e <_vfiprintf_r+0x156>
8004128: 7863 ldrb r3, [r4, #1]
800412a: 2b2a cmp r3, #42 @ 0x2a
800412c: d132 bne.n 8004194 <_vfiprintf_r+0x1ac>
800412e: 9b03 ldr r3, [sp, #12]
8004130: 1d1a adds r2, r3, #4
8004132: 681b ldr r3, [r3, #0]
8004134: 9203 str r2, [sp, #12]
8004136: ea43 73e3 orr.w r3, r3, r3, asr #31
800413a: 3402 adds r4, #2
800413c: 9305 str r3, [sp, #20]
800413e: f8df a0d4 ldr.w sl, [pc, #212] @ 8004214 <_vfiprintf_r+0x22c>
8004142: 7821 ldrb r1, [r4, #0]
8004144: 2203 movs r2, #3
8004146: 4650 mov r0, sl
8004148: f7fc f86a bl 8000220 <memchr>
800414c: b138 cbz r0, 800415e <_vfiprintf_r+0x176>
800414e: 9b04 ldr r3, [sp, #16]
8004150: eba0 000a sub.w r0, r0, sl
8004154: 2240 movs r2, #64 @ 0x40
8004156: 4082 lsls r2, r0
8004158: 4313 orrs r3, r2
800415a: 3401 adds r4, #1
800415c: 9304 str r3, [sp, #16]
800415e: f814 1b01 ldrb.w r1, [r4], #1
8004162: 4829 ldr r0, [pc, #164] @ (8004208 <_vfiprintf_r+0x220>)
8004164: f88d 1028 strb.w r1, [sp, #40] @ 0x28
8004168: 2206 movs r2, #6
800416a: f7fc f859 bl 8000220 <memchr>
800416e: 2800 cmp r0, #0
8004170: d03f beq.n 80041f2 <_vfiprintf_r+0x20a>
8004172: 4b26 ldr r3, [pc, #152] @ (800420c <_vfiprintf_r+0x224>)
8004174: bb1b cbnz r3, 80041be <_vfiprintf_r+0x1d6>
8004176: 9b03 ldr r3, [sp, #12]
8004178: 3307 adds r3, #7
800417a: f023 0307 bic.w r3, r3, #7
800417e: 3308 adds r3, #8
8004180: 9303 str r3, [sp, #12]
8004182: 9b09 ldr r3, [sp, #36] @ 0x24
8004184: 443b add r3, r7
8004186: 9309 str r3, [sp, #36] @ 0x24
8004188: e76a b.n 8004060 <_vfiprintf_r+0x78>
800418a: fb0c 3202 mla r2, ip, r2, r3
800418e: 460c mov r4, r1
8004190: 2001 movs r0, #1
8004192: e7a8 b.n 80040e6 <_vfiprintf_r+0xfe>
8004194: 2300 movs r3, #0
8004196: 3401 adds r4, #1
8004198: 9305 str r3, [sp, #20]
800419a: 4619 mov r1, r3
800419c: f04f 0c0a mov.w ip, #10
80041a0: 4620 mov r0, r4
80041a2: f810 2b01 ldrb.w r2, [r0], #1
80041a6: 3a30 subs r2, #48 @ 0x30
80041a8: 2a09 cmp r2, #9
80041aa: d903 bls.n 80041b4 <_vfiprintf_r+0x1cc>
80041ac: 2b00 cmp r3, #0
80041ae: d0c6 beq.n 800413e <_vfiprintf_r+0x156>
80041b0: 9105 str r1, [sp, #20]
80041b2: e7c4 b.n 800413e <_vfiprintf_r+0x156>
80041b4: fb0c 2101 mla r1, ip, r1, r2
80041b8: 4604 mov r4, r0
80041ba: 2301 movs r3, #1
80041bc: e7f0 b.n 80041a0 <_vfiprintf_r+0x1b8>
80041be: ab03 add r3, sp, #12
80041c0: 9300 str r3, [sp, #0]
80041c2: 462a mov r2, r5
80041c4: 4b12 ldr r3, [pc, #72] @ (8004210 <_vfiprintf_r+0x228>)
80041c6: a904 add r1, sp, #16
80041c8: 4630 mov r0, r6
80041ca: f3af 8000 nop.w
80041ce: 4607 mov r7, r0
80041d0: 1c78 adds r0, r7, #1
80041d2: d1d6 bne.n 8004182 <_vfiprintf_r+0x19a>
80041d4: 6e6b ldr r3, [r5, #100] @ 0x64
80041d6: 07d9 lsls r1, r3, #31
80041d8: d405 bmi.n 80041e6 <_vfiprintf_r+0x1fe>
80041da: 89ab ldrh r3, [r5, #12]
80041dc: 059a lsls r2, r3, #22
80041de: d402 bmi.n 80041e6 <_vfiprintf_r+0x1fe>
80041e0: 6da8 ldr r0, [r5, #88] @ 0x58
80041e2: f7ff fddd bl 8003da0 <__retarget_lock_release_recursive>
80041e6: 89ab ldrh r3, [r5, #12]
80041e8: 065b lsls r3, r3, #25
80041ea: f53f af1f bmi.w 800402c <_vfiprintf_r+0x44>
80041ee: 9809 ldr r0, [sp, #36] @ 0x24
80041f0: e71e b.n 8004030 <_vfiprintf_r+0x48>
80041f2: ab03 add r3, sp, #12
80041f4: 9300 str r3, [sp, #0]
80041f6: 462a mov r2, r5
80041f8: 4b05 ldr r3, [pc, #20] @ (8004210 <_vfiprintf_r+0x228>)
80041fa: a904 add r1, sp, #16
80041fc: 4630 mov r0, r6
80041fe: f000 f879 bl 80042f4 <_printf_i>
8004202: e7e4 b.n 80041ce <_vfiprintf_r+0x1e6>
8004204: 08004918 .word 0x08004918
8004208: 08004922 .word 0x08004922
800420c: 00000000 .word 0x00000000
8004210: 08003fc3 .word 0x08003fc3
8004214: 0800491e .word 0x0800491e
08004218 <_printf_common>:
8004218: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800421c: 4616 mov r6, r2
800421e: 4698 mov r8, r3
8004220: 688a ldr r2, [r1, #8]
8004222: 690b ldr r3, [r1, #16]
8004224: f8dd 9020 ldr.w r9, [sp, #32]
8004228: 4293 cmp r3, r2
800422a: bfb8 it lt
800422c: 4613 movlt r3, r2
800422e: 6033 str r3, [r6, #0]
8004230: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
8004234: 4607 mov r7, r0
8004236: 460c mov r4, r1
8004238: b10a cbz r2, 800423e <_printf_common+0x26>
800423a: 3301 adds r3, #1
800423c: 6033 str r3, [r6, #0]
800423e: 6823 ldr r3, [r4, #0]
8004240: 0699 lsls r1, r3, #26
8004242: bf42 ittt mi
8004244: 6833 ldrmi r3, [r6, #0]
8004246: 3302 addmi r3, #2
8004248: 6033 strmi r3, [r6, #0]
800424a: 6825 ldr r5, [r4, #0]
800424c: f015 0506 ands.w r5, r5, #6
8004250: d106 bne.n 8004260 <_printf_common+0x48>
8004252: f104 0a19 add.w sl, r4, #25
8004256: 68e3 ldr r3, [r4, #12]
8004258: 6832 ldr r2, [r6, #0]
800425a: 1a9b subs r3, r3, r2
800425c: 42ab cmp r3, r5
800425e: dc26 bgt.n 80042ae <_printf_common+0x96>
8004260: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
8004264: 6822 ldr r2, [r4, #0]
8004266: 3b00 subs r3, #0
8004268: bf18 it ne
800426a: 2301 movne r3, #1
800426c: 0692 lsls r2, r2, #26
800426e: d42b bmi.n 80042c8 <_printf_common+0xb0>
8004270: f104 0243 add.w r2, r4, #67 @ 0x43
8004274: 4641 mov r1, r8
8004276: 4638 mov r0, r7
8004278: 47c8 blx r9
800427a: 3001 adds r0, #1
800427c: d01e beq.n 80042bc <_printf_common+0xa4>
800427e: 6823 ldr r3, [r4, #0]
8004280: 6922 ldr r2, [r4, #16]
8004282: f003 0306 and.w r3, r3, #6
8004286: 2b04 cmp r3, #4
8004288: bf02 ittt eq
800428a: 68e5 ldreq r5, [r4, #12]
800428c: 6833 ldreq r3, [r6, #0]
800428e: 1aed subeq r5, r5, r3
8004290: 68a3 ldr r3, [r4, #8]
8004292: bf0c ite eq
8004294: ea25 75e5 biceq.w r5, r5, r5, asr #31
8004298: 2500 movne r5, #0
800429a: 4293 cmp r3, r2
800429c: bfc4 itt gt
800429e: 1a9b subgt r3, r3, r2
80042a0: 18ed addgt r5, r5, r3
80042a2: 2600 movs r6, #0
80042a4: 341a adds r4, #26
80042a6: 42b5 cmp r5, r6
80042a8: d11a bne.n 80042e0 <_printf_common+0xc8>
80042aa: 2000 movs r0, #0
80042ac: e008 b.n 80042c0 <_printf_common+0xa8>
80042ae: 2301 movs r3, #1
80042b0: 4652 mov r2, sl
80042b2: 4641 mov r1, r8
80042b4: 4638 mov r0, r7
80042b6: 47c8 blx r9
80042b8: 3001 adds r0, #1
80042ba: d103 bne.n 80042c4 <_printf_common+0xac>
80042bc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
80042c0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80042c4: 3501 adds r5, #1
80042c6: e7c6 b.n 8004256 <_printf_common+0x3e>
80042c8: 18e1 adds r1, r4, r3
80042ca: 1c5a adds r2, r3, #1
80042cc: 2030 movs r0, #48 @ 0x30
80042ce: f881 0043 strb.w r0, [r1, #67] @ 0x43
80042d2: 4422 add r2, r4
80042d4: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
80042d8: f882 1043 strb.w r1, [r2, #67] @ 0x43
80042dc: 3302 adds r3, #2
80042de: e7c7 b.n 8004270 <_printf_common+0x58>
80042e0: 2301 movs r3, #1
80042e2: 4622 mov r2, r4
80042e4: 4641 mov r1, r8
80042e6: 4638 mov r0, r7
80042e8: 47c8 blx r9
80042ea: 3001 adds r0, #1
80042ec: d0e6 beq.n 80042bc <_printf_common+0xa4>
80042ee: 3601 adds r6, #1
80042f0: e7d9 b.n 80042a6 <_printf_common+0x8e>
...
080042f4 <_printf_i>:
80042f4: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
80042f8: 7e0f ldrb r7, [r1, #24]
80042fa: 9e0c ldr r6, [sp, #48] @ 0x30
80042fc: 2f78 cmp r7, #120 @ 0x78
80042fe: 4691 mov r9, r2
8004300: 4680 mov r8, r0
8004302: 460c mov r4, r1
8004304: 469a mov sl, r3
8004306: f101 0243 add.w r2, r1, #67 @ 0x43
800430a: d807 bhi.n 800431c <_printf_i+0x28>
800430c: 2f62 cmp r7, #98 @ 0x62
800430e: d80a bhi.n 8004326 <_printf_i+0x32>
8004310: 2f00 cmp r7, #0
8004312: f000 80d1 beq.w 80044b8 <_printf_i+0x1c4>
8004316: 2f58 cmp r7, #88 @ 0x58
8004318: f000 80b8 beq.w 800448c <_printf_i+0x198>
800431c: f104 0642 add.w r6, r4, #66 @ 0x42
8004320: f884 7042 strb.w r7, [r4, #66] @ 0x42
8004324: e03a b.n 800439c <_printf_i+0xa8>
8004326: f1a7 0363 sub.w r3, r7, #99 @ 0x63
800432a: 2b15 cmp r3, #21
800432c: d8f6 bhi.n 800431c <_printf_i+0x28>
800432e: a101 add r1, pc, #4 @ (adr r1, 8004334 <_printf_i+0x40>)
8004330: f851 f023 ldr.w pc, [r1, r3, lsl #2]
8004334: 0800438d .word 0x0800438d
8004338: 080043a1 .word 0x080043a1
800433c: 0800431d .word 0x0800431d
8004340: 0800431d .word 0x0800431d
8004344: 0800431d .word 0x0800431d
8004348: 0800431d .word 0x0800431d
800434c: 080043a1 .word 0x080043a1
8004350: 0800431d .word 0x0800431d
8004354: 0800431d .word 0x0800431d
8004358: 0800431d .word 0x0800431d
800435c: 0800431d .word 0x0800431d
8004360: 0800449f .word 0x0800449f
8004364: 080043cb .word 0x080043cb
8004368: 08004459 .word 0x08004459
800436c: 0800431d .word 0x0800431d
8004370: 0800431d .word 0x0800431d
8004374: 080044c1 .word 0x080044c1
8004378: 0800431d .word 0x0800431d
800437c: 080043cb .word 0x080043cb
8004380: 0800431d .word 0x0800431d
8004384: 0800431d .word 0x0800431d
8004388: 08004461 .word 0x08004461
800438c: 6833 ldr r3, [r6, #0]
800438e: 1d1a adds r2, r3, #4
8004390: 681b ldr r3, [r3, #0]
8004392: 6032 str r2, [r6, #0]
8004394: f104 0642 add.w r6, r4, #66 @ 0x42
8004398: f884 3042 strb.w r3, [r4, #66] @ 0x42
800439c: 2301 movs r3, #1
800439e: e09c b.n 80044da <_printf_i+0x1e6>
80043a0: 6833 ldr r3, [r6, #0]
80043a2: 6820 ldr r0, [r4, #0]
80043a4: 1d19 adds r1, r3, #4
80043a6: 6031 str r1, [r6, #0]
80043a8: 0606 lsls r6, r0, #24
80043aa: d501 bpl.n 80043b0 <_printf_i+0xbc>
80043ac: 681d ldr r5, [r3, #0]
80043ae: e003 b.n 80043b8 <_printf_i+0xc4>
80043b0: 0645 lsls r5, r0, #25
80043b2: d5fb bpl.n 80043ac <_printf_i+0xb8>
80043b4: f9b3 5000 ldrsh.w r5, [r3]
80043b8: 2d00 cmp r5, #0
80043ba: da03 bge.n 80043c4 <_printf_i+0xd0>
80043bc: 232d movs r3, #45 @ 0x2d
80043be: 426d negs r5, r5
80043c0: f884 3043 strb.w r3, [r4, #67] @ 0x43
80043c4: 4858 ldr r0, [pc, #352] @ (8004528 <_printf_i+0x234>)
80043c6: 230a movs r3, #10
80043c8: e011 b.n 80043ee <_printf_i+0xfa>
80043ca: 6821 ldr r1, [r4, #0]
80043cc: 6833 ldr r3, [r6, #0]
80043ce: 0608 lsls r0, r1, #24
80043d0: f853 5b04 ldr.w r5, [r3], #4
80043d4: d402 bmi.n 80043dc <_printf_i+0xe8>
80043d6: 0649 lsls r1, r1, #25
80043d8: bf48 it mi
80043da: b2ad uxthmi r5, r5
80043dc: 2f6f cmp r7, #111 @ 0x6f
80043de: 4852 ldr r0, [pc, #328] @ (8004528 <_printf_i+0x234>)
80043e0: 6033 str r3, [r6, #0]
80043e2: bf14 ite ne
80043e4: 230a movne r3, #10
80043e6: 2308 moveq r3, #8
80043e8: 2100 movs r1, #0
80043ea: f884 1043 strb.w r1, [r4, #67] @ 0x43
80043ee: 6866 ldr r6, [r4, #4]
80043f0: 60a6 str r6, [r4, #8]
80043f2: 2e00 cmp r6, #0
80043f4: db05 blt.n 8004402 <_printf_i+0x10e>
80043f6: 6821 ldr r1, [r4, #0]
80043f8: 432e orrs r6, r5
80043fa: f021 0104 bic.w r1, r1, #4
80043fe: 6021 str r1, [r4, #0]
8004400: d04b beq.n 800449a <_printf_i+0x1a6>
8004402: 4616 mov r6, r2
8004404: fbb5 f1f3 udiv r1, r5, r3
8004408: fb03 5711 mls r7, r3, r1, r5
800440c: 5dc7 ldrb r7, [r0, r7]
800440e: f806 7d01 strb.w r7, [r6, #-1]!
8004412: 462f mov r7, r5
8004414: 42bb cmp r3, r7
8004416: 460d mov r5, r1
8004418: d9f4 bls.n 8004404 <_printf_i+0x110>
800441a: 2b08 cmp r3, #8
800441c: d10b bne.n 8004436 <_printf_i+0x142>
800441e: 6823 ldr r3, [r4, #0]
8004420: 07df lsls r7, r3, #31
8004422: d508 bpl.n 8004436 <_printf_i+0x142>
8004424: 6923 ldr r3, [r4, #16]
8004426: 6861 ldr r1, [r4, #4]
8004428: 4299 cmp r1, r3
800442a: bfde ittt le
800442c: 2330 movle r3, #48 @ 0x30
800442e: f806 3c01 strble.w r3, [r6, #-1]
8004432: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff
8004436: 1b92 subs r2, r2, r6
8004438: 6122 str r2, [r4, #16]
800443a: f8cd a000 str.w sl, [sp]
800443e: 464b mov r3, r9
8004440: aa03 add r2, sp, #12
8004442: 4621 mov r1, r4
8004444: 4640 mov r0, r8
8004446: f7ff fee7 bl 8004218 <_printf_common>
800444a: 3001 adds r0, #1
800444c: d14a bne.n 80044e4 <_printf_i+0x1f0>
800444e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8004452: b004 add sp, #16
8004454: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8004458: 6823 ldr r3, [r4, #0]
800445a: f043 0320 orr.w r3, r3, #32
800445e: 6023 str r3, [r4, #0]
8004460: 4832 ldr r0, [pc, #200] @ (800452c <_printf_i+0x238>)
8004462: 2778 movs r7, #120 @ 0x78
8004464: f884 7045 strb.w r7, [r4, #69] @ 0x45
8004468: 6823 ldr r3, [r4, #0]
800446a: 6831 ldr r1, [r6, #0]
800446c: 061f lsls r7, r3, #24
800446e: f851 5b04 ldr.w r5, [r1], #4
8004472: d402 bmi.n 800447a <_printf_i+0x186>
8004474: 065f lsls r7, r3, #25
8004476: bf48 it mi
8004478: b2ad uxthmi r5, r5
800447a: 6031 str r1, [r6, #0]
800447c: 07d9 lsls r1, r3, #31
800447e: bf44 itt mi
8004480: f043 0320 orrmi.w r3, r3, #32
8004484: 6023 strmi r3, [r4, #0]
8004486: b11d cbz r5, 8004490 <_printf_i+0x19c>
8004488: 2310 movs r3, #16
800448a: e7ad b.n 80043e8 <_printf_i+0xf4>
800448c: 4826 ldr r0, [pc, #152] @ (8004528 <_printf_i+0x234>)
800448e: e7e9 b.n 8004464 <_printf_i+0x170>
8004490: 6823 ldr r3, [r4, #0]
8004492: f023 0320 bic.w r3, r3, #32
8004496: 6023 str r3, [r4, #0]
8004498: e7f6 b.n 8004488 <_printf_i+0x194>
800449a: 4616 mov r6, r2
800449c: e7bd b.n 800441a <_printf_i+0x126>
800449e: 6833 ldr r3, [r6, #0]
80044a0: 6825 ldr r5, [r4, #0]
80044a2: 6961 ldr r1, [r4, #20]
80044a4: 1d18 adds r0, r3, #4
80044a6: 6030 str r0, [r6, #0]
80044a8: 062e lsls r6, r5, #24
80044aa: 681b ldr r3, [r3, #0]
80044ac: d501 bpl.n 80044b2 <_printf_i+0x1be>
80044ae: 6019 str r1, [r3, #0]
80044b0: e002 b.n 80044b8 <_printf_i+0x1c4>
80044b2: 0668 lsls r0, r5, #25
80044b4: d5fb bpl.n 80044ae <_printf_i+0x1ba>
80044b6: 8019 strh r1, [r3, #0]
80044b8: 2300 movs r3, #0
80044ba: 6123 str r3, [r4, #16]
80044bc: 4616 mov r6, r2
80044be: e7bc b.n 800443a <_printf_i+0x146>
80044c0: 6833 ldr r3, [r6, #0]
80044c2: 1d1a adds r2, r3, #4
80044c4: 6032 str r2, [r6, #0]
80044c6: 681e ldr r6, [r3, #0]
80044c8: 6862 ldr r2, [r4, #4]
80044ca: 2100 movs r1, #0
80044cc: 4630 mov r0, r6
80044ce: f7fb fea7 bl 8000220 <memchr>
80044d2: b108 cbz r0, 80044d8 <_printf_i+0x1e4>
80044d4: 1b80 subs r0, r0, r6
80044d6: 6060 str r0, [r4, #4]
80044d8: 6863 ldr r3, [r4, #4]
80044da: 6123 str r3, [r4, #16]
80044dc: 2300 movs r3, #0
80044de: f884 3043 strb.w r3, [r4, #67] @ 0x43
80044e2: e7aa b.n 800443a <_printf_i+0x146>
80044e4: 6923 ldr r3, [r4, #16]
80044e6: 4632 mov r2, r6
80044e8: 4649 mov r1, r9
80044ea: 4640 mov r0, r8
80044ec: 47d0 blx sl
80044ee: 3001 adds r0, #1
80044f0: d0ad beq.n 800444e <_printf_i+0x15a>
80044f2: 6823 ldr r3, [r4, #0]
80044f4: 079b lsls r3, r3, #30
80044f6: d413 bmi.n 8004520 <_printf_i+0x22c>
80044f8: 68e0 ldr r0, [r4, #12]
80044fa: 9b03 ldr r3, [sp, #12]
80044fc: 4298 cmp r0, r3
80044fe: bfb8 it lt
8004500: 4618 movlt r0, r3
8004502: e7a6 b.n 8004452 <_printf_i+0x15e>
8004504: 2301 movs r3, #1
8004506: 4632 mov r2, r6
8004508: 4649 mov r1, r9
800450a: 4640 mov r0, r8
800450c: 47d0 blx sl
800450e: 3001 adds r0, #1
8004510: d09d beq.n 800444e <_printf_i+0x15a>
8004512: 3501 adds r5, #1
8004514: 68e3 ldr r3, [r4, #12]
8004516: 9903 ldr r1, [sp, #12]
8004518: 1a5b subs r3, r3, r1
800451a: 42ab cmp r3, r5
800451c: dcf2 bgt.n 8004504 <_printf_i+0x210>
800451e: e7eb b.n 80044f8 <_printf_i+0x204>
8004520: 2500 movs r5, #0
8004522: f104 0619 add.w r6, r4, #25
8004526: e7f5 b.n 8004514 <_printf_i+0x220>
8004528: 08004929 .word 0x08004929
800452c: 0800493a .word 0x0800493a
08004530 <__sflush_r>:
8004530: f9b1 200c ldrsh.w r2, [r1, #12]
8004534: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8004538: 0716 lsls r6, r2, #28
800453a: 4605 mov r5, r0
800453c: 460c mov r4, r1
800453e: d454 bmi.n 80045ea <__sflush_r+0xba>
8004540: 684b ldr r3, [r1, #4]
8004542: 2b00 cmp r3, #0
8004544: dc02 bgt.n 800454c <__sflush_r+0x1c>
8004546: 6c0b ldr r3, [r1, #64] @ 0x40
8004548: 2b00 cmp r3, #0
800454a: dd48 ble.n 80045de <__sflush_r+0xae>
800454c: 6ae6 ldr r6, [r4, #44] @ 0x2c
800454e: 2e00 cmp r6, #0
8004550: d045 beq.n 80045de <__sflush_r+0xae>
8004552: 2300 movs r3, #0
8004554: f412 5280 ands.w r2, r2, #4096 @ 0x1000
8004558: 682f ldr r7, [r5, #0]
800455a: 6a21 ldr r1, [r4, #32]
800455c: 602b str r3, [r5, #0]
800455e: d030 beq.n 80045c2 <__sflush_r+0x92>
8004560: 6d62 ldr r2, [r4, #84] @ 0x54
8004562: 89a3 ldrh r3, [r4, #12]
8004564: 0759 lsls r1, r3, #29
8004566: d505 bpl.n 8004574 <__sflush_r+0x44>
8004568: 6863 ldr r3, [r4, #4]
800456a: 1ad2 subs r2, r2, r3
800456c: 6b63 ldr r3, [r4, #52] @ 0x34
800456e: b10b cbz r3, 8004574 <__sflush_r+0x44>
8004570: 6c23 ldr r3, [r4, #64] @ 0x40
8004572: 1ad2 subs r2, r2, r3
8004574: 2300 movs r3, #0
8004576: 6ae6 ldr r6, [r4, #44] @ 0x2c
8004578: 6a21 ldr r1, [r4, #32]
800457a: 4628 mov r0, r5
800457c: 47b0 blx r6
800457e: 1c43 adds r3, r0, #1
8004580: 89a3 ldrh r3, [r4, #12]
8004582: d106 bne.n 8004592 <__sflush_r+0x62>
8004584: 6829 ldr r1, [r5, #0]
8004586: 291d cmp r1, #29
8004588: d82b bhi.n 80045e2 <__sflush_r+0xb2>
800458a: 4a2a ldr r2, [pc, #168] @ (8004634 <__sflush_r+0x104>)
800458c: 40ca lsrs r2, r1
800458e: 07d6 lsls r6, r2, #31
8004590: d527 bpl.n 80045e2 <__sflush_r+0xb2>
8004592: 2200 movs r2, #0
8004594: 6062 str r2, [r4, #4]
8004596: 04d9 lsls r1, r3, #19
8004598: 6922 ldr r2, [r4, #16]
800459a: 6022 str r2, [r4, #0]
800459c: d504 bpl.n 80045a8 <__sflush_r+0x78>
800459e: 1c42 adds r2, r0, #1
80045a0: d101 bne.n 80045a6 <__sflush_r+0x76>
80045a2: 682b ldr r3, [r5, #0]
80045a4: b903 cbnz r3, 80045a8 <__sflush_r+0x78>
80045a6: 6560 str r0, [r4, #84] @ 0x54
80045a8: 6b61 ldr r1, [r4, #52] @ 0x34
80045aa: 602f str r7, [r5, #0]
80045ac: b1b9 cbz r1, 80045de <__sflush_r+0xae>
80045ae: f104 0344 add.w r3, r4, #68 @ 0x44
80045b2: 4299 cmp r1, r3
80045b4: d002 beq.n 80045bc <__sflush_r+0x8c>
80045b6: 4628 mov r0, r5
80045b8: f7ff fbf4 bl 8003da4 <_free_r>
80045bc: 2300 movs r3, #0
80045be: 6363 str r3, [r4, #52] @ 0x34
80045c0: e00d b.n 80045de <__sflush_r+0xae>
80045c2: 2301 movs r3, #1
80045c4: 4628 mov r0, r5
80045c6: 47b0 blx r6
80045c8: 4602 mov r2, r0
80045ca: 1c50 adds r0, r2, #1
80045cc: d1c9 bne.n 8004562 <__sflush_r+0x32>
80045ce: 682b ldr r3, [r5, #0]
80045d0: 2b00 cmp r3, #0
80045d2: d0c6 beq.n 8004562 <__sflush_r+0x32>
80045d4: 2b1d cmp r3, #29
80045d6: d001 beq.n 80045dc <__sflush_r+0xac>
80045d8: 2b16 cmp r3, #22
80045da: d11e bne.n 800461a <__sflush_r+0xea>
80045dc: 602f str r7, [r5, #0]
80045de: 2000 movs r0, #0
80045e0: e022 b.n 8004628 <__sflush_r+0xf8>
80045e2: f043 0340 orr.w r3, r3, #64 @ 0x40
80045e6: b21b sxth r3, r3
80045e8: e01b b.n 8004622 <__sflush_r+0xf2>
80045ea: 690f ldr r7, [r1, #16]
80045ec: 2f00 cmp r7, #0
80045ee: d0f6 beq.n 80045de <__sflush_r+0xae>
80045f0: 0793 lsls r3, r2, #30
80045f2: 680e ldr r6, [r1, #0]
80045f4: bf08 it eq
80045f6: 694b ldreq r3, [r1, #20]
80045f8: 600f str r7, [r1, #0]
80045fa: bf18 it ne
80045fc: 2300 movne r3, #0
80045fe: eba6 0807 sub.w r8, r6, r7
8004602: 608b str r3, [r1, #8]
8004604: f1b8 0f00 cmp.w r8, #0
8004608: dde9 ble.n 80045de <__sflush_r+0xae>
800460a: 6a21 ldr r1, [r4, #32]
800460c: 6aa6 ldr r6, [r4, #40] @ 0x28
800460e: 4643 mov r3, r8
8004610: 463a mov r2, r7
8004612: 4628 mov r0, r5
8004614: 47b0 blx r6
8004616: 2800 cmp r0, #0
8004618: dc08 bgt.n 800462c <__sflush_r+0xfc>
800461a: f9b4 300c ldrsh.w r3, [r4, #12]
800461e: f043 0340 orr.w r3, r3, #64 @ 0x40
8004622: 81a3 strh r3, [r4, #12]
8004624: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8004628: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
800462c: 4407 add r7, r0
800462e: eba8 0800 sub.w r8, r8, r0
8004632: e7e7 b.n 8004604 <__sflush_r+0xd4>
8004634: 20400001 .word 0x20400001
08004638 <_fflush_r>:
8004638: b538 push {r3, r4, r5, lr}
800463a: 690b ldr r3, [r1, #16]
800463c: 4605 mov r5, r0
800463e: 460c mov r4, r1
8004640: b913 cbnz r3, 8004648 <_fflush_r+0x10>
8004642: 2500 movs r5, #0
8004644: 4628 mov r0, r5
8004646: bd38 pop {r3, r4, r5, pc}
8004648: b118 cbz r0, 8004652 <_fflush_r+0x1a>
800464a: 6a03 ldr r3, [r0, #32]
800464c: b90b cbnz r3, 8004652 <_fflush_r+0x1a>
800464e: f7ff faa1 bl 8003b94 <__sinit>
8004652: f9b4 300c ldrsh.w r3, [r4, #12]
8004656: 2b00 cmp r3, #0
8004658: d0f3 beq.n 8004642 <_fflush_r+0xa>
800465a: 6e62 ldr r2, [r4, #100] @ 0x64
800465c: 07d0 lsls r0, r2, #31
800465e: d404 bmi.n 800466a <_fflush_r+0x32>
8004660: 0599 lsls r1, r3, #22
8004662: d402 bmi.n 800466a <_fflush_r+0x32>
8004664: 6da0 ldr r0, [r4, #88] @ 0x58
8004666: f7ff fb9a bl 8003d9e <__retarget_lock_acquire_recursive>
800466a: 4628 mov r0, r5
800466c: 4621 mov r1, r4
800466e: f7ff ff5f bl 8004530 <__sflush_r>
8004672: 6e63 ldr r3, [r4, #100] @ 0x64
8004674: 07da lsls r2, r3, #31
8004676: 4605 mov r5, r0
8004678: d4e4 bmi.n 8004644 <_fflush_r+0xc>
800467a: 89a3 ldrh r3, [r4, #12]
800467c: 059b lsls r3, r3, #22
800467e: d4e1 bmi.n 8004644 <_fflush_r+0xc>
8004680: 6da0 ldr r0, [r4, #88] @ 0x58
8004682: f7ff fb8d bl 8003da0 <__retarget_lock_release_recursive>
8004686: e7dd b.n 8004644 <_fflush_r+0xc>
08004688 <__swbuf_r>:
8004688: b5f8 push {r3, r4, r5, r6, r7, lr}
800468a: 460e mov r6, r1
800468c: 4614 mov r4, r2
800468e: 4605 mov r5, r0
8004690: b118 cbz r0, 800469a <__swbuf_r+0x12>
8004692: 6a03 ldr r3, [r0, #32]
8004694: b90b cbnz r3, 800469a <__swbuf_r+0x12>
8004696: f7ff fa7d bl 8003b94 <__sinit>
800469a: 69a3 ldr r3, [r4, #24]
800469c: 60a3 str r3, [r4, #8]
800469e: 89a3 ldrh r3, [r4, #12]
80046a0: 071a lsls r2, r3, #28
80046a2: d501 bpl.n 80046a8 <__swbuf_r+0x20>
80046a4: 6923 ldr r3, [r4, #16]
80046a6: b943 cbnz r3, 80046ba <__swbuf_r+0x32>
80046a8: 4621 mov r1, r4
80046aa: 4628 mov r0, r5
80046ac: f000 f82a bl 8004704 <__swsetup_r>
80046b0: b118 cbz r0, 80046ba <__swbuf_r+0x32>
80046b2: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff
80046b6: 4638 mov r0, r7
80046b8: bdf8 pop {r3, r4, r5, r6, r7, pc}
80046ba: 6823 ldr r3, [r4, #0]
80046bc: 6922 ldr r2, [r4, #16]
80046be: 1a98 subs r0, r3, r2
80046c0: 6963 ldr r3, [r4, #20]
80046c2: b2f6 uxtb r6, r6
80046c4: 4283 cmp r3, r0
80046c6: 4637 mov r7, r6
80046c8: dc05 bgt.n 80046d6 <__swbuf_r+0x4e>
80046ca: 4621 mov r1, r4
80046cc: 4628 mov r0, r5
80046ce: f7ff ffb3 bl 8004638 <_fflush_r>
80046d2: 2800 cmp r0, #0
80046d4: d1ed bne.n 80046b2 <__swbuf_r+0x2a>
80046d6: 68a3 ldr r3, [r4, #8]
80046d8: 3b01 subs r3, #1
80046da: 60a3 str r3, [r4, #8]
80046dc: 6823 ldr r3, [r4, #0]
80046de: 1c5a adds r2, r3, #1
80046e0: 6022 str r2, [r4, #0]
80046e2: 701e strb r6, [r3, #0]
80046e4: 6962 ldr r2, [r4, #20]
80046e6: 1c43 adds r3, r0, #1
80046e8: 429a cmp r2, r3
80046ea: d004 beq.n 80046f6 <__swbuf_r+0x6e>
80046ec: 89a3 ldrh r3, [r4, #12]
80046ee: 07db lsls r3, r3, #31
80046f0: d5e1 bpl.n 80046b6 <__swbuf_r+0x2e>
80046f2: 2e0a cmp r6, #10
80046f4: d1df bne.n 80046b6 <__swbuf_r+0x2e>
80046f6: 4621 mov r1, r4
80046f8: 4628 mov r0, r5
80046fa: f7ff ff9d bl 8004638 <_fflush_r>
80046fe: 2800 cmp r0, #0
8004700: d0d9 beq.n 80046b6 <__swbuf_r+0x2e>
8004702: e7d6 b.n 80046b2 <__swbuf_r+0x2a>
08004704 <__swsetup_r>:
8004704: b538 push {r3, r4, r5, lr}
8004706: 4b29 ldr r3, [pc, #164] @ (80047ac <__swsetup_r+0xa8>)
8004708: 4605 mov r5, r0
800470a: 6818 ldr r0, [r3, #0]
800470c: 460c mov r4, r1
800470e: b118 cbz r0, 8004718 <__swsetup_r+0x14>
8004710: 6a03 ldr r3, [r0, #32]
8004712: b90b cbnz r3, 8004718 <__swsetup_r+0x14>
8004714: f7ff fa3e bl 8003b94 <__sinit>
8004718: f9b4 300c ldrsh.w r3, [r4, #12]
800471c: 0719 lsls r1, r3, #28
800471e: d422 bmi.n 8004766 <__swsetup_r+0x62>
8004720: 06da lsls r2, r3, #27
8004722: d407 bmi.n 8004734 <__swsetup_r+0x30>
8004724: 2209 movs r2, #9
8004726: 602a str r2, [r5, #0]
8004728: f043 0340 orr.w r3, r3, #64 @ 0x40
800472c: 81a3 strh r3, [r4, #12]
800472e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8004732: e033 b.n 800479c <__swsetup_r+0x98>
8004734: 0758 lsls r0, r3, #29
8004736: d512 bpl.n 800475e <__swsetup_r+0x5a>
8004738: 6b61 ldr r1, [r4, #52] @ 0x34
800473a: b141 cbz r1, 800474e <__swsetup_r+0x4a>
800473c: f104 0344 add.w r3, r4, #68 @ 0x44
8004740: 4299 cmp r1, r3
8004742: d002 beq.n 800474a <__swsetup_r+0x46>
8004744: 4628 mov r0, r5
8004746: f7ff fb2d bl 8003da4 <_free_r>
800474a: 2300 movs r3, #0
800474c: 6363 str r3, [r4, #52] @ 0x34
800474e: 89a3 ldrh r3, [r4, #12]
8004750: f023 0324 bic.w r3, r3, #36 @ 0x24
8004754: 81a3 strh r3, [r4, #12]
8004756: 2300 movs r3, #0
8004758: 6063 str r3, [r4, #4]
800475a: 6923 ldr r3, [r4, #16]
800475c: 6023 str r3, [r4, #0]
800475e: 89a3 ldrh r3, [r4, #12]
8004760: f043 0308 orr.w r3, r3, #8
8004764: 81a3 strh r3, [r4, #12]
8004766: 6923 ldr r3, [r4, #16]
8004768: b94b cbnz r3, 800477e <__swsetup_r+0x7a>
800476a: 89a3 ldrh r3, [r4, #12]
800476c: f403 7320 and.w r3, r3, #640 @ 0x280
8004770: f5b3 7f00 cmp.w r3, #512 @ 0x200
8004774: d003 beq.n 800477e <__swsetup_r+0x7a>
8004776: 4621 mov r1, r4
8004778: 4628 mov r0, r5
800477a: f000 f84f bl 800481c <__smakebuf_r>
800477e: f9b4 300c ldrsh.w r3, [r4, #12]
8004782: f013 0201 ands.w r2, r3, #1
8004786: d00a beq.n 800479e <__swsetup_r+0x9a>
8004788: 2200 movs r2, #0
800478a: 60a2 str r2, [r4, #8]
800478c: 6962 ldr r2, [r4, #20]
800478e: 4252 negs r2, r2
8004790: 61a2 str r2, [r4, #24]
8004792: 6922 ldr r2, [r4, #16]
8004794: b942 cbnz r2, 80047a8 <__swsetup_r+0xa4>
8004796: f013 0080 ands.w r0, r3, #128 @ 0x80
800479a: d1c5 bne.n 8004728 <__swsetup_r+0x24>
800479c: bd38 pop {r3, r4, r5, pc}
800479e: 0799 lsls r1, r3, #30
80047a0: bf58 it pl
80047a2: 6962 ldrpl r2, [r4, #20]
80047a4: 60a2 str r2, [r4, #8]
80047a6: e7f4 b.n 8004792 <__swsetup_r+0x8e>
80047a8: 2000 movs r0, #0
80047aa: e7f7 b.n 800479c <__swsetup_r+0x98>
80047ac: 20000018 .word 0x20000018
080047b0 <_sbrk_r>:
80047b0: b538 push {r3, r4, r5, lr}
80047b2: 4d06 ldr r5, [pc, #24] @ (80047cc <_sbrk_r+0x1c>)
80047b4: 2300 movs r3, #0
80047b6: 4604 mov r4, r0
80047b8: 4608 mov r0, r1
80047ba: 602b str r3, [r5, #0]
80047bc: f7fc fdbc bl 8001338 <_sbrk>
80047c0: 1c43 adds r3, r0, #1
80047c2: d102 bne.n 80047ca <_sbrk_r+0x1a>
80047c4: 682b ldr r3, [r5, #0]
80047c6: b103 cbz r3, 80047ca <_sbrk_r+0x1a>
80047c8: 6023 str r3, [r4, #0]
80047ca: bd38 pop {r3, r4, r5, pc}
80047cc: 2000029c .word 0x2000029c
080047d0 <__swhatbuf_r>:
80047d0: b570 push {r4, r5, r6, lr}
80047d2: 460c mov r4, r1
80047d4: f9b1 100e ldrsh.w r1, [r1, #14]
80047d8: 2900 cmp r1, #0
80047da: b096 sub sp, #88 @ 0x58
80047dc: 4615 mov r5, r2
80047de: 461e mov r6, r3
80047e0: da0d bge.n 80047fe <__swhatbuf_r+0x2e>
80047e2: 89a3 ldrh r3, [r4, #12]
80047e4: f013 0f80 tst.w r3, #128 @ 0x80
80047e8: f04f 0100 mov.w r1, #0
80047ec: bf14 ite ne
80047ee: 2340 movne r3, #64 @ 0x40
80047f0: f44f 6380 moveq.w r3, #1024 @ 0x400
80047f4: 2000 movs r0, #0
80047f6: 6031 str r1, [r6, #0]
80047f8: 602b str r3, [r5, #0]
80047fa: b016 add sp, #88 @ 0x58
80047fc: bd70 pop {r4, r5, r6, pc}
80047fe: 466a mov r2, sp
8004800: f000 f848 bl 8004894 <_fstat_r>
8004804: 2800 cmp r0, #0
8004806: dbec blt.n 80047e2 <__swhatbuf_r+0x12>
8004808: 9901 ldr r1, [sp, #4]
800480a: f401 4170 and.w r1, r1, #61440 @ 0xf000
800480e: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000
8004812: 4259 negs r1, r3
8004814: 4159 adcs r1, r3
8004816: f44f 6380 mov.w r3, #1024 @ 0x400
800481a: e7eb b.n 80047f4 <__swhatbuf_r+0x24>
0800481c <__smakebuf_r>:
800481c: 898b ldrh r3, [r1, #12]
800481e: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
8004820: 079d lsls r5, r3, #30
8004822: 4606 mov r6, r0
8004824: 460c mov r4, r1
8004826: d507 bpl.n 8004838 <__smakebuf_r+0x1c>
8004828: f104 0347 add.w r3, r4, #71 @ 0x47
800482c: 6023 str r3, [r4, #0]
800482e: 6123 str r3, [r4, #16]
8004830: 2301 movs r3, #1
8004832: 6163 str r3, [r4, #20]
8004834: b003 add sp, #12
8004836: bdf0 pop {r4, r5, r6, r7, pc}
8004838: ab01 add r3, sp, #4
800483a: 466a mov r2, sp
800483c: f7ff ffc8 bl 80047d0 <__swhatbuf_r>
8004840: 9f00 ldr r7, [sp, #0]
8004842: 4605 mov r5, r0
8004844: 4639 mov r1, r7
8004846: 4630 mov r0, r6
8004848: f7ff fb18 bl 8003e7c <_malloc_r>
800484c: b948 cbnz r0, 8004862 <__smakebuf_r+0x46>
800484e: f9b4 300c ldrsh.w r3, [r4, #12]
8004852: 059a lsls r2, r3, #22
8004854: d4ee bmi.n 8004834 <__smakebuf_r+0x18>
8004856: f023 0303 bic.w r3, r3, #3
800485a: f043 0302 orr.w r3, r3, #2
800485e: 81a3 strh r3, [r4, #12]
8004860: e7e2 b.n 8004828 <__smakebuf_r+0xc>
8004862: 89a3 ldrh r3, [r4, #12]
8004864: 6020 str r0, [r4, #0]
8004866: f043 0380 orr.w r3, r3, #128 @ 0x80
800486a: 81a3 strh r3, [r4, #12]
800486c: 9b01 ldr r3, [sp, #4]
800486e: e9c4 0704 strd r0, r7, [r4, #16]
8004872: b15b cbz r3, 800488c <__smakebuf_r+0x70>
8004874: f9b4 100e ldrsh.w r1, [r4, #14]
8004878: 4630 mov r0, r6
800487a: f000 f81d bl 80048b8 <_isatty_r>
800487e: b128 cbz r0, 800488c <__smakebuf_r+0x70>
8004880: 89a3 ldrh r3, [r4, #12]
8004882: f023 0303 bic.w r3, r3, #3
8004886: f043 0301 orr.w r3, r3, #1
800488a: 81a3 strh r3, [r4, #12]
800488c: 89a3 ldrh r3, [r4, #12]
800488e: 431d orrs r5, r3
8004890: 81a5 strh r5, [r4, #12]
8004892: e7cf b.n 8004834 <__smakebuf_r+0x18>
08004894 <_fstat_r>:
8004894: b538 push {r3, r4, r5, lr}
8004896: 4d07 ldr r5, [pc, #28] @ (80048b4 <_fstat_r+0x20>)
8004898: 2300 movs r3, #0
800489a: 4604 mov r4, r0
800489c: 4608 mov r0, r1
800489e: 4611 mov r1, r2
80048a0: 602b str r3, [r5, #0]
80048a2: f7fc fd20 bl 80012e6 <_fstat>
80048a6: 1c43 adds r3, r0, #1
80048a8: d102 bne.n 80048b0 <_fstat_r+0x1c>
80048aa: 682b ldr r3, [r5, #0]
80048ac: b103 cbz r3, 80048b0 <_fstat_r+0x1c>
80048ae: 6023 str r3, [r4, #0]
80048b0: bd38 pop {r3, r4, r5, pc}
80048b2: bf00 nop
80048b4: 2000029c .word 0x2000029c
080048b8 <_isatty_r>:
80048b8: b538 push {r3, r4, r5, lr}
80048ba: 4d06 ldr r5, [pc, #24] @ (80048d4 <_isatty_r+0x1c>)
80048bc: 2300 movs r3, #0
80048be: 4604 mov r4, r0
80048c0: 4608 mov r0, r1
80048c2: 602b str r3, [r5, #0]
80048c4: f7fc fd1f bl 8001306 <_isatty>
80048c8: 1c43 adds r3, r0, #1
80048ca: d102 bne.n 80048d2 <_isatty_r+0x1a>
80048cc: 682b ldr r3, [r5, #0]
80048ce: b103 cbz r3, 80048d2 <_isatty_r+0x1a>
80048d0: 6023 str r3, [r4, #0]
80048d2: bd38 pop {r3, r4, r5, pc}
80048d4: 2000029c .word 0x2000029c
080048d8 <_init>:
80048d8: b5f8 push {r3, r4, r5, r6, r7, lr}
80048da: bf00 nop
80048dc: bcf8 pop {r3, r4, r5, r6, r7}
80048de: bc08 pop {r3}
80048e0: 469e mov lr, r3
80048e2: 4770 bx lr
080048e4 <_fini>:
80048e4: b5f8 push {r3, r4, r5, r6, r7, lr}
80048e6: bf00 nop
80048e8: bcf8 pop {r3, r4, r5, r6, r7}
80048ea: bc08 pop {r3}
80048ec: 469e mov lr, r3
80048ee: 4770 bx lr
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