Assign footprints (testing), Create pcb outline

This commit is contained in:
jonny 2024-10-24 14:04:11 +02:00
parent 8f1a55a689
commit b3455c31e7
5 changed files with 99884 additions and 1979 deletions

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@ -2033,7 +2033,7 @@
(justify left)
)
)
(property "Footprint" ""
(property "Footprint" "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal"
(at 132.842 85.09 90)
(effects
(font
@ -2128,7 +2128,7 @@
)
)
)
(property "Footprint" ""
(property "Footprint" "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal"
(at 173.99 90.678 90)
(effects
(font
@ -2711,7 +2711,7 @@
(justify left)
)
)
(property "Footprint" ""
(property "Footprint" "Capacitor_THT:C_Disc_D7.0mm_W2.5mm_P5.00mm"
(at 181.3052 97.79 0)
(effects
(font
@ -3092,7 +3092,7 @@
)
)
)
(property "Footprint" ""
(property "Footprint" "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal"
(at 86.36 97.028 90)
(effects
(font
@ -3466,7 +3466,7 @@
)
)
)
(property "Footprint" ""
(property "Footprint" "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal"
(at 140.97 97.028 90)
(effects
(font
@ -3561,7 +3561,7 @@
)
)
)
(property "Footprint" ""
(property "Footprint" "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal"
(at 187.96 108.458 90)
(effects
(font
@ -3656,7 +3656,7 @@
)
)
)
(property "Footprint" ""
(property "Footprint" "Diode_SMD:D_SOD-123F"
(at 110.617 100.33 0)
(effects
(font
@ -3847,7 +3847,7 @@
(justify right)
)
)
(property "Footprint" ""
(property "Footprint" "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal"
(at 203.708 83.82 90)
(effects
(font
@ -3944,7 +3944,7 @@
(justify right)
)
)
(property "Footprint" ""
(property "Footprint" "LED_THT:LED_D3.0mm_Clear"
(at 201.93 93.98 0)
(effects
(font
@ -4041,7 +4041,7 @@
(justify right)
)
)
(property "Footprint" ""
(property "Footprint" "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal"
(at 155.448 82.55 90)
(effects
(font

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@ -1,2 +1,94 @@
(kicad_pcb (version 20240108) (generator "pcbnew") (generator_version "8.0")
)
(kicad_pcb
(version 20240108)
(generator "pcbnew")
(generator_version "8.0")
(general
(thickness 1.6)
(legacy_teardrops no)
)
(paper "A4")
(layers
(0 "F.Cu" signal)
(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
(50 "User.1" user)
(51 "User.2" user)
(52 "User.3" user)
(53 "User.4" user)
(54 "User.5" user)
(55 "User.6" user)
(56 "User.7" user)
(57 "User.8" user)
(58 "User.9" user)
)
(setup
(pad_to_mask_clearance 0)
(allow_soldermask_bridges_in_footprints no)
(pcbplotparams
(layerselection 0x00010fc_ffffffff)
(plot_on_all_layers_selection 0x0000000_00000000)
(disableapertmacros no)
(usegerberextensions no)
(usegerberattributes yes)
(usegerberadvancedattributes yes)
(creategerberjobfile yes)
(dashed_line_dash_ratio 12.000000)
(dashed_line_gap_ratio 3.000000)
(svgprecision 4)
(plotframeref no)
(viasonmask no)
(mode 1)
(useauxorigin no)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(pdf_front_fp_property_popups yes)
(pdf_back_fp_property_popups yes)
(dxfpolygonmode yes)
(dxfimperialunits yes)
(dxfusepcbnewfont yes)
(psnegative no)
(psa4output no)
(plotreference yes)
(plotvalue yes)
(plotfptext yes)
(plotinvisibletext no)
(sketchpadsonfab no)
(subtractmaskfromsilk no)
(outputformat 1)
(mirror no)
(drillshape 1)
(scaleselection 1)
(outputdirectory "")
)
)
(net 0 "")
(gr_rect
(start 40 33)
(end 200 133)
(stroke
(width 0.05)
(type default)
)
(fill none)
(layer "Edge.Cuts")
(uuid "1804d5e7-a4e7-4bf5-93d1-4f8c3414827d")
)
)

View File

@ -1,7 +1,7 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "",
"active_layer_preset": "All Layers",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],

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